25. Device electronic signature (DESIG)

The device electronic signature is stored in the System memory area of the flash memory module, and can be read using the debug interface or by the CPU. It contains factoryprogrammed identification and calibration data that allow the user firmware or other external devices to automatically match the characteristics of the microcontroller.

25.1 DESIG registers

25.1.1 DESIG ADC trimming max diff (DESIG_ADCMAXDIFF)

Address offset: 0x000

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:16]
												r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET[19:16]				GAIN[11:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:20	Reserved, must be kept at reset value.
Bits 19:12	OFFSET[19:12] : ADC trimming offset maximum differential (ADC_VINP - ADC_VINM at 1.2 V).
Bits 11:0	GAIN[11:0] : ADC trimming gain maximum differential (ADC_VINP - ADC_VINM at 1.2 V).

25.1.2 DESIG ADC trimming max negative (DESIG_ADCMAXNEG)

Address offset: 0x004

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:16]
												r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET[19:16]				GAIN[11:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:20	Reserved, must be kept at reset value.
Bits 19:12	OFFSET[19:12] : ADC trimming offset maximum negative (ADC_VINM at 1.2 V).
Bits 11:0	GAIN[11:0] : ADC trimming gain maximum negative (ADC_VINM at 1.2 V).

25.1.3 DESIG ADC trimming max positive (DESIG_ADCMAXPOS)

Address offset: 0x008

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:16]
												r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET[19:16]				GAIN[11:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:20	Reserved, must be kept at reset value.
Bits 19:12	OFFSET[19:12] : ADC trimming offset maximum positive (ADC_VINP at 1.2 V).
Bits 11:0	GAIN[11:0] : ADC trimming gain maximum positive (ADC_VINP at 1.2 V).

25.1.4 DESIG ADC trimming mean diff (DESIG_ADCMEANDIFF)

Address offset: 0x00C

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:16]
												r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET[19:16]				GAIN[11:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:20	Reserved, must be kept at reset value.
Bits 19:12	OFFSET[19:12] : ADC trimming offset mean differential (ADC_VINP - ADC_VINM at 2.4 V).
Bits 11:0	GAIN[11:0] : ADC trimming gain mean differential (ADC_VINP - ADC_VINM at 2.4 V).

25.1.5 DESIG ADC trimming mean negative (DESIG_ADCMEANNEG)

Address offset: 0x010

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:16]
												r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET[19:16]				GAIN[11:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:20	Reserved, must be kept at reset value.
Bits 19:12	OFFSET[19:12] : ADC trimming offset mean negative (ADC_VINM at 2.4 V).
Bits 11:0	GAIN[11:0] : ADC trimming gain mean negative (ADC_VINM at 2.4 V).

25.1.6 DESIG ADC trimming max positive (DESIG_ADCMEANPOS)

Address offset: 0x000

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:16]
												r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET[19:16]				GAIN[11:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:20	Reserved, must be kept at reset value.
Bits 19:12	OFFSET[19:12] : ADC trimming offset mean positive (ADC_VINP at 2.4 V).
Bits 11:0	GAIN[11:0] : ADC trimming gain mean positive (ADC_VINP at 2.4 V).

25.1.7 DESIG ADC trimming min diff (DESIG_ADCMINDIFF)

Address offset: 0x018

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:16]
												r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET[19:16]				GAIN[11:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:20	Reserved, must be kept at reset value.
Bits 19:12	OFFSET[19:12] : ADC trimming offset minimum differential (ADC_VINP - ADC_VINM at 3.6 V).
Bits 11:0	GAIN[11:0] : ADC trimming gain minimum differential (ADC_VINP - ADC_VINM at 3.6 V).

25.1.8 DESIG ADC trimming min negative (DESIG_ADCMINNEG)

Address offset: 0x01C

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:16]
												r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET[19:16]				GAIN[11:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:20	Reserved, must be kept at reset value.
Bits 19:12	OFFSET[19:12] : ADC trimming offset minimum negative (ADC_VINM at 3.6 V).
Bits 11:0	GAIN[11:0] : ADC trimming gain minimum negative (ADC_VINM at 3.6 V).

25.1.9 DESIG ADC trimming min positive (DESIG_ADCMINPOS)

Address offset: 0x020

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:16]
												r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET[19:16]				GAIN[11:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:20	Reserved, must be kept at reset value.
Bits 19:12	OFFSET[19:12] : ADC trimming offset minimum positive (ADC_VINP at 3.6 V).
Bits 11:0	GAIN[11:0] : ADC trimming gain minimum positive (ADC_VINP at 3.6 V).

25.1.10 DESIG reference temperature register (DESIG_TSREFR)

Address offset: 0x05C

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TS_REF[31:16]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TS_REF[15:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:0

TS_REF[31:0] : reference temperature for ADC at 30°C.

25.1.11 DESIG temperature calibration register (DESIG_TSCAL1R)

Address offset: 0x060

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TS_CAL[31:16]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TS_CAL[15:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:0

TS_CAL[31:0] : temperature measurement calibration for ADC at 30°C.

25.1.12 DESIG package data register (DESIG_PKGR)

Address offset: 0x0EC

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PKG[31:16]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PKG[15:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:0

TS_REF[31:0]:
Package type:
0x5F325F32: VFQFPN32
0xAC36AC36: WLCSP36

25.1.13 DESIG 64-bit unique device identifier register 1 (DESIG_UID64R1)

Address offset: 0x0F0

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UID[31:16]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UID[15:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:0

UID[31:0]: unique serial number (first 4 bytes)

25.1.14 DESIG 64-bit unique device identifier register 2 (DESIG_UID64R2)

Address offset: 0x0F4

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UID[63:48]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UID[47:32]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:0

UID[63:32] : unique serial number (last 4 bytes)

25.1.15 DESIG register map

Table 248. PWRC register map

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x000	DESIG_ADCMA XDlFF	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:12]								GAIN[11:0]
0x000	Reset value													X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
0x004	DESIG_ADCMA XNEG	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:12]								GAIN[11:0]
0x004	Reset value													X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
0x008	DESIG_ADCMA XPOS	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:12]								GAIN[11:0]
0x008	Reset value													X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
0x00C	DESIG_ADCME ANDIFF	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:12]								GAIN[11:0]
0x00C	Reset value													X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
0x010	DESIG_ADCME ANNEG	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:12]								GAIN[11:0]
0x010	Reset value													X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
0x014	DESIG_ADCME ANPOS	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:12]								GAIN[11:0]
0x014	Reset value													X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
0x018	DESIG_ADCMI NDIFF	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:12]								GAIN[11:0]
0x018	Reset value													X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
0x01C	DESIG_ADCMI NNEG	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:12]								GAIN[11:0]
0x01C	Reset value													X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
0x020	DESIG_ADCMI NPOS	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:12]								GAIN[11:0]
0x020	Reset value													X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
0x024 - 0x5B	Reserved	Res.
0x05C	DESIG_TSREF R	TS_REF[31:0]
0x05C	Reset value	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
0x060	DESIG_TSCAL 1R	PKG [31:0]

ST logo

STMicroelectronics logo

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x060	Reset value	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
0x064 0xE8	Reserved	Res.
0x0EC	DESIG_PKGR	PKG[31:0]
0x0EC	Reset value	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
0x0F0	DESIG_UID64R 1	UID[31:0]
0x0F0	Reset value	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
0x0F4	DESIG_UID64R 2	UID[63:32]
0x0F4	Reset value	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Refer to Memory map and register boundary addresses for the register boundary addresses.

Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST product(s) identified in this documentation may be certified by various security certification bodies and/or may implement our own security measures as set forth herein. However, no level of security certification and/or built-in security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the customer needs both in relation to the ST product alone, as well as when combined with other components and/or software for the customer end product or application. In particular, take note that:

• ST products may have been certified by one or more security certification bodies, such as Platform Security Architecture ( www.psacertified.org ) and/or Security Evaluation standard for IoT Platforms ( www.trustcb.com ). For details concerning whether the ST product(s) referenced herein have received security certification along with the level and current status of such certification, either visit the relevant certification standards website or go to the relevant product page on www.st.com for the most up to date information. As the status and/or level of security certification for an ST product can change from time to time, customers should re-check security certification status/level as needed. If an ST product is not shown to be certified under a particular security standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST products. These certification bodies are therefore independently responsible for granting or revoking security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations, assessments, testing, or other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard technologies which may be used in conjunction with an ST product are based on standards which were not developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open technologies or for any methods which have been or may be developed to bypass, decrypt or crack such algorithms or technologies.
• While robust security testing may be done, no level of certification can absolutely guarantee protections against all attacks, including, for example, against advanced attacks which have not been tested for, against new or unidentified forms of attack, or against any form of attack when using an ST product outside of its specification or intended use, or in conjunction with other components or software which are used by customer to create their end product or application. ST is not responsible for resistance against such attacks. As such, regardless of the incorporated security features and/or any information or support that may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for meets their needs, both in relation to the ST product alone and when incorporated into a customer end product or application.
• All security features of ST products (inclusive of any hardware, software, documentation, and the like), including but not limited to any enhanced security features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the applicable written and signed contract terms specifically provide otherwise.

Revision history

Table 249. Document revision history

Date

Version

Changes

27-Jun-2024

1

Initial release.

21-Nov-2024

2

Updated:

Section 7.3.2: I/O pin alternate function multiplexer and mapping (EVENTOUT description)
Table 8. GPIO alternate options AF3 - AF4
Section 12.5.2: ADC mode

Added note to refer to DESIG registers for calibration values in:

Section 12.2.2: Temperature sensor subsystem
Section 12.2.3: Battery sensor
Section 12.2.5: Calibration points
Section 12.6.11: ADC gain and offset correction 1 register (COMP_1)
Section 12.6.12: ADC gain and offset correction 2 register (COMP_2)
Section 12.6.13: ADC gain and offset correction 3 register (COMP_3)
Section 12.6.14: ADC gain and offset correction 4 register (COMP_4)

07-Apr-2025

3

Added:

Correct references to Deepstop mode

Updated:

Bluetooth Low Energy to Bluetooth LE throughout document
Use of These bits have no effect , where applicable.
Section 6.6: RCC registers
Section 9.5.5: Enabling protection example
Table 23. System memory protection
Section 19: Inter-integrated circuit (I ²C) interface: Master replaced by controller and Slave replaced by target throughout the section.

Contents

1	Documentation conventions	2
1.1	General information	2
1.2	List of abbreviations for registers	2
1.3	Glossary	2
1.4	Availability of peripherals	3
1.5	Acronyms	4
2	System and memory overview	7
2.1	System architecture	7
2.1.1	S0: CPU (Cortex®-M0+) S-bus	8
2.1.2	S1: DMA-bus	8
2.1.3	S2: Radio system-bus	8
2.1.4	BusMatrix	9
2.2	Memory organization	9
2.2.1	Introduction	9
2.2.2	Memory map and register boundary addresses	11
2.3	Arm® Cortex®-M0+	12
2.3.1	CPU memory remap	13
2.3.2	Interrupts	14
3	AHB up/down converter	16
3.1	AHB up/down converter description	16
4	I/O operating modes	18
5	Power controller (PWRC)	24
5.1	Features	24
5.2	Power supply domains	24
5.3	Power voltage supervisor	25
5.3.1	Power-on reset POR / power-down reset (PDR) / Brown-Out Reset (BOR)	25
5.3.2	Power voltage detection (PVD)	26
5.4	Operating modes	26
5.4.1	Run mode	26
5.4.2	Deepstop mode	27
5.4.3	Shutdown mode	29
5.4.4	Operating mode transition management	31
5.5	SMPS step-down regulator	31
5.6	I/O pull-ups/pull-downs during low power mode	33
5.7	PWRC registers	34

5.7.1	Control register 1 (PWRC_CR1) . . . . .	34
5.7.2	Control register 2 (PWRC_CR2) . . . . .	35
5.7.3	Control register 3 (PWRC_CR3) . . . . .	36
5.7.4	Control register 4 (PWRC_CR4) . . . . .	38
5.7.5	Status register 1 (PWRC_SR1) . . . . .	40
5.7.6	Status register 2 (PWRC_SR2) . . . . .	42
5.7.7	Control register 5 (PWRC_CR5) . . . . .	43
5.7.8	I/O port A pull-up control register (PWRC_PUCRA) . . . . .	45
5.7.9	I/O port A pull-down control register (PWRC_PDCRA) . . . . .	47
5.7.10	I/O port B pull-up control register (PWRC_PUCRB) . . . . .	49
5.7.11	I/O port B pull-down control register (PWRC_PDCRB) . . . . .	51
5.7.12	Control register 6 (PWRC_CR6) . . . . .	53
5.7.13	Control register 7 (PWRC_CR7) . . . . .	55
5.7.14	Status register 3(PWRC_SR3) . . . . .	57
5.7.15	I/O Deepstop drive configuration register (PWRC_IOxCFG) . . . . .	59
5.7.16	Debug register (PWRC_DBGR) . . . . .	61
5.7.17	Extended status and reset register (PWRC_EXTSRR) . . . . .	62
5.7.18	PWRC register map . . . . .	63
5.8	Programmer model . . . . .	66
5.8.1	Reset reason management . . . . .	66
5.8.2	SMPS output level re-programming . . . . .	66
6	Reset and clock controller (RCC) . . . . .	68
6.1	Reset management. . . . .	68
6.1.1	General description. . . . .	68
6.1.2	Power reset. . . . .	69
6.1.3	Watchdog reset. . . . .	69
6.1.4	LOCKUP reset . . . . .	69
6.1.5	System reset request . . . . .	69
6.1.6	Deepstop exit . . . . .	69
6.2	Clock management . . . . .	69
6.2.1	System clock details . . . . .	70
6.2.2	Peripherals clock details . . . . .	70
6.2.3	Slow clock frequency details . . . . .	73
6.3	System frequency switch while MR_BLE is used . . . . .	73
6.4	Clock observation on external pad . . . . .	73
6.5	Miscellaneous . . . . .	74
6.5.1	IO BOOSTER . . . . .	74
6.6	RCC registers . . . . .	75

6.6.1	Clock source control register (RCC_CR) . . . . .	76
6.6.2	Clocks configuration register (RCC_CFGR) . . . . .	78
6.6.3	Clocks sources software calibration register (RCC_CSSWCR) . . . . .	80
6.6.4	Clock interrupt enable register (RCC_CIER) . . . . .	82
6.6.5	Clock interrupt flag register (RCC_CIFR) . . . . .	83
6.6.6	Clock switch command register (RCC_CSCMDR) . . . . .	85
6.6.7	AHB0 macro cells reset register (RCC_AHBRSTR) . . . . .	85
6.6.8	APB0 macro cells reset register (RCC_APB0RSTR) . . . . .	87
6.6.9	APB1 macro cells reset register (RCC_APB1RSTR) . . . . .	88
6.6.10	APB2 macro cells reset register (RCC_APB2RSTR) . . . . .	90
6.6.11	AHB0 macro cells clock enable register (RCC_AHBENR) . . . . .	91
6.6.12	APB0 macro cell clock enable register (RCC_APB0ENR) . . . . .	92
6.6.13	APB1 macro cells clock enable register (RCC_APB1ENR) . . . . .	93
6.6.14	APB2 macro cells clock enable register (RCC_APB2ENR) . . . . .	95
6.6.15	V33 reset status register (RCC_CSR) . . . . .	96
6.6.16	RF software high speed external register (RCC_RFSWHSECR) . . . . .	96
6.6.17	RF high speed external register (RCC_RFHSECR) . . . . .	98
6.6.18	RCC register map . . . . .	99
6.7	Programmer model . . . . .	104
6.7.1	Switch the system on the PLL64M clock tree . . . . .	104
6.7.2	Use the direct HSE instead of the RC64MPLL block . . . . .	104
6.7.3	Changing the system clock frequency while the MR_BLE is enabled . . . . .	104
7	General-purpose I/Os (GPIO) . . . . .	105
7.1	Introduction . . . . .	105
7.2	GPIO main features . . . . .	105
7.3	GPIO functional description . . . . .	105
7.3.1	General-purpose I/O (GPIO) . . . . .	107
7.3.2	I/O pin alternate function multiplexer and mapping . . . . .	107
7.3.3	I/O port control registers . . . . .	108
7.3.4	I/O port data registers . . . . .	108
7.3.5	I/O data bitwise handling . . . . .	108
7.3.6	GPIO locking mechanism . . . . .	109
7.3.7	I/O alternate function input/output . . . . .	109
7.3.8	External interrupt/wakeup lines . . . . .	109
7.3.9	Input configuration . . . . .	109
7.3.10	Output configuration . . . . .	110
7.3.11	Alternate function configuration . . . . .	111
7.3.12	Analog configuration . . . . .	111

7.3.13	Using the LSE oscillator pins as GPIOs . . . . .	112
7.4	GPIO registers . . . . .	113
7.4.1	GPIO port mode register (GPIOx_MODER) (x = A, B) . . . . .	113
7.4.2	GPIO port output type register (GPIOx_OTYPER) (x = A, B) . . . . .	114
7.4.3	GPIO port output speed register (GPIOx_OSPEEDR) (x = A, B). . . . .	114
7.4.4	GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A, B) . . . . .	115
7.4.5	GPIO port input data register (GPIOx_IDR) (x = A, B). . . . .	115
7.4.6	GPIO port output data register (GPIOx_ODR) (x = A, B). . . . .	116
7.4.7	GPIO port bit set/reset register (GPIOx_BSRR) (x = A, B) . . . . .	116
7.4.8	GPIO port configuration lock register (GPIOx_LCKR) (x = A, B) . . . . .	117
7.4.9	GPIO alternate function low register (GPIOx_AFRL) (x = A, B). . . . .	118
7.4.10	GPIO alternate function high register (GPIOx_AFRH) (x = A, B). . . . .	118
7.4.11	GPIO register map . . . . .	119
8	System controller (SYSCFG) . . . . .	121
8.1	SYSCFG main features . . . . .	121
8.2	System controller registers. . . . .	122
8.2.1	Die ID register (DIE_ID) . . . . .	122
8.2.2	JTAG ID register (JTAG_ID) . . . . .	123
8.2.3	I2C Fast-Mode Plus pin capability control register (I2C_FMP_CTRL) . . . . .	124
8.2.4	I/O interrupt detection type register (IO_DTR). . . . .	125
8.2.5	I/O interrupt edge register (IO_IBER) . . . . .	126
8.2.6	I/O interrupt polarity event register (IO_IEVR). . . . .	127
8.2.7	I/O interrupt enable register (IO_IER) . . . . .	128
8.2.8	I/O Interrupt status and clear register (IO_ISCR). . . . .	129
8.2.9	Power controller interrupt enable register (PWRC_IER) . . . . .	130
8.2.10	Power controller interrupt status and clear register (PWRC_ISCR). . . . .	131
8.2.11	I/O analog switch control register (GPIO_SWA_CTRL). . . . .	132
8.2.12	MR_BLE RX or TX sequence information detection type register (BLERXTX_DTR). . . . .	133
8.2.13	MR_BLE RX or TX sequence information detection type register (BLERXTX_IBER) . . . . .	134
8.2.14	MR_BLE RX or TX sequence information detection event register (BLERXTX_IEVR) . . . . .	135
8.2.15	MR_BLE RX or TX sequence information detection interrupt enable register (BLERXTX_IER). . . . .	135
8.2.16	MR_BLE RX or TX sequence information detection status and clear register (BLERXTX_ISCR). . . . .	136
8.2.17	System controller register map . . . . .	137
9	Embedded Flash memory . . . . .	140
9.1	Flash main features . . . . .	140
9.2	Description . . . . .	140

9.3	Flash controller register map . . . . .	141
9.4	Flash controller registers . . . . .	142
9.4.1	Command register (COMMAND). . . . .	142
9.4.2	Configuration register (CONFIG). . . . .	143
9.4.3	Interrupt status register (IRQSTAT). . . . .	144
9.4.4	Interrupt mask register (IRQMASK). . . . .	145
9.4.5	Raw status register (IRQRAW) . . . . .	146
9.4.6	SIZE register . . . . .	147
9.4.7	Address register (ADDRESS) . . . . .	148
9.4.8	Linear feedback shift register (LFSRVAL) . . . . .	148
9.4.9	Main flash page protection registers (PAGEPROTx) . . . . .	149
9.4.10	Data registers (DATA0-DATA3) . . . . .	149
9.5	Programmer model . . . . .	151
9.5.1	General information. . . . .	151
9.5.2	Read function examples . . . . .	151
9.5.3	Erase function examples. . . . .	152
9.5.4	Write function examples . . . . .	152
9.5.5	Enabling protection example. . . . .	154
9.5.6	OTP function example. . . . .	154
9.5.7	Write page protection example . . . . .	155
10	DMA controller (DMA). . . . .	156
10.1	DMA introduction. . . . .	156
10.2	DMA main features . . . . .	156
10.3	DMA functional description . . . . .	156
10.3.1	DMA transactions . . . . .	156
10.3.2	Arbiter . . . . .	157
10.3.3	DMA channels. . . . .	157
10.3.4	Programmable data width, data alignment and endians . . . . .	158
10.3.5	Error management . . . . .	159
10.3.6	Interrupts. . . . .	159
10.3.7	DMA request mapping . . . . .	159
10.4	DMA registers . . . . .	160
10.4.1	DMA interrupt status register (DMA_ISR) . . . . .	160
10.4.2	DMA interrupt flag clear register (DMA_IFCR) . . . . .	161
10.4.3	DMA channel x configuration register (DMA_CCRx) (x = 1..8, where x = channel number) . . . . .	161
10.4.4	DMA channel x number of data register (DMA_CNDTRx) (x = 1..8, where x = channel number). . . . .	163

10.4.5	DMA channel x peripheral address register (DMA_CPARx) (x = 1..8, where x = channel number) . . . . .	163
10.4.6	DMA channel x memory address register (DMA_CMARx) (x = 1..8, where x = channel number) . . . . .	164
10.4.7	DMA register map . . . . .	165
11	DMA request multiplexer (DMAMUX) . . . . .	169
11.1	Introduction . . . . .	169
11.2	DMAMUX main features . . . . .	169
11.3	DMAMUX implementation . . . . .	169
11.3.1	DMAMUX instantiation . . . . .	169
11.3.2	DMAMUX mapping . . . . .	170
11.4	DMAMUX functional description . . . . .	170
11.4.1	DMAMUX block diagram . . . . .	170
11.4.2	DMAMUX channels . . . . .	171
11.4.3	DMAMUX request line multiplexer . . . . .	171
11.5	DMAMUX registers . . . . .	172
11.5.1	DMAMUX request line multiplexer channel x configuration register (DMAMUX_CxCR) . . . . .	172
11.5.2	DMAMUX register map . . . . .	173
12	Analog digital converter (ADC) . . . . .	175
12.1	Features . . . . .	175
12.2	ADC presentation . . . . .	175
12.2.1	Programmable gain amplifier (PGA) . . . . .	176
12.2.2	Temperature sensor subsystem . . . . .	178
12.2.3	Battery sensor . . . . .	178
12.2.4	ADC input mode conversion . . . . .	178
12.2.5	Calibration points . . . . .	179
12.2.6	Steady-state input impedance . . . . .	179
12.2.7	Input signal sampling transient response . . . . .	179
12.2.8	Decimation filter (DF) . . . . .	180
12.2.9	Down sampler (DS) . . . . .	183
12.3	Interrupts . . . . .	183
12.4	DMA interface . . . . .	183
12.5	ADC modes . . . . .	184
12.5.1	Analog audio mode . . . . .	184
12.5.2	ADC mode . . . . .	186
12.5.3	Digital audio mode . . . . .	187
12.5.4	Full mode . . . . .	188
12.5.5	Occasional mode . . . . .	188

12.5.6	Concurrent functions . . . . .	189
12.6	ADC registers . . . . .	190
12.6.1	Version register (VERSION_ID) . . . . .	190
12.6.2	ADC configuration register (CONF) . . . . .	191
12.6.3	ADC control register (CTRL) . . . . .	193
12.6.4	ADC occasional mode control register (OCM_CTRL) . . . . .	194
12.6.5	ADC PGA configuration register (PGA_CONF) . . . . .	195
12.6.6	ADC input voltage switch selection register (SWITCH) . . . . .	196
12.6.7	Decimation filter configuration register (DF_CONF) . . . . .	197
12.6.8	Down sampler configuration register (DS_CONF) . . . . .	199
12.6.9	ADC sequence programming 1 register (SEQ_1) . . . . .	200
12.6.10	ADC sequence programming 2 register (SEQ_2) . . . . .	201
12.6.11	ADC gain and offset correction 1 register (COMP_1) . . . . .	202
12.6.12	ADC gain and offset correction 2 register (COMP_2) . . . . .	203
12.6.13	ADC gain and offset correction 3 register (COMP_3) . . . . .	204
12.6.14	ADC gain and offset correction 4 register (COMP_4) . . . . .	205
12.6.15	ADC gain and offset selection register (COMP_SEL) . . . . .	206
12.6.16	ADC watchdog threshold register (WD_TH) . . . . .	208
12.6.17	ADC watchdog configuration register (WD_CONF) . . . . .	209
12.6.18	Down sampler data out register (DS_DATAOUT) . . . . .	210
12.6.19	Decimation filter data out register (DF_DATAOUT) . . . . .	211
12.6.20	ADC interrupt status register (IRQ_STATUS) . . . . .	212
12.6.21	ADC interrupt enable register (IRQ_ENABLE) . . . . .	214
12.6.22	ADC timers configuration register (TIMER_CONF) . . . . .	215
12.6.23	ADC registers map . . . . .	216
13	Random number generator (RNG) . . . . .	220
13.1	Features . . . . .	220
13.2	RNG registers . . . . .	221
13.2.1	RNG configuration register (RNG_CR) . . . . .	221
13.2.2	RNG status flag register (RNG_SR) . . . . .	221
13.2.3	RNG value register (RNG_VAL) . . . . .	222
13.2.4	RNG register map . . . . .	223
14	Public key accelerator (PKA) . . . . .	224
14.1	Features . . . . .	224
14.2	PKA registers . . . . .	225
14.2.1	PKA command and status register (PKA_CSR) . . . . .	225
14.2.2	PKA interrupt status register (PKA_ISR) . . . . .	226
14.2.3	PKA control register (PKA_IEN) . . . . .	227

14.2.4	PKA register map . . . . .	228
14.3	Programmer model . . . . .	229
14.3.1	Basic sequence. . . . .	229
14.3.2	Data location in PKA_RAM . . . . .	229
15	Cyclic redundancy check calculation unit (CRC) . . . . .	230
15.1	Introduction . . . . .	230
15.2	CRC main features . . . . .	230
15.3	CRC functional description. . . . .	230
15.3.1	CRC block diagram. . . . .	230
15.3.2	CRC operation . . . . .	230
15.4	CRC registers . . . . .	232
15.4.1	Data register (CRC_DR) . . . . .	232
15.4.2	Independent data register (CRC_IDR) . . . . .	232
15.4.3	Control register (CRC_CR) . . . . .	233
15.4.4	Initial CRC value (CRC_INIT) . . . . .	234
15.4.5	CRC polynomial (CRC_POL) . . . . .	234
15.4.6	CRC register map . . . . .	235
16	Advanced-control timers (TIM1) . . . . .	236
16.1	TIM1 introduction. . . . .	236
16.2	TIM1 main features . . . . .	236
16.3	TIM1 functional description . . . . .	238
16.3.1	Time-base unit . . . . .	238
16.3.2	Counter modes . . . . .	239
16.3.3	Repetition counter. . . . .	247
16.3.4	External trigger input. . . . .	248
16.3.5	Clock selection . . . . .	249
16.3.6	Capture/compare channels . . . . .	251
16.3.7	Input capture mode . . . . .	253
16.3.8	PWM input mode . . . . .	254
16.3.9	Forced output mode . . . . .	254
16.3.10	Output compare mode . . . . .	255
16.3.11	PWM mode . . . . .	255
16.3.12	Asymmetric PWM mode . . . . .	258
16.3.13	Combined PWM mode . . . . .	258
16.3.14	Combined 3-phase PWM mode . . . . .	259
16.3.15	Complementary outputs and deadtime insertion . . . . .	260
16.3.16	Using the break function . . . . .	261

16.3.17	Clearing the OCxREF signal on an external event . . . . .	264
16.3.18	One-pulse mode . . . . .	266
16.3.19	Retriggerable one-pulse mode (OPM). . . . .	268
16.3.20	Encoder interface mode . . . . .	268
16.3.21	UIF bit remapping . . . . .	270
16.3.22	Timer input XOR function . . . . .	270
16.4	TIM1 registers . . . . .	272
16.4.1	TIM1 control register 1 (TIMx_CR1) . . . . .	272
16.4.2	TIM1 control register 2 (TIMx_CR2) . . . . .	274
16.4.3	TIM1 slave mode control register (TIMx_SMCR). . . . .	275
16.4.4	TIM1 interrupt enable register (TIMx_DIER) . . . . .	278
16.4.5	TIM1 status register (TIMx_SR) . . . . .	279
16.4.6	TIM1 event generation register (TIMx_EGR). . . . .	281
16.4.7	TIM1 capture/compare mode register 1 (TIMx_CCMR1). . . . .	282
16.4.8	TIM1 capture/compare mode register 2 (TIMx_CCMR2). . . . .	286
16.4.9	TIM1 capture/compare enable register (TIMx_CCER). . . . .	288
16.4.10	TIM1 counter (TIMx_CNT) . . . . .	291
16.4.11	TIM1 prescaler (TIMx_PSC) . . . . .	292
16.4.12	TIM1 auto-reload register (TIMx_ARR) . . . . .	293
16.4.13	TIM1 repetition counter register (TIMx_RCR) . . . . .	294
16.4.14	TIM1 capture/compare register 1 (TIMx_CCR1) . . . . .	295
16.4.15	TIM1 capture/compare register 2 (TIMx_CCR2) . . . . .	296
16.4.16	TIM1 capture/compare register 3 (TIMx_CCR3) . . . . .	297
16.4.17	TIM1 capture/compare register 4 (TIMx_CCR4) . . . . .	298
16.4.18	TIM1 break and deadtime register (TIMx_BDTR) . . . . .	299
16.4.19	TIM1 capture/compare mode register 3 (TIMx_CCMR3). . . . .	303
16.4.20	TIM1 capture/compare register 5 (TIMx_CCR5) . . . . .	304
16.4.21	TIM1 capture/compare register 6 (TIMx_CCR6) . . . . .	305
16.4.22	TIM1 alternate function option register 1 (TIMx_AF1) . . . . .	306
16.4.23	TIM1 alternate function option register 2 (TIMx_AF2) . . . . .	308
16.4.24	TIM1 register map. . . . .	310
17	Real-time clock (RTC). . . . .	315
17.1	Introduction . . . . .	315
17.2	RTC main features . . . . .	315
17.3	RTC functional description. . . . .	316
17.3.1	RTC block diagram . . . . .	316
17.3.2	Clock and prescalers. . . . .	316
17.3.3	Real-time clock and calendar . . . . .	317

17.3.4	Programmable alarm. . . . .	317
17.3.5	Periodic auto-wakeup . . . . .	317
17.3.6	RTC initialization and configuration. . . . .	318
17.3.7	Reading the calendar . . . . .	319
17.3.8	Resetting the RTC. . . . .	319
17.3.9	RTC synchronization. . . . .	319
17.3.10	RTC smooth digital calibration. . . . .	320
17.3.11	Calibration clock output. . . . .	321
17.3.12	Alarm output . . . . .	322
17.4	RTC low-power modes . . . . .	322
17.5	RTC interrupts . . . . .	322
17.6	RTC registers. . . . .	323
17.6.1	RTC time register (RTC_TR). . . . .	323
17.6.2	RTC date register (RTC_DR) . . . . .	324
17.6.3	RTC control register (RTC_CR) . . . . .	325
17.6.4	RTC initialization and status register (RTC_ISR). . . . .	327
17.6.5	RTC prescaler register (RTC_PRER) . . . . .	329
17.6.6	RTC wakeup timer register (RTC_WUTR). . . . .	330
17.6.7	RTC alarm A register (RTC_ALRMAR) . . . . .	331
17.6.8	RTC write protection register (RTC_WPR) . . . . .	332
17.6.9	RTC sub-second register (RTC_SSR). . . . .	333
17.6.10	RTC shift control register (RTC_SHIFTR) . . . . .	334
17.6.11	RTC calibration register (RTC_CALR). . . . .	335
17.6.12	RTC alarm A sub second register (RTC_ALRMASSR) . . . . .	336
17.6.13	RTC backup registers (RTC_BKPxR) . . . . .	337
17.6.14	RTC register map . . . . .	338
18	Independent watchdog (IWDG). . . . .	341
18.1	Introduction . . . . .	341
18.2	IWDG main features . . . . .	341
18.3	IWDG functional description . . . . .	341
18.3.1	Window option . . . . .	341
18.3.2	Register access protection . . . . .	342
18.3.3	Debug mode . . . . .	342
18.4	IWDG registers . . . . .	343
18.4.1	Key register (IWDG_KR). . . . .	343
18.4.2	Prescaler register (IWDG_PR) . . . . .	344
18.4.3	Reload register (IWDG_RLR) . . . . .	345
18.4.4	Status register (IWDG_SR). . . . .	346

18.4.5	Window register (IWDG_WINR) . . . . .	347
18.4.6	IWDG register map . . . . .	348
19	Inter-integrated circuit (I ²C) interface . . . . .	349
19.1	Introduction . . . . .	349
19.2	I ²C main features . . . . .	349
19.3	I ²C implementation . . . . .	350
19.4	I ²C functional description . . . . .	350
19.4.1	I ²C block diagram . . . . .	350
19.4.2	I ²C clock requirements . . . . .	351
19.4.3	Mode selection . . . . .	351
19.4.4	I ²C initialization . . . . .	352
19.4.5	Software reset . . . . .	355
19.4.6	Data transfer . . . . .	356
19.4.7	I ²C target mode . . . . .	357
19.4.8	I ²C controller mode . . . . .	362
19.4.9	I ²C_TIMINGR register configuration examples . . . . .	372
19.4.10	SMBus specific features . . . . .	373
19.4.11	SMBus initialization . . . . .	375
19.4.12	SMBus: I ²C_TIMEOUTR register configuration examples . . . . .	376
19.4.13	SMBus target mode . . . . .	377
19.4.14	Error conditions . . . . .	382
19.4.15	DMA requests . . . . .	383
19.5	I ²C interrupts . . . . .	384
19.6	I ²C registers . . . . .	386
19.6.1	Control register 1 (I ²C_CR1) . . . . .	386
19.6.2	Control register 2 (I ²C_CR2) . . . . .	388
19.6.3	Own address 1 register (I ²C_OAR1) . . . . .	391
19.6.4	Own address 2 register (I ²C_OAR2) . . . . .	392
19.6.5	Timing register (I ²C_TIMINGR) . . . . .	393
19.6.6	Timeout register (I ²C_TIMEOUTR) . . . . .	394
19.6.7	Interrupt and status register (I ²C_ISR) . . . . .	395
19.6.8	Interrupt clear register (I ²C_ICR) . . . . .	397
19.6.9	PEC register (I ²C_PECR) . . . . .	398
19.6.10	Receive data register (I ²C_RXDR) . . . . .	399
19.6.11	Transmit data register (I ²C_TXDR) . . . . .	400
19.6.12	I ²C register map . . . . .	401
20	Universal synchronous asynchronous receiver transmitter (USART) . . . . .	404

20.1	USART introduction .....	404
20.2	USART main features .....	404
20.3	USART extended features .....	405
20.4	USART implementation .....	405
20.5	USART functional description .....	406
20.5.1	USART character description .....	407
20.5.2	FIFOs and thresholds .....	408
20.5.3	Transmitter .....	409
20.5.4	Receiver .....	411
20.5.5	Baud rate generation. ....	416
20.5.6	Tolerance of the USART receiver to clock deviation .....	417
20.5.7	Auto baud rate detection .....	418
20.5.8	Multiprocessor communication .....	418
20.5.9	Modbus communication .....	420
20.5.10	Parity control .....	420
20.5.11	LIN (local interconnection network) mode .....	421
20.5.12	USART synchronous mode .....	423
20.5.13	Single-wire half-duplex communication .....	426
20.5.14	Receiver timeout .....	426
20.5.15	Smartcard mode .....	427
20.5.16	IrDA SIR ENDEC block .....	430
20.5.17	Continuous communication using DMA .....	432
20.5.18	RS232 hardware flow control and RS485 driver enable .....	434
20.6	USART interrupts .....	436
20.7	USART registers .....	437
20.7.1	Control register 1 (USARTx_CR1) .....	437
20.7.2	Control register 2 (USARTx_CR2) .....	441
20.7.3	Control register 3 (USARTx_CR3) .....	445
20.7.4	Baud rate register (USARTx_BRR) .....	449
20.7.5	Guard Time and prescaler register (USARTx_GTPR) .....	450
20.7.6	Receiver timeout register (USARTx_RTOR) .....	451
20.7.7	Request register (USARTx_RQR) .....	452
20.7.8	Interrupt and status register (USARTx_ISR) .....	453
20.7.9	Interrupt flag clear register (USART_ICR) .....	458
20.7.10	Receive data register (USART_RDR) .....	460
20.7.11	Transmit data register (USART_TDR) .....	461
20.7.12	Prescaler register (USARTx_PRESC) .....	462
20.7.13	USART register map .....	463

21	Universal Asynchronous Receiver Transmitter (LPUART) .....	466
21.1	LPUART introduction .....	466
21.2	LPUART main features. ....	466
21.3	LPUART functional description .....	466
21.3.1	LPUART character description .....	468
21.3.2	FIFOs and thresholds .....	469
21.3.3	Transmitter .....	470
21.3.4	Receiver .....	472
21.3.5	Baud rate generation. ....	475
21.3.6	Multiprocessor communication .....	475
21.3.7	Parity control .....	477
21.3.8	Single-wire half-duplex communication .....	477
21.3.9	Continuous communication using DMA. ....	478
21.3.10	RS232 Hardware flow control and RS485 Driver Enable. ....	480
21.4	LPUART interrupts .....	482
21.5	LPUART registers .....	483
21.5.1	Control register 1 (LPUART_CR1) .....	483
21.5.2	Control register 2 (LPUART_CR2) .....	486
21.5.3	Control register 3 (LPUART_CR3) .....	488
21.5.4	Baud rate register (LPUART_BRR). ....	491
21.5.5	Request register (LPUART_RQR). ....	492
21.5.6	Interrupt and status register (LPUART_ISR). ....	493
21.5.7	Interrupt flag clear register (LPUART_ICR). ....	497
21.5.8	Receive data register (LPUART_RDR) .....	498
21.5.9	Transmit data register (LPUART_TDR). ....	499
21.5.10	Prescaler register (LPUART_PRESC). ....	500
21.5.11	LPUART register map. ....	501
22	Serial peripheral interface / inter-IC sound (SPI/I2S) .....	503
22.1	Introduction .....	503
22.2	SPI main features .....	503
22.3	I2S main features .....	503
22.4	SPI/I2S implementation .....	504
22.5	SPI functional description. ....	504
22.5.1	General description. ....	504
22.5.2	Communications between one master and one slave .....	505
22.5.3	Standard multi-slave communication. ....	507
22.5.4	Slave select (NSS) pin management. ....	508

22.5.5	Communication formats . . . . .	509
22.5.6	Configuration of SPI . . . . .	511
22.5.7	Procedure to enable SPI . . . . .	512
22.5.8	Data transmission and reception procedures . . . . .	512
22.5.9	SPI status flags . . . . .	519
22.5.10	SPI error flags . . . . .	520
22.5.11	NSS pulse mode . . . . .	521
22.5.12	TI mode . . . . .	521
22.5.13	CRC calculation . . . . .	522
22.6	SPI interrupts . . . . .	523
22.7	I2S functional description . . . . .	523
22.7.1	I2S general description . . . . .	523
22.7.2	Supported audio protocols . . . . .	525
22.7.3	Clock generator . . . . .	530
22.7.4	I2S master mode . . . . .	533
22.7.5	I2S slave mode . . . . .	535
22.7.6	I2S error flags . . . . .	536
22.7.7	DMA features . . . . .	536
22.8	I2S interrupts . . . . .	536
22.9	SPI and I ²S registers . . . . .	537
22.9.1	SPI control register 1 (SPIx_CR1) . . . . .	537
22.9.2	SPI control register 2 (SPIx_CR2) . . . . .	539
22.9.3	SPI status register (SPIx_SR) . . . . .	541
22.9.4	SPI data register (SPIx_DR) . . . . .	542
22.9.5	SPI CRC polynomial register (SPIx_CRCPR) . . . . .	543
22.9.6	SPI Rx CRC register (SPIx_RXCRCR) . . . . .	543
22.9.7	SPI Tx CRC register (SPIx_TXCRCR) . . . . .	543
22.9.8	SPIx_I2S configuration register (SPIx_I2SCFGR) . . . . .	544
22.9.9	SPIx_I2S prescaler register (SPIx_I2SPR) . . . . .	545
22.9.10	SPI/I2S register map . . . . .	547
23	Radio IP . . . . .	549
23.1	Introduction . . . . .	549
23.2	Functional description . . . . .	549
23.3	Radio resource manager (RRM) . . . . .	550
23.3.1	UDRA . . . . .	550
23.3.2	Direct register access . . . . .	553
23.3.3	RRM registers . . . . .	553

23.4	Radio FSM . . . . .	573
23.4.1	Radio FSM sequences . . . . .	574
23.4.2	Radio FSM interrupts . . . . .	574
23.5	Radio controller . . . . .	574
23.5.1	Slow clock measurement . . . . .	574
23.5.2	Radio FSM interrupt management . . . . .	574
23.5.3	Radio controller registers . . . . .	575
23.6	Bluetooth LE controller sequence . . . . .	576
23.6.1	Timers . . . . .	576
23.6.2	Bluetooth LE sequence description . . . . .	577
23.6.3	Bluetooth LE sequence summary . . . . .	580
23.6.4	TX and RX sequence signals . . . . .	581
23.6.5	Bluetooth LE controller registers . . . . .	582
23.7	Bluetooth LE RAM tables . . . . .	592
23.7.1	GlobalStatMach RAM table . . . . .	592
23.7.2	StatMach RAM table . . . . .	598
23.7.3	TxRxPack RAM table . . . . .	607
23.8	Wakeup block . . . . .	611
23.8.1	Absolute time . . . . .	611
23.8.2	Interpolated time . . . . .	611
23.8.3	Sleep request and wakeup management . . . . .	611
23.8.4	Wakeup block registers . . . . .	612
24	Debug support (DBG) . . . . .	616
24.1	SWD debug features . . . . .	616
25	Device electronic signature (DESIG) . . . . .	617
25.1	DESIG registers . . . . .	617
25.1.1	DESIG ADC trimming max diff (DESIG_ADCMAXDIFF) . . . . .	617
25.1.2	DESIG ADC trimming max negative (DESIG_ADCMAXNEG) . . . . .	618
25.1.3	DESIG ADC trimming max positive (DESIG_ADCMAXPOS) . . . . .	619
25.1.4	DESIG ADC trimming mean diff (DESIG_ADCMEANDIFF) . . . . .	620
25.1.5	DESIG ADC trimming mean negative (DESIG_ADCMEANNEG) . . . . .	621
25.1.6	DESIG ADC trimming max positive (DESIG_ADCMEANPOS) . . . . .	622
25.1.7	DESIG ADC trimming min diff (DESIG_ADCMINDIFF) . . . . .	623
25.1.8	DESIG ADC trimming min negative (DESIG_ADCMINNEG) . . . . .	624
25.1.9	DESIG ADC trimming min positive (DESIG_ADCMINPOS) . . . . .	625
25.1.10	DESIG reference temperature register (DESIG_TSREFR) . . . . .	626
25.1.11	DESIG temperature calibration register (DESIG_TSCAL1R) . . . . .	627

25.1.12	DESIG package data register (DESIG_PKGR) . . . . .	628
25.1.13	DESIG 64-bit unique device identifier register 1 (DESIG_UID64R1) . . . . .	629
25.1.14	DESIG 64-bit unique device identifier register 2 (DESIG_UID64R2) . . . . .	630
25.1.15	DESIG register map . . . . .	631
	Important security notice . . . . .	633
	Revision history . . . . .	634

List of tables

Table 1.	List of abbreviations for registers . . . . .	2
Table 2.	Acronyms . . . . .	4
Table 3.	STM32WB07xC and STM32WB06xC memory map and peripheral register boundary addresses . . . . .	11
Table 4.	SRAM0 reserved locations . . . . .	12
Table 5.	Address remapping depending on REMAP bit . . . . .	12
Table 6.	Interrupt vectors. . . . .	14
Table 7.	GPIO alternate options AF0 - AF2 . . . . .	19
Table 8.	GPIO alternate options AF3 - AF4 . . . . .	21
Table 9.	I/O analog feature mapping . . . . .	23
Table 10.	SMPS BOM information . . . . .	32
Table 11.	PWRC register map . . . . .	63
Table 12.	Flags versus CPU reboot reason . . . . .	66
Table 13.	Wakeup reason flags . . . . .	66
Table 14.	CPU versus MR_BLE clock dependency. . . . .	72
Table 15.	RCC register map and reset values . . . . .	99
Table 16.	Port bit configuration . . . . .	107
Table 17.	GPIO register map and reset values. . . . .	119
Table 18.	SYSCFG register map and reset values . . . . .	137
Table 19.	Flash memory section address . . . . .	140
Table 20.	Flash APB registers . . . . .	141
Table 21.	Command list available for customer . . . . .	142
Table 22.	Flash size information. . . . .	147
Table 23.	System memory protection . . . . .	154
Table 24.	Programmable data width and endian behavior (when PINC=MINC=1 and NDT=4) . . . . .	158
Table 25.	DMA interrupt requests. . . . .	159
Table 26.	DMA register map and reset values . . . . .	165
Table 27.	DMAMUX instantiation . . . . .	169
Table 28.	DMAMUX map . . . . .	170
Table 29.	DMAMUX register map and reset values. . . . .	173
Table 30.	PGA parameters . . . . .	177
Table 31.	Calibration points. . . . .	179
Table 32.	Output data rate with ADC input at 1 MHz for analog mode . . . . .	181
Table 33.	CIC filter output frequency with digital microphone input . . . . .	181
Table 34.	Minimum decimation factor for the CIC / total versus pdm_rate . . . . .	182
Table 35.	ADC interrupt requests . . . . .	183
Table 36.	ADC mode summary . . . . .	184
Table 37.	ADC register map and reset values . . . . .	216
Table 38.	RNG register list . . . . .	223
Table 39.	PKA register map. . . . .	228
Table 40.	ECC scalar multiplication data location . . . . .	229
Table 41.	CRC register map and reset values . . . . .	235
Table 42.	Behavior of timer outputs versus BRK/BK2inputs . . . . .	264
Table 43.	Counting direction versus encodersignals . . . . .	269
Table 44.	Output control bits for complementary OCx and OCxN channels with break feature . . . . .	290
Table 45.	TIM1 register map and reset values . . . . .	310
Table 46.	RTC register map and reset values . . . . .	338
Table 47.	IWDG register map . . . . .	348
Table 48.	STM32WB07xC and STM32WB06xC I ²C implementation . . . . .	350
Table 49.	I ²C-SMBUS specification data setup and hold times . . . . .	354
Table 50.	I ²C configurable table . . . . .	357
Table 51.	I ²C-SMBUS specification clock timings . . . . .	364
Table 52.	Examples of timings settings for f _I2CCLK= 16 MHz . . . . .	372

Table 53.	SMBus timeout specifications . . . . .	374
Table 54.	SMBUS with PEC configuration . . . . .	376
Table 55.	Examples of TIMEOUTA settings (max. $t_{TIMEOUT} = 25$ ms) . . . . .	376
Table 56.	Example of TIMEOUTB settings. . . . .	377
Table 57.	Examples of TIMEOUTA settings (max. $t_{IDLE} = 50$ $\mu$ s) . . . . .	377
Table 58.	I ²C interrupt requests . . . . .	384
Table 59.	I ²C register map . . . . .	401
Table 60.	USART/LPUART features . . . . .	405
Table 61.	Noise detection from sampled data . . . . .	415
Table 62.	Tolerance of the USART receiver when BRR [3:0] = 0000 (high-density devices) . . . . .	417
Table 63.	Tolerance of the USART receiver when BRR[3:0] is different from 0000 (high-density devices) . . . . .	417
Table 64.	Frame formats. . . . .	420
Table 65.	USART interrupt requests . . . . .	436
Table 66.	USART register map . . . . .	463
Table 67.	Frame formats. . . . .	477
Table 68.	LPUART interrupt requests . . . . .	482
Table 69.	LPUART register map and reset values . . . . .	501
Table 70.	STM32WB07xC and STM32WB06xC SPI implementation. . . . .	504
Table 71.	SPI interrupts requests . . . . .	523
Table 72.	Audio frequency precision using I2SCLK = 32 MHz . . . . .	532
Table 73.	Audio frequency precision using I2SCLK = 16 MHz . . . . .	533
Table 74.	I ²S interrupt request. . . . .	536
Table 75.	Command start list details . . . . .	551
Table 76.	UDRA command format in RAM. . . . .	551
Table 77.	RRM register list . . . . .	553
Table 78.	RRM_ID register description . . . . .	555
Table 79.	RRM_CTRL register description. . . . .	555
Table 80.	UDRA_CTRL0 register description. . . . .	555
Table 81.	UDRA_IRQ_ENABLE register description. . . . .	556
Table 82.	UDRA_IRQ_STATUS register description . . . . .	556
Table 83.	UDRA_RADIO_CFG_PTR register description . . . . .	556
Table 84.	SEMA_IRQ_ENABLE register description. . . . .	556
Table 85.	SEMA_IRQ_STATUS register description . . . . .	556
Table 86.	BLE_IRQ_ENABLE register description . . . . .	557
Table 87.	BLE_IRQ_STATUS register description. . . . .	557
Table 88.	VP_CPU_CMD_BUS register description . . . . .	558
Table 89.	VP_CPU_SEMA_BUS register description . . . . .	558
Table 90.	VP_CPU_IRQ_ENABLE register description . . . . .	558
Table 91.	VP_CPU_IRQ_STATUS register description . . . . .	559
Table 92.	AA0_DIG_USR register description . . . . .	559
Table 93.	AA1_DIG_USR register description . . . . .	560
Table 94.	AA2_DIG_USR register description . . . . .	560
Table 95.	AA3_DIG_USR register description . . . . .	560
Table 96.	DEM_MOD_DIG_USR register description . . . . .	560
Table 97.	RADIO_FSM_USR register description. . . . .	561
Table 98.	PHYCTRL_DIG_USR register description. . . . .	561
Table 99.	AFC0_DIG_ENG register description . . . . .	561
Table 100.	AFC1_DIG_ENG register description . . . . .	562
Table 101.	AFC2_DIG_ENG register description . . . . .	562
Table 102.	AFC3_DIG_ENG register description . . . . .	562
Table 103.	CR0_DIG_ENG register description . . . . .	562
Table 104.	CR0_LR register description . . . . .	562
Table 105.	VIT_CONF_DIG_ENG register description . . . . .	562
Table 106.	LR_PD_THR_DIG_ENG register description . . . . .	563
Table 107.	LR_RSSI_THR_DIG_ENG register description . . . . .	563

Table 108.	LR_AAC_THR_DIG_ENG register description . . . . .	563
Table 109.	DTB0_DIG_ENG register description . . . . .	563
Table 110.	DTB5_DIG_ENG register description . . . . .	563
Table 111.	MOD0_DIG_TST register description . . . . .	564
Table 112.	MOD1_DIG_TST register description . . . . .	564
Table 113.	MOD2_DIG_TST register description . . . . .	564
Table 114.	MOD3_DIG_TST register description . . . . .	564
Table 115.	RXADC_ANA_USR register description . . . . .	564
Table 116.	LDO_ANA_ENG register description . . . . .	565
Table 117.	CBIAS0_ANA_ENG register description . . . . .	565
Table 118.	CBIAS1_ANA_ENG register description . . . . .	565
Table 119.	CBIAS_ANA_TEST register description . . . . .	566
Table 120.	SYNTHCAL0_DIG_OUT register description . . . . .	566
Table 121.	SYNTHCAL1_DIG_OUT register description . . . . .	566
Table 122.	SYNTHCAL2_DIG_OUT register description . . . . .	566
Table 123.	SYNTHCAL3_DIG_OUT register description . . . . .	567
Table 124.	SYNTHCAL4_DIG_OUT register description . . . . .	567
Table 125.	. SYNTHCAL5_DIG_OUT register description . . . . .	567
Table 126.	FSM_STATUS_DIG_OUT register description . . . . .	568
Table 127.	IRQ_STATUS_DIG_OUT register description . . . . .	568
Table 128.	RSSI0_DIG_OUT register description . . . . .	568
Table 129.	RSSI1_DIG_OUT register description . . . . .	568
Table 130.	AGC_DIG_OUT register description . . . . .	569
Table 131.	DEMOD_DIG_OUT register description . . . . .	569
Table 132.	AGC0_ANA_TST register . . . . .	569
Table 133.	AGC1_ANA_TST register description . . . . .	569
Table 134.	AGC2_ANA_TST register description . . . . .	570
Table 135.	AGC0_DIG_ENG register description . . . . .	570
Table 136.	AGC1_DIG_ENG register description . . . . .	570
Table 137.	AGC2_DIG_ENG register description . . . . .	570
Table 138.	AGC3_DIG_ENG register description . . . . .	570
Table 139.	AGC4_DIG_ENG register description . . . . .	570
Table 140.	AGC5_DIG_ENG register description . . . . .	571
Table 141.	AGC6_DIG_ENG register description . . . . .	571
Table 142.	AGC7_DIG_ENG register description . . . . .	571
Table 143.	AGC8_DIG_ENG register description . . . . .	571
Table 144.	AGC9_DIG_ENG register description . . . . .	571
Table 145.	AGC10_DIG_ENG register description . . . . .	571
Table 146.	AGC11_DIG_ENG register description . . . . .	571
Table 147.	AGC12_DIG_ENG register description . . . . .	572
Table 148.	AGC13_DIG_ENG register description . . . . .	572
Table 149.	AGC14_DIG_ENG register description . . . . .	572
Table 150.	AGC15_DIG_ENG register description . . . . .	572
Table 151.	AGC16_DIG_ENG register description . . . . .	572
Table 152.	AGC17_DIG_ENG register description . . . . .	572
Table 153.	AGC18_DIG_ENG register description . . . . .	572
Table 154.	AGC19_DIG_ENG register description . . . . .	573
Table 155.	AGC20_DIG_ENG register description . . . . .	573
Table 156.	RXADC_HW_TRIM_OUT register description . . . . .	573
Table 157.	CBIAS0_HW_TRIM_OUT register description . . . . .	573
Table 158.	CBIAS1_HW_TRIM_OUT register description . . . . .	573
Table 159.	AGC_HW_TRIM_OUT register description . . . . .	573
Table 160.	Radio Controller registers list . . . . .	575
Table 161.	RADIO_CONTROL_ID register description . . . . .	575
Table 162.	CLK32COUNT_REG register description . . . . .	575

Table 163.	CLK32PERIOD_REG register description . . . . .	575
Table 164.	CLK32FREQUENCY_REG register description . . . . .	575
Table 165.	RADIO_CONTROL_IRQ_STATUS register description . . . . .	576
Table 166.	RADIO_CONTROL_IRQ_ENABLE register description . . . . .	576
Table 167.	Bluetooth LE controller register list . . . . .	582
Table 168.	INTERRUPT 1REG register description . . . . .	583
Table 169.	INTERRUPT2REG register description . . . . .	585
Table 170.	TIMEOUTDESTREG register description . . . . .	585
Table 171.	TIMEOUTREG register description . . . . .	585
Table 172.	TIMERCAPTUREREG register description . . . . .	585
Table 173.	CMDREG register description . . . . .	585
Table 174.	STATUSREG register description . . . . .	586
Table 175.	INTERRUPT1ENABLEREG register description . . . . .	588
Table 176.	INTERRUPT1LATENCYREG register description . . . . .	588
Table 177.	MANAESKEY0REG register description . . . . .	589
Table 178.	MANAESKEY1REG register description . . . . .	589
Table 179.	MANAESKEY2REG register description . . . . .	589
Table 180.	MANAESKEY3REG register description . . . . .	589
Table 181.	MANAESCLEARTEXT0REG register description . . . . .	589
Table 182.	MANAESCLEARTEXT1REG register description . . . . .	589
Table 183.	MANAESCLEARTEXT2REG register description . . . . .	589
Table 184.	MANAESCLEARTEXT3REG register description . . . . .	589
Table 185.	MANAESCHIPHERTEXT0REG register description . . . . .	589
Table 186.	MANAESCHIPHERTEXT1REG register description . . . . .	589
Table 187.	MANAESCHIPHERTEXT2REG register description . . . . .	590
Table 188.	MANAESCHIPHERTEXT3REG register description . . . . .	590
Table 189.	MANAESCMDREG register description . . . . .	590
Table 190.	MANAESSTATREG register description . . . . .	590
Table 191.	AESLEPRIVPOINTERREG register description . . . . .	590
Table 192.	AESLEPRIVHASHREG register description . . . . .	590
Table 193.	AESLEPRIVCMDREG register description . . . . .	590
Table 194.	AESLEPRIVSTATREG register description . . . . .	591
Table 195.	DEBUGCMDREG register description . . . . .	591
Table 196.	DEBUGSTATUSREG register description . . . . .	591
Table 197.	GlobalStatMach . . . . .	593
Table 198.	GlobalStatMach.WORD0 register description . . . . .	593
Table 199.	GlobalStatMach.WORD1 register description . . . . .	594
Table 200.	GlobalStatMach.WORD2 register description . . . . .	595
Table 201.	GlobalStatMach.WORD3 register description . . . . .	596
Table 202.	GlobalStatMach.WORD4 register description . . . . .	596
Table 203.	GlobalStatMach.WORD5 register description . . . . .	597
Table 204.	GlobalStatMach.WORD6 register description . . . . .	598
Table 205.	StatMach . . . . .	598
Table 206.	StatMach.WORD0 register description . . . . .	599
Table 207.	StatMach.WORD1 register description . . . . .	600
Table 208.	StatMach.WORD2 register description . . . . .	601
Table 209.	StatMach.WORD3 register description . . . . .	601
Table 210.	StatMach.WORD4 register description . . . . .	601
Table 211.	StatMach.WORD5 register description . . . . .	601
Table 212.	StatMach.WORD6 register description . . . . .	601
Table 213.	StatMach.WORD7 register description . . . . .	602
Table 214.	StatMach.WORD8 register description . . . . .	602
Table 215.	StatMach.WORD9 register description . . . . .	603
Table 216.	StatMach.WORDA register description . . . . .	604
Table 217.	StatMach.WORDB register description . . . . .	604

Table 218.	StatMach.WORDC register description . . . . .	604
Table 219.	StatMach.WORDD register description . . . . .	605
Table 220.	StatMach.WORDE register description . . . . .	605
Table 221.	StatMach.WORDF register description . . . . .	605
Table 222.	StatMach.WORD10 register description . . . . .	605
Table 223.	StatMach.WORD11 register description . . . . .	605
Table 224.	StatMach.WORD12 register description . . . . .	605
Table 225.	StatMach.WORD13 register description . . . . .	606
Table 226.	StatMach.PaPower values . . . . .	607
Table 227.	TxRxPack . . . . .	607
Table 228.	TxRxPack.WORD0 register description. . . . .	607
Table 229.	TxRxPack.WORD1 register description. . . . .	608
Table 230.	TxRxPack.WORD2 register description. . . . .	609
Table 231.	TxRxPack.WORD3 register description. . . . .	609
Table 232.	TxRxPack.WORD4 register description. . . . .	610
Table 233.	Wakeup block register list . . . . .	612
Table 234.	WAKEUP_OFFSET register description . . . . .	613
Table 235.	ABSOLUTE_TIME register description . . . . .	613
Table 236.	MINIMUM_PERIOD_LENGTH register description. . . . .	613
Table 237.	AVERAGE_PERIOD_LENGTH register description . . . . .	613
Table 238.	MAXIMUM_PERIOD_LENGTH register description . . . . .	613
Table 239.	STATISTIC_RESTART register description . . . . .	614
Table 240.	BLUE_WAKEUP_TIME register description. . . . .	614
Table 241.	BLUE_SLEEP_REQUEST_MODE register description . . . . .	614
Table 242.	CM0_WAKEUP_TIME register description . . . . .	614
Table 243.	CM0_SLEEP_REQUEST_MODE register description. . . . .	614
Table 244.	WAKEUP_BLE_IRQ_ENABLE register description. . . . .	615
Table 245.	WAKEUP_BLE_IRQ_STATUS register description . . . . .	615
Table 246.	WAKEUP_CM0_IRQ_ENABLE register description . . . . .	615
Table 247.	WAKEUP_CM0_IRQ_STATUS register description . . . . .	615
Table 248.	PWRC register map . . . . .	631
Table 249.	Document revision history . . . . .	634

List of figures

Figure 1.	STM32WB07xC and STM32WB06xC system architecture . . . . .	8
Figure 2.	Memory map . . . . .	10
Figure 3.	AHB up/down converter . . . . .	16
Figure 4.	Power supply domain overview . . . . .	25
Figure 5.	Power-on reset/power-down reset waveform . . . . .	25
Figure 6.	Power regulators and SMPS configuration in Run mode . . . . .	27
Figure 7.	Power regulators and SMPS configuration in Deepstop mode . . . . .	29
Figure 8.	Power regulators and SMPS configuration in Shutdown mode . . . . .	30
Figure 9.	PWRC state machine for operating modes transition . . . . .	31
Figure 10.	Power supply configuration . . . . .	32
Figure 11.	PWRC SMPS state machine overview . . . . .	32
Figure 12.	Reset generation . . . . .	68
Figure 13.	Peripheral clock tree overview . . . . .	71
Figure 14.	RCC_LCO / RCC_MCO output clocks . . . . .	74
Figure 15.	Basic structure of a mixed analog/digital five-volt tolerant I/O port bit . . . . .	106
Figure 16.	Basic structure of a digital only five-volt tolerant I/O port bit . . . . .	106
Figure 17.	Input floating/pull-up/pull-down configurations . . . . .	110
Figure 18.	Output configuration . . . . .	110
Figure 19.	Alternate function configuration . . . . .	111
Figure 20.	High impedance-analog configuration . . . . .	112
Figure 21.	DMAMUX block diagram . . . . .	170
Figure 22.	ADC top level diagram . . . . .	176
Figure 23.	Microphone setup . . . . .	177
Figure 24.	ADC sampling time T _swand sampling period T _s. . . . .	180
Figure 25.	Effect of analog source resistance . . . . .	180
Figure 26.	Simplified decimation filter block diagram . . . . .	181
Figure 27.	CRC calculation unit block diagram . . . . .	230
Figure 28.	Advanced-control timer block diagram . . . . .	237
Figure 29.	Counter timing diagram with prescaler division change from 1 to 2 . . . . .	238
Figure 30.	Counter timing diagram with prescaler division change from 1 to 4 . . . . .	239
Figure 31.	Counter timing diagram, internal clock divided by 1 . . . . .	240
Figure 32.	Counter timing diagram, internal clock divided by 2 . . . . .	240
Figure 33.	Counter timing diagram, internal clock divided by 4 . . . . .	240
Figure 34.	Counter timing diagram, internal clock divided by N . . . . .	241
Figure 35.	Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .	241
Figure 36.	Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .	242
Figure 37.	Counter timing diagram, internal clock divided by 1 . . . . .	243
Figure 38.	Counter timing diagram, internal clock divided by 2 . . . . .	243
Figure 39.	Counter timing diagram, internal clock divided by 4 . . . . .	243
Figure 40.	Counter timing diagram, internal clock divided by N . . . . .	244
Figure 41.	Counter timing diagram, update event when repetition counter is not used . . . . .	244
Figure 42.	Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .	245
Figure 43.	Counter timing diagram, internal clock divided by 2 . . . . .	245
Figure 44.	Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .	246
Figure 45.	Counter timing diagram, internal clock divided by N . . . . .	246
Figure 46.	Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .	246
Figure 47.	Counter timing diagram, update event with ARPE=1 (counter overflow) . . . . .	247
Figure 48.	Update rate examples depending on mode and TIMx_RCR register settings . . . . .	248
Figure 49.	External trigger input block . . . . .	248
Figure 50.	Control circuit in normal mode, internal clock divided by 1 . . . . .	249
Figure 51.	TI2 external clock connection example . . . . .	249
Figure 52.	Control circuit in external clock mode 1 . . . . .	250
Figure 53.	External trigger input block . . . . .	250

Figure 54.	Control circuit in external clock mode 2 . . . . .	251
Figure 55.	Capture/compare channel (example: channel 1 input stage) . . . . .	251
Figure 56.	Capture/compare channel 1 main circuit . . . . .	252
Figure 57.	Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .	252
Figure 58.	Output stage of capture/compare channel (channel 4) . . . . .	252
Figure 59.	Output stage of capture/compare channel (channel 5, idem ch.6) . . . . .	253
Figure 60.	PWM input mode timing . . . . .	254
Figure 61.	Output compare mode, toggle on OC1. . . . .	255
Figure 62.	Edge-aligned PWM waveforms (ARR=8) . . . . .	256
Figure 63.	Center-aligned PWM waveforms (ARR=8) . . . . .	257
Figure 64.	Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .	258
Figure 65.	Combined PWM mode on channel 1 and 3. . . . .	259
Figure 66.	3-phase combined PWM signals with multiple trigger pulses per period . . . . .	260
Figure 67.	Complementary output with deadtime insertion . . . . .	261
Figure 68.	Deadtime waveforms with delay greater than the negative pulse. . . . .	261
Figure 69.	Deadtime waveforms with delay greater than the positive pulse . . . . .	261
Figure 70.	Break and break2 circuitry overview . . . . .	262
Figure 71.	Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .	263
Figure 72.	PWM output state following BRK and BRK2 pins assertion (OSSI=1). . . . .	264
Figure 73.	PWM output state following BRK assertion (OSSI=0). . . . .	264
Figure 74.	Clearing TIMx_OCxREF . . . . .	265
Figure 75.	6-step generation, COM example (OSSR=1) . . . . .	266
Figure 76.	Example of one-pulse mode . . . . .	267
Figure 77.	Retriggerable one-pulse mode . . . . .	268
Figure 78.	Example of counter operation in encoder interface mode . . . . .	269
Figure 79.	Example of encoder interface mode with TI1FP1 polarity inverted . . . . .	270
Figure 80.	Measuring time interval between edges on 3 signals . . . . .	271
Figure 81.	RTC block diagram . . . . .	316
Figure 82.	Independent watchdog block diagram . . . . .	342
Figure 83.	I ²C block diagram . . . . .	350
Figure 84.	I ²C bus protocol . . . . .	352
Figure 85.	Setup and hold timings . . . . .	353
Figure 86.	I ²C initialization flowchart. . . . .	355
Figure 87.	Data reception . . . . .	356
Figure 88.	Data transmission . . . . .	356
Figure 89.	Target initialization flowchart. . . . .	359
Figure 90.	Transfer sequence flowchart for I ²C target transmitter, NOSTRETCH=0 . . . . .	360
Figure 91.	Transfer sequence flowchart for I ²C target transmitter, NOSTRETCH=1 . . . . .	360
Figure 92.	Transfer bus diagram for I ²C target transmitter . . . . .	361
Figure 93.	Transfer sequence flowchart for target receiver with NOSTRETCH=0 . . . . .	361
Figure 94.	Transfer sequence flowchart for target receiver with NOSTRETCH=1 . . . . .	362
Figure 95.	Transfer bus diagrams for I ²C target receiver . . . . .	362
Figure 96.	Controller clock generation. . . . .	364
Figure 97.	Controller initialization flowchart . . . . .	366
Figure 98.	10-bit address read access with HEAD10R=1. . . . .	366
Figure 99.	Transfer sequence flowchart for I ²C controller transmitter for N 255 bytes . . . . .	367
Figure 100.	Transfer sequence flowchart for I ²C controller transmitter for N>255 bytes. . . . .	368
Figure 101.	Transfer bus diagrams for I ²C controller transmitter. . . . .	369
Figure 102.	Transfer sequence flowchart for I ²C controller receiver for N>255 bytes. . . . .	370
Figure 103.	Transfer sequence flowchart for I ²C controller receiver for N >255 bytes . . . . .	371
Figure 104.	Transfer bus diagrams for I ²C controller receiver. . . . .	372
Figure 105.	Timeout intervals for t _LOW:SEXT, t _LOW:MEXT. . . . .	375
Figure 106.	Transfer sequence flowchart for SMBus target transmitter N bytes + PEC . . . . .	377
Figure 107.	Transfer bus diagrams for SMBus target transmitter (SBC=1). . . . .	378

Figure 108.	Transfer sequence flowchart for SMBus target receiver N bytes + PEC . . . . .	379
Figure 109.	Bus transfer diagrams for SMBus target receiver (SBC=1) . . . . .	380
Figure 110.	Bus transfer diagrams for SMBus controller transmitter . . . . .	381
Figure 111.	Bus transfer diagrams for SMBus controller receiver . . . . .	382
Figure 112.	I ²C interrupt mapping diagram . . . . .	385
Figure 113.	USART block diagram . . . . .	407
Figure 114.	Word length programming . . . . .	408
Figure 115.	Configurable stop bits . . . . .	409
Figure 116.	TC/TXE behavior when transmitting . . . . .	411
Figure 117.	Start bit detection when oversampling by 16 or 8. . . . .	412
Figure 118.	usart_ker_ck clock divider block diagram . . . . .	414
Figure 119.	Data sampling when oversampling by 16 . . . . .	415
Figure 120.	Data sampling when oversampling by 8 . . . . .	415
Figure 121.	Mute mode using Idle line detection. . . . .	419
Figure 122.	Mute mode using address mark detection . . . . .	420
Figure 123.	Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .	422
Figure 124.	Break detection in LIN mode vs. framing error detection. . . . .	423
Figure 125.	USART example of synchronous master transmission . . . . .	424
Figure 126.	USART data clock timing diagram M=0 . . . . .	424
Figure 127.	USART data clock timing diagram (M bits = 01) . . . . .	425
Figure 128.	RX data setup/hold time. . . . .	425
Figure 129.	ISO 7816-3 asynchronous protocol . . . . .	427
Figure 130.	Parity error detection using 1.5 stop bits. . . . .	429
Figure 131.	IrDA SIR ENDEC - block diagram . . . . .	432
Figure 132.	IrDA data modulation (3/16) - normal mode . . . . .	432
Figure 133.	Transmission using DMA . . . . .	433
Figure 134.	Reception using DMA . . . . .	434
Figure 135.	Hardware flow control between 2 USARTs . . . . .	434
Figure 136.	RS232 RTS flow control. . . . .	435
Figure 137.	RS232 CTS flow control. . . . .	435
Figure 138.	LPUART Block diagram . . . . .	467
Figure 139.	LPUART word length programming . . . . .	469
Figure 140.	Configurable stop bits . . . . .	471
Figure 141.	TC/TXE behavior when transmitting . . . . .	472
Figure 142.	lpuart_ker_ck clock divider block diagram . . . . .	474
Figure 143.	Mute mode using idle line detection. . . . .	476
Figure 144.	Mute mode using address mark detection . . . . .	476
Figure 145.	Transmission using DMA . . . . .	479
Figure 146.	Reception using DMA . . . . .	480
Figure 147.	Hardware flow control between 2 LPUARTs . . . . .	480
Figure 148.	RS232 RTS flow control. . . . .	481
Figure 149.	RS232 RTS flow control. . . . .	481
Figure 150.	SPI block diagram. . . . .	505
Figure 151.	Full-duplex single master/single slave application . . . . .	506
Figure 152.	Half-duplex single master/single slave application . . . . .	506
Figure 153.	Simplex single master/single slave application (master in transmit-only/slave in receive-only mode) . . . . .	507
Figure 154.	Master and three independent slaves . . . . .	508
Figure 155.	Hardware/software slave select management. . . . .	509
Figure 156.	Data clock timing diagram . . . . .	510
Figure 157.	Data alignment when data length is not equal to 8-bit or 16-bit . . . . .	511
Figure 158.	Packing data in FIFO for transmission and reception . . . . .	514
Figure 159.	Master full-duplex communication . . . . .	516
Figure 160.	Slave full-duplex communication . . . . .	517
Figure 161.	Master full-duplex communication with CRC. . . . .	518
Figure 162.	Master full-duplex communication in packed mode . . . . .	519

Figure 163.	NSSP pulse generation in Motorola SPI master mode . . . . .	521
Figure 164.	TI mode transfer . . . . .	522
Figure 165.	I ²S block diagram . . . . .	524
Figure 166.	I ²S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0) . . . . .	525
Figure 167.	I ²S Philips standard waveforms (24-bit frame with CPOL = 0) . . . . .	525
Figure 168.	Transmitting 0x8EAA33 . . . . .	526
Figure 169.	Receiving 0x8EAA33 . . . . .	526
Figure 170.	I ²S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . .	526
Figure 171.	Example of 16-bit data frame extended to 32-bit channel frame . . . . .	526
Figure 172.	MSB justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . .	527
Figure 173.	MSB justified 24-bit frame length with CPOL = 0 . . . . .	527
Figure 174.	MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .	527
Figure 175.	LSB justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . .	528
Figure 176.	LSB justified 24-bit frame length with CPOL = 0 . . . . .	528
Figure 177.	Operations required to transmit 0x3478AE . . . . .	528
Figure 178.	Operations required to receive 0x3478AE . . . . .	529
Figure 179.	LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .	529
Figure 180.	Example of 16-bit data frame extended to 32-bit channel frame (2) . . . . .	529
Figure 181.	PCM standard waveforms (16-bit) . . . . .	530
Figure 182.	PCM standard waveforms (16-bit extended to 32-bit packet frame) . . . . .	530
Figure 183.	Audio sampling frequency definition . . . . .	531
Figure 184.	I ²S clock generator architecture . . . . .	531
Figure 185.	TX sequence . . . . .	580
Figure 186.	RX sequence . . . . .	581
Figure 187.	RAM table tree . . . . .	592
Figure 188.	Wakeup event . . . . .	612

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