24. Debug support (DBG)

24.1 SWD debug features

The STM32WB07xC and STM32WB06xC device JTAG ID[31:0] is the following:

• • 0000 0010000000011110 00000100000 1
• • (0x0201_E041)

The Cortex-M0+ subsystem of the STM32WB07xC and STM32WB06xC embeds 4 breakpoints and 2 watchpoints.

The STM32WB07xC and STM32WB06xC devices embed:

• • the ARM serial wire debug port which enables serial wire debug (2-wire) to be connected to the CPU (default after power-on reset).

Note: When device enters in Deepstop mode, the SWD debug port is not powered. As consequence, debug access is disabled and the chip cannot be accessed through SWD channel. One possible recovery option is to activate the internal embedded UART bootloader through the PA10 pin (just force PA10 high during hardware reset).