19. Inter-integrated circuit (I 2 C) interface

19.1 Introduction

The I ² C (inter-integrated circuit) bus interface handles communications between the microcontroller and the serial I ² C bus. It provides multicontroller capability, and controls all I ² C bus-specific sequencing, protocol, arbitration, and timing. It supports standard mode (Sm), fast mode (Fm) and fast mode plus (Fm+).

It is also SMBus (system management bus) and PMBus (power management bus) compatible.

DMA can be used to reduce CPU overload.

19.2 I ² C main features

• • I ² C bus specification rev 03 compatibility:
  • – Target and controller modes
  • – Multi controller capability
  • – Standard mode (up to 100 kHz)
  • – Fast mode (up to 400 kHz)
  • – Fast mode plus (up to 1 MHz)
  • – 7-bit and 10-bit addressing mode
  • – Multiple 7-bit target addresses (two addresses, one with configurable mask)
  • – All 7-bit addresses acknowledge mode
  • – General call
  • – Programmable setup and hold times
  • – Easy to use event management
  • – Optional clock stretching
  • – Software reset
• • 1-byte buffer with DMA capability
• • Programmable analog and digital noise filters.

The following additional features are also available depending on the product implementation (see Section 19.3: I ² C implementation ):

• • SMBus specification rev 2.0 compatibility:
  • – Hardware PEC (packet error checking) generation and verification with ACK control
  • – Command and data acknowledge control
  • – Address resolution protocol (ARP) support
  • – Host and device support
  • – SMBus alert
  • – Timeouts and idle condition detection
• • PMBus rev 1.1 standard compatibility
• • Independent clock: a choice of independent clock sources allowing the I ² C communication speed to be independent from the PCLK reprogramming.

Note: For the Fast mode plus mode, it is strongly recommended to use I ² C pins mentioned as open-drain capable (embedding a 10ns/50ns filter).

19.3 I2C implementation

This manual describes the full set of features implemented in I2C1 and I2C2.

Table 48. STM32WB07xC and STM32WB06xC I ² C implementation

1. X=supported

19.4 I2C functional description

In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa. The interrupts are enabled or disabled by software. The interface is connected to the I ² C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected with a standard (up to 100 kHz), Fast mode (up to 400 kHz) or Fast mode plus (up to 1 MHz) I ² C bus.

This interface can also be connected to an SMBus with the data pin (SDA) and clock pin (SCL).

If SMBus feature is supported: the additional optional SMBus alert pin (SMBA) is also available.

19.4.1 I2C block diagram

The block diagram of the I ² C interface is shown below.

Figure 83. I ² C block diagram

The I ² C is clocked by an independent clock source which allows the I ² C to operate independently from the PCLK frequency.

This independent clock source is a fixed 16-MHz clock. Refer to Section 6: Reset and clock controller (RCC) for more details.

I ² C I/Os supports 20 mA output current drive for Fast mode plus operation. This is enabled by setting the driving capability control bits for SCL and SDA in Section 8.2.3: I2C Fast-Mode Plus pin capability control register (I2C_FMP_CTRL) .

19.4.2 I2C clock requirements

The I ² C kernel is clocked by I2CCLK.

The I2CCLK period \( t_{I2CCLK} \) must respect the following conditions:

with:

\( t_{LOW} \) : SCL low time and \( t_{HIGH} \) : SCL high time

\( t_{filters} \) : when enabled, the sum of the delays brought by the analog filter and by the digital filter. Analog filter delay is a maximum 260 ns. Digital filter delay is \( DNF \times t_{I2CCLK} \) .

The PCLK clock period \( t_{PCLK} \) must respect the following condition: \( t_{PCLK} < 4/3 t_{SCL} \)

with \( t_{SCL} \) : SCL period.

19.4.3 Mode selection

The interface can operate in one of the four following modes:

• • Target transmitter
• • Target receiver
• • Controller transmitter
• • Controller receiver

By default, it operates in target mode. The interface automatically switches from target to controller when it generates a START condition, and from controller to target if an arbitration loss or a STOP generation occurs, allowing multicontroller capability.

Communication flow

In controller mode, the I ² C interface initiates a data transfer and generates the clock signal. A serial data transfer always begins with a START condition and ends with a STOP condition. Both START and STOP conditions are generated in controller mode by software.

In target mode, the interface can recognize its own addresses (7 or 10-bit), and the general call address. The general call address detection can be enabled or disabled by software. The reserved SMBus addresses can also be enabled by software.

Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the START condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in controller mode.

A ninth clock pulse follows the eight clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to the following figure.

Figure 84. I ² C bus protocol

Acknowledge can be enabled or disabled by software. The I ² C interface addresses can be selected by software.

19.4.4

I ² C initialization

Enabling and disabling the peripheral

The I ² C peripheral clock must be configured and enabled in the clock controller (refer to Section 6: Reset and clock controller (RCC) ).

Then the I ² C can be enabled by setting the PE bit in the I2C_CR1 register. When the I ² C is disabled (PE=0), the I ² C performs a software reset. Refer to Section 19.4.5: Software reset for more details.

Noise filters

Before you enable the I ² C peripheral by setting the PE bit in the I2C_CR1 register, you must configure the noise filters, if needed. By default, an analog noise filter is present on the SDA and SCL inputs. This analog filter is compliant with the I ² C specification which requires the suppression of spikes with a pulse width up to 50 ns in fast mode and Fast mode plus. You can disable this analog filter by setting the ANFOFF bit, and/or select a digital filter by configuring the DNF[3:0] bit in the I2C_CR1 register.

When the digital filter is enabled, the level of the SCL or the SDA line is internally changed only if it remains stable for more than DNF x I2CCLK periods. This allows spikes to be suppressed with a programmable length of 1 to 15 I2CCLK periods.

Caution: Changing the filter configuration is not allowed when the I ² C is enabled.

I ² C timings

The timings must be configured in order to guarantee a correct data hold and set-up time, used in controller and target modes. This is done by programming the PRESC[3:0], SCLDEL[3:0] and SDADEL[3:0] bits in the I2C_TIMINGR register.

Figure 85. Setup and hold timings

• When the SCL falling edge is internally detected, a delay is inserted before sending SDA output. This delay is \( t_{SDADEL} = SDADEL \times t_{PRESC} + t_{I2CCLK} \) where \( t_{PRESC} = (PRESC+1) \times t_{I2CCLK} \) . \( t_{SDADEL} \) and impacts the hold time \( t_{HD;DAT} \) . The total SDA output delay is: \( t_{SYNC1} + \{[SDADEL \times (PRESC+1) + 1] \times t_{I2CCLK}\} \) \( t_{SYNC1} \) duration depends on these parameters:
  • SCL falling slope
  • When enabled, input delay \( t_{SYNC1} \) brought by the analog filter: \( t_{AF(min)} < t_{AF} < t_{AF(max)} \) ns.
  • When enabled, input delay brought by the digital filter: \( t_{DNF} = DNF \times t_{I2CCLK} \)
  • Delay due to SCL synchronization to I2CCLK clock (two to three I2CCLK periods)

In order to bridge the undefined region of the SCL falling edge, you must program SDADEL in such a way that:
\( \{t_{r(max)} + t_{HD;DAT(min)} - t_{AF(min)} - [(DNF + 3) \times t_{I2CCLK}]\} / \{(PRESC + 1) \times t_{I2CCLK}\} \leq SDADEL \)
\( SDADEL \leq \{t_{HD;DAT(max)} - t_{AF(max)} - [(DNF + 4) \times t_{I2CCLK}]\} / \{(PRESC + 1) \times t_{I2CCLK}\} \)

Note: \( t_{AF(min)} \) / \( t_{AF(max)} \) are part of the equation only when the analog filter is enabled. Refer to the device datasheet for \( t_{AF} \) values.

The maximum \( t_{HD;DAT} \) could be 3.45 µs, 0.9 µs, and 0.45 µs for standard mode, Fast mode and Fast mode plus, but must be less than the maximum of \( t_{VD;DAT} \) by a transition time. This maximum must only be met if the device does not stretch the LOW period ( \( t_{LOW} \) ) of the SCL signal. If the clock stretches the SCL, the data must be validated by the set-up time before it releases the clock.

The SDA rising edge is usually the worst case, so in this case the previous equation becomes:
\( SDADEL \leq \{t_{VD;DAT(max)} - t_{r(max)} - 260 \text{ ns} - [(DNF + 4) \times t_{I2CCLK}]\} / \{(PRESC + 1) \times t_{I2CCLK}\} \) .

Note: This condition can be violated when NOSTRETCH=0, because the device stretches SCL low to guarantee the set-up time, according to the SCLDEL value.

Refer to Table 49. I ² C-SMBUS specification data setup and hold times for \( t_r \) , \( t_f \) , \( t_{HD;DAT} \) and \( t_{VD;DAT} \) standard values.

• After sending SDA output, the SCL line is kept at a low level during the set-up time. This set-up time is \( t_{SCLDEL} = (SCLDEL+1) \times t_{PRESC} \) where \( t_{PRESC} = (PRESC+1) \times t_{I2CCLK} \) \( t_{SCLDEL} \) impacts the set-up time \( t_{SU;DAT} \) .

In order to bridge the undefined region of the SDA transition (rising edge usually worst case), you must program SCLDEL in such a way that:
\( \{[t_{r(max)} + t_{SU;DAT(min)}] / [(PRESC+1)] \times t_{I2CCLK}\} - 1 \leq SCLDEL \)

Refer to Table 49. I ² C-SMBUS specification data setup and hold times for \( t_r \) and \( t_{SU;DAT} \) standard values.

The SDA and SCL transition time values to be used to are the ones in the application. Using the maximum values from the standard increases the constraints for the SDADEL and SCLDEL calculation, but ensures the feature whatever the application.

Table 49. I ² C-SMBUS specification data setup and hold times

Additionally, in controller mode, the SCL clock high and low levels must be configured by programming the PRESC[3:0], SCLH[7:0] and SCLL[7:0] bits in the I2C_TIMINGR register.

• When the SCL falling edge is internally detected, a delay is inserted before releasing the SCL output. This delay is \( t_{SCLL} = (SCLL+1) \times t_{PRESC} \) where \( t_{PRESC} = (PRESC+1) \times t_{I2CCLK} \) .

\( t_{SCLL} \) impacts the SCL low time \( t_{LOW} \) .

• When the SCL rising edge is internally detected, a delay is inserted before forcing the SCL output to a low level. This delay is \( t_{SCLH} = (SCLH+1) \times t_{PRESC} \) where \( t_{PRESC} = (PRESC+1) \times t_{I2CCLK} \) . \( t_{SCLH} \) impacts the SCL high time \( t_{HIGH} \) .

Refer to Section 19.4.8: I2C controller mode for more details.

Caution: Changing the timing configuration is not allowed when the I ² C is enabled.

The I ² C target NOSTRETCH mode must also be configured before enabling the peripheral.

Caution: Changing the NOSTRETCH configuration is not allowed when the I ² C is enabled.

Figure 86. I ² C initialization flowchart

graph TD
    A([Initial settings]) --> B[Clear PE bit in I2C_CR1]
    B --> C[Configure ANFOFF and DNF[3:0] in I2C_CR1]
    C --> D["Configure PRESC[3:0],
SDADEL[3:0], SCLDEL[3:0],
SCLH[7:0], SCLL[7:0] in I2C_TIMINGR"]
    D --> E[Configure NOSTRETCH in I2C_CR1]
    E --> F[Set PE bit in I2C_CR1]
    F --> G([End])
  

19.4.5 Software reset

A software reset can be performed by clearing the PE bit in the I2C_CR1 register. In that case I ² C lines SCL and SDA are released. Internal state machines are reset and communication control bits, as well as status bits come back to their reset value. The configuration registers are not impacted.

Here is the list of impacted register bits:

1. 1. I2C_CR2 register: START, STOP, NACK
   2. I2C_ISR register: BUSY, TXE, TXIS, RXNE, ADDR, NACKF, TCR, TC, STOPF, BERR, ARLO, OVR
2. and in addition when the SMBus feature is supported:

1. I2C_CR2 register: PECBYTE
2. I2C_ISR register: PECERR, TIMEOUT, ALERT

PE must be kept low during at least three APB clock cycles in order to perform the software reset. This is ensured by writing the following software sequence: - Write PE=0 - Check PE=0 - Write PE=1.

19.4.6 Data transfer

The data transfer is managed through transmit and receive data registers and a shift register.

Reception

The SDA input fills the shift register. After the eighth SCL pulse (when the complete data byte is received), the shift register is copied into the I2C_RXDR register if it is empty (RXNE=0). If RXNE=1, meaning that the previous received data byte has not yet been read, the SCL line is stretched low until I2C_RXDR is read. The stretch is inserted between the 8 ^th and 9 ^th SCL pulse (before the acknowledge pulse).

Figure 87. Data reception

Transmission

If the I2C_TXDR register is not empty (TXE=0), its content is copied into the shift register after the ninth SCL pulse (the acknowledge pulse). Then the shift register content is shifted out on the SDA line. If TXE=1, meaning that no data is written yet in I2C_TXDR, the SCL line is stretched low until I2C_TXDR is written. The stretch is done after the ninth SCL pulse.

Figure 88. Data transmission

Hardware transfer management

The I ² C has a byte counter embedded in the hardware in order to manage byte transfer and to close the communication in various modes such as:

• • NACK, STOP, and ReSTART generation in controller mode
• • ACK control in target receiver mode

• • PEC generation/checking when SMBus feature is supported

The byte counter is always used in controller mode. By default it is disabled in target mode, but it can be enabled by software by setting the SBC (target byte control) bit in the I2C_CR2 register.

The number of bytes to be transferred is programmed in the NBBYTES[7:0] bitfield in the I2C_CR2 register. If the number of bytes to be transferred (NBBYTES) is greater than 255, or if a receiver wants to control the acknowledge value of a received data byte, the reload mode must be selected by setting the RELOAD bit in the I2C_CR2 register. In this mode, the TCR flag is set when the number of bytes programmed in NBBYTES has been transferred, and an interrupt is generated if TCIE is set. SCL is stretched as long as the TCR flag is set. TCR is cleared by software when NBBYTES is written to a nonzero value.

When the NBBYTES counter is reloaded with the last number of bytes, the RELOAD bit must be cleared.

When RELOAD=0 in controller mode, the counter can be used in two modes:

• • Automatic end mode (AUTOEND = '1' in the I2C_CR2 register). In this mode, the controller automatically sends a STOP condition once the number of bytes programmed in the NBBYTES[7:0] bitfield has been transferred.
• • Software end mode (AUTOEND = '0' in the I2C_CR2 register). In this mode, software action is expected once the number of bytes programmed in the NBBYTES[7:0] bitfield has been transferred; the TC flag is set and an interrupt is generated if the TCIE bit is set. The SCL signal is stretched as long as the TC flag is set. The TC flag is cleared by software when the START or STOP bit is set in the I2C_CR2 register. This mode must be used when the controller wants to send a RESTART condition.

Caution: The AUTOEND bit has no effect when the RELOAD bit is set.

Table 50. I ² C configurable table

19.4.7 I ² C target mode

I ² C target initialization

In order to work in target mode, you must enable at least one target address. Two registers, I2C_OAR1 and I2C_OAR2, are available in order to program the target own addresses OA1 and OA2.

• • OA1 can be configured either in 7-bit mode (by default) or in 10-bit addressing mode by setting the OA1MODE bit in the I2C_OAR1 register.
  OA1 is enabled by setting the OA1EN bit in the I2C_OAR1 register.
• • If additional target addresses are required, you can configure the second target address OA2. Up to seven OA2 LSB can be masked by configuring the OA2MSK[2:0] bits in the I2C_OAR2 register. Therefore, for OA2MSK configured from 1 to 6, only OA2[7:2], OA2[7:3], OA2[7:4], OA2[7:5], OA2[7:6] or OA2[7] are compared with the received address. As soon as OA2MSK is not equal to 0, the address comparator for OA2 excludes the I ² C reserved addresses (0000 XXX and 1111 XXX), which are not acknowledged. If OA2MSK=7, all received 7-bit addresses are acknowledged (except reserved addresses). OA2 is always a 7-bit address.
  These reserved addresses can be acknowledged if they are enabled by the specific enable bit, if they are programmed in the I2C_OAR1 or I2C_OAR2 register with OA2MSK=0.
  OA2 is enabled by setting the OA2EN bit in the I2C_OAR2 register.
• • The general call address is enabled by setting the GCEN bit in the I2C_CR1 register.

When the I ² C is selected by one of its enabled addresses, the ADDR interrupt status flag is set, and an interrupt is generated if the ADDRIE bit is set.

By default, the target uses its clock stretching capability, which means that it stretches the SCL signal at low level when needed, in order to perform software actions. If the controller does not support clock stretching, the I ² C must be configured with NOSTRETCH=1 in the I2C_CR1 register.

After receiving an ADDR interrupt, if several addresses are enabled you must read the ADDCODE[6:0] bits in the I2C_ISR register in order to check which address matched. DIR flag must also be checked in order to know the transfer direction.

Target clock stretching (NOSTRETCH = 0)

In default mode, the I ² C target stretches the SCL clock in the following situations:

• • When the ADDR flag is set: the received address matches with one of the enabled target addresses. This stretch is released when the ADDR flag is cleared by software setting the ADDRCF bit.
• • In transmission, if the previous data transmission is completed and no new data is written in the I2C_TXDR register, or if the first data byte is not written when the ADDR flag is cleared (TXE=1). This stretch is released when the data is written to the I2C_TXDR register.
• • In reception when the I2C_RXDR register is not read yet and a new data reception is completed. This stretch is released when I2C_RXDR is read.
• • When TCR = 1 in target byte Control mode, reload mode (SBC=1 and RELOAD=1), meaning that the last data byte has been transferred. This stretch is released when then TCR is cleared by writing a nonzero value in the NBBYTES[7:0] field.
• • After SCL falling edge detection, the I ² C stretches SCL low during \( [(SDADEL+SCLDEL+1) \times (PRESC+1) + 1] \times tI2CCLK \) .

Target without clock stretching (NOSTRETCH = 1)

When NOSTRETCH = 1 in the I2C_CR1 register, the I ² C target does not stretch the SCL signal.

• • The SCL clock is not stretched while the ADDR flag is set.
• • In transmission, the data must be written in the I2C_TXDR register before the first SCL pulse corresponding to its transfer occurs. If not, an underrun occurs, the OVR flag is set in the I2C_ISR register and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register. The OVR flag is also set when the first data transmission starts and the STOPF bit is still set (has not been cleared). Therefore, if you clear the STOPF flag of the previous transfer only after writing the first data to be transmitted in the next transfer, you ensure that the OVR status is provided, even for the first data to be transmitted.
• • In reception, the data must be read from the I2C_RXDR register before the ninth SCL pulse (ACK pulse) of the next data byte occurs. If not an overrun occurs, the OVR flag is set in the I2C_ISR register and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

Target byte control mode

In order to allow byte ACK control in target reception mode, target byte control mode must be enabled by setting the SBC bit in the I2C_CR1 register. This is required to be compliant with SMBus standards.

Reload mode must be selected in order to allow byte ACK control in target reception mode (RELOAD=1). To get control of each byte, NBBYTES must be initialized to 0x1 in the ADDR interrupt subroutine, and reloaded to 0x1 after each received byte. When the byte is received, the TCR bit is set, stretching the SCL signal low between the 8 ^th and 9 ^th SCL pulses. You can read the data from the I2C_RXDR register, and then decide to acknowledge it or not by configuring the ACK bit in the I2C_CR2 register. The SCL stretch is released by programming NBBYTES to a non-zero value: the acknowledge or not- acknowledge is sent and the next byte can be received.

NBYTES can be loaded with a value greater than 0x1, and in this case, the reception flow is continuous during NBBYTES data reception.

Note: The SBC bit must be configured when the I ² C is disabled, or when the target is not addressed, or when ADDR=1. The RELOAD bit value can be changed when ADDR=1, or when TCR=1.

Caution: Target byte control mode is not compatible with NOSTRETCH mode. Setting SBC when NOSTRETCH=1 is not allowed.

Figure 89. Target initialization flowchart

graph TD
    A([Target initialization]) --> B[Initial settings]
    B --> C[Clear {OA1EN, OA2EN} in I2C_CR1]
    C --> D["Configure {OA1[9:0], OA1MODE, OA1EN, OA2[6:0], OA2MSK[2:0], OA2EN, GCEN}"]
    D --> E[Configure SBC in I2C_CR1*]
    E --> F["Enable interrupts and/or DMA in I2C_CR1"]
    F --> G([End])
  

*SBC must be set to support SMBus features

Target transmitter

A transmit interrupt status (TXIS) is generated when the I2C_TXDR register becomes empty. An interrupt is generated if the TXIE bit is set in the I2C_CR1 register.

The TXIS bit is cleared when the I2C_TXDR register is written with the next data byte to be transmitted.

When a NACK is received, the NACKF bit is set in the I2C_ISR register and an interrupt is generated if the NACKIE bit is set in the I2C_CR1 register. The target automatically releases the SCL and SDA lines in order to let the controller perform a STOP or a RESTART condition. The TXIS bit is not set when a NACK is received.

When a STOP is received and the STOPIE bit is set in the I2C_CR1 register, the STOPF flag is set in the I2C_ISR register and an interrupt is generated. In most applications, the SBC bit is usually programmed to '0'. In this case, If TXE = 0 when the target address is received (ADDR=1), you can choose either to send the content of the I2C_TXDR register as the first data byte, or to flush the I2C_TXDR register by setting the TXE bit in order to program a new data byte.

In target byte control mode (SBC=1), the number of bytes to be transmitted must be programmed in NBBYTES in the address match interrupt subroutine (ADDR=1). In this case, the number of TXIS events during the transfer corresponds to the value programmed in NBBYTES.

Caution: When NOSTRETCH=1, the SCL clock is not stretched while the ADDR flag is set, so you cannot flush the I2C_TXDR register content in the ADDR subroutine, in order to program the first data byte. The first data byte to be sent must be previously programmed in the I2C_TXDR register:

• • This data can be the data written in the last TXIS event of the previous transmission message
• • If this data byte is not the one to be sent, the I2C_TXDR register can be flushed by setting the TXE bit in order to program a new data byte. The STOPF bit must be cleared only after these actions, in order to guarantee that they are executed before the first data transmission starts, following the address acknowledge.

If STOPF is still set when the first data transmission starts, an underrun error is generated (the OVR flag is set).

If you need a TXIS event, (Transmit Interrupt or Transmit DMA request), you must set the TXIS bit in addition to the TXE bit, in order to generate a TXIS event.

Figure 90. Transfer sequence flowchart for I2C target transmitter, NOSTRETCH=0

graph TD
    Start([Target transmission]) --> Init[Target initialization]
    Init --> ADDR{I2C_ISR.ADDR = 1?}
    ADDR -- No --> Init
    ADDR -- Yes --> Read[Read ADDCODE and DIR in I2C_ISR
Optional: Set I2C_ISR.TXE = 1
Set I2C_ICR.ADDRCF]
    Read --> TXIS{I2C_ISR.TXIS = 1?}
    TXIS -- No --> Init
    TXIS -- Yes --> Write[Write I2C_TXDR.TXDATA]
    Write --> Init
    style ADDR fill:none,stroke:none
    style TXIS fill:none,stroke:none
  

Figure 91. Transfer sequence flowchart for I2C target transmitter, NOSTRETCH=1

graph TD
    Start([Target transmission]) --> Init[Target initialization]
    Init --> TXIS{I2C_ISR.TXIS = 1?}
    Init --> STOPF{I2C_ISR.STOPF = 1?}
    TXIS -- No --> Init
    TXIS -- Yes --> Write[Write I2C_TXDR.TXDATA]
    Write --> Init
    STOPF -- No --> Init
    STOPF -- Yes --> Optional[Optional: Set I2C_ISR.TXE = 1
and I2C_ISR.TXIS=1]
    Optional --> StopCF[Set I2C_ICR.STOPCF]
    StopCF --> Init
    style TXIS fill:none,stroke:none
    style STOPF fill:none,stroke:none
  

Figure 92. Transfer bus diagram for I2C target transmitter

graph TD
    Start([Target reception]) --> Init[Target initialization]
    Init --> RXNE{I2C_ISR.RXNE = 1?}
    RXNE -- Yes --> Read[Read I2C_RXDR.RXDATA]
    Read --> RXNE
    RXNE -- No --> STOPF{I2C_ISR.STOPF = 1?}
    STOPF -- Yes --> StopCF[Set I2C_ICR.STOPCF]
    StopCF --> RXNE
    STOPF -- No --> RXNE
  

Target receiver

RXNE is set in I2C_ISR when the I2C_RXDR is full, and generates an interrupt if RXIE is set in I2C_CR1. RXNE is cleared when I2C_RXDR is read.

When a STOP is received and STOPIE is set in I2C_CR1, STOPF is set in I2C_ISR and an interrupt is generated.

Figure 93. Transfer sequence flowchart for target receiver with NOSTRETCH=0

graph TD
    Start([Target reception]) --> Init[Target initialization]
    Init --> ADDR{I2C_ISR.ADDR = 1?}
    ADDR -- Yes --> ReadAddr[Read ADDCODE and DIR in I2C_ISR
Set I2C_ICR.ADDRCF]
    ReadAddr --> RXNE{I2C_ISR.RXNE = 1?}
    RXNE -- Yes --> Write[Write I2C_RXDR.RXDATA]
    Write --> RXNE
    RXNE -- No --> ADDR
  

Figure 94. Transfer sequence flowchart for target receiver with NOSTRETCH=1

graph TD
    Start([Target reception]) --> Init[Target initialization]
    Init --> RXNE{I2C_ISR.RXNE = 1?}
    RXNE -- Yes --> Read[Read I2C_RXDR.RXDATA]
    Read --> RXNE
    RXNE -- No --> STOPF{I2C_ISR.STOPF = 1?}
    STOPF -- Yes --> Stop[Set I2C_ICR.STOPCF]
    Stop --> RXNE
    STOPF -- No --> RXNE
  

Figure 95. Transfer bus diagrams for I2C target receiver

Example I2C target receiver 3 bytes, NOSTRETCH=0:

EV1: ADDR ISR: check ADDCODE and DIR, set ADDRCF
EV2: RXNE ISR: rd data1
EV3: RXNE ISR: rd data2
EV4: RXNE ISR: rd data3

Example I2C target receiver 3 bytes, NOSTRETCH=1:

EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2
EV3: RXNE ISR: rd data3
EV4: STOPF ISR: set STOPCF

19.4.8 I2C controller mode
I2C controller initialization

Before enabling the peripheral, the I ² C controller clock must be configured by setting the SCLH and SCLL bits in the I2C_TIMINGR register.

A clock synchronization mechanism is implemented in order to support multi-controller environment and target clock stretching.

In order to allow clock synchronization:

• • The low level of the clock is counted using the SCLL counter, starting from the SCL low-level internal detection.
• • The high level of the clock is counted using the SCLH counter, starting from the SCL high-level internal detection.

The I ² C detects its own SCL low level after a \( t_{\text{SYNC1}} \) delay depending on the SCL falling edge, SCL input noise filters (analog + digital) and SCL synchronization to the I2CxCLK clock. The I ² C releases SCL to a high level once the SCLL counter reaches the value programmed in the SCLL[7:0] bits in the I2C_TIMINGR register.

The I ² C detects its own SCL high level after a \( t_{\text{SYNC2}} \) delay depending on the SCL rising edge, SCL input noise filters (analog + digital) and SCL synchronization to I2CxCLK clock. The I ² C ties SCL to a low level once the SCLH counter reaches the value programmed in the SCLH[7:0] bits in the I2C_TIMINGR register.

Consequently, the controller clock period is:

The duration of \( t_{\text{SYNC1}} \) depends on these parameters:

• • SCL falling slope
• • When enabled, the input delay induced by the analog filter
• • When enabled, the input delay induced by the digital filter: \( \text{DNF} \times t_{\text{I2CCLK}} \)
• • Delay due to SCL synchronization with I2CCLK clock (two to three I2CCLK periods)

The duration of \( t_{\text{SYNC2}} \) depends on these parameters:

• • SCL rising slope
• • When enabled, the input delay induced by the analog filter
• • When enabled, the input delay induced by the digital filter: \( \text{DNF} \times t_{\text{I2CCLK}} \)
• • Delay due to SCL synchronization with I2CCLK clock (two to three I2CCLK periods)

Figure 96. Controller clock generation

Caution: In order to be I ² C or SMBus compliant, the controller clock must respect the timings given below:

Table 51. I ² C-SMBUS specification clock timings

Note: SCLL is also used generate the t _BUF and t _SU:STA timings.

SCLH is also used to generate the t _HD:STA and t _SU:STO timings.

Refer to Section 19.4.9: I2C_TIMINGR register configuration examples for examples of I2C_TIMINGR settings vs. I2CCLK frequency.

Controller communication initialization (address phase)

In order initiate the communication, program the following parameters for the addressed target in the I2C_CR2 register:

• • Addressing mode (7-bit or 10-bit): ADD10
• • Target address to be sent: SADD[9:0]
• • Transfer direction: RD_WRN
• • In case of a 10-bit address read: HEAD10R bit. HEAD10R must be configured to indicate if the complete address sequence must be sent, or only the header in case of a direction change.
• • The number of bytes to be transferred: NBYTES[7:0]. If the number of bytes is equal to or greater than 255 bytes, NBYTES[7:0] must initially be filled with 0xFF.

Then set the START bit in the I2C_CR2 register. Changing all the above bits is not allowed when the START bit is set.

Then the controller automatically sends the START condition followed by the target address as soon as it detects that the bus is free (BUSY = 0) and after a delay of t _BUF .

In case of an arbitration loss, the controller automatically switches back to target mode and can acknowledge its own address if it is addressed as a target.

Note: The START bit is reset by hardware when the target address has been sent on the bus, whatever the received acknowledge value. The START bit is also reset by hardware if an arbitration loss occurs. If the I ² C is addressed as a target (ADDR=1) while the START bit is set, the I ² C switches to target mode and the START bit is cleared when the ADDRCF bit is set.

Note: The same procedure is applied for a repeated start condition. In this case BUSY=1.

Figure 97. Controller initialization flowchart

graph TD
    A([Controller initialization]) --> B[Initial settings]
    B --> C[Enable interrupts and/or DMA in I2C_CR1]
    C --> D([End])
  

Initialization of a controller receiver addressing a 10-bit address target

• • If the target address is in 10-bit format, you can choose to send the complete read sequence by clearing the HEAD10R bit in the I2C_CR2 register. In this case the controller automatically sends the following complete sequence after the START bit is set: (Re)Start + target address 10-bit header Write + target address second byte + REStart + target address 10-bit header Read
• • If the controller addresses a 10-bit address target, transmits data to this target and then reads data from the same target, a controller transmission flow must be done first. Then a repeated start is set with the 10-bit target address configured with HEAD10R=1. In this case the controller sends this sequence: ReStart + target address 10-bit header Read.

Figure 98. 10-bit address read access with HEAD10R=1

Controller transmitter

In the case of a write transfer, the TXIS flag is set after each byte transmission, after the ninth SCL pulse when an ACK is received.

A TXIS event generates an interrupt if the TXIE bit is set in the I2C_CR1 register. The flag is cleared when the I2C_TXDR register is written with the next data byte to be transmitted.

The number of TXIS events during the transfer corresponds to the value programmed in NBBYTES[7:0]. If the total number of data bytes to be sent is greater than 255, reload mode must be selected by setting the RELOAD bit in the I2C_CR2 register. In this case, when NBBYTES data have been transferred, the TCR flag is set and the SCL line is stretched low until NBBYTES[7:0] is written to a nonzero value.

The TXIS flag is not set when a NACK is received.

• • When RELOAD=0 and NBYTES data have been transferred:
  • – In automatic end mode (AUTOEND=1), a STOP is automatically sent.
  • – In software end mode (AUTOEND=0), the TC flag is set and the SCL line is stretched low in order to perform software actions:
    A RESTART condition can be requested by setting the START bit in the I2C_CR2 register with the proper target address configuration, and number of bytes to be transferred. Setting the START bit clears the TC flag and the START condition is sent on the bus.
    A STOP condition can be requested by setting the STOP bit in the I2C_CR2 register. Setting the STOP bit clears the TC flag and the STOP condition is sent on the bus.
• • If a NACK is received: the TXIS flag is not set, and a STOP condition is automatically sent after the NACK reception. The NACKF flag is set in the I2C_ISR register, and an interrupt is generated if the NACKIE bit is set.

Figure 99. Transfer sequence flowchart for I2C controller transmitter for N 255 bytes

graph TD
    Start([Controller transmission]) --> Init[Controller initialization]
    Init --> Config["NBYTES = N
AUTOEND = 0 for RESTART; 1 for STOP
Configure target address
Set I2C_CR2.START"]
    Config --> NACKF{I2C_ISR.NACKF = 1?}
    NACKF -- Yes --> End1([End])
    NACKF -- No --> TXIS{I2C_ISR.TXIS = 1?}
    TXIS -- Yes --> Write[Write I2C_TXDR]
    Write --> NBYTES{NBYTES transmitted?}
    NBYTES -- No --> NACKF
    NBYTES -- Yes --> TC{I2C_ISR.TC = 1?}
    TC -- Yes --> Restart["Set I2C_CR2.START with
target address NBYTES ..."]
    TC -- No --> End2([End])
    Restart --> End2
    End2 -.-> Dashed[ ]
    style Dashed fill:none,stroke:none
  

Figure 100. Transfer sequence flowchart for I2C controller transmitter for N>255 bytes

graph TD
    Start([Controller Transmission]) --> Init[Controller initialization]
    Init --> Config["NBYTES = 0xFF; N=N-255
RELOAD = 1
Configure target address
Set I2C_CR2.START"]
    Config --> LoopStart(( ))
    LoopStart --> NACKF{"I2C_ISR.NACKF
= 1?"}
    NACKF -- Yes --> End1([End])
    NACKF -- No --> TXIS{"I2C_ISR.TXIS
= 1?"}
    TXIS -- Yes --> Write[Write I2C_TXDR]
    Write --> Transmitted{"NBYTES
transmitted?"}
    Transmitted -- No --> LoopStart
    Transmitted -- Yes --> TC{"I2C_ISR.TC
= 1?"}
    TC -- Yes --> CCR["Set I2C_CCR.START
with target address
NBYTES.."]
    CCR -.-> Dotted[⋮]
    Dotted --> End2([End])
    TC -- No --> TCR{"I2C_ISR.TCR
= 1?"}
    TCR -- Yes --> Logic["IF N < 256
NBYTES = N; N = 0; RELOAD = 0
AUTOEND = 0 for RESTART; 1 for STOP
ELSE
NBYTES = 0xFF; N = N-255
RELOAD = 1"]
    Logic --> LoopStart
    TCR -- No --> LoopStart
  

Figure 101. Transfer bus diagrams for I2C controller transmitter

Example I2C controller transmitter 2 bytes, automatic end mode (STOP)

INIT: program target address, program NBYTES = 2, AUTOEND=1, set START
EV1: TXIS ISR: wr data1
EV2: TXIS ISR: wr data2

Example I2C controller transmitter 2 bytes, software end (RESTART)

INIT: program target address, program NBYTES = 2, AUTOEND=0, set START
EV1: TXIS ISR: wr data1
EV2: TXIS ISR: wr data2
EV3: TC ISR: program target address, program NBYTES = N, set START

Controller receiver

In the case of a read transfer, the RXNE flag is set after each byte reception, after the eighth SCL pulse. An RXNE event generates an interrupt if the RXIE bit is set in the I2C_CR1 register. The flag is cleared when I2C_RXDR is read.

If the total number of data bytes to be received is greater than 255, reload mode must be selected by setting the RELOAD bit in the I2C_CR2 register. In this case, when NBYTES[7:0] data have been transferred, the TCR flag is set and the SCL line is stretched low until NBYTES[7:0] is written to a nonzero value.

• • When RELOAD=0 and NBYTES[7:0] data have been transferred:
  • – In automatic end mode (AUTOEND=1), a NACK, and a STOP are automatically sent after the last received byte
  • – In software end mode (AUTOEND=0), a NACK is automatically sent after the last received byte, the TC flag is set and the SCL line is stretched low in order to allow software actions:
    A RESTART condition can be requested by setting the START bit in the I2C_CR2 register with the proper target address configuration, and number of bytes to be transferred. Setting the START bit clears the TC flag and the START condition, followed by the target address, are sent on the bus. A STOP condition can be requested by setting the STOP bit in the I2C_CR2 register. Setting the STOP bit clears the TC flag and the STOP condition is sent on the bus.

Figure 102. Transfer sequence flowchart for I ² C controller receiver for N>255 bytes

graph TD
    Start([Controller reception]) --> Init[Controller initialization]
    Init --> Config["NBYTES = N
AUTOEND = 0 for RESTART; 1 for STOP
Configure target address
Set I2C_CR2.START"]
    Config --> RXNE{I2C_ISR.RXNE = 1?}
    RXNE -- No --> RXNE
    RXNE -- Yes --> Read[Read I2C_RXDR]
    Read --> NBYTES{NBYTES received?}
    NBYTES -- No --> RXNE
    NBYTES -- Yes --> TC{I2C_ISR.TC = 1?}
    TC -- Yes --> SetCR2["Set I2C_CR2.START with
target address NBYTES..."]
    TC -- No --> End([End])
    SetCR2 -.-> Dots[⋮]
  

Figure 103. Transfer sequence flowchart for I ² C controller receiver for N >255 bytes

graph TD
    Start([Controller
reception]) --> Init[Controller initialization]
    Init --> Setup["NBYTES = 0xFF; N=N-255
RELOAD = 1
Configure target address
Set I2C_CR2.START"]
    Setup --> RXNE{I2C_ISR.RXNE
= 1?}
    RXNE -- No --> RXNE
    RXNE -- Yes --> Read[Read I2C_RXDR]
    Read --> NBytes{NBYTES
received?}
    NBytes -- No --> RXNE
    NBytes -- Yes --> TC{I2C_ISR.TC =
1?}
    TC -- Yes --> SetStart["Set I2C_CR2.START with
target address NBYTES ..."]
    SetStart -.-> Dots[...] 
    TC -- No --> TCR{I2C_ISR.TCR
= 1?}
    TCR -- Yes --> EndCondition["IF N < 256
NBYTES = N; N=0; RELOAD=0
AUTOEND=0 for RESTART; 1 for STOP
ELSE
NBYTES = 0xFF; N=N-255
RELOAD=1"]
    TCR -- No --> End([End])
    EndCondition --> RXNE
    Dots --> End
  

Figure 104. Transfer bus diagrams for I2C controller receiver

Example I2C controller receiver 2 bytes, automatic end mode (STOP)

INIT: program target address, program NBYTES = 2, AUTOEND=1, set START
EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2

Example I2C controller receiver 2 bytes, software end mode (RESTART)

INIT: program target address, program NBYTES = 2, AUTOEND=0, set START
EV1: RXNE ISR: rd data1
EV2: RXNE ISR: read data2
EV3: TC ISR: program target address, program NBYTES = N, set START

19.4.9 I2C_TIMINGR register configuration examples

The tables below provide examples of how to program the I2C_TIMINGR to obtain timings compliant with the I2C specifications.

Table 52. Examples of timings settings for f _I2CCLK = 16 MHz

1. 1. SCL period \( t_{SCL} \) is greater than \( t_{SCLL} + t_{SCLH} \) due to SCL internal detection delay. Values provided for \( t_{SCL} \) are examples only.
2. 2. \( t_{SYNC1} + t_{SYNC2} \) minimum value is \( 4 \times t_{I2CCLK} = 250 \) ns. Example with \( t_{SYNC1} + t_{SYNC2} = 1000 \) ns
3. 3. \( t_{SYNC1} + t_{SYNC2} \) minimum value is \( 4 \times t_{I2CCLK} = 250 \) ns. Example with \( t_{SYNC1} + t_{SYNC2} = 750 \) ns
4. 4. \( t_{SYNC1} + t_{SYNC2} \) minimum value is \( 4 \times t_{I2CCLK} = 250 \) ns. Example with \( t_{SYNC1} + t_{SYNC2} = 500 \) ns

19.4.10 SMBus specific features

This section is relevant only when SMBus feature is supported. Refer to Section 19.3: I2C implementation .

Introduction

The system management bus (SMBus) is a two-wire interface through which various devices can communicate with each other and with the rest of the system. It is based on I ² C principles of operation. SMBus provides a control bus for system and power management related tasks.

This peripheral is compatible with the SMBUS specification rev 2.0 ( http://smbus.org ).

The system management bus specification refers to three types of devices.

• • A target is a device that receives or responds to a command
• • A controller is a device that issues commands, generates the clocks and terminates the transfer
• • A host is a specialized controller that provides the main interface to the system's CPU. A host must be a controller-target and must support the SMBus host notify protocol. Only one host is allowed in a system.

This peripheral can be configured as controller or target device, and also as a host.

SMBUS is based on I ² C specification rev 2.1.

Bus protocols

There are eleven possible command protocols for any given device. A device may use any or all of the 11 protocols to communicate. The protocols are Quick Command, Send byte, Receive byte, Write byte, Write Word, Read byte, Read Word, Process Call, Block Read, Block Write and Block Write-Block Read Process Call. These protocols should be implemented by the user software.

For more details of these protocols, refer to SMBus specification version 2.0 ( http://smbus.org ).

Address resolution protocol (ARP)

SMBus target address conflicts can be resolved by dynamically assigning a new unique address to each target device. In order to provide a mechanism to isolate each device for the purpose of address assignment each device must implement a unique device identifier (UDID). This 128-bit number is implemented by software.

This peripheral supports the address resolution protocol (ARP). The SMBus Device Default Address (0b1100 001) is enabled by setting the SMBDEN bit in the I2C_CR1 register. The ARP commands should be implemented by the user software.

Arbitration is also performed in target mode for ARP support.

For more details of the SMBus Address Resolution Protocol, refer to SMBus specification version 2.0 ( http://smbus.org ).

Received command and data acknowledge control

An SMBus receiver must be able to NACK each received command or data. In order to allow the ACK control in target mode, the target byte Control mode must be enabled by setting SBC bit in the I2C_CR1 register.

Host Notify protocol

This peripheral supports the Host Notify protocol by setting the SMBHEN bit in the I2C_CR1 register. In this case the host acknowledges the SMBus Host address (0b0001 000).

When this protocol is used, the device acts as a controller and the host as a target.

SMBus alert

The SMBus ALERT optional signal is supported. A target-only device can signal the host through the SMBALERT# pin that it wants to talk. The host processes the interrupt and simultaneously accesses all SMBALERT# devices through the Alert Response Address (0b0001 100). Only the device(s) which pulled SMBALERT# low acknowledges the Alert Response Address.

When configured as a target device (SMBHEN=0), the SMBA pin is pulled low by setting the ALERTEN bit in the I2C_CR1 register. The Alert Response Address is enabled at the same time.

When configured as a host (SMBHEN=1), the ALERT flag is set in the I2C_ISR register when a falling edge is detected on the SMBA pin and ALERTEN=1. An interrupt is generated if the ERRIE bit is set in the I2C_CR1 register. When ALERTEN=0, the ALERT line is considered high even if the external SMBA pin is low.

If the SMBus ALERT pin is not needed, the SMBA pin can be used as a standard GPIO if ALERTEN=0.

Packet error checking

A packet error checking mechanism has been introduced in the SMBus specification to improve reliability and communication robustness. Packet Error Checking is implemented by appending a Packet Error Code (PEC) at the end of each message transfer. The PEC is calculated by using the \( C(x) = x^8 + x^2 + x + 1 \) CRC-8 polynomial on all the message bytes (including addresses and read/write bits).

The peripheral embeds a hardware PEC calculator and allows a non Acknowledge to be sent automatically when the received byte does not match with the hardware calculated PEC.

Timeouts

This peripheral embeds hardware timers in order to be compliant with the three timeouts defined in SMBus specification version 2.0.

Table 53. SMBus timeout specifications

1. • \( t_{LOW:SEXT} \) is the cumulative time a given target device is allowed to extend the clock cycles in one message from the initial START to the STOP. It is possible that, another target device or the controller also extends the clock causing the combined clock low extend time to be greater than \( t_{LOW:SEXT} \) . Therefore, this parameter is measured with the target device as the sole target of a full-speed controller.
2. • \( t_{LOW:MEXT} \) is the cumulative time a controller device is allowed to extend its clock cycles within each byte of a message as defined from START-to-ACK, ACK-to-ACK, or ACK-to-STOP. It is possible that a target device or another controller also extends the clock causing the combined clock low time to be greater than \( t_{LOW:MEXT} \) on a given byte. Therefore, this parameter is measured with a full speed target device as the sole target of the controller.

Figure 105. Timeout intervals for \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \)

Bus idle detection

A controller can assume that the bus is free if it detects that the clock and data signals have been high for \( t_{IDLE} \) greater than \( t_{HIGH, MAX} \) . (Refer to Table 51. I ² C-SMBUS specification clock timings).

This timing parameter covers the condition where a controller has been dynamically added to the bus and may not have detected a state transition on the SMBCLK or SMBDAT lines. In this case, the controller must wait long enough to ensure that a transfer is not currently in progress. The peripheral supports a hardware bus idle detection.

19.4.11 SMBus initialization

This section is relevant only when SMBus feature is supported. Refer to Section 19.3: I ² C implementation.

In addition to I ² C initialization, some other specific initializations must be done in order to perform SMBus communication:

Received command and data acknowledge control (target mode)

An SMBus receiver must be able to NACK each received command or data. In order to allow ACK control in target mode, the target byte control mode must be enabled by setting the SBC bit in the I ² C_CR1 register. Refer to Section 19.4.7: I ² C target mode "target byte control mode" for more details.

Specific address (target mode)

The specific SMBus addresses should be enabled if needed.

• • The SMBus Device Default address (0b1100 001) is enabled by setting the SMBDEN bit in the I ² C_CR1 register
• • The SMBus Host address (0b0001 000) is enabled by setting the SMBHEN bit in the I ² C_CR1 register.
• • The Alert Response Address (0b0001100) is enabled by setting the ALERTEN bit in the I ² C_CR1 register.

Packet error checking

PEC calculation is enabled by setting the PECEN bit in the I ² C_CR1 register. Then the PEC transfer is managed with the help of a hardware byte counter: NBBYTES[7:0] in the I ² C_CR2 register. The PECEN bit must be configured before enabling the I ² C.

The PEC transfer is managed with the hardware byte counter, so the SBC bit must be set when interfacing the SMBus in target mode. The PEC is transferred after NBBYTES-1 data have been transferred when the PECBYTE bit is set and the RELOAD bit is cleared. If RELOAD is set, PECBYTE has no effect.

Caution: Changing the PECEN configuration is not allowed when the I ² C is enabled.

Table 54. SMBUS with PEC configuration

Timeout detection

The timeout detection is enabled by setting the TIMOUTEN and TEXTEN bits in the I2C_TIMEOUTR register. The timers must be programmed in such a way that they detect a timeout before the maximum time given in the SMBus specification version 2.0.

• • \( t_{\text{TIMEOUT}} \) check

In order to enable the \( t_{\text{TIMEOUT}} \) check, the 12-bit TIMEOUTA[11:0] bits must be programmed with the timer reload value in order to check the \( t_{\text{TIMEOUT}} \) parameter. The TIDLE bit must be configured to '0' in order to detect the SCL low level timeout.

Then the timer is enabled by setting the TIMOUTEN in the I2C_TIMEOUTR register.

If SCL is tied low for a time greater than \( (\text{TIMEOUTA}+1) \times 2048 \times t_{\text{I2CCLK}} \) , the TIMEOUT flag is set in the I2C_ISR register.

Refer to Table 55. Examples of TIMEOUTA settings (max. \( t_{\text{TIMEOUT}} = 25 \text{ ms} \) ) .

Caution: Changing the TIMEOUTA[11:0] bits and TIDLE bit configuration is not allowed when the TIMOUTEN bit is set.

• • \( t_{\text{LOW:SEXT}} \) and \( t_{\text{LOW:MEXT}} \) check

Depending on whether the peripheral is configured as a controller or as a target, the 12-bit TIMEOUTB timer must be configured in order to check \( t_{\text{LOW:SEXT}} \) for a target and \( t_{\text{LOW:MEXT}} \) for a controller. As the standard specifies only a maximum, you can choose the same value for both.

Then the timer is enabled by setting the TEXTEN bit in the I2C_TIMEOUTR register.

If the SMBus peripheral performs a cumulative SCL stretch for a time greater than \( (\text{TIMEOUTB}+1) \times 2048 \times t_{\text{I2CCLK}} \) , the timeout interval, the TIMEOUT flag is set in the I2C_ISR register.

Refer to Table 56. Example of TIMEOUTB settings .

Caution: Changing the TIMEOUTB configuration is not allowed when the TEXTEN bit is set.

Bus idle detection

In order to enable the \( t_{\text{IDLE}} \) check, the 12-bit TIMEOUTA[11:0] field must be programmed with the timer reload value in order to obtain the \( t_{\text{IDLE}} \) parameter. The TIDLE bit must be configured to '1' in order to detect both SCL and SDA high level timeout.

Then the timer is enabled by setting the TIMOUTEN bit in the I2C_TIMEOUTR register.

If both the SCL and SDA lines remain high for a time greater than \( (\text{TIMEOUTA}+1) \times 4 \times t_{\text{I2CCLK}} \) , the TIMEOUT flag is set in the I2C_ISR register.

Refer to Table 57. Examples of TIMEOUTA settings (max. \( t_{\text{IDLE}} = 50 \text{ } \mu\text{s} \) ) .

Caution: Changing the TIMEOUTA and TIDLE configuration is not allowed when the TIMOUTEN is set.

19.4.12 SMBus: I2C_TIMEOUTR register configuration examples

This section is relevant only when SMBus feature is supported. Refer to Section 19.3: I2C implementation .

• • Configuring the maximum duration of \( t_{\text{TIMEOUT}} \) to 25 ms:

Table 55. Examples of TIMEOUTA settings (max. \( t_{\text{TIMEOUT}} = 25 \text{ ms} \) )

• • Configuring the maximum duration of \( t_{\text{LOW:SEXT}} \) and \( t_{\text{LOW:MEXT}} \) to 8 ms:

Table 56. Example of TIMEOUTB settings

• Configuring the maximum duration of \( t_{IDLE} \) to 50 \( \mu\text{s} \) :

Table 57. Examples of TIMEOUTA settings (max. \( t_{IDLE} = 50 \mu\text{s} \) )

19.4.13 SMBus target mode

This section is relevant only when SMBus feature is supported. Refer to Section 19.3: I2C implementation .

In addition to I ² C target transfer management (refer to Section 19.4.7: I2C target mode ) some additional software flowcharts are provided to support SMBus.

SMBus target transmitter

When the IP is used in SMBus, SBC must be programmed to '1' in order to allow the PEC transmission at the end of the programmed number of data bytes. When the PECBYTE bit is set, the number of bytes programmed in NBYTES[7:0] includes the PEC transmission. In that case the total number of TXIS interrupts is NBYTES-1 and the content of the I2C_PECR register is automatically transmitted if the controller requests an extra byte after the NBYTES-1 data transfer.

Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

Figure 106. Transfer sequence flowchart for SMBus target transmitter N bytes + PEC

graph TD
    Start([SMBus target transmission]) --> Init[Target initialization]
    Init --> AddrCheck{I2C_ISR.ADDR = 1?}
    AddrCheck -- No --> Init
    AddrCheck -- Yes --> ReadAndSet[Read ADDCODE and DIR in I2C_ISR
I2C_CR2.NBYTES = N + 1
PECBYTE=1
Set I2C_ICR.ADDRCF]
    ReadAndSet --> TxIsCheck{I2C_ISR.TXIS = 1?}
    TxIsCheck -- No --> TxIsCheck
    TxIsCheck -- Yes --> Write[Write I2C_TXDR.TXDATA]
    Write --> TxIsCheck

Figure 107. Transfer bus diagrams for SMBus target transmitter (SBC=1)

Example SMBus target transmitter 2 bytes + PEC,

EV1: ADDR ISR: check ADDCODE, program NBYTES=3, set PECBYTE, set ADDRCF
EV2: TXIS ISR: wr data1
EV3: TXIS ISR: wr data2

SMBus target receiver

When the I ² C is used in SMBus mode, SBC must be programmed to '1' in order to allow the PEC checking at the end of the programmed number of data bytes. In order to allow the ACK control of each byte, the reload mode must be selected (RELOAD=1).

Refer to Section 19.4.7: I2C target mode "target bite control mode" for more details.

In order to check the PEC byte, the RELOAD bit must be cleared and the PECBYTE bit must be set. In this case, after NBYTES-1 data have been received, the next received byte is compared with the internal I2C_PECR register content. A NACK is automatically generated if the comparison does not match, and an ACK is automatically generated if the comparison matches, whatever the ACK bit value. Once the PEC byte is received, it is copied into the I2C_RXDR register like any other data, and the RXNE flag is set.

In the case of a PEC mismatch, the PECERR flag is set and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

If no ACK software control is needed, you can program PECBYTE=1 and, in the same write operation, program NBYTES with the number of bytes to be received in a continuous flow. After NBYTES-1 are received, the next received byte is checked as being the PEC.

Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

Figure 108. Transfer sequence flowchart for SMBus target receiver N bytes + PEC

graph TD
    Start([SMBus target reception]) --> Init[Target initialization]
    Init --> ADDR{I2C_ISR.ADDR = 1?}
    ADDR -- No --> ADDR
    ADDR -- Yes --> ReadAddr[Read ADDCODE and DIR in I2C_ISR
I2C_CR2.NBYTES = 1, RELOAD = 1
PECBYTE=1
Set I2C_ICR.ADDRCF]
    ReadAddr --> RXNE{I2C_ISR.RXNE = 1?
I2C_ISR.TCR = 1?}
    RXNE -- No --> RXNE
    RXNE -- Yes --> ReadData1[Read I2C_RXDR.RXDATA
Program I2C_CR2.NACK = 0
I2C_CR2.NBYTES = 1
N = N - 1]
    ReadData1 --> N1{N = 1?}
    N1 -- No --> RXNE
    N1 -- Yes --> ReadData2[Read I2C_RXDR.RXDATA
Program RELOAD = 0
NACK = 0 and NBYTES = 1]
    ReadData2 --> RXNE2{I2C_ISR.RXNE = 1?}
    RXNE2 -- No --> RXNE2
    RXNE2 -- Yes --> ReadData3[Read I2C_RXDR.RXDATA]
    ReadData3 --> End([End])
  

Figure 109. Bus transfer diagrams for SMBus target receiver (SBC=1)

EV1: ADDR ISR: check ADDCODE and DIR, program NBYS = 3, PECBYTE=1, RELOAD=0, set ADDRCF
EV2: RXNE ISR: rd data1
EV3: RXNE ISR: rd data2
EV4: RXNE ISR: rd PEC

EV1: ADDR ISR: check ADDCODE and DIR, program NBYS = 1, PECBYTE=1, RELOAD=1, set ADDRCF
EV2: RXNE-TCR ISR: rd data1, program NACK=0 and NBYS = 1
EV3: RXNE-TCR ISR: rd data2, program NACK=0, NBYS = 1 and RELOAD=0
EV4: RXNE-TCR ISR: rd PEC

This section is relevant only when the SMBus feature is supported. Refer to Section 19.3: I2C implementation . In addition to I ² C controller transfer management (refer to Section 19.4.8: I2C controller mode ) some additional software flowcharts are provided to support SMBus.

SMBus controller transmitter

When the SMBus controller wants to transmit the PEC, the PECBYTE bit must be set and the number of bytes must be programmed in the NBYS[7:0] field, before setting the START bit. In this case, the total number of TXIS interrupts is NBYS-1. So, if the PECBYTE bit is set when NBYS=0x1, the content of the I2C_PECR register is automatically transmitted.

If the SMBus controller wants to send a STOP condition after the PEC, the automatic end mode should be selected (AUTOEND=1). In this case, the STOP condition automatically follows the PEC transmission.

When the SMBus controller wants to send a RESTART condition after the PEC, software mode must be selected (AUTOEND=0). In this case, once NBYS-1 have been transmitted, the I2C_PECR register content is transmitted and the TC flag is set after the PEC transmission, stretching the SCL line low. The RESTART condition must be programmed in the TC interrupt subroutine.

Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

Figure 110. Bus transfer diagrams for SMBus controller transmitter

Example SMBus controller transmitter 2 bytes + PEC, automatic end mode (STOP)

INIT: program target address, program NBYTES = 3, AUTOEND=1, set PECBYTE, set START
EV1: TXIS ISR: wr data1
EV2: TXIS ISR: wr data2

Example SMBus controller transmitter 2 bytes + PEC, software end mode (RESTART)

INIT: program target address, program NBYTES = 3, AUTOEND=0, set PECBYTE, set START
EV1: TXIS ISR: wr data1
EV2: TXIS ISR: wr data2
EV3: TC ISR: program target address, program NBYTES = N, set START

SMBus controller receiver

When the SMBus controller wants to receive the PEC followed by a STOP at the end of the transfer, an automatic end mode can be selected (AUTOEND=1). The PECBYTE bit must be set and the target address must be programmed, before setting the START bit. In this case, after NBYTES-1 data have been received, the next received byte is automatically checked versus the I2C_PECR register content. A NACK response is given to the PEC byte, followed by a STOP condition.

When the SMBus controller receiver wants to receive the PEC byte followed by a RESTART condition at the end of the transfer, software mode must be selected (AUTOEND=0). The PECBYTE bit must be set and the target address must be programmed, before setting the START bit. In this case, after NBYTES-1 data have been received, the next received byte is automatically checked versus the I2C_PECR register content. The TC flag is set after the PEC byte reception, stretching the SCL line low. The RESTART condition can be programmed in the TC interrupt subroutine.

Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

Figure 111. Bus transfer diagrams for SMBus controller receiver

Example SMBus controller receiver 2 bytes + PEC, automatic end mode (STOP)

INIT: program target address, program NBYS = 3, AUTOEND=1, set PECBYTE, set START
EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2
EV3: RXNE ISR: rd PEC

Example SMBus controller receiver 2 bytes + PEC, software end mode (RESTART)

INIT: program target address, program NBYS = 3, AUTOEND=0, set PECBYTE, set START
EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2
EV3: RXNE ISR: read PEC
EV4: TC ISR: program target address, program NBYS = N, set START

19.4.14 Error conditions

The following are error conditions which may cause communication to fail.

Bus error (BERR)

A bus error is detected when a START or a STOP condition is detected and is not located after a multiple of nine SCL clock pulses. A START or a STOP condition is detected when an SDA edge occurs while SCL is high.

The bus error flag is set only if the I ² C is involved in the transfer as controller or addressed target (i.e. not during the address phase in target mode).

In case of a misplaced START or RESTART detection in target mode, the I ² C enters an address recognition state like for a correct START condition.

When a bus error is detected, the BERR flag is set in the I2C_ISR register, and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

Arbitration loss (ARLO)

An arbitration loss is detected when a high level is sent on the SDA line, but a low level is sampled on the SCL rising edge.

• • In controller mode, arbitration loss is detected during the address phase, data phase and data acknowledge phase. In this case, the SDA and SCL lines are released. The START control bit is cleared by hardware and the controller switches automatically to target mode.
• • In target mode, arbitration loss is detected during data phase and data acknowledge phase. In this case, the transfer is stopped, and the SCL and SDA lines are released.

When an arbitration loss is detected, the ARLO flag is set in the I2C_ISR register, and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

Overrun/underrun error (OVR)

An overrun or underrun error is detected in target mode when NOSTRETCH=1 and:

• • In reception when a new byte is received and the RXDR register has not been read yet. The new received byte is lost, and a NACK is automatically sent as a response to the new byte.
• • In transmission:
  • – When STOPF=1 and the first data byte should be sent. The content of the I2C_TXDR register is sent if TXE=0, 0xFF if not.
  • – When a new byte should be sent and the I2C_TXDR register has not been written yet, 0xFF is sent.

When an overrun or underrun error is detected, the OVR flag is set in the I2C_ISR register, and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

Packet Error Checking Error (PECERR)

This section is relevant only when the SMBus feature is supported. Refer to Section 19.3: I2C implementation .

A PEC error is detected when the received PEC byte does not match with the I2C_PECR register content. A NACK is automatically sent after the wrong PEC reception.

When a PEC error is detected, the PECERR flag is set in the I2C_ISR register, and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

Timeout Error (TIMEOUT)

This section is relevant only when the SMBus feature is supported. Refer to Section 19.3: I2C implementation .

A timeout error occurs for any of these conditions:

• • TIDLE=0 and SCL remained low for the time defined in the TIMEOUTA[11:0] bits: this is used to detect a SMBus timeout
• • TIDLE=1 and both SDA and SCL remained high for the time defined in the TIMEOUTA [11:0] bits: this is used to detect a bus idle condition
• • Controller cumulative clock low extend time reached the time defined in the TIMEOUTB[11:0] bits (SMBus tLOW:MEXTparameter)
• • Target cumulative clock low extend time reached the time defined in TIMEOUTB[11:0] bits (SMBus tLOW:SEXTparameter).

When a timeout violation is detected in controller mode, a STOP condition is automatically sent.

When a timeout violation is detected in target mode, the SDA and SCL lines are automatically released.

When a timeout error is detected, the TIMEOUT flag is set in the I2C_ISR register, and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

Alert (ALERT)

This section is relevant only when the SMBus feature is supported. Refer to Section 19.3: I2C implementation .

The ALERT flag is set when the I ² C interface is configured as a host (SMBHEN=1), the alert pin detection is enabled (ALERTEN=1) and a falling edge is detected on the SMBA pin. An interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

19.4.15 DMA requests

Transmission using DMA

DMA (Direct Memory Access) can be enabled for transmission by setting the TXDMAEN bit in the I2C_CR1 register. Data is loaded from an SRAM area configured using the DMA peripheral (see Section 10: DMA controller (DMA) ) to the I2C_TXDR register whenever the TXIS bit is set.

Only the data are transferred with DMA.

• • In controller mode: the initialization, the target address, direction, number of bytes and START bit are programmed by software (the transmitted target address cannot be transferred with DMA). When all data is transferred using DMA, the DMA must be initialized before setting the START bit. The end of transfer is managed with the NBYPES counter.
• • In target mode:
  • – With NOSTRETCH=0, when all data are transferred using DMA, the DMA must be initialized before the address match event, or in ADDR in the the interrupt subroutine, before clearing ADDR
  • – With NOSTRETCH=1, the DMA must be initialized before the address match event.
• • For instances supporting SMBus: the PEC transfer is managed with NBYPES counter.

Refer to Section 19.4.13: SMBus target mode "SMBus target transmitter" and "SMBus controller transmitter" for more details.

Note: If DMA is used for transmission, the TXIE bit does not need to be enabled.

Reception using DMA

DMA (direct memory access) can be enabled for reception by setting the RXDMAEN bit in the I2C_CR1 register. Data is loaded from the I2C_RXDR register to an SRAM area configured using the DMA peripheral (refer to Section 10: DMA controller (DMA) ) whenever the RXNE bit is set. Only the data (including PEC) are transferred with DMA.

• • In controller mode, the initialization, the target address, direction, number of bytes and START bit are programmed by software. When all data is transferred using DMA, the DMA must be initialized before setting the START bit. The end of transfer is managed with the NBYTES counter.
• • In target mode with NOSTRETCH=0, when all data are transferred using DMA, the DMA must be initialized before the address match event, or in the ADDR interrupt subroutine, before clearing the ADDR flag.
• • If SMBus is supported (see Section 19.3: I2C implementation ): the PEC transfer is managed with the NBYTES counter.

Note: If DMA is used for reception, the RXIE bit does not need to be enabled.

19.5 I2C interrupts

The table below gives the list of I ² C interrupt requests.

Table 58. I ² C interrupt requests

Depending on the product implementation, all these interrupt events can either share the same interrupt vector (I ² C global interrupt), or be grouped into two interrupt vectors (I ² C event interrupt and I ² C error interrupt). In order to enable the I ² C interrupts, the following sequence is required:

• • Configure and enable the I ² C IRQ channel in the NVIC
• • Configure the I ² C to generate interrupts

Figure 112. I ² C interrupt mapping diagram

19.6 I2C registers

Refer to Section 1.5: Acronyms for a list of abbreviations used in register descriptions. The peripheral registers are accessed by words (32-bit).

19.6.1 Control register 1 (I2C_CR1)

Address offset: 0x00 Reset value: 0x0000 0000

Access: no wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to \( 2 \times PCLK1 + 6 \times I2CCLK \) .

19.6.2 Control register 2 (I2C_CR2)

Address offset: 0x04

Reset value: 0x0000 0000

Access: no wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK.

19.6.3 Own address 1 register (I2C_OAR1)

Address offset: 0x08

Reset value: 0x0000 0000

Access: no wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to \( 2 \times PCLK1 + 6 \times I2CCLK \) .

19.6.4 Own address 2 register (I2C_OAR2)

Address offset: 0x0C

Reset value: 0x0000 0000

Access: no wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to \( 2 \times PCLK1 + 6 \times I2CCLK \) .

19.6.5 Timing register (I2C_TIMINGR)

Address offset: 0x10

Reset value: 0x0000 0000

Access: no wait states

Note: This register must be configured when the I ² C is disabled (PE = 0).

19.6.6 Timeout register (I2C_TIMEOUTR)

Address offset: 0x14

Reset value: 0x0000 0000

Access: no wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to \( 2 \times PCLK1 + 6 \times I2CCLK \) .

Note: If the SMBus feature is not supported, this register is reserved and forced by hardware to "0x00000000". Refer to Section 19.3: I2C implementation.

19.6.7 Interrupt and status register (I2C_ISR)

Address offset: 0x18

Reset value: 0x0000 0001

Access: no wait states

19.6.8 Interrupt clear register (I2C_ICR)

Address offset: 0x1C

Reset value: 0x0000 0000

Access: no wait states

19.6.9 PEC register (I2C_PECR)

Address offset: 0x20

Reset value: 0x0000 0000

Access: no wait states

Note: If the SMBus feature is not supported, this register is reserved and forced by hardware to “0x00000000”. Refer to Section 19.3: I2C implementation.

19.6.10 Receive data register (I2C_RXDR)

Address offset: 0x24

Reset value: 0x0000 0000

Access: no wait states

19.6.11 Transmit data register (I2C_TXDR)

Address offset: 0x28

Reset value: 0x0000 0000

Access: no wait states

19.6.12 I2C register map

The table below provides the I ² C register map and reset values.

Table 59. I ² C register map

Refer to Table 3. STM32WB07xC and STM32WB06xC memory map and peripheral register boundary addresses for the register boundary addresses.