16. Advanced-control timers (TIM1)

In this section, “TIMx” should be understood as “TIM1” since there is only one instance of this timer in the STM32WB07xC and STM32WB06xC devices.

16.1 TIM1 introduction

The advanced-control timers (TIM1) consist of a 16-bit auto-reload counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with deadtime insertion).

Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler on the timer input clock which is at 64 MHz.

16.2 TIM1 main features

TIM1 timer features include:

• • 16-bit up, down, up/down auto-reload counter
• • 16-bit programmable prescaler allowing dividing (also “on-the-fly”) the counter clock frequency either by any factor between 1 and 65536
• • Up to 6 independent channels for:
  • – Input capture (except channels 5 and 6)
  • – Output compare
  • – PWM generation (edge and center-aligned mode)
  • – One-pulse mode output
• • Complementary outputs with programmable deadtime
• • Synchronization circuit to control the timer with external signals
• • Repetition counter to update the timer registers only after a given number of cycles of the counter
• • 2 break inputs to put the timer output signals in a safe user selectable configuration
• • Interrupt generation on the following events:
  • – Update: counter overflow/underflow, counter initialization (by software or internal/external trigger)
  • – Trigger event (counter start, stop, initialization or count by internal/external trigger)
  • – Input capture
  • – Output compare
• • Supports incremental (quadrature) encoder for positioning purposes
• • Trigger input for external clock or cycle-by-cycle current management.

Figure 28. Advanced-control timer block diagram

Notes:

Reg Preload registers transferred to active registers on U event according to control bit

Event

Interrupt & DMA output

DT58432/V1

16.3 TIM1 functional description

16.3.1 Time-base unit

The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

• • Counter register(TIMx_CNT)
• • Prescaler register(TIMx_PSC)
• • Auto-reload register(TIMx_ARR)
• • Repetition counter register(TIMx_RCR)

The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The contents of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow (or underflow when down-counting) and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration.

The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling).

Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register.

Prescaler description

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on-the-fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.

Figure 29. Counter timing diagram with prescaler division change from 1 to 2 and Figure 30. Counter timing diagram with prescaler division change from 1 to 4 give some examples of the counter behavior when the prescaler ratio is changed on-the-fly

Figure 29. Counter timing diagram with prescaler division change from 1 to 2

Figure 30. Counter timing diagram with prescaler division change from 1 to 4

16.3.2

Counter modes

Up-counting mode

In up-counting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

If the repetition counter is used, the update event (UEV) is generated after up-counting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR) + 1. Otherwise, the update event is generated at each counter overflow.

Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event.

The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit):

• • The repetition counter is reloaded with the content of TIMx_RCR register
• • The auto-reload shadow register is updated with the preload value (TIMx_ARR)
• • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.

Figure 31. Counter timing diagram, internal clock divided by 1

Figure 32. Counter timing diagram, internal clock divided by 2

Figure 33. Counter timing diagram, internal clock divided by 4

Figure 34. Counter timing diagram, internal clock divided by N

Figure 35. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)

Figure 36. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)

Down-counting mode

In down-counting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event.

If the repetition counter is used, the update event (UEV) is generated after down-counting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR) +1. Otherwise, the update event is generated at each counter underflow.

Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event.

The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate does not change).

In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit):

• • The repetition counter is reloaded with the content of TIMx_RCR register
• • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register)
• • The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one.

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.

Figure 37. Counter timing diagram, internal clock divided by 1

Figure 38. Counter timing diagram, internal clock divided by 2

Figure 39. Counter timing diagram, internal clock divided by 4

Figure 40. Counter timing diagram, internal clock divided by N

Figure 41. Counter timing diagram, update event when repetition counter is not used

Center-aligned mode (up/down-counting)

In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto-reload value down to 1 and generates a counter underflow event. Then it restarts counting from 0.

Center-aligned mode is active when the CMS bits in TIMx_CR1 register is not equal to '00'. The output compare interrupt flag of channels configured in output is set when: the counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3, CMS = "11").

In this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated by hardware and gives the current direction of the counter.

The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from 0, as well as the counter of the prescaler.

The UEV update event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value.

In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates a UEV update event but without setting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit):

• • The repetition counter is reloaded with the content of TIMx_RCR register
• • The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register)
• • The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that if the update source is a counter overflow, the auto-reload is updated before the counter is reloaded, so that the next period is the expected one (the counter is loaded with the new value).

The following figures show some examples of the counter behavior for different clock frequencies.

Figure 42. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6

Note: Here, center-aligned mode 1 is used (for more details refer to Section 16.4: TIM1 registers).

Figure 43. Counter timing diagram, internal clock divided by 2

Figure 44. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

Figure 45. Counter timing diagram, internal clock divided by N

Figure 46. Counter timing diagram, update event with ARPE=1 (counter underflow)

Figure 47. Counter timing diagram, update event with ARPE=1 (counter overflow)

16.3.3

Repetition counter

Section 16.3.1: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows/underflows. It is actually generated only when the repetition counter has reached zero. This can be useful when generating PWM signals.

This means that data are transferred from the preload registers to the shadow registers (TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx capture/compare registers in compare mode) every N+1 counter overflows or underflows, where N is the value in the TIMx_RCR repetition counter register.

The repetition counter is decremented:

• • At each counter overflow in up-counting mode
• • At each counter underflow in down-counting mode
• • At each counter overflow and at each counter underflow in center-aligned mode. Although this limits the maximum number of repetition to 32768 PWM cycles, it makes it possible to update the duty cycle twice per PWM period. When refreshing compare registers only once per PWM period in center-aligned mode, maximum resolution is \( 2 \times T_{ck} \) , due to the symmetry of the pattern.

The repetition counter is an auto-reload type; the repetition rate is maintained as defined by the TIMx_RCR register value (refer to Figure 48. Update rate examples depending on mode and TIMx_RCR register settings).

When the update event is generated by software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave mode controller, it occurs immediately whatever the value of the repetition counter is and the repetition counter is reloaded with the content of the TIMx_RCR register.

In center-aligned mode, for odd values of RCR, the update event occurs either on the overflow or on the underflow depending on when the RCR register was written and when the counter was launched: if the RCR was written before launching the counter, the UEV occurs on the overflow. If the RCR was written after launching the counter, the UEV occurs on the underflow.

For example, for RCR = 3, the UEV is generated each 4 ^th overflow or underflow event depending on when the RCR was written.

Figure 48. Update rate examples depending on mode and TIMx_RCR register settings

16.3.4 External trigger input

The timer features an external trigger input ETR. It can be used as:

• • External clock (external clock mode 2, see Section 16.3.5 )
• • Trigger for the slave mode (see Section 16.4: TIM1 registers )
• • PWM reset input for cycle-by-cycle current regulation Section 16.3.17: Clearing the OCxREF signal on an external event ).

Figure 49. External trigger input block below describes the ETR input conditioning. The input polarity is defined with the ETP bit in TIMx_SMCR register. The trigger can be prescaled with the divider programmed by the ETPS[1:0] bit field and digitally filtered with the ETF[3:0] bit field.

Figure 49. External trigger input block

The ETR input comes from input pins (see Table 8. GPIO alternate options AF3 - AF4 and Table 9. I/O analog feature mapping ).

16.3.5 Clock selection

The counter clock can be provided by the following clock sources:

• • Internal clock (CK_INT)
• • External clock mode1: external input pin

Note: Only channel 1 and channel 2 support the external clock mode 1.

• • External clock mode 2: external trigger input ETR
• • Encoder mode.

Internal clock source (CK_INT)

If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.

Figure 50. Control circuit in normal mode, internal clock divided by 1 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.

Figure 50. Control circuit in normal mode, internal clock divided by 1

External clock source mode 1

This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input.

Figure 51. TI2 external clock connection example

For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure:

1. 1. Select the proper TI2x source (internal or external) with the TI2SEL[3:0] bits in the TIMx_TISEL register.
2. 2. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = '01' in the TIMx_CCMR1 register.

1. 3. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000).
2. 4. Select rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER register.
3. 5. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register.
4. 6. Select TI2 as the trigger input source by writing TS=110 in the TIMx_SMCR register.
5. 7. Enable the counter by writing CEN=1 in the TIMx_CR1 register.

Note: The capture prescaler is not used for triggering, so you do not need to configure it.

When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.

The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input.

Figure 52. Control circuit in external clock mode 1

External clock source mode 2

This mode is selected by writing ECE=1 in the TIMx_SMCR register.

The counter can count at each rising or falling edge on the external trigger input ETR.

Shown below in Figure 53. External trigger input block.

Figure 53. External trigger input block

For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure:

1. 1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
2. 2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register.
3. 3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register.
4. 4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5. 5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.

The counter counts once each 2 ETR rising edges.

The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal.

Figure 54. Control circuit in external clock mode 2

16.3.6 Capture/compare channels

Each capture/compare channel is built around a capture/compare register (including a shadow register), an input stage for capture (with digital filter, multiplexing, and prescaler, except for channels 5 and 6) and an output stage (with comparator and output control).

Figure 55. Capture/compare channel (example: channel 1 input stage) to Figure 58. Output stage of capture/compare channel (channel 4) give an overview of one capture/compare channel.

The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS).

Figure 55. Capture/compare channel (example: channel 1 input stage)

The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain.

Figure 56. Capture/compare channel 1 main circuit

Figure 57. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3)

Note: OCxREF, where x is the rank of the complementary channel.

Figure 58. Output stage of capture/compare channel (channel 4)

Figure 59. Output stage of capture/compare channel (channel 5, idem ch.6)

The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register.

In capture mode, captures are actually done in the shadow register, which is copied into the preload register.

In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter.

16.3.7 Input capture mode

In input capture mode, the capture/compare registers ( TIMx_CCRx ) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCxIF flag ( TIMx_SR register) is set and an interrupt can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the overcapture flag CCxOF ( TIMx_SR register) is set. CCxIF can be cleared by software by writing it to '0' or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to '0'.

The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure:

• • Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input and the TIMx_CCR1 register becomes read-only.
• • Program the input filter duration you need with respect to the signal you connect to the timer (when the input is one of the TIx ( ICxF bits in the TIMx_CCMRx register). Imagine that, when toggling, the input signal is not stable during, at most, 5 internal clock cycles. A filter duration longer than these 5 clock cycles must be programmed. A transition on TI1 can be validated when 8 consecutive samples with the new level have been detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register.
• • Select the edge of the active transition on the TI1 channel by writing CC1P and CC1NP bits to 0 in the TIMx_CCER register (rising edge in this case).
• • Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to '00' in the TIMx_CCMR1 register).
• • Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register.
• • If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register. When an input capture occurs:
  • – The TIMx_CCR1 register gets the value of the counter on the active transition.
  • – CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared.
  • – An interrupt is generated depending on the CC1IE bit.

In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data.

Note: IC interrupt can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register.

16.3.8 PWM input mode

Note: Only channel 1 and channel 2 support this PWM input mode.

This mode is a particular case of input capture mode. The procedure is the same except:

• • Two ICx signals are mapped on the same TIx input
• • These 2 ICx signals are active on edges with opposite polarity
• • One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode.

For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value):

• • Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected).
• • Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P and CC1NP bits to '0' (active on rising edge).
• • Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1 selected).
• • Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P and CC2NP bits to CC2P/CC2NP='10' (active on falling edge).
• • Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register (TI1FP1 selected).
• • Configure the slave mode controller in reset mode: write the SMS bits to 0100 in the TIMx_SMCR register.
• • Enable the captures: write the CC1E and CC2E bits to '1' in the TIMx_CCER register.

Figure 60. PWM input mode timing

16.3.9 Forced output mode

In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter.

To force an output compare signal (OCXREF/OCx) to its active level, you just need to write 0101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus, OCXREF is forced high (OCxREF is always active high) and OCx gets an opposite value to CCxP polarity bit.

For example: CCxP=0 (OCx active high) => OCx is forced to high level.

The OCxREF signal can be forced low by writing the OCxM bits to 0100 in the TIMx_CCMRx register.

Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt can be sent accordingly. This is described in the output compare mode section below.

16.3.10 Output compare mode

This function is used to control an output waveform or indicate when a period of time has elapsed. Channels 1 to 6 can be output.

When a match is found between the capture/compare register and the counter, the output compare function:

• • Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCxM=0000), be set active (OCxM=0001), be set inactive (OCxM=0010) or can toggle (OCxM=0011) on match.
• • Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).
• • Generates an interrupt if the corresponding interrupt mask is set (CCxIE bit in the TIMx_DIER register).

The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register.

In output compare mode, the update event UEV has no effect on OCxREF and OCx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in one-pulse mode).

Procedure:

1. 1. Select the counter clock (internal, external, prescaler)
2. 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3. 3. Set the CCxIE bit if an interrupt request is to be generated.
4. 4. Select the output mode. For example:
   1. a. Write OCxM = 0011 to toggle OCx output pin when CNT matches CCRx
   2. b. Write OCxPE = 0 to disable preload register
   3. c. Write CCxP = 0 to select active high polarity
   4. d. Write CCxE = 1 to enable the output
5. 5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.

The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE='0', otherwise the TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 61. Output compare mode, toggle on OC1

Figure 61. Output compare mode, toggle on OC1

16.3.11 PWM mode

Pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.

The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing ‘0110’ (PWM mode 1) or ‘0111’ (PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in up-counting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.

As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register.

OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by a combination of the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers). Refer to the TIMx_CCER register description for more details.

In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether \( TIMx\_CCRx \leq TIMx\_CNT \) or \( TIMx\_CNT \leq TIMx\_CCRx \) (depending on the direction of the counter).

The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register.

PWM edge-aligned mode

• • Up-counting configuration

Up-counting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Section 16.3.2: Counter modes .

In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as \( TIMx\_CNT < TIMx\_CCRx \) , otherwise it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’.

Figure 62. Edge-aligned PWM waveforms (ARR=8) shows some edge-aligned PWM waveforms in an example where TIMx_ARR=8.

Figure 62. Edge-aligned PWM waveforms (ARR=8)

• • Down-counting configuration

Down-counting is active when DIR bit in TIMx_CR1 register is high. Refer to Section 16.3.2: Counter modes .

In PWM mode 1, the reference signal OCxRef is low as long as \( TIMx\_CNT > TIMx\_CCRx \) else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM is not possible in this mode.

PWM center-aligned mode

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from '00' (all the remaining configurations having the same effect on the OCxRef/OCx signals). The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to Section 16.3.2: Counter modes.

Figure 63. Center-aligned PWM waveforms (ARR=8) shows some center-aligned PWM waveforms in an example where:

• • TIMx_ARR=8
• • PWM mode is the PWM mode 1
• • The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register.

Figure 63. Center-aligned PWM waveforms (ARR=8)

Hints on using center-aligned mode

• • When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software.

• • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. In particular:
  1. 1. The direction is not updated if you write a value in the counter that is greater than the auto-reload value (TIMx_CNT > TIMx_ARR). For example, if the counter was counting up, it continues to count up.
  2. 2. The direction is updated if you write 0 or write the TIMx_ARR value in the counter but no Update Event UEV is generated.
• • The safest way to use center-aligned mode is to generate an update by software (setting the UG bit in the TIMx_EGR register) just before starting the counter and not to write the counter while it is running.

16.3.12 Asymmetric PWM mode

Asymmetric mode allows two center-aligned PWM signals to be generated with a programmable phase-shift. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and the phase-shift are determined by a pair of TIMx_CCRx registers. One register controls the PWM during up-counting, the second during down-counting, so that PWM is adjusted every half PWM cycle:

• • OC1REFC (or OC2REFC) is controlled by TIMx_CCR1 and TIMx_CCR2
• • OC3REFC (or OC4REFC) is controlled by TIMx_CCR3 and TIMx_CCR4

Asymmetric PWM mode can be selected independently on two channels (one OCx output per pair of CCR registers) by writing '1110' (asymmetric PWM mode 1) or '1111' (asymmetric PWM mode 2) in the OCxM bits in the TIMx_CCMRx register.

Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones.

When a given channel is used as asymmetric PWM channel, its complementary channel can also be used. For instance, if an OC1REFC signal is generated on channel 1 (asymmetric PWM mode 1), it is possible to output either the OC2REF signal on channel 2, or an OC2REFC signal resulting from asymmetric PWM mode 1.

Figure 64. Generation of 2 phase-shifted PWM signals with 50% duty cycle represents an example of signals that can be generated using the asymmetric PWM mode (channels 1 to 4 are configured in asymmetric PWM mode 1). Together with the deadtime generator, this allows a full-bridge phase-shifted DC to DC converter to be controlled.

Figure 64. Generation of 2 phase-shifted PWM signals with 50% duty cycle

16.3.13 Combined PWM mode

Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase-shift between respective pulses. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and delay are determined by the two TIMx_CCRx registers. The resulting signals, OCxREFC, are made of an OR or AND logical combination of two reference PWMs:

• • OC1REFC (or OC2REFC) is controlled by TIMx_CCR1 and TIMx_CCR2
• • OC3REFC (or OC4REFC) is controlled by TIMx_CCR3 and TIMx_CCR4

Combined PWM mode can be selected independently on two channels (one OCx output per pair of CCR registers) by writing '1100' (combined PWM mode 1) or '1101' (combined PWM mode 2) in the OCxM bits in the TIMx_CCMRx register.

When a given channel is used as combined PWM channel, its complementary channel must be configured in the opposite PWM mode (for instance, one in combined PWM mode 1 and the other in combined PWM mode 2).

Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones.

Figure 65. Combined PWM mode on channel 1 and 3 represents an example of signals that can be generated using the asymmetric PWM mode, obtained with the following configuration:

• • Channel 1 is configured in combined PWM mode 2

• • Channel 2 is configured in PWM mode 1
• • Channel 3 is configured in combined PWM mode 2
• • Channel 4 is configured in PWM mode 1.

Figure 65. Combined PWM mode on channel 1 and 3

16.3.14 Combined 3-phase PWM mode

Combined 3-phase PWM mode allows one to three center-aligned PWM signals to be generated with a single programmable signal ANDed in the middle of the pulses. The OC5REF signal is used to define the resulting combined signal. The 3-bit GC5C[3:1] in the TIMx_CCR5 allows the selection on which reference signal the OC5REF is combined. The resulting signals, OCxREFC, are made of an AND logical combination of two reference PWMs:

• • If GC5C1 is set, OC1REFC is controlled by TIMx_CCR1 and TIMx_CCR5
• • If GC5C2 is set, OC2REFC is controlled by TIMx_CCR2 and TIMx_CCR5
• • If GC5C3 is set, OC3REFC is controlled by TIMx_CCR3 and TIMx_CCR5

Combined 3-phase PWM mode can be selected independently on channels 1 to 3 by setting at least one of the 3-bits GC5C[3:1].

Figure 66. 3-phase combined PWM signals with multiple trigger pulses per period

16.3.15 Complementary outputs and deadtime insertion

The advanced-control timers (TIM1) can output two complementary signals and manage the switching-off and the switching-on instants of the outputs.

Note: This feature concerns channels 1 to 4 only.

This time is generally known as the deadtime and you have to adjust it depending on the devices you have connected to the outputs and their characteristics (intrinsic delays of level-shifters, delays due to power switches...)

You can select the polarity of the outputs (main output OCx or complementary OCxN) independently for each output. This is done by writing to the CCxP and CCxNP bits in the TIMx_CCER register.

The complementary signals OCx and OCxN are activated by a combination of several control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx, OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers.

Refer to Table 44. Output control bits for complementary OCx and OCxN channels with break feature for more details. In particular, the deadtime is activated when switching to the idle-state (MOE falling down to 0).

The deadtime insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. There is one 10-bit deadtime generator for each channel. From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high:

• • The OCx output signal is the same as the reference signal except for the rising edge, which is delayed relative to the reference rising edge
• • The OCxN output signal is the opposite of the reference signal except for the rising edge, which is delayed relative to the reference falling edge

If the delay is greater than the width of the active output (OCx or OCxN) then the corresponding pulse is not generated.

The following figures show the relationships between the output signals of the deadtime generator and the reference signal OCxREF (we suppose CCxP=0, CCxNP=0, MOE=1, CCxE=1 and CCxNE=1 in these examples).

Figure 67. Complementary output with deadtime insertion

Figure 68. Deadtime waveforms with delay greater than the negative pulse

Figure 69. Deadtime waveforms with delay greater than the positive pulse

The deadtime delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 16.4.18: TIM1 break and deadtime register (TIMx_BDTR) for delay calculation.

Re-directing OCxREF to OCx or OCxN

In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER register.

This allows you to send a specific waveform (such as PWM or static active level) on one output while the complementary remains in its inactive level. Other alternative possibilities are to have both outputs at inactive level or both outputs active and complementary with deadtime.

Note: When OCxN is enabled (CCxE=0, CCxNE=1) only, it is not complemented and becomes active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes active when OCxREF is high whereas OCxN is complemented and becomes active when OCxREF is low.

16.3.16 Using the break function

The purpose of the break function is to protect power switches driven by PWM signals generated with the TIM1 timer. The break inputs are usually connected to fault outputs of power stages and 3-phase inverters. When activated, the break circuitry shuts down the PWM outputs and forces them to a predefined safe state.

The break features two channels which gather the application fault from input pins. A break2 channel is able to force the outputs to an inactive state. The output enable signal and output levels during break depend on several control bits:

• the MOE bit in TIMx_BDTR register allows the outputs to be enabled/disabled by software and is reset in case of break or break2 event

• the OSSI bit in the TIMx_BDTR register defines whether the timer controls the output in inactive state or releases the control to the GPIO controller (typically to have it in Hi-Z mode)
• the OISx and OISxN bits in the TIMx_CR2 register which are setting the output shutdown level, either active or inactive. The OCx and OCxN outputs cannot be set both to active level at a given time, whatever the OISx and OISxN values. Refer to Table 44. Output control bits for complementary OCx and OCxN channels with break feature for more details.

When exiting from reset, the break circuit is disabled and the MOE bit is low. The break functions are globally enabled by setting the BKE and BKE2 bits in the TIMx_BDTR register. The break input global polarities can be selected by configuring the BKP and BKP2 bits in the TIMx_BDTR register. BKEx and BKPx can be modified at the same time. When the BKEx and BKPx bits are written, a delay of 1 APB clock cycle is applied before the writing is effective. Consequently, it is necessary to wait for 1 APB clock period to correctly read back the bit after the write operation.

Note: Since MOE falling edge can be asynchronous, a resynchronization circuit has been inserted between the actual signal (acting on the outputs) and the synchronous control bit (accessed in the TIMx_BDTR register). It results in some delays between the asynchronous and the synchronous signals. In particular, if you write MOE to 1 whereas it was low, you must insert a delay (dummy instruction) before reading it correctly. This is because you write the asynchronous signal and read the synchronous signal.

The break can be generated from multiple sources, which can be individually enabled and with programmable edge sensitivity, using the TIMx_AF1 and TIMx_AF2 registers.

Break events can also be generated by software using BG and B2G bits in the TIMx_EGR register. The software break generation using BG and B2G is active whatever the BKE and the BKE2 enable bits values.

Figure 70. Break and break2 circuitry overview

Caution

An asynchronous (clockless) operation is only guaranteed when the programmable filter is disabled. If it is enabled, a fail-safe clock mode must be used to guarantee that break events are handled.

When one of the breaks occurs (selected level on the one of the break inputs):

• The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or even releasing the control to the GPIO controller (selected by the OSSI bit). This feature functions even if the MCU oscillator is off
• Each output channel is driven with the level programmed in the OISx bit in the TIMx_CR2 register as soon as MOE=0. If OSSI=0, the timer releases the output control (taken over by the GPIO controller) while the enable output remains high

• • When complementary outputs are used:
  1. 1. The outputs are first put into an inactive state (depending on the polarity). This is done asynchronously so that it works even if no clock is provided to the timer
  2. 2. If the timer clock is still present, then the dead-time generator is reactivated in order to drive the outputs with the level programmed in the OISx and OISxN bits after a dead-time. Even in this case, OCx and OCxN cannot be driven to their active level together. Note that because of the resynchronization on MOE, the dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles)
  3. 3. If OSSI=0, the timer releases the output control (taken over by the GPIO controller which forces a Hi-Z state) otherwise the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high
• • The break status flag (BIF and B2IF bits in the TIMx_SR register) is set. An interrupt can be generated if the BIE bit in the TIMx_DIER register is set
• • If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again at the next update event UEV. This can be used to perform a regulation, for instance. Otherwise, MOE remains low until you write it to '1' again. In this case, it can be used for security and you can connect the break input to an alarm from power drivers, thermal sensors or any security components.

Note: The break inputs are active on level. Thus, the MOE cannot be set while the break input is active (neither automatically nor by software). In the meantime, the status flag BIF and B2IF cannot be cleared.

In addition to the break input and the output management, a write protection has been implemented inside the break circuit to safeguard the application. It allows you to freeze the configuration of several parameters (dead-time duration, OCx/OCxN polarities and state when disabled, OCxM configurations, break enable and polarity). You can choose from 3 levels of protection selected by the LOCK bits in the TIMx_BDTR register. Refer to Section 16.4.18: TIM1 break and deadtime register (TIMx_BDTR) . The LOCK bits can be written only once after an MCU reset.

Figure 71. Various output behavior in response to a break event on BRK (OSSI = 1) shows an example of behavior of the outputs in response to a break.

Figure 71. Various output behavior in response to a break event on BRK (OSSI = 1)

The two break inputs have different behaviors on timer outputs:

• • The BRKIN input can either disable (inactive state) or force the PWM outputs to a predefined safe state
• • BRKIN2 can only disable (inactive state) the PWM outputs.

The BRKIN has a higher priority than BRKIN2 input, as described in Table 42. Behavior of timer outputs versus BRK/BK2inputs .

Note: BRKIN2 must only be used with OSSR = OSSI = 1.

Table 42. Behavior of timer outputs versus BRK/BK2inputs

Figure 72. PWM output state following BRK and BRK2 pins assertion (OSSI=1) gives an example of OCx and OCxN output behavior in case of active signals on BRK and BRK2 inputs. In this case, both outputs have active high polarities (CCxP = CCxNP = 0 in TIMx_CCER register).

Figure 72. PWM output state following BRK and BRK2 pins assertion (OSSI=1)

Figure 73. PWM output state following BRK assertion (OSSI=0)

16.3.17 Clearing the OCxREF signal on an external event

The OCxREF signal of a given channel can be cleared when a high level is applied on the ETRF input (OCxCE enable bit in the corresponding TIMx_CCMRx register set to 1) if TIMx_SMCR.OCCS bit is set to 1.

This function can only be used in output compare and PWM modes. It does not work in forced mode.

1. 1. The external trigger prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR register set to '00'.
2. 2. The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to '0'.
3. 3. The external trigger polarity (ETP) and the external trigger filter (ETF) can be configured according to the user needs.

Figure 74. Clearing TIMx_OCxREF shows the behavior of the OCxREF signal when the ETRF input becomes high, for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in PWM mode.

Figure 74. Clearing TIMx OCxREF

Note: In case of a PWM with a 100% duty cycle (if \( CCRx > ARR \) ), then OCxREF is enabled again at the next counter overflow.

16.3.17.1 6-step PWM generation

When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Therefore the user can program in advance the configuration for the next step and change the configuration of all the channels at the same time. COM can be generated by software by setting the COM bit in the TIMx_EGR register or by hardware (on TRGI rising edge).

A flag is set when the COM event occurs (COMIF bit in the TIMx_SR register), which can generate an interrupt (if the COMIE bit is set in the TIMx_DIER register).

Figure 75. 6-step generation, COM example ( \( OSSR=1 \) ) describes the behavior of the OCx and OCxN outputs when a COM event occurs, in 3 different examples of programmed configurations.

Figure 75. 6-step generation, COM example (OSSR=1)

16.3.18 One-pulse mode

One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.

Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. You select one-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV.

A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be:

• • In up-counting: \( CNT < CCRx \leq ARR \) (in particular, \( 0 < CCRx \) )
• • In down-counting: \( CNT > CCRx \)

Figure 76. Example of one-pulse mode

For example you may want to generate a positive pulse on OC1 with a length of \( t_{PULSE} \) and after a delay of \( t_{DELAY} \) as soon as a positive edge is detected on the TI2 input pin.

Let us use TI2FP2 as trigger 1:

• • Map TI2FP2 to TI2 by writing CC2S='01' in the TIMx_CCMR1 register
• • TI2FP2 must detect a rising edge, write CC2P='0' and CC2NP='0' in the TIMx_CCER register
• • Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS='110' in the TIMx_SMCR register
• • TI2FP2 is used to start the counter by writing SMS to '110' in the TIMx_SMCR register (trigger mode).

The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler).

• • The \( t_{DELAY} \) is defined by the value written in the TIMx_CCR1 register.
• • The \( t_{PULSE} \) is defined by the difference between the auto-reload value and the compare value ( \( TIMx\_ARR - TIMx\_CCR1 \) )
• • Assume that you want to build a waveform with a transition from '0' to '1' when a compare match occurs and a transition from '1' to '0' when the counter reaches the auto-reload value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1 register. You can optionally enable the preload registers by writing OC1PE='1' in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to write the compare value in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for the external trigger event on TI2. CC1P is written to '0' in this example.

In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.

You only want 1 pulse (single mode), so you write '1' in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the repetitive mode is selected.

Particular case: OCx fast enable:

In one-pulse mode, the edge detection on TIx input sets the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. Several clock cycles are needed for these operations. The minimum delay \( t_{DELAY} \) is the minimum we can get.

If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus, without taking into account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.

16.3.19 Retriggerable one-pulse mode (OPM)

This mode allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length, but with the following differences with non-retriggerable one-pulse mode described in Section 16.3.18: One-pulse mode:

• • The pulse starts as soon as the trigger occurs (no programmable delay)
• • The pulse is extended if a new trigger occurs before the previous one is completed.

The timer must be in slave mode, with the bits SMS[3:0] = '1000' (combined reset + trigger mode) in the TIMx_SMCR register, and the OCxM[3:0] bits set to '1000' or '1001' for retriggerable OPM mode 1 or 2.

If the timer is configured in up-counting mode, the corresponding CCRx must be set to 0 (the ARR register sets the pulse length). If the timer is configured in down-counting mode, the ARR must be set to 0 (the CCRx register sets the pulse length).

Note: The OCxM[3:0] and SMS[3:0] bit fields are split into two parts for compatibility reasons, the most significant bits are not contiguous with the 3 least significant ones. In retriggerable one-pulse mode, the CCxIF flags are not significant.

Figure 77. Retriggerable one-pulse mode

16.3.20 Encoder interface mode

To select encoder interface mode write SMS='001' in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS='010' if it is counting on TI1 edges only and SMS='011' if it is counting on both TI1 and TI2 edges.

Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register. When needed, you can program the input filter as well. CC1NP and CC2NP must be kept low.

The two inputs TI1 and TI2 are used to interface to a quadrature encoder. Refer to Table 43. Counting direction versus encodersignals.

The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2 after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted, TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in TIMx_CR1 register written to '1'). The sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on TI1 only, TI2 only or both TI1 and TI2.

Encoder interface mode acts simply as an external clock with the direction selection. This means that the counter just counts continuously between 0 and the auto-reload value in the TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must configure TIMx_ARR before starting. In the same way, the capture, compare, prescaler, repetition counter, trigger output features continue to work as normal. Encoder mode and external clock mode 2 are not compatible and must not be selected together.

Note: The prescaler must be set to zero when encoder mode is enabled.

In this mode, the counter is modified automatically following the speed and the direction of the quadrature encoder and its content, therefore, it always represents the encoder position. The count direction corresponds to the rotation direction of the connected sensor. The table below summarizes the possible combinations, assuming TI1 and TI2 do not switch at the same time.

Table 43. Counting direction versus encodersignals

A quadrature encoder can be connected directly to the MCU without any external interface logic. However, comparators are normally used to convert the encoder differential outputs to digital signals. This greatly increases noise immunity. The third encoder output, which indicates the mechanical zero position, may be connected to an external interrupt input and trigger a counter reset.

Figure 78. Example of counter operation in encoder interface mode gives an example of counter operation, showing count signal generation and direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near to one of the switching points. For this example we assume that the configuration is the following:

• • CC1S='01' (TIMx_CCMR1 register, TI1FP1 mapped on TI1)
• • CC2S='01' (TIMx_CCMR2 register, TI1FP2 mapped on TI2)
• • CC1P='0' and CC1NP='0' (TIMx_CCER register, TI1FP1 non-inverted, TI1FP1=TI1)
• • CC2P='0' and CC2NP='0' (TIMx_CCER register, TI1FP2 non-inverted, TI1FP2= TI2)
• • SMS='011' (TIMx_SMCR register, both inputs are active on both rising and falling edges)
• • CEN='1' (TIMx_CR1 register, counter enabled).

Figure 78. Example of counter operation in encoder interface mode

Figure 79. Example of encoder interface mode with TI1FP1 polarity inverted gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P='1').

Figure 79. Example of encoder interface mode with TI1FP1 polarity inverted

The timer, when configured in encoder interface mode, provides some information on the sensor current position. You can obtain the dynamic information (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode (not available in the STM32WB07xC and STM32WB06xC devices). The output of the encoder, which indicates the mechanical zero, can be used for this purpose. Depending on the time between two events, the counter can also be read at regular times. You can do this by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer).

The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the update interrupt flag (UIF) into the timer counter register bit 31 (TIMxCNT[31]). This allows both the counter value and a potential roll-over condition signaled by the UIFCPY flag to be read in an atomic way. It eases the calculation of angular speed by avoiding race conditions caused, for instance, by a processing shared between a background task (counter reading) and an interrupt (update interrupt).

There is no latency between the UIF and UIFCPY flag assertions.

In 32-bit timer implementations, when the IUFREMAP bit is set, bit 31 of the counter is overwritten by the UIFCPY flag upon read access (the counter most significant bit is only accessible in write mode).

16.3.21 UIF bit remapping

The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the update interrupt flag UIF into the timer counter register bit 31 (TIMxCNT[31]). This allows both the counter value and a potential roll-over condition signaled by the UIFCPY flag to be read in an atomic way. In particular cases, it can ease the calculations by avoiding race conditions, caused for instance by a processing shared between a background task (counter reading) and an interrupt (update interrupt). There is no latency between the UIF and UIFCPY flags assertion.

16.3.22 Timer input XOR function

The TI1S bit, in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of an XOR gate, combining the two input pins TIMx_CH1 and TIMx_CH2. The XOR output can be used with all the timer input functions such as trigger or input capture. It is convenient to measure the interval between edges on two input signals, as per Figure 80. Measuring time interval between edges on 3 signals.

Figure 80. Measuring time interval between edges on 3 signals

16.4 TIM1 registers

16.4.1 TIM1 control register 1 (TIMx_CR1)

Address offset: 0x00

Reset value: 0x0000

16.4.2 TIM1 control register 2 (TIMx_CR2)

Address offset: 0x04

Reset value: 0x0000

16.4.3 TIM1 slave mode control register (TIMx_SMCR)

Address offset: 0x08

Reset value: 0x0000

16.4.4 TIM1 interrupt enable register (TIMx_DIER)

Address offset: 0x0C

Reset value: 0x0000

16.4.5 TIM1 status register (TIMx_SR)

Address offset: 0x10

Reset value: 0x0000

16.4.6 TIM1 event generation register (TIMx_EGR)

Address offset: 0x14

Reset value: 0x0000

16.4.7 TIM1 capture/compare mode register 1 (TIMx_CCMR1)

Address offset: 0x18

Reset value: 0x0000

The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So you must take care that the same bit can have a different meaning for the input stage and for the output stage.

Output compare mode:

Input capture mode

16.4.8 TIM1 capture/compare mode register 2 (TIMx_CCMR2)

Address offset: 0x1C

Reset value: 0x0000

Refer to Section 16.4.7: TIM1 capture/compare mode register 1 (TIMx_CCMR1).

Output compare mode

Input capture mode

16.4.9 TIM1 capture/compare enable register (TIMx_CCER)

Address offset: 0x20

Reset value: 0x0000

Table 44. Output control bits for complementary OCx and OCxN channels with break feature

1. When both outputs of a channel are not used (control taken over by GPIO), the OISx, OISxN, CCxP and CCxNP bits must be kept cleared.

Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels depends on the OCx and OCxN channel state and the GPIO registers.

16.4.10 TIM1 counter (TIMx_CNT)

Address offset: 0x24

Reset value: 0x0000

16.4.11 TIM1 prescaler (TIMx_PSC)

Address offset: 0x28

Reset value: 0x0000

16.4.12 TIM1 auto-reload register (TIMx_ARR)

Address offset: 0x2C

Reset value: 0xFFFF

16.4.13 TIM1 repetition counter register (TIMx_RCR)

Address offset: 0x30

Reset value: 0x0000

16.4.14 TIM1 capture/compare register 1 (TIMx_CCR1)

Address offset: 0x34

Reset value: 0x0000

Bits
15:0

16.4.15 TIM1 capture/compare register 2 (TIMx_CCR2)

Address offset: 0x38

Reset value: 0x0000

16.4.16 TIM1 capture/compare register 3 (TIMx_CCR3)

Address offset: 0x3C

Reset value: 0x0000

16.4.17 TIM1 capture/compare register 4 (TIMx_CCR4)

Address offset: 0x40

Reset value: 0x0000

16.4.18 TIM1 break and deadtime register (TIMx_BDTR)

Address offset: 0x44

Reset value: 0x0000

Note: As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on the LOCK configuration, it may be necessary to configure all of them during the first write access to the TIMx_BDTR register.

16.4.19 TIM1 capture/compare mode register 3 (TIMx_CCMR3)

Address offset: 0x54

Reset value: 0x00000000

Refer to Section 16.4.7: TIM1 capture/compare mode register 1 (TIMx_CCMR1) about the configuration of channels 5 and 6.

Output compare mode

16.4.20 TIM1 capture/compare register 5 (TIMx_CCR5)

Address offset: 0x58

Reset value: 0x0000

16.4.21 TIM1 capture/compare register 6 (TIMx_CCR6)

Address offset: 0x5C

Reset value: 0x0000

16.4.22 TIM1 alternate function option register 1 (TIMx_AF1)

Address offset: 0x60

Reset value: 0x0001

16.4.23 TIM1 alternate function option register 2 (TIMx_AF2)

Address offset: 0x64

Reset value: 0x0001

16.4.24 TIM1 register map

TIM1 registers are mapped as 16-bit addressable registers as described in the table below:

Table 45. TIM1 register map and reset values

page 313/660

Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses.