13. Random number generator (RNG)

The RNG is a random number generator based on a continuous analog noise that provides a 16-bit value to the host when read.

13.1 Features

• AHB slave peripheral
• Deliver 16-bit random number produced by an analog generator
• Minimum period of 1.25 µs (corresponding to 20 RNGCLK cycles) between two consecutive random numbers. This is automatically managed by a pulling spacer counter that adds wait-state on the AHB bus when reading occurs too closely to the previous one
• Monitoring of the entropy of the RNG to flag abnormal behavior (generation of stable values or stable sequence of values)
• 2 clock domains:
- – RNGCLK: 16 MHz for the normalization and shifter (specific serial to 16-bit parallel conversion)
- – HCLK: AHB clock (16 MHz, 32 MHz or 64 MHz) for the AHB interface
• Can be disabled to reduce power consumption.

Power consumption and RNG:

The internal free-running oscillators are quite power consuming. It is possible to stop them when the RNG is not used

• After a PORESETn, the internal free-running oscillators are stopped by default to limit consumption
• When the RNG clock tree is enabled through the RCC after a PORESETn, the oscillators are automatically restarted
• If the SW enables the RNG clock tree through the RCC, it does not stop the internal oscillator. The SW has to first set the RNG_CR[2] = RNG_DISto stop them.
• On the other side, the SW has to restart them by clearing the RNG_DISbit once the RNG clock tree is re-enabled.

13.2 RNG registers

13.2.1 RNG configuration register (RNG_CR)

Address offset: 0x00

Reset value: 0x0000

This register configures the RNG.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	TST_CLK	RNG_DIS	Res.	Res.
												nw	nw

Bits 31:4	Reserved, must be kept at reset value.
Bit 3	TST_CLK: RNG test clock bit. Writing this bit with 1b starts the logic that detects the presence of the RNG_CLK. Then wait (with a timeout of at least four RNGCLK cycles) for REVCLK = 1b in the RNG_SR register. If REVCLK = 0b after timeout elapsed, it means that RNGCLK is not present and reading RNG_VAL register triggers an AHB error response. For security reasons, software should check that the RNGCLK is present before reading random values. This bit is auto-cleared and always read as 0.
Bit 2	RNG_DIS: RNG disable bit. This bit enables or disables the random number generator. 0: RNG is enabled (default) 1: RNG is disabled. The internal free-running oscillators are put in power-down mode and the RNG clock is stopped at the input of the block.
Bits 1:0	Reserved, must be kept at reset value.

13.2.2 RNG status flag register (RNG_SR)

Address offset: 0x04

Reset value: 0x0000

This register provides status flags of the RNG.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	FAULT	REVCLK	RNGRDY
													rc_w1	r	r

Bits 31:3

Reserved, must be kept at reset value.

Bit 2

FAULT: Fault reveal bit.

This bit is set by hardware when a faulty sequence of bits occurs. The faulty sequences are:

Sequence of more than 32 consecutive bits of samevalue (0b or 1b)
Sequence of more than 16 consecutive alternation of 0band 1b (010101...01b).

Writing this bit with 1b clears it. Writing with 0b has no effect.

Bit 1	REVCLK: RNGCLK clock reveal bit. A write with 1b to bit TSTCLK in RNG_CR resets this bit. If the RNGCLK is present, this bit is 1b after four RNGCLK cycles after the end of the write to RNG_CR. If REVCLK = 0b after this period, it means the RNGCLK is not present and reading RNG_VAL triggers an AHB error response.
Bit 0	RNGRDY: New random value ready. 0: The RNG_VAL register value is not yet valid. If performing a read access to RNG_VAL, the host is on hold (by wait-states insertion on the AHB bus) until a random value is available. 1: The RNG_VAL register contains a valid random number. This bit remains at 0b when the RNG is disabled (RNGDIS bit = 1b in RNG_CR)

13.2.3 RNG value register (RNG_VAL)

Address offset: 0x08

Reset value: 0xXXXX

This register delivers a 16-bit random value when read. After being read, this register delivers a new random value only after 20 cycles of RNGCLK. If the host performs a new read before the period has elapsed, the RNG inserts a wait-state on the AHB bus.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RANDOM_VALUE
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:16	Reserved, must be kept at reset value.
Bit 15:0	RANDOM_VALUE: Random value.

13.2.4 RNG register map

Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses.

Note: Despite RNG registers being addressed through AHB, only 32-bit accesses are allowed. Any 8-bit or 16-bit access generates an AHB error leading to a hard fault on Cortex-M0+.

Table 38. RNG register list

Address offset	Name	RW ⁽¹⁾	Reset	Description
0x00	RNG_CR	RW	0x00000000	RNG configuration register. See Section 13.2: RNG registers
0x04	RNG_SR	RO	0x00000000	RNG status register. See Section 13.2: RNG registers
0x08	RNG_VAL	RO	0x00000000	RNG 16-bit random value. See Section 13.2: RNG registers

1. These acronyms have the following meaning: RW = read and write; RO = read only.