12. Analog digital converter (ADC)

The STM32WB07xC and STM32WB06xC embed a 12-bit ADC. The ADC consists of a 12-bit successive approximation analog-to-digital converter (SAR) with 2 x 8 multiplexed channels allowing measurements of up to eight external sources and up to two internal sources.

12.1 Features

• • Conversion frequency is up to 1 Msps
• • Three input voltage ranges are supported (0 → 1.2 V, 0 → 2.4 V, 0 → 3.6 V)
• • Up to eight analog single-ended channels or four analog differential inputs or a mix of both
• • One analog microphone supported through two GPIOs configured in analog mode (an input for the analog microphone and a Vbias output for the analog microphone)
• • Temperature sensor conversion
• • Battery level conversion up to 3.6 V
• • Continuous or single acquisition
• • Digital decimation filter to process a digital audio PDM stream provided by 2 GPIOs and for ADC post-processing, especially for analog audio stream
• • Five modes of conversion are possible:
  • – ADC continuous or single mode
  • – Analog continuous audio mode
  • – Occasional conversions
  • – Digital continuous audio mode
  • – Full mode
• • ADC down sampler for multi-purpose applications to improve analog performance while off-loading the CPU (ratio adjustable from 1 to 128)
• • A watchdog feature to inform when data is outside thresholds (available for all modes except the digital audio mode)
• • DMA capability
• • Interrupt sources with flags.

12.2 ADC presentation

Figure 22. ADC top level diagram shows the top level diagram of the ADC.

The analog ADC can be configured to interface with the following inputs:

• • External signals through ADC_VINPx and ADC_VINMx, where x=0,1,2 or 3
  • – Up to 4 differential inputs
  • – Up to 8 single-ended inputs
• • Analog microphone interface
• • Temperature sensor battery level detector up to 3.6 V
• • Battery level detector up to 3.6 V

Figure 22. ADC top level diagram

In parallel of the analog ADC, a digital microphone can be supported (PDM interface through two GPIOs).

The input of the data path can come from:

• • the analog ADC
• • a digital microphone signal

The conversion data path can go through:

• • a decimation filter
• • a down sampler (for static or low frequency input signals)

The existence of those two different data paths allows some concurrent conversion (specific combinations).

Caution: Do not change the configuration registers related to the function in use. Any change done by the user on the different bits are applied immediately, with an immediate effect on the on-going process (conversion, decimator filter or downsampler). This action can lead to unexpected results.

For VBAT < 2.7 V, the IO booster needs to be activated to maintain linearity.

12.2.1 Programmable gain amplifier (PGA)

The input signal coming from the analog microphone is amplified with a programmable gain amplifier (PGA) (see Figure 23. Microphone setup) from 0 dB to 30 dB by step of 3 dB.

The signal is then filtered by a low-pass filter with -1 dB at 20 kHz.

The PGA output voltage is 1.2 V and is inverted versus the VIN_MIC input signal.

Figure 23. Microphone setup

graph LR
    MIC((MIC)) --|Cin| PGA_VIN
    VBIAS_MIC -- 0.5 to 0.9 x VBAT --> MIC
    subgraph PGA_interface
        PGA_VIN(PGA_VIN PB4) --- R1[100kΩ]
        R1 --- OP_IN_POS[+]
        VCMDEC(VCMDEC PB2) --- C1[100nF]
        XVBAT(XVBAT PB3) --- C2[100nF]
        C1 --- GND
        C2 --- GND
        OP_IN_NEG[-] --- VCM
        OP_OUT[VOUT to ADC]
    end

VBIAS_MIC, whose function is independent of PGA_VIN, is used as the microphone power supply. In order to accommodate different microphone supply specifications with a battery that could vary between 1.7 V and 3.6 V, VBIAS_MIC voltage is adjustable as a ratio of VBAT, between 0.5 and 0.9. Refer to the section on PGA_CONF registers for details.

100 nF capacitors need to be connected to VCMDEC and XVBAT respectively to filter out the noise above 1 kHz.

PGA_VIN has a typical input common-mode voltage, VCM, of 750 mV. In order to avoid DC conflicts which could cause saturation in the PGA, a coupling capacitor, Cin, needs to be connected between the microphone and PGA_VIN. The recommended value is 1 µF but one could use a lower value (see Table 30. PGA parameters ). The smaller the capacitor, the quicker the start-up time but with the drawback of the input signal being attenuated. For example, with a Cin of 10 nF a 1 kHz signal would be attenuated by approximately 1 dB.

The PGA gain is adjustable between 0 dB and 30 dB in steps of 3 dB (see Section 12.6.5: ADC PGA configuration register (PGA_CONF) ). In order to avoid distortion in the PGA, the gain setting would need to be adjusted in accordance with the microphone output peak voltage. Below are the PGA maximum output peak voltage values to be respected along with the formula for estimating the maximum PGA gain with respect to the microphone sensitivity, S ₀ .

Table 30. PGA parameters

Note: \( \text{Maximum PGA gain in dB} = \text{MxVout} - S_0 - 3 \) [N.B. Sensitivity for analog mics are in dBVrms]

Note: E.g. With the microphone sensitivity = -38 dB in a typical setting and no attenuation in the input signal: \( \text{Maximum PGA gain} = -5.8 + 38 - 3 = 29.2 \text{ dB} \) .

Note: The usage of the PGA in analog audio mode implies connecting 3 external capacitors on PB2/PB3/PB4 I/Os. The user has to ensure that the analog switch is well configured to select the PGA external capacitor mode (see Section 8.2.11: I/O analog switch control register (GPIO_SWA_CTRL) for details) and then that those two pads are programmed in analog mode (see Section 7.4.1: GPIO port mode register (GPIOx_MODER) (x = A, B) for details) in this order. A filter needs to be added to the output of the decimation filter in order to filter out the DC level.

12.2.2 Temperature sensor subsystem

The temperature sensor can be used to measure the junction temperature ( \( T_j \) ) of the device. The temperature sensor is internally connected to the ADC input channels which are used to convert the sensor output voltage to a digital value.

The temperature sensor needs to be enabled through the PWRC_CR2.ENTS bit.

The temperature sensor measurement conversion is on the input range 0 to 1.2 V as the temperature range is:

• • for minimum temperature = \( -40\text{ }^\circ\text{C} \) , \( V_{min} = 0.585\text{ V} \)
• • for maximum temperature = \( +125\text{ }^\circ\text{C} \) , \( V_{max} = 0.999\text{ V} \)

The temperature sensor output voltage changes linearly with temperature. The offset of this line varies from chip-to-chip due to process variation. The uncalibrated internal temperature sensor is more suited for applications that detect temperature variations instead of absolute temperatures. To improve the accuracy of the temperature sensor measurement, calibration values are stored in system memory for each device by ST during production. During the manufacturing process, the calibration data of the temperature sensor and the internal voltage reference are stored in the system memory area. The user application can then read them and use them to improve the accuracy of the temperature sensor or the internal reference. In this way the temperature can be calculated with this formula:

Where:

C85 is the temperature sensor calibration value acquired at \( 85\text{ }^\circ\text{C} \) readable @0x10001E68.

C30 is the temperature sensor calibration value acquired at \( 30\text{ }^\circ\text{C} \) readable @0x10001E60.

Cmeas is the actual temperature sensor output value converted by ADC.

Note: ADC gain calibration for VINPx range 1.2 V only must be applied. Offset calibration must be 0 (not used).

Note: Refer to Section 25.1: DESIG registers for information about the location where these calibration values are stored.

12.2.3 Battery sensor

The battery sensor can be used to measure the internal battery voltage of the device. The battery input is internally connected to the ADC input channels which are used to convert the sensor output voltage to a digital value.

The battery sensor range is up to 3.6 V.

The formula for ADC converted data after calibration is the following:

Code = Integer(4096/3.6 * VIN) [clamped at 4095]

As calibration points the VBAT is considered as single negative input with 3.6 V range.

Note: Refer to Section 25.1: DESIG registers for information about the location where these calibration values are stored.

12.2.4 ADC input mode conversion

The ADC is designed to deliver a digital value corresponding to the ratio between the analog power supply and the voltage applied on the converted channel. For most application use cases, it is necessary to convert this ratio into a voltage independent of VDDA.

The formula for ADC digital converted data after calibration and offset is the following:

• • Single-ended input mode
  Code = Integer(Slope* VIN) [clamped at 4095]
  where Slope for single-ended input mode has the following value:
  3.6 V mode: Slope = 4096/3.6 [calibrated gain = 1/3]
  2.4 V mode: Slope = 4096/2.4 [calibrated gain = 1/2]
  1.2 V mode: Slope = 4096/1.25 [calibrated gain = 0.96, gain clamped at 1]

• • Differential input mode
  Code = \( Integer(Slope \cdot (VINP - VINN)) + 2048 \) [clamped at 4095]
  where Slope for differential input mode has the following value:
  3.6 V mode: Slope = 2048/3.6 [calibrated gain = 1/3]
  2.4 V mode: Slope = 2048/2.4 [calibrated gain = 1/2]
  1.2 V mode: Slope = 2048/1.25 [calibrated gain = 0.96, gain clamped at 1]

12.2.5 Calibration points

Calibration values are stored in the system memory for each device by ST during production. Each value consists of a 12-bit unsigned value for the gain and an 8-bit signed value for the offset as follows:

OFFSET[18:12] | GAIN[11:0]

These values can be written inside the registers COMP_x with x=1, 2, 3, 4 to apply a point to a particular ADC input. The COMP_SEL register allows a specific calibration point to be associated to one of the ADC inputs.

The offset value can be written inside the COMP_x register only if it fits in the 7-bit of register field, that means offset is in [-64, 63]. Otherwise, it can be removed by the output raw data manually as raw_value + offset.

The negative offset values need to be converted as:

offset | 0x80, if the bitfield BIT_INVERT_SN=1 (default value).

Below the list of the calibration points and their location in the system memory.

Table 31. Calibration points

Note: Previous version of the calibration points has the offset in 7-bit signed. This version can be recognized as the user can read at address 0x10001EFC the value 0.

Note: Refer to Section Section 25.1: DESIG registers for information about the location where these calibration values are stored.

12.2.6 Steady-state input impedance

As the input nature of the ADC is a switched-capacitor, its steady-state input impedance is defined as the impedance seen in DC. It depends only on the analog sampling frequency, Fs, and the input capacitor, Cin: \( Z_{in} = 1/(C_{in} \cdot F_s) \) .

12.2.7 Input signal sampling transient response

As represented in Figure 25. Effect of analog source resistance , the analog signal path consists of a series resistance (Rext) between source and pin, the internal switch resistor (Rin) and the internal sampling capacitor (Cin). The charging of the capacitor is controlled by Rin. When there is Rext in series, the effective value of charging of Cin is governed by Rin+Rext. So the charging time constant becomes (Rin+Rext)*Cin and the necessary time to reach a given accuracy is longer. The ADC has a fixed sampling time Tsw depending on ADC frequency which is 1/Ts as shown in Figure 24. ADC sampling time Tsw and sampling period Ts .

Figure 24. ADC sampling time Tsw and sampling period Ts

Figure 25. Effect of analog source resistance

Knowing that: \( R_{in}=550\ \Omega \) , \( C_{in}=4\ pF \) , and imposing a maximum sampling error of 1/2 bits, we can determine the maximum input resistance as below:

where:

12.2.8 Decimation filter (DF)

The purpose of the decimation filter (DF) is to provide a way to reduce the incoming fixed rate sample to some fixed output data rates, while improving the overall noise performance (signal to noise ratio).

The decimation filter is used to process either the PDM data stream from a digital MEMS microphone or from the output of the 12-bit ADC, mainly targeting the audio sources of signal.

The input data rate of the decimation filter is:

• in analog audio / full mode: 1 Mpbs

• in digital audio mode: the PDM clock rate itself (configured through PDM_RATE bit field of the DF_CONF register). The constraint is to fit the MEMS microphone range of possible frequencies (typically 1 to 3 MHz). The decimation filter is composed of two chained blocks:
  • a CIC filter capable to perform a wide range of decimation factors
  • a FIR filter performing the last stage of decimation and compensating the attenuation effect of the CIC filter.

The FIR filter has a fixed decimation rate of 3

Figure 26. Simplified decimation filter block diagram

graph LR
    Input[input F] --> CIC[Flexible Decimation Factor CIC Filter]
    CIC --> Intermediate["F/(M/3)"]
    Intermediate --> FIR[Decimation by 3 FIR filter]
    FIR --> Output[data F/M]
    subgraph Decimation Factor=M
    CIC
    FIR
    end

Table 32. Output data rate with ADC input at 1 MHz for analog mode and Table 33. CIC filter output frequency with digital microphone input list the decimation factors and the output frequencies according to the supported inputs (ADC or digital microphone).

The relationship between input data rate and output data rate is that the input data rate is:

• divided by DF_CIC_DEC_FACTOR
• then divided by 3
• divided by 2 if DF_CIC_DHF is set

Note: This divider by 2 is too noisy for digital audio scenario; to be kept for analog scenarios only.

• multiplied by 1.2 if DF_ITP1P2 is set

Table 32. Output data rate with ADC input at 1 MHz for analog mode

1. The 200 kHz use-case is not supposed to be used for the analog audio scenario. It mainly targets sensor measurements.

2. This is a possible configuration but neither verified nor guaranteed (to be validated in lab).

Note: A constraint on the ratio between APB system clock (F _PCLK ) and the output data rate (DR _out ) must be respected:

• In analog audio mode and in full mode, the ratio to respect is \( F_{PCLK} / DR_{out} \geq 6 \) .

Example: F _PCLK must be at least 2 MHz to have a DR _out = 200 kHz.

If the DMA is not used to get the data output by the decimation filter path, the CPU needs to be clocked at a frequency ratio high enough (taking into account bus matrix latency) to avoid missing samples.

Table 33. CIC filter output frequency with digital microphone input

Table 34. Minimum decimation factor for the CIC / total versus pdm_rate provides the value of the allowable minimum decimation factor for the CIC filter and for the complete chain versus the pdm_rate input parameter.

Table 34. Minimum decimation factor for the CIC / total versus pdm_rate

When the input of the decimation filter comes from 12-bit ADC, an unsigned-to-signed data conversion is possible through a configuration bit (DF_I_U2S bit in DF_CONF register).

The output of the decimation filter can also be converted from signed to unsigned through a configuration bit (DF_O_S2U bit in DF_CONF register) to be compatible with the down sampler output which is always signed.

The input PDM data is sampled either on the falling edge or the rising edge of the PDM clock. This is configurable through DF_MICRO_L_RN bit in the DF_CONF register. The PDM clock is generated by a division of the decimation filter clock (always 32 MHz) according to the targeted output frequency.

12.2.9 Down sampler (DS)

This down sampler is a simple averaging filter, which can divide the ADC frequency by 1 to 128 by power of 2. The goal is to handle multiple ADC samples and average them into a single data with increased data width ranging from 12-bit to 16-bit.

The down sampler increases the data precision but reduces the output data rate.

Note: A constraint on the ratio between APB system clock ( \( F_{PCLK} \) ) and the output data rate ( \( DR_{out} \) ) must be respected:

• • In ADC mode, the ratio to respect is \( F_{PCLK} / DR_{out} \geq 4 \) .

Example: \( F_{PCLK} \) must be at least 2 MHz to have a \( DR_{out} = 500 \) kHz.

If the DMA is not used to get the data output by the down sampler filter path, the CPU needs to be clocked at a frequency ratio high enough (taking into account bus matrix latency) to avoid missing samples.

12.3 Interrupts

There are 6 maskable interrupts generated by the ADC block. These interrupts are combined to produce one single interrupt output, which is the only interrupt line from the ADC to the CPU.

Table 35. ADC interrupt requests

12.4 DMA interface

The ADC has two DMA channels interface:

• • one to get down sampler data output value (DS_DATAOUT register),
• • one to get Decimation Filter data output value (DF_DATAOUT register)

The DMA feature is enabled by software through CONF register respectively by DMA_DS_ENA bit for down sampler data output and DMA_DF_ENA bit for decimation filter data output.

When DMA feature is disabled for one or both output, the data can be read by the CPU through the corresponding APB register.

12.5 ADC modes

Table 36. ADC mode summary provides an overview of the different supported modes.

Table 36. ADC mode summary

12.5.1 Analog audio mode

Presentation

The Analog audio mode has the following characteristics:

• The input in the analog audio mode is the analog microphone signal
• The input signal is amplified with a programmable gain amplifier (PGA) from 0 dB to 30 dB
• The data path is from the analog audio PGA interface, the ADC and the decimation filter (down sampler not used in this mode)
• The converted data is output in the DF_DATAOUT register
• The analog audio mode conversion sequence is always in continuous mode.

Analog audio mode usage

This paragraph describes the process to use the analog audio mode:

• Program the PB2 and PB3 I/Os to connect the two external capacitors to the PGA analog block. This is done in two steps (keep the order):
  • first, program the PB2 and PB3 analog switch to select the PGA external capacitor mode by setting the GPIO_SWA_CTRL[1] bit in the SYSCFG block,
  • then, program the PB2 and PB3 I/Os to be in analog mode through the GPIOB_MODER[5:4] and GPIOB_MODER[7:6] bit field of the GPIOB block.
• Enable the LDO of the ADC by setting the ADC_LDO_ENA bit in the CTRL register.

Caution: This LDO enable bit must not be set when VFQFPN32 devices are used because the VDDA pin used to supply the ADC LDO is not available on this package.

• Power on the ADC if not yet done by setting the ADC_ON_OFF bit in the CTRL register
• Program the wanted PGA gain through the PGA_GAIN bit field of the PGA_CONF register
• Set the analog bias voltage through the PGA_BIAS bit field of the PGA_CONF register
• Program the analog audio mode through the OP_MODE bit field in the CONF register
• Modify the data rate of the decimation filter if needed
• Program the continuous mode (mandatory in this mode) by setting the CONT bit in the CONF register
• Start the conversion by setting the START_CONV bit in CTRL register
• Each time a data is available at the output of the decimation filter, the data is stored in the DF_DATAOUT register and the EODF flag is set (as analog audio mode goes through the decimation filter)

• • To get the converted values:
  • – Either the DMA is enabled on DF data path (through DMA_DF_ENA bit in CONF register) and DMA copies the data in RAM at the end of each data conversion (via the APB bus)
  • – Or the software has enabled the EODF_IRQ interrupt and is able to get the data from DF_DATAOUT register before a new converted data is generated.

Note: If the CPU does not manage to get the converted data before a new converted data is generated, the OVR_DF_IRQ flag is raised to inform a data has been lost. The software can program the hardware behavior in case of overrun through the OVR_DF_CFG bit in CONF register:

• • if 0, the previous data is kept, the new one is lost.
• • if 1, the previous data is lost, the new one is kept.
• • The data conversion goes on until the software stops it by setting the STOP_OP_MODE bit in the CTRL register: in this case, the conversion stops immediately and on-going conversion data are issued.

12.5.2 ADC mode

Presentation

The ADC mode has the following characteristics:

• • The input in the ADC mode can be the eight external channels and the two internal sources (VBAT and temperature sensor)
• • The data path goes from the ADC to the down sampler (decimation filter is not used in this mode)
• • The converted data is output in the DS_DATAOUT register
• • The output data rates are in the range 4.4 ksps to 1 Msps
• • The 12-bit converted data can be extended up to 16-bit data thanks to the down sampler. However, in this case, the output data rate is decreased
• • A regular sequence of conversion can be executed in single or continuous mode
  • – A regular sequence consists of chaining ADC conversions on any ADC input channel (except the analog microphone) and in any order.
  • – A regular sequence can chain up to 16 conversions.
  • – The source of the input for each conversion of the sequence is selected through SEQx bit field in SEQ_1 and SEQ_2 registers.
  • – This regular sequence can be run once or repeated continuously by setting the CONT bit in CONF register.

ADC mode usage

This paragraph describes the process to use the ADC mode:

• • Enable the LDO of the ADC by setting the ADC_LDO_ENA bit in the CTRL register

Note: This LDO enable bit must not be set when VFQFPN32 devices are used because the VDDA pin used to supply the ADC LDO is not available on this package.

• • Power on the ADC if not yet done by setting the ADC_ON_OFF bit in the CTRL register
• • Program the targeted data rate through SAMPLE_RATE and DS_CONF registers
• • Program the input voltage selections through SWITCH register
• • Program the COMP_1 to COMP_4 and the COMP_SEL registers
• • Program the ADC mode through the OP_MODE bit field in the CONF register
• • Program the targeted regular sequence (up to 16 chained conversions) through SEQ_1 and SEQ_2 registers
• • Specify the length of the sequence in SEQ_LEN bit field in CONF (from 0 for one conversion to 0xF for sixteen conversions).

To have more than one conversion, ensure the bit SEQUENCE is well at 1 in CONF register.

• • Program the CONT bit and the SEQ_LEN bit field in the CONF register, considering SEQUENCE bit is always set) depending on the wished sequence:
  • – CONT = 0 and SEQ_LEN = 0 to have a single conversion on a single channel.
  • – CONT = 0 and SEQ_LEN > 0 to have a single run of a sequence chaining several conversions on different channels/sources.
  • – CONT = 1 and SEQ_LEN = 0 to have a continuous conversion of a single channel/source.
  • – CONT = 1 and SEQ_LEN > 0 to have a continuous run of sequence chaining several conversions on different channels/sources.
• • Launch the programmed regular sequence by setting the START_CONV bit in CTRL register
• • Each time a data is available at the output of the down sampler, the data is stored in the DS_DATAOUT register and the EODS flag is set (as analog mode goes through the down sampler)
• • To get the converted values:
  • – Either the DMA is enabled on DS data path (through DMA_DS_ENA bit in CONF register) and DMA copies the converted data in RAM at the end of each data conversion
  • – Or the software has enabled the EODS_IRQ interrupt and is able to get the data from DS_DATAOUT register before a new converted data is generated.

Note: If the CPU does not manage to get the converted data before a new converted data is generated, the OVR_DS_IRQ flag is raised to inform a data has been lost. The software can program the hardware behavior in case of overrun through the OVR_DS_CFG bit in CONF register:

• • if 0, the previous data is kept, the new one is lost.
• • if 1, the previous data is lost, the new one is kept.
• • Each time the regular sequence is completed, the EOS_IRQ flag is raised (and may generate an interrupt if enabled)
• • If the sequence is a single sequence (CONT=0), the ADC stops at the end of the sequence and does not restart until START_CONV bit is not set again
• • If continuous conversion is enabled (CONT = 1), the ADC restarts a new sequence, and data conversion goes on until the software stops it, by setting the STOP_OP_MODE bit in the CTRL register; in this case, the ADC stops immediately, and the data from any on-going conversion is discarded.

12.5.3 Digital audio mode

Presentation

The digital audio mode aims to interconnect with an external digital MEMS microphone. The digital audio mode has the following characteristics:

• • Only the decimation filter and the digital control resources are used
• • The decimation filter interfaces with the external microphone with 2 GPIOs:
  • – PDM_CLK: a clock output at programmable frequency through PDM_RATE[3:0] of the DF_CONF register (see Section 12.6.2: ADC configuration register (CONF) ),
  • – PDM_DATA: pulse density modulation input data.
• • The converted data is output in the DF_DATAOUT register
• • The digital audio mode conversion sequence is always in continuous mode.

Digital audio mode usage

This paragraph describes the process to use the digital audio mode:

• • Program the PDM_CLK and PDM_DATA alternate functions on targeted IOs to have the digital microphone connected to the decimation filter
• • Program the DF_MICRO_L_RN bit in the DF_CONF register to select the right or the left channel of the microphone
• • Program the decimator rate through the DF_ITP1P2, DF_CIC_DHF and DF_CIC_DEC_FACTOR bit fields of the DF_CONF register
• • Ensure the OP_MODE bit field in the CONF register is equal to 2
• • As soon as the software sets the DIG_AUD_MODE bit in the CTRL register, the decimation filter starts sending the PDM_CLK and processing continuously the data received from the PDM_DATA input
• • Each time a filtered data is available, the data is stored in the DF_DATAOUT register and the EODF_IRQ flag is raised (as digital audio mode goes through the decimation filter).

Note: The first filtered data is available after a delay depending on the latency of the filter (according to the decimation factor) to guarantee the first issued value is correct.

• • To get the converted values:
  • – Either the DMA is enabled on DF data path (through DMA_DF_ENA bit in CONF register) and DMA copies the converted data in RAM at the end of each data conversion
  • – Or the software has enabled the EODF_IRQ interrupt and is able to get the data from DF_DATAOUT register before a new converted data is generated.

Note: If the CPU does not manage to get the converted data before a new converted data is generated, the OVR_DF_IRQ flag is raised to inform a data has been lost.

Note: The software can program the hardware behavior in case of overrun through the OVR_DF_CFG bit in CONF register:

• • if 0, the previous data is kept, the new one is lost.
• • if 1, the previous data is lost, the new one is kept.

• • As soon as the software clears the DIG_AUD_MODE bit in the CTRL register, the conversion is stopped immediately and the on-going conversion is not completed.

12.5.4 Full mode

Presentation

The full mode is the same mode as the analog audio mode but with the other analog channels than the audio PGA interface.

The full mode has the following characteristics:

• • The input in the full mode can be the eight external channels and the two internal sources (VBAT and temperature sensor)
• • The data path is from the ADC through the decimation filter (down sampler not used in this mode)
• • The converted data is output in the DF_DATAOUT register
• • The full mode conversion sequence is always in continuous mode
• • CONF.SEQ_LEN[3:0]=0x0 is the only supported configuration for this mode.

Full mode usage

This paragraph describes the process to use the full mode:

• • Enable the LDO of the ADC by setting the ADC_LDO_ENA bit in the CTRL register

Note: This LDO enable bit must not be set when VFQFPN32 devices are used because the VDDA pin used to supply the ADC LDO is not available on this package.

• • Power on the ADC if not yet done by setting the ADC_ON_OFF bit in the CTRL register
• • Program the full mode through the OP_MODE bit field in the CONF register
• • Program the targeted data rate
• • Program the continuous mode (mandatory in this mode) by setting the CONT bit in the CONF register
• • Ensure CONF.SEQ_LEN[3:0]=0x0
• • Start the conversion by setting the START_CONV bit in CTRL register
• • Each time a conversion is completed, the converted data is stored in the DF_DATAOUT register and the EODF flag is set (as analog audio mode goes through the decimation filter)
• • To get the converted values:
  • – Either the DMA is enabled on DF data path (through DMA_DF_ENA bit in CONF register) and DMA copies the converted data in RAM at the end of each data conversion
  • – Or the software has enabled the EODF_IRQ interrupt and is able to get the data from DF_DATAOUT register before a new converted data is generated.

Note: If the CPU does not manage to get the converted data before a new converted data is generated, the OVR_DF_IRQ flag is raised to inform a data has been lost.

Note: The software can program the hardware behavior in case of overrun through the OVR_DF_CFG bit in CONF register:

• • if 0, the previous data is kept, the new one is lost.
• • if 1, the previous data is lost, the new one is kept.
• • The data conversion goes on until the software stops it by setting the STOP_OP_MODE bit in the CTRL register: in this case, the conversion stops immediately and on-going conversion data are not issued.

12.5.5 Occasional mode

Presentation

The occasional mode has the following characteristics:

• • The occasional mode input is either the VBAT or the temperature sensor
• • The data path is from the ADC through the down sampler
• • The converted data is output in the DS_DATAOUT register
• • The occasional mode is always a single conversion

• • The occasional mode is only a complementary mode to analog AUDIO mode or full mode and cannot be activated alone
• • The applied down sampler ratio is always 1 for this mode. The DS ratio programmed in the DS_RATIO bit field of the DS_RATIO register is not taken into account.

Occasional usage

This paragraph describes the process to use the occasional mode:

• • Select the source to be converted during the occasional mode (VBAT or temperature sensor) through the OCM_SRC bit field in the OCM_CTRL register
• • Set the OCM_ENA bit in the OCM_CTRL register to start the occasional conversion
• • Once the single conversion is completed, the converted data is stored in the DS_DATAOUT register and the EODS flag is set (as occasional mode goes through the down sampler)
• • To get the converted values:
  • – Either the DMA is enabled on DS data path (through DMA_DS_ENA bit in CONF register) and DMA copies the converted data in RAM at the end of each data conversion
  • – Or the software has enabled the EODS_IRQ interrupt and is able to get the data from DS_DATAOUT register before a new converted data is generated.

12.5.6 Concurrent functions

Some modes support having concurrent conversions:

• • ADC mode and digital audio mode
• • Analog audio mode and occasional mode
• • Full mode and occasional mode.

In this case the data are available in DF_DATAOUT and/or in DS_DATAOUT registers, depending on the selected concurrent modes.

Note: Audio analog mode, full mode and occasional mode use a common hardware resource (12-bit ADC block). Furthermore, the audio analog mode and the full mode are continuous. So when the occasional mode is used in concurrent mode, they lose one conversion. In this configuration, the hardware keeps the previous data on lost conversion.

12.6 ADC registers

12.6.1 Version register (VERSION_ID)

Address offset: 0x00

Reset value: 0x0000 0020

12.6.2 ADC configuration register (CONF)

Address offset: 0x04

Reset value: 0x0002 0002

12.6.3 ADC control register (CTRL)

Address offset: 0x08

Reset value: 0x0000 0000

1. When setting the STOP_MODE_OP, the user has to wait around 10 µs before starting a new ADC conversion by setting the START_CONV bit.

12.6.4 ADC occasional mode control register (OCM_CTRL)

Address offset: 0x0C

Reset value: 0x0000 0000

12.6.5 ADC PGA configuration register (PGA_CONF)

Address offset: 0x10

Reset value: 0x0000 0000

12.6.6 ADC input voltage switch selection register (SWITCH)

Address offset: 0x14

Reset value: 0x0000 0000

12.6.7 Decimation filter configuration register (DF_CONF)

Address offset: 0x18

Reset value: 0x0000 3015

12.6.8 Down sampler configuration register (DS_CONF)

Address offset: 0x1C

Reset value: 0x0000 0000

12.6.9 ADC sequence programming 1 register (SEQ_1)

Address offset: 0x20

Reset value: 0x0000 0000

12.6.10 ADC sequence programming 2 register (SEQ_2)

Address offset: 0x24

Reset value: 0x0000 0000

12.6.11 ADC gain and offset correction 1 register (COMP_1)

Address offset: 0x28

Reset value: 0x0000 0555

Note: Refer to Section 25.1: DESIG registers for information about the location where the calibration values are stored.

12.6.12 ADC gain and offset correction 2 register (COMP_2)

Address offset: 0x2C

Reset value: 0x0000 0555

Note: Refer to Section 25.1: DESIG registers for information about the location where the calibration values are stored.

12.6.13 ADC gain and offset correction 3 register (COMP_3)

Address offset: 0x30

Reset value: 0x0000 0555

Note: Refer to Section 25.1: DESIG registers for information about the location where the calibration values are stored.

12.6.14 ADC gain and offset correction 4 register (COMP_4)

Address offset: 0x34

Reset value: 0x0000 0555

Note: Refer to Section 25.1: DESIG registers for information about the location where the calibration values are stored.

12.6.15 ADC gain and offset selection register (COMP_SEL)

Address offset: 0x38

Reset value: 0x0000 0000

12.6.16 ADC watchdog threshold register (WD_TH)

Address offset: 0x3C

Reset value: 0x0FFF 0000

12.6.17 ADC watchdog configuration register (WD_CONF)

Address offset: 0x40

Reset value: 0x0000 0000

12.6.18 Down sampler data out register (DS_DATAOUT)

Address offset: 0x44

Reset value: 0x0000 0000

12.6.19 Decimation filter data out register (DF_DATAOUT)

Address offset: 0x48

Reset value: 0x0000 0000

12.6.20 ADC interrupt status register (IRQ_STATUS)

Address offset: 0x4C

Reset value: 0x0000 0000

12.6.21 ADC interrupt enable register (IRQ_ENABLE)

Address offset: 0x50

Reset value: 0x0000 0000

12.6.22 ADC timers configuration register (TIMER_CONF)

Address offset: 0x54

Reset value: 0x0000 9628

12.6.23 ADC registers map

Table 37. ADC register map and reset values

Refer to Table 3. STM32WB07xC and STM32WB06xC memory map and peripheral register boundary addresses for the register boundary addresses.