8. System controller (SYSCFG)

The system Controller is a set of registers (configuration, control and status) linked to system features of the STM32WB07xC and STM32WB06xC device.

8.1 SYSCFG main features

The system controller set of registers are mainly linked to:

• Provide the JTAG_ID, Die ID and cut version
• Manage the interrupts linked to GPIO feature
• Manage the interrupts linked to the power controller (PWRC)
• Manage the interrupt linked to MR_BLE reception and transmission sequences
• Enable/disable I ²C fast-mode plus driving capability on some I/Os

Note: This peripheral is in the non-retained power domain so all settings done in the associated registers are lost after a Deepstop.

8.2 System controller registers

8.2.1 Die ID register (DIE_ID)

This register provides the device version and cut information.

Address offset: 0x00

Reset value: 0x0000 0120

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	PRODUCT[3:0]				VERSION[3:0]				REVISION[3:0]
				r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:12	Reserved, must be kept at reset value.
Bits 11:8	PRODUCT: Product version.
Bits 7:4	VERSION: Cut version.
Bits 3:0	REVISION: Cut revision (metal fix).

8.2.2 JTAG ID register (JTAG_ID)

This register provides the JTAG ID of the STM32WB07xC and STM32WB06xC.

Address offset: 0x04

Reset value: 0x0201E041

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
VERSION_NUMBER[3:0]				PART_NUMBER[15:4]
				r	r	r	r	r	r	r	r	r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PART_NUMBER[3:0]				MANUF_ID[10:0]											Res.
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:28	VERSION_NUMBER : Version.
Bits 27:12	PART_NUMBER : Part number.
Bits 11:1	MANUF_ID : Manufacturer ID.
Bit 0	RESERVED

8.2.3 I2C Fast-Mode Plus pin capability control register (I2C_FMP_CTRL)

This register allows activating the fast-mode Plus driving capability on I ²C open-drain pads.

Address offset: 0x08

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.									I2C2_P_B7_FM_P	I2C2_P_B6_FM_P	I2C1_P_A1_FM_P	I2C1_P_A0_FM_P
												rw	rw	rw	rw

Bits 31:4	Reserved, must be kept at reset value.
Bit 3	I2C2_PB7_FMP : I2C2 Fast-Mode Plus driving capability for I2C2_SDA on PB7 I/O. 0: PB7 pin operated in standard mode 1: FM+ mode is enabled on PB7 pin, and speed control is bypassed
Bit 2	I2C2_PB6_FMP : I2C2 Fast-Mode Plus driving capability for I2C2_SCL on PB6 I/O. 0: PB6 pin operated in standard mode 1: FM+ mode is enabled on PB6 pin, and speed control is bypassed
Bit 1	I2C1_PA1_FMP : I2C1 Fast-Mode Plus driving capability for I2C1_SDA on PA1 I/O. 0: PA1 pin operated in standard mode 1: FM+ mode is enabled on PA1 pin, and speed control is bypassed
Bit 0	I2C1_PA0_FMP : I2C1 Fast-Mode Plus driving capability for I2C1_SCL on PA0 I/O. 0: PA0 pin operated in standard mode 1: FM+ mode is enabled on PA0 pin, and speed control is bypassed

8.2.4 I/O interrupt detection type register (IO_DTR)

Address offset: 0x0C

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PB15_DT	PB14_DT	PB13_DT	PB12_DT	PB11_DT	PB10_DT	PB9_DT	PB8_DT	PB7_DT	PB6_DT	PB5_DT	PB4_DT	PB3_DT	PB2_DT	PB1_DT	PB0_DT
r/w	r/w	r/w	r/w	r/w	r/w	r/w	r/w	r/w	r/w	r/w	r/w	r/w	r/w	r/w	r/w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA15_DT	PA14_DT	PA13_DT	PA12_DT	PA11_DT	PA10_DT	PA9_DT	PA8_DT	PA7_DT	PA6_DT	PA5_DT	PA4_DT	PA3_DT	PA2_DT	PA1_DT	PA0_DT
r/w	r/w	r/w	r/w	r/w	r/w	r/w	r/w	r/w	r/w	r/w	r/w	r/w	r/w	r/w	r/w

Bits 31:16	PBx_DT (x=15 to 0): Interrupt detection type for port B I/Os. 0: Edge detection 1: Level detection
Bits 15:0	PAx_DT (x=15 to 0): Interrupt detection type for port A I/Os. 0: Edge detection 1: Level detection

8.2.5 I/O interrupt edge register (IO_IBER)

Address offset: 0x10

Reset value: 0x0000 0000

PB15_IBE

PB14_IBE

PB13_IBE

PB12_IBE

PB11_IBE

PB10_IBE

PB9_IBE

PB8_IBE

PB7_IBE

PB6_IBE

PB5_IBE

PB4_IBE

PB3_IBE

PB2_IBE

PB1_IBE

PB0_IBE

r/w

PA15_IBE

PA14_IBE

PA13_IBE

PA12_IBE

PA11_IBE

PA10_IBE

PA9_IBE

PA8_IBE

PA7_IBE

PA6_IBE

PA5_IBE

PA4_IBE

PA3_IBE

PA2_IBE

PA1_IBE

PA0_IBE

r/w

Bits 31:16	PBx_IBE (x=15 to 0): Interrupt edge selection for port B I/Os. 0: Single edge detection 1: Both edges detection
Bits 15:0	PAx_IBE (x=15 to 0): Interrupt edge selection for port A I/Os. 0: Single edge detection 1: Both edges detection

8.2.6 I/O interrupt polarity event register (IO_IEVR)

Address offset: 0x14

Reset value: 0x0000 0000

PB15_IEV

PB14_IEV

PB13_IEV

PB12_IEV

PB11_IEV

PB10_IEV

PB9_IEV

PB8_IEV

PB7_IEV

PB6_IEV

PB5_IEV

PB4_IEV

PB3_IEV

PB2_IEV

PB1_IEV

PB0_IEV

r/w

PA15_IEV

PA14_IEV

PA13_IEV

PA12_IEV

PA11_IEV

PA10_IEV

PA9_IEV

PA8_IEV

PA7_IEV

PA6_IEV

PA5_IEV

PA4_IEV

PA3_IEV

PA2_IEV

PA1_IEV

PA0_IEV

r/w

Bits 31:16	PBx_IEV (x=15 to 0): Interrupt polarity event for port B I/Os. 0: Falling edge / low level 1: Rising edge / high level
Bits 15:0	PAx_IEV (x=15 to 0): Interrupt polarity event for port A I/Os. 0: Falling edge / low level 1: Rising edge / high level

8.2.7 I/O interrupt enable register (IO_IER)

Address offset: 0x18

Reset value: 0x0000 0000

PB15_IE

PB14_IE

PB13_IE

PB12_IE

PB11_IE

PB10_IE

PB9_IE

PB8_IE

PB7_IE

PB6_IE

PB5_IE

PB4_IE

PB3_IE

PB2_IE

PB1_IE

PB0_IE

PA15_IE

PA14_IE

PA13_IE

PA12_IE

PA11_IE

PA10_IE

PA9_IE

PA8_IE

PA7_IE

PA6_IE

PA5_IE

PA4_IE

PA3_IE

PA2_IE

PA1_IE

PA0_IE

Bits 31:16	PBx_IE (x=15 to 0): Interrupt enable for port B I/Os. 0: Interrupt is disabled 1: Interrupt is enabled
Bits 15:0	PAx_IE (x=15 to 0): Interrupt enable for port A I/Os. 0: Interrupt is disabled 1: Interrupt is enabled

8.2.8 I/O Interrupt status and clear register (IO_ISCR)

Address offset: 0x1C

Reset value: 0x0000 0000

PB15_ISC

PB14_ISC

PB13_ISC

PB12_ISC

PB11_ISC

PB10_ISC

PB9_ISC

PB8_ISC

PB7_ISC

PB6_ISC

PB5_ISC

PB4_ISC

PB3_ISC

PB2_ISC

PB1_ISC

PB0_ISC

rc_w1

PA15_ISC

PA14_ISC

PA13_ISC

PA12_ISC

PA11_ISC

PA10_ISC

PA9_ISC

PA8_ISC

PA7_ISC

PA6_ISC

PA5_ISC

PA4_ISC

PA3_ISC

PA2_ISC

PA1_ISC

PA0_ISC

rc_w1

Bits 31:16	PBx_ISC (x=15 to 0): Interrupt status (before mask) for port B I/Os. 0: No pending interrupt 1: Event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit
Bits 15:0	PAx_ISC (x=15 to 0): Interrupt status (before mask) for port A I/Os. 0: No pending interrupt 1: Event occurred on corresponding I/O / interrupt occurred (if enabled). Cleared by writing 1 in the bit

8.2.9 Power controller interrupt enable register (PWRC_IER)

This register allows control of the enable or mask on the interrupt sources of the power controller (PWRC) block.

Address offset: 0x20

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.										WKUP_IE	PVD_IE	Res.
													rw	rw

Bits 31:3	Reserved, must be kept at reset value.
Bit 2	WKUP_IE: Power controller wakeup event interrupt enable. 0: Interrupt on wakeup event seen by the PWRC is disabled 1: Interrupt on wakeup event seen by the PWRC is enabled
Bit 1	PVD_IE: Programmable voltage detector interrupt enable. 0: PVD interrupt is disabled 1: PVD interrupt is enabled
Bit 0	Reserved, must be kept at reset value.

8.2.10 Power controller interrupt status and clear register (PWRC_ISCR)

This register allows checking the status and clear the interrupt sources of the power controller (PWRC) block.

Address offset: 0x24

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	WKUP_ISC	PVD_ISC	Res.
													rc_w1	rc_w1

Bits 31:3	Reserved, must be kept at reset value.
Bit 2	WKUP_ISC: Indicates the power controller receives a wakeup event. • 0: No pending interrupt • 1: Wakeup event on PWRC occurred / interrupt occurred (if enabled). Cleared by writing 1 in the bit. This flag is read at 1 if a wakeup event arrives so close to the low-power mode entry requests that the PWRC aborts before shutting down the system.
Bit 1	PVD_ISC: Programmable voltage detector status. • 0: No pending interrupt • 1: Voltage went under programmed threshold / interrupt occurred (if enabled). Cleared by writing 1 in the bit. See Section 5.3.2: Power voltage detection (PVD) for details.
Bit 0	Reserved, must be kept at default value.

8.2.11 I/O analog switch control register (GPIO_SWA_CTRL)

This register allows selecting the analog source to connect on analog pads embedding two features.

Address offset: 0x28

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	PGACA P_nVIN 0	ATB1_n PVD
														rw	rw

Bits 31:2

Reserved, must be kept at reset value.

Bit 1

PGACAP_nVIN0: Select the analog feature on PB2/PB3 between connecting external capacitors on PGA (for analog audio mode) and VINM/P0 for ADC measurements when the PB2/3 I/Os are programmed in analog mode (in the associated GPIO_MODER register):

0: VINM/P0 feature is selected (default)
1: External capacitors for PGA feature is selected

WARNING: No specific HW protection is in place if the configuration selects the PGA external capacitor and the SW enables the ADC in analog measurements through VINM/P0 pins.

Bit 0

ATB1_nPVD: Select the analog feature on PB14 between ATB1 and PVD when the PB14 I/O is programmed in analog mode (in the associated GPIO_MODER register):

0: PVD external voltage feature is selected (default)
1: ATB1 feature is selected

8.2.12 MR_BLE RX or TX sequence information detection type register (BLERXTX_DTR)

This register allows selecting the type of detection (level or edge) on RADIO_RX_SEQUENCE and RADIO_TX_SEQUENCE coming from the MR_BLE IP.

Address offset: 0x2C

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	RX_DT	TX_DT
														rw	rw

Bits 31:2	Reserved, must be kept at reset value.
Bit 1	RX_DT : Detection type on RADIO_RX_SEQUENCE signal: 0: Detection on edge (default) 1: Detection on level
Bit 0	TX_DT : Detection type on RADIO_TX_SEQUENCE signal: 0: Detection on edge (default) 1: Detection on level

8.2.13 MR_BLE RX or TX sequence information detection type register (BLERXTX_IBER)

This register is used to activate RADIO_RX_SEQUENCE and RADIO_TX_SEQUENCE signal detection on single edge or both edges when edge detection type is active.

Address offset: 0x30

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	RX_IBE	TX_IBE
														rw	rw

Bits 31:2	Reserved, must be kept at reset value.
Bit 1	RX_IBE : Interrupt edge register on RADIO_RX_SEQUENCE signal: 0: Detection on single edge (default) 1: Detection on both edges
Bit 0	TX_IBE : Interrupt edge register on RADIO_TX_SEQUENCE signal: 0: Detection on single edge(default) 1: Detection on both edges

8.2.14 MR_BLE RX or TX sequence information detection event register (BLERXTX_IEVR)

This register defines the polarity of the RADIO_RX_SEQUENCE and RADIO_TX_SEQUENCE signals detection.

Address offset: 0x34

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	RX_IEV	TX_IEV
														rw	rw

Bits 31:2	Reserved, must be kept at reset value.
Bit 1	RX_IEV: Interrupt polarity event on RADIO_RX_SEQUENCE signal: 0: Detection on falling edge / low level (default) 1: Detection on rising edge / high level
Bit 0	TX_IEV: Interrupt polarity event on RADIO_TX_SEQUENCE signal: 0: Detection on falling edge / low level (default) 1: Detection on rising edge / high level

8.2.15 MR_BLE RX or TX sequence information detection interrupt enable register (BLERXTX_IER)

This register defines the interrupt enable of the RADIO_RX_SEQUENCE and RADIO_TX_SEQUENCE signals.

Address offset: 0x38

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.

Bits 31:2	Reserved, must be kept at reset value.
Bit 1	RX_IE: Interrupt enable on RADIO_RX_SEQUENCE signal: 0: Interrupt disabled (default) 1: Interrupt enabled
Bit 0	TX_IE: Interrupt enable on RADIO_TX_SEQUENCE signal: 0: Interrupt disabled (default) 1: Interrupt enabled

8.2.16 MR_BLE RX or TX sequence information detection status and clear register (BLERXTX_ISCR)

This register allows checking the status and clear the interrupt linked to the RADIO_RX_SEQUENCE and RADIO_TX_SEQUENCE information provided by the MR_BLE IP.

Address offset: 0x3C

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	RX_ISC	TX_ISC
														rc_wc1	rc_wr1

Bits 31:2	Reserved, must be kept at reset value.
Bit 1	RX_ISC: Interrupt status on RADIO_RX_SEQUENCE signal (can be a rising or a falling edge depending on BLERXTX_IEVR and BLERXTX_IBER): 0: No activity on RADIO_RX_SEQUENCE detected 1: Activity on RADIO_RX_SEQUENCE occurred
Bit 0	TX_ISC: Interrupt status on RADIO_TX_SEQUENCE signal (can be a rising or a falling edge depending on BLERXTX_IEVR and BLERXTX_IBER): 0: No activity on RADIO_TX_SEQUENCE detected 1: Activity on RADIO_TX_SEQUENCE occurred

8.2.17 System controller register map

Refer to Table 3. STM32WB07xC and STM32WB06xC memory map and peripheral register boundary addresses for the system controller base address location in the STM32WB07xC and STM32WB06xC.

Table 18. SYSCFG register map and reset values

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x00	DIE_ID	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	PRODUCT			VERSION			REVISION
0x00	Reset value																					0	0	0	1	0	0	1	0	0	0	0	0
0x04	JTAG_ID	VERSION_NUMBER													PART_NUMBER											MANUF_ID						Res.
0x04	Reset value	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	1	1	0	0	0	0	0	0	1	0	0	0	0	0	1
0x08	I2C_FMP_CT_RL	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	I2C2_PBT7_FMP	I2C2_PBT6_FMP	I2C1_PA1_FMP	I2C1_PA0_FMP
0x08	Reset value																													0	0	0	0
0x0C	IO_DTR	PB15_DT	PB14_DT	PB13_DT	PB12_DT	PB11_DT	PB10_DT	PB9_DT	PB8_DT	PB7_DT	PB6_DT	PB5_DT	PB4_DT	PB3_DT	PB2_DT	PB1_DT	PB0_DT	PA15_DT	PA14_DT	PA13_DT	PA12_DT	PA11_DT	PA10_DT	PA9_DT	PA8_DT	PA7_DT	PA6_DT	PA5_DT	PA4_DT	PA3_DT	PA2_DT	PA1_DT	PA0_DT
0x0C	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x10	IO_IBE	PB15_IBE	PB14_IBE	PB13_IBE	PB12_IBE	PB11_IBE	PB10_IBE	PB9_IBE	PB8_IBE	PB7_IBE	PB6_IBE	PB5_IBE	PB4_IBE	PB3_IBE	PB2_IBE	PB1_IBE	PB0_IBE	PA15_IBE	PA14_IBE	PA13_IBE	PA12_IBE	PA11_IBE	PA10_IBE	PA9_IBE	PA8_IBE	PA7_IBE	PA6_IBE	PA5_IBE	PA4_IBE	PA3_IBE	PA2_IBE	PA1_IBE	PA0_IBE
0x10	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x14	IO_IEV	PB15_IEV	PB14_IEV	PB13_IEV	PB12_IEV	PB11_IEV	PB10_IEV	PB9_IEV	PB8_IEV	PB7_IEV	PB6_IEV	PB5_IEV	PB4_IEV	PB3_IEV	PB2_IEV	PB1_IEV	PB0_IEV	PA15_IEV	PA14_IEV	PA13_IEV	PA12_IEV	PA11_IEV	PA10_IEV	PA9_IEV	PA8_IEV	PA7_IEV	PA6_IEV	PA5_IEV	PA4_IEV	PA3_IEV	PA2_IEV	PA1_IEV	PA0_IEV
0x14	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

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Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x18	IO_IER	PB15_IE	PB14_IE	PB13_IE	PB12_IE	PB11_IE	PB10_IE	PB9_IE	PB8_IE	PB7_IE	PB6_IE	PB5_IE	PB4_IE	PB3_IE	PB2_IE	PB1_IE	PB0_IE	PA15_IE	PA14_IE	PA13_IE	PA12_IE	PA11_IE	PA10_IE	PA9_IE	PA8_IE	PA7_IE	PA6_IE	PA5_IE	PA4_IE	PA3_IE	PA2_IE	PA1_IE	PA0_IE
0x18	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x1C	IO_ISCR	PB15_ISC	PB14_ISC	PB13_ISC	PB12_ISC	PB11_ISC	PB10_ISC	PB9_ISC	PB8_ISC	PB7_ISC	PB6_ISC	PB5_ISC	PB4_ISC	PB3_ISC	PB2_ISC	PB1_ISC	PB0_ISC	PA15_ISC	PA14_ISC	PA13_ISC	PA12_ISC	PA11_ISC	PA10_ISC	PA9_ISC	PA8_ISC	PA7_ISC	PA6_ISC	PA5_ISC	PA4_ISC	PA3_ISC	PA2_ISC	PA1_ISC	PA0_ISC
0x1C	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x20	PWRC_IER	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	WKUP_IE	PVD_IE	Res.
0x20	Reset value																														0	0
0x24	PWRC_ISCR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	WKUP_ISC	PVD_ISC	Res.
0x24	Reset value																														0	0
0x28	Reserved
0x2C	BLERXTX_DTR	Res.																														RX_DT	TX_DT
0x2C	Reset value																															0	0
0x30	BLERXTX_IBER	Res.																														RX_IBE	TX_IBE
0x30	Reset value																															0	0
0x34	BLERXTX_IEVR	Res.																														RX_IEV	TX_IBV
0x34	Reset value																															0	0
0x38	BLERXTX_IER	Res.																														RX_IE	TX_IB
0x38	Reset value																															0	0
0x3C	BLERXTX_ISCR	Res.																														RX_ISC	TX_ISC
0x3C	Reset value																															0	0

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Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x3C																																0	0