6. Reset and clock controller (RCC)

The RCC block manages the clock and reset generation for all the peripherals of the STM32WB07xC and STM32WB06xC devices.

6.1 Reset management

6.1.1 General description

Figure 12. Reset generation shows the general principle of reset generation.

Note: The system reset information is output on the NRSTn pad to inform the external world and reset other elements on the board if needed.

Two different resets are available in the design:

• • PORESETn: this reset is provided by the LPMU analog block and corresponds to a POR or BOR root cause. It is linked to power voltage ramp-up or ramp-down. The PORESETn reset impacts all the resources of the device.

Note: A Shutdown exits is equivalent to a POR/BOR situation and generates a PORESETn.

• • PADRESETn (aka system reset): this reset is built through several sources:
  • – PORESETn
  • – the watchdog reset
  • – the CPU LOCKUP reset
  • – the CPU software system reset
  • – the NRSTn external pad

Note: The system reset is called PADRESETn as when an internal reset source is activated (watchdog, software, etc.), the NRSTn pad toggles to inform the external world a reset occurs.

This system reset resets all the resources of the device except:

• • Debug features (SWD, test registers...)
• • Flash controller key management part
• • RTC timer
• • Power controller (PWRC)
• • Part of the RCC registers

The pulse generator guarantees a minimum reset pulse duration of 20 µs for each internal reset source. In case of reset from the NRSTn external pad, the reset pulse is generated when the pad is asserted low.

6.1.2 Power reset

The PORESETn signal is active when the power supply of the device is below a threshold value or when the regulator does not provide the target voltage. The PORESETn resets all the resources of the device.

6.1.3 Watchdog reset

The STM32WB07xC and STM32WB06xC device embeds a watchdog timer which may be used to recover from software crashes. See Section 18: Independent watchdog (IWDG) for details about watchdog usage and programming.

6.1.4 LOCKUP reset

The Cortex-M0+ generates a LOCKUP to indicate the core is in the lock-up state resulting from an unrecoverable exception. The LOCKUP reset is masked if a debugger is connected to the Cortex-M0+. The user can use the SWD to reset or recover the code in this case.

6.1.5 System reset request

The system reset request is generated by the debug circuitry of the Cortex-M0+. The debugger sets the SYSRESETREQ bit of the application interrupt and reset control register (AIRCR). This system reset request through the AIRCR can also be done by the embedded software (in hard fault handler for instance). For more details on the Cortex-M0+ system control and ID registers, refer to section B3.2.2 of the "ARMv6-M Architecture" reference manual.

6.1.6 Deepstop exit

The low-power Deepstop state leads to switching off a part of the 1.2 V (power domain called V12i), while keeping the rest of the 1.2 V at 1 V (power domain called V12o) and the 3.3 V (VDDIO).

When the device exits the Deepstop mode, only the V12i power domain is reset as it is the only power domain that lost the power supply.

6.2 Clock management

Three different clock sources may be used to drive the system clock (CLK_SYS) in the STM32WB07xC and STM32WB06xC:

• • HSI: high speed internal 64 MHz RC oscillator (provided by the RC64MPLL analog block),
• • PLL64M: 64 MHz PLL clock (provided by the RC64MPLL analog block),
• • HSE (high speed external):
  • – high speed 32 MHz external crystal
  • – or provided by a single-ended 32 MHz input instead of a crystal.

The STM32WB07xC and STM32WB06xC devices have also have a slow frequency clock tree used by some timers (RTC, watchdog and MR_BLE radio timer). Four different clock sources can be used for this slow clock tree:

• • LSI: low speed low drift internal RC with a fixed frequency between 24 kHz and 49 kHz depending on the sample. It is called 32 kHz clock inside this document to simplify.
• • LSE:
  • – 32.768 kHz low speed external crystal.
  • – or provided by a single-ended 32.768 kHz input instead of a crystal.
• • The system clock divided by 2048. In this case, the slow clock is available in Deepstop low-power mode.
• • LSI_LPMU: 32 kHz clock used by the LPMU analog block.

6.2.1 System clock details

The HSI and the PLL64M clocks are provided by the same analog block called RC64MPLL. The 64 MHz clock output by this block can be:

• • a non accurate clock (target is 1% typical) when no external XO provides an input clock to this block
• • an accurate clock when the external XO provides the 32 MHz and once its internal PLL is locked

Note: The usage of PLL64M or HSE as clock source is mandatory for Bluetooth radio operations (need of a high accuracy on the clock).

The software process to switch the system on the accurate clock is indicated in Section 6.7: Programmer model . This fast clock source is used to generate all the fast clock of the device through dividers.

After reset, the CLK_SYS is divided by four to provide a 16 MHz to the whole system (CPU, DMA, memories and peripherals).

Then the software can program another system clock frequency in the following list:

• • 1 MHz (forbidden when radio or ADC is in use)
• • 2 MHz (forbidden when radio or ADC is in use)
• • 4 MHz (forbidden when radio or ADC is in use)
• • 8 MHz (forbidden when radio is in use)
• • 16 MHz
• • 32 MHz
• • 64 MHz (forbidden when I ² S is in use)

Note: Forbidden configuration means that the “in use” feature cannot work if the system clock runs at this frequency. Special care must be taken when programming the CLK_SYS as some constraints need to be respected: CLK_SYS frequency must be greater or equal to CLK_SYS_BLE.

6.2.2 Peripherals clock details

This fast clock source is also used to generate several internal fast clocks in the system:

• • A TIM1 kernel clock that is the maximum reachable frequency of the system (64 MHz in RC64MPLL configuration and 32 MHz in HSE).
• • An always 32 MHz requested by few peripherals such as: the MR_BLE radio IP for instance
• • An always 16 MHz requested by few peripherals like serial interfaces (to maintain fixed baud rate while system clock is switching from one frequency to another) or like Flash controller and MR_BLE radio IP (to have a fixed reference clock to manage delays).

Figure 13. Peripheral clock tree overview shows an overview of the peripheral clock tree.

Figure 13. Peripheral clock tree overview

Most of the peripherals use the system clock only (CLK_SYS) except:

• • I2C, USART, LPUART:
  • – In parallel with the system clock, they use an always 16 MHz clock to have a fixed reference clock for baud rate management. The goal is to allow the CPU to boost or slow down the system clock (depending on on-going activities) without impacting a potential on-going serial interface transfer on external I/Os.
• • SPI:
  • – When using the I ² S mode, the baud rate is managed through the always 16 MHz or always 32 MHz clock

1. Note: The CPU/system clock frequency must be equal or slower than the I ² S clock frequency.
2. • • When running in other modes than the I2S, the baud rate is managed by the system clock. This implies the baud rate is impacted by dynamic system clock frequency changes.
   • • RNG:
     • – In parallel with the system clock, the RNG uses an always 16 MHz clock to generate at a constant frequency the random number whatever the system clock frequency.
   • • Flash controller:
     • – In parallel with the system clock, the Flash controller uses an always 16 MHz clock to generate specific delays required by the Flash memory during programming and erase operation for instance
   • • PKA:
     • – In parallel with the system clock, the PKA uses a clock at half of the system clock frequency as PKA RAM is a single port RAM
   • • MR_BLE IP
     • – MR_BLE IP does not use directly the system clock for its APB / AHB interfaces but the system clock with a potential divider (1 or 2 or 4). Table 14. CPU versus MR_BLE clock dependency
     • – In parallel with the CLK_SYS_BLE, the MR_BLE uses an always 16 MHz and an always 32 MHz for modulator, demodulator and to have a fixed reference clock to manage specific delays

Table 14. CPU versus MR_BLE clock dependency

• • ADC
  • – In parallel with the system clock, the ADC uses a 64 MHz prescaled clock (called CLKANA_ADC) running at 16 MHz

Note: When the ADC is used, the system clock must run at minimum 8 Mhz to be able to read the ADC sample before they are overloaded by a new sample.

• • This CLKANA_ADC is divided by 2 or 4 to feed the SMPS analog block.

Note: To avoid SNR degradation of the ADC, SMPS and ADC clocks must be synchronous

6.2.3 Slow clock frequency details

As explained at the beginning of the clock management sub-chapter, four different clock sources can be used for this slow clock tree:

• • LSI: low speed low drift internal RC with a fixed frequency between 24 kHz and 49 kHz depending on the sample. It is called 32 kHz clock inside this document to simplify.
• • LSE: 32.768 kHz low speed external crystal (or single-ended input frequency).

Note: If the external oscillator is used, the PB12/PB13 I/Os are automatically connected to this feature when RCC_CR.LSEON bit is set (GPIO_MODERX configuration is overloaded).

Caution: The user has to disable the pulls on PB12/PB13 by software to have the feature working fine. If the single-ended input option is used, then the PB13 I/O must be configured as digital input mode.

The system clock divided by 2048. In this case, the slow clock is not available in Deepstop low-power mode.

LSI_LPMU: 32 kHz clock used by the LPMU analog block. Only one source at a time drives the whole low speed clock tree.

Note: By default after a PORESETn, all low speed sources are OFF. After a PADRESETn, the slow clock configuration is the one programmed before the PADRESETn.

The slow clock activation and selection are relevant during the Deepstop low-power mode and at wakeup as they clock the timers involved in wakeup events generation.

Note: If LSI configuration is used, the software must measure the slow clock frequency to know the associated period that is used by the timers. A slow clock measurement feature is available in the MR_BLE IP.

6.3 System frequency switch while MR_BLE is used

The CPU/system clock frequency can be from 1 MHz to 64 MHz while the MR_BLE clock frequency can be 16 MHz or 32 MHz.

When the radio is used on the device, the system clock frequency selection must respect some rules:

• • the system clock frequency must be 16 MHz, 32 MHz or 64 MHz and greater than or equal to the MR_BLE frequency. Other options make the radio not functional.
• • changing the frequency of the system must be done through the RCC_CSCMDR register mechanism to avoid any risk of crashing the radio scenarios.

This proper system frequency switch is managed through the collaboration of several blocks:

• • the RCC (see Section 6.6.6: Clock switch command register (RCC_CSCMDR) )
• • the AHBUPCONV and the AHBDOWNCONV blocks (see Section 3: AHB up/down converter )

Using this safe mechanism, the software requests a system clock frequency change and is informed by the hardware when the new frequency is really in place through a status bit (see Section 6.6.6: Clock switch command register (RCC_CSCMDR) ) and an associated interrupt line on the CPU (see Section 2.3.2: Interrupts ).

The software sequence is described in Section 6.7.3: Changing the system clock frequency while the MR_BLE is enabled .

6.4 Clock observation on external pad

It is possible to output some internal clocks on external pads:

• • the low speed clocks can be output on the RCC_LCO I/O
• • the high speed clocks can be output on the RCC_MCO I/O

This is possible by programming the associated I/O in the good alternate function (see Table 7. GPIO alternate options AF0 - AF2 ).

The selection of the clock to output for each I/O is programmable through an RCC register (see Section 6.6.2: Clocks configuration register (RCC_CFGR) for more details).

Figure 14. RCC_LCO / RCC_MCO output clocks shows the possible configurations to output an internal clock.

Figure 14. RCC_LCO / RCC_MCO output clocks

DT58430V1

6.5 Miscellaneous

6.5.1 IO BOOSTER

Some analog switches are used to select the analog VINM/P pair input signals to be used by the ADC.

An IO BOOSTER block has been added to boost the voltage on the command of those analog switches when the VBAT goes below a threshold (2.7 V) to guarantee the good behavior of those switches. This block has to be enabled by the software when needed through RCC_CFGR.IOBOOSTEN bit.

6.6 RCC registers

Refer to Table 3. STM32WB07xC and STM32WB06xC memory map and peripheral register boundary addresses for the RCC base address location in the STM32WB07xC and STM32WB06xC.

6.6.1 Clock source control register (RCC_CR)

This register controls the enable on the different clock sources (low and high speed).

Note: The control bits linked to high speed clock source are reset on PADRESETn. The control bits linked to slow speed clock source are reset on PORESETn only (identified by the table footnote). As this register is in V12o power domain, its content is not modified after a wakeup from Deepstop and system clock is restored with configuration present before Deepstop mode entry.

Address offset: 0x00

Reset value: 0x0000 1400

1. 1. This bit is reset on PORESETn only.
2. 2. The LSEBYP and LSEON bits must not be used at the same time. If the user decides to dynamically change the slow clock source between external XO and clock injection on RCC_OSC32_IN, they have to ensure both LSEON and LSEBYP are low at a time to reset the LSERDY flag.

6.6.2 Clocks configuration register (RCC_CFGR)

Note: The control bits linked to high speed clock source are reset on PADRESETn. The control bits linked to slow speed clock source are reset on PORESETn only (identified by the table footnote).

Address offset: 0x08

Reset value: 0x0000 0440

1. This bit is reset on PORESETn only.

6.6.3 Clocks sources software calibration register (RCC_CSSWCR)

This register allows overloading the trimming values loaded automatically by hardware with other values.

Note: The control bits linked to high speed clock source are reset on PADRESETn. The control bits linked to high speed clock source are reset on PORESETn only (identified by the table footnote).

Address offset: 0x0C

Reset value: 0x0000 0000

1. 1. This bit is reset on PORESETn only.

6.6.4 Clock interrupt enable register (RCC_CIER)

This register controls the enable on interrupt sources.

This register is reset on PADRESETn.

Address offset: 0x18

Reset value: 0x0000 0000

6.6.5 Clock interrupt flag register (RCC_CIFR)

This register provides the status flag linked to clock source ready state or not. It is also used to clear the flags.

This register is reset on PADRESETn.

Address offset: 0x1C

Reset value: 0x0000 0008

6.6.6 Clock switch command register (RCC_CSCMDR)

This register allows switching the CPU / system clock frequency safely while the MR_BLE is active.

Requesting a frequency clock switch holds the AHB/APB transfers between the MR_BLE and the rest of the system to execute safely the clock switching and release AHB / APB transfers as soon as the new frequency is in place.

A dedicated line of interrupt (instead of the RCC line) is used on the NVIC for the EOFSEQ_IRQ information (see Table 6. Interrupt vectors).

Note: Anyway, the user must keep the CPU/system frequency at minimum 16 MHz clock when the radio is used.

This register is reset on PADRESETn.

Address offset: 0x20

Reset value: 0x0000 0000

6.6.7 AHB0 macro cells reset register (RCC_AHBRSTR)

This register allows resetting individually by software each IP located in the AHB0 mapping. This register is reset on PADRESETn.

Address offset: 0x30

Reset value: 0x0000 0000

6.6.8 APB0 macro cells reset register (RCC_APB0RSTR)

This register allows resetting individually by software each IP located in the APB0 mapping. This register is reset on PADRESETn.

Note: Each bit is set and reset by the software.

Address offset: 0x34

Reset value: 0x0000 0000

6.6.9 APB1 macro cells reset register (RCC_APB1RSTR)

This register allows resetting individually by software each IP located in the APB1 mapping. This register is reset on PADRESETn.

Address offset: 0x38

Reset value: 0x0000 0000

6.6.10 APB2 macro cells reset register (RCC_APB2RSTR)

This register allows resetting individually by software each IP located in the APB2 mapping (radio).

This register is reset on PADRESETn.

Address offset: 0x40

Reset value: 0x0000 0000

6.6.11 AHB0 macro cells clock enable register (RCC_AHBENR)

This register allows resetting individually by software each IP located in the AHB0 mapping. This register is reset on PADRESETn.

Note: Each IP clock gating is controlled by only 1 bit which gates both AHB clock and kernel clock when the IP uses one.

Address offset: 0x50

Reset value: 0x0000 000C

6.6.12 APB0 macro cell clock enable register (RCC_APB0ENR)

This register allows gating individually by software the clock of each IP located in the APB0 mapping.

Note: Each IP clock gating is controlled by only 1 bit, which gates both APB clock and kernel clock when the IP uses one.

This register is reset on PADRESETn (except one bit identified with a table footnote).

Address offset: 0x54

Reset value: 0x0000 0000

1. This bit is reset on PORESETn only.

6.6.13 APB1 macro cells clock enable register (RCC_APB1ENR)

This register allows gating individually by software the clock of each IP located in the APB1 mapping.

Note: Each IP clock gating is controlled by only 1 bit, which gates both APB clock and kernel clock when the IP uses one.

This register is reset on PADRESETn.

Address offset: 0x58

Reset value: 0x0000 0000

6.6.14 APB2 macro cells clock enable register (RCC_APB2ENR)

This register allows gating by software the MR_BLE clock located in the APB2 mapping (radio) and programming the frequency to be used by the MR_BLE IP.

Note: Gating the MR_BLE means both MR_BLE fast and slow clock trees (so including WAKEUP block).

This register is reset on PADRESETn.

Address offset: 0x60

Reset value: 0x0000 0002

6.6.15 V33 reset status register (RCC_CSR)

This register provides the reset reason flags. It is set automatically by hardware on any new reset event and must be cleared by software.

Table 13. Wakeup reason flags provides a summary of active flags versus reset reason.

This register is reset on PORESETn.

Address offset: 0x94

Reset value: 0x0C00 0000

6.6.16 RF software high speed external register (RCC_RFSWHSECR)

This register is reset on PADRESETn.

Address offset: 0x98

Reset value: 0x0000 0030

6.6.17 RF high speed external register (RCC_RFHSECR)

This register is reset on PADRESETn.

Address offset: 0x9C

Reset value: 0x0000 0000 when STM32WB07xC and STM32WB06xC flash memory is empty, or else depends on trimmed values flashed in the sample.

Note: The XOTUNE value depends on the choice of the external XO component. For this reason, the RCC_RFSWHSECR.SWXOTUNE bit field is the one to program and select before starting the XO.

6.6.18 RCC register map

Refer to Table 3. STM32WB07xC and STM32WB06xC memory map and peripheral register boundary addresses for the RCC base address location in the STM32WB07xC and STM32WB06xC.

The green cells indicate the register is in the V12o power domain. This implies those registers are not reset on Deepstop exit.

Table 15. RCC register map and reset values

6.7 Programmer model

6.7.1 Switch the system on the PLL64M clock tree

To switch the system from the HSI clock source to the PLL64M clock source, the user has to:

1. 1. Enable the HSE (32 MHz external crystal)
2. 2. Wait for the HSE ready flag information (through interrupt or by polling)
3. 3. Request to enable the PLL
4. 4. Wait for the PLL ready flag information (through interrupt or by polling). From this point, the clock source for the whole fast clock tree is the accurate PLL64M source.

Note: A status flag and an associated interrupt are available to inform the software in case of HSIPLL64M unlock event. See RCC_CIER and RCC_CIFR registers.

6.7.2 Use the direct HSE instead of the RC64MPLL block

If the application does not target to use the 64 MHz system clock frequency, the system can be configured to use directly the 32 MHz provided by the external XO (HSE).

This configuration choice is supposed to be static and to be used when 64 MHz is never used.

In this case, the software has to:

1. 1. Ensure the RCC_CR.CLKSYSDIV bit field is programmed with a system frequency less than 64 MHz
2. 2. Enable the external XO (by setting the RCC_CR.HSEON if not yet done)
3. 3. Wait for the HSE ready flag information (through interrupt or by polling)
4. 4. Set the RCC_CFGR.HSESEL bit to switch the fast clock tree on HSE path. If both clocks (HSI and HSE) are present, the switch should take around 4 clock cycles
5. 5. To save power, the software can stop the RC64MPLL analog block by setting the RCC_CFGR.STOPHSI bit.

Note: A hardware mechanism is in place to restart the RC64MPLL and switch back the clock tree on it if the HSERDY is low or if the CLKSYSDIV bit field has been programmed to request 64 MHz.

Caution: The HSE configuration is not lost on a Deepstop sequence. So at wakeup, the system restarts the HSE (thanks to HEON bit). However, the SW has to switch the system clock back to HSI or PLL64M path to be able to enter in Deepstop/Shutdown, so at wakeup:

• • the clock tree runs on RC64MPLL block (HSI or PLL64M)
• • the SW has to reprogram the HSE mode. However, it is important to avoid the switch of clock tree between HSI and HSE while the MR_BLE already triggered a wakeup event and started its sequence. The SW has to anticipate the CPU wakeup to ensure the final clock source is restored before the radio starts any activity.

6.7.3 Changing the system clock frequency while the MR_BLE is enabled

As long as the MR_BLE is enabled (by setting the RCC_APB2ENR.MRBLEEN), the application software has no guarantee the radio is running or about to start a sequence that makes the MR_BLE IP perform an AHB access to the RAM. Changing the system clock and by this action changing the ratio between MR_BLE clock domain and system clock domain could create a crash if not managed carefully.

For this reason, a hardware mechanism has been put in place and must be used to change the system frequency when MR_BLE is ON.

The sequence to execute to change the system clock is the following:

1. 1. Ensure the targeted frequency is greater than or equal to the MR_BLE frequency (visible in RCC_APB2ENR.CKBLEDIV[1:0])
2. 2. Program the wanted frequency in the RCC_CSCMDR.CLKSYSDIV bit field and set the RCC_CSCMDR.REQUEST bit
3. 3. Wait for the RCC_CSCMDR.EOFSEQ_IRQ flag information (through interrupt or by polling)
4. 4. When the flag (and the interrupt if enabled) is set, the system is running on the new frequency
5. 5. The RCC_CFGR.CLKSYSDIV[1:0] bit field has been updated by hardware to the new frequency value.

Note: If the software requested a frequency below 16 MHz, the current final frequency is 16 MHz (associated value is readable in the RCC_CFGR.CLKSYSDIV[1:0]). If the software requested a frequency at 16 MHz while the MR_BLE is clocked at 32 MHz, the wanted frequency is used but the radio scenario is no longer functional.