4. I/O operating modes

The STM32WB07xC and STM32WB06xC devices propose up to 32 programmable I/Os (depending on the package).

Each I/O can be programmed in several modes:

• Input mode
• General purpose output mode
• Alternate function
• Analog mode (when available)

The STM32WB07xC and STM32WB06xC devices support eight alternate modes called AFx (x = 0 to 7). The configuration of each I/O for those alternate modes is detailed in Table 8. GPIO alternate options AF3 - AF4 and Table 9. I/O analog feature mapping .

Caution: When an external slow clock XO is used (LSE on PB12 and PB13 I/Os), the USART transfers done on PB14 / PB15 I/Os in AF7 generate some disturbances on the slow clock.

Note: I/Os features presented in Table 8. GPIO alternate options AF3 - AF4 and Table 9. I/O analog feature mapping are valid only when the associated I/O is programmed as alternate function.

Refer to Section 7: General-purpose I/Os (GPIO) for more details on all configurations.

The number of I/Os available in the STM32WB07xC and STM32WB06xC devices depends on the package:

• 20 I/Os in VFQFPN32
• 30 I/Os in WLCSP49
• 32 I/Os in VFQFPN48

Type acronyms correspond to:

• I: input
• O: output
• I/O: input output
• OD: open drain

Note: Pin names in bold indicate the I/O is able to wake up the device and is able to be in input or output during Deepstop.

Table 7. GPIO alternate options AF0 - AF2

Pin name	AF0 mode		AF1 mode		AF2 mode
Pin name	Type	Signal	Type	Signal	Type	Signal
Port A
PA0 ⁽¹⁾	I/OD	I2C1_SCL	I	USART_CTS	O	I2S2_MCK
PA1 ⁽¹⁾	I/OD	I2C1_SDA	I/O	SPI2_MISO	I/OD	USART_TX
PA2	I/O	DEBUG_SWDIO	I/O	USART_CK	I	TIM_BKIN
PA3	I	DEBUG_SWCLK	O	USART_RTS_DE	I	TIM_BKIN2
PA4	O	RCC_LCO	I/O	SPI2_NSS/I2S2_WS	-	-
PA5	O	RCC_MCO	I/O	SPI2_SCK/ I2S2_SCK	-	-
PA6	I	LPUART_CTS	I/O	SPI2_MOSI/I2S2_SD	-	-
PA7	O	LPUART_RTS_DE	I/O	SPI2_MISO	-	-
PA8	I/O	USART_RX	I/O	SPI1_MOSI	O	RADIO_RX_SEQUENCE
PA9	I/O	USART_TX	I/O	SPI1_SCK	O	RTC_OUT
PA10	O	RCC_LCO	I/O	SPI1_MISO	O	RADIO_TX_SEQUENCE
PA11	O	RCC_MCO	I/O	SPI1_NSS	O	RADIO_RX_SEQUENCE
PA12 ⁽¹⁾	I/O	I2C1_SMBA	I/O	DEBUG_SWDIO	I/O	SPI1_NSS
PA13 ⁽²⁾	I/O	I2C2_SCL	I	DEBUG_SWCLK	I/O	SPI1_SCK
PA14 ⁽¹⁾	I/O	I2C2_SDA	-	-	I/O	SPI1_MISO
PA15 ⁽¹⁾	I/O	I2C2_SMBA	-	-	I/O	SPI1_MOSI
Port B
PB0 ⁽¹⁾	I/O	USART_RX	O	LPUART_RTS_DE	-	-
PB1 ⁽¹⁾	I/O	SPI1_NSS	O	PDM_CLK	-	-
PB2 ⁽¹⁾	O	USART_RTS_DE	I	PDM_DATA	-	-
PB3 ⁽¹⁾	I	USART_CTS	I/O	LPUART_TX	-	-
PB4 ⁽¹⁾	I/O	LPUART_TX	I/O	SPI2_MISO	-	-
PB5 ⁽¹⁾	I/O	LPUART_RX	I/O	SPI2_MOSI /I2S2_SD	-	-
PB6 ⁽¹⁾	OD	I2C2_SCL	I/O	SPI2_NSS /I2S2_WS	-	-
PB7 ⁽¹⁾	OD	I2C2_SDA	I/O	SPI2_SCK /I2S2_SCK	-	-
PB8	I/O	USART_CK	I/O	LPUART_RX	-	-
PB9	I/O	USART_TX	I	LPUART_CTS	O	I2S2_MCK
PB10	I/O	SPI1_NSS	I/O	SPI2_SCK /I2S2_SCK	I/O	I2C1_SDA
PB11	I/O	SPI1_SCK	I/O	SPI2_NSS /I2S2_WS	I/O	I2C1_SCL
PB12 ⁽¹⁾⁽²⁾	I/O	SPI1_SCK	O	RCC_LCO	I	PDM_DATA
PB13 ⁽¹⁾⁽³⁾	I/O	SPI1_MISO	I/O	I2C2_SCL	O	PDM_CLK
PB14 ⁽¹⁾	I/O	SPI1_MOSI	I/O	I2C2_SDA	I	TIM1_ETR
PB15 ⁽¹⁾	I/O	I2C1_SMBA	O	RADIO_TX_SEQUENCE	O	RCC_MCO

1. This I/O is able to be configured as analog (mixedI/O) in VFQFPN32 package.
2. This I/O is shared with OSC32_OUT (low speed clock oscillator pin) available on VFQFPN48 package from a WLCSP49.
3. This I/O is shared with OSC32_IN (low speed clock oscillator pin).

Note: Refer to the device datasheet for details about the available pin for each supported device package.

Note: For Table 8. GPIO alternate options AF3 - AF4 , pin names in bold indicate the I/O is able to wake up the device and is able to be in input or output during Deepstop.

Table 8. GPIO alternate options AF3 - AF4

Pin name	AF3 mode		AF4 mode
Pin name	Type	Signal	Type	Signal
Port A
PA0 ⁽¹⁾	I	-	I/O	TIM1_CH3
PA1 ⁽¹⁾	O	-	I/O	TIM1_CH4
PA2	O	I2S3_MCK	O	-
PA3	I/O	SPI3_SCK/ I2S3_SCK	O	-
PA4	I/O	LPUART_TX	I/O	TIM1_CH1
PA5	I/O	LPUART_RX	I/O	TIM1_CH2
PA6	I/O	SPI2_NSS/ I2S2_WS	I/O	TIM1_CH1
PA7	I/O	SPI2_SCK/I2S2_SCK	I/O	TIM1_CH2
PA8	I/O	SPI3_MISO	I/O	TIM1_CH3
PA9	I/O	SPI3_NSS/ I2S3_WS	I/O	TIM1_CH4
PA10	O	I2S3_MCK	O	-
PA11	I/O	SPI3_MOSI/ I2S3_SD	O	-
PA12 ⁽²⁾	I/O	SPI2_MOSI/ I2S2_SD	I/O	TIM1_CH1
PA13 ⁽²⁾	I/O	SPI2_MISO	I	TIM1_ETR
PA14 ⁽²⁾	-	-	I	TIM1_BKIN
PA15 ⁽²⁾	-	-	I	TIM1_BKIN2
Port B
PB0 ⁽²⁾	I/O	TIM1_CH2N	-	-
PB1 ⁽²⁾	I	TIM1_ETR	-	-
PB2 ⁽²⁾	I/O	TIM1_CH3	-	-
PB3 ⁽²⁾	I/O	TIM1_CH4	-	-
PB4 ⁽²⁾	I	PDM_DATA	-	-
PB5 ⁽²⁾	O	PDM_CLK	-	-
PB6 ⁽¹⁾	I/O	LPUART_TX	I/O	TIM1_CH1
PB7 ⁽¹⁾	I/O	LPUART_RX	I/O	TIM1_CH2
PB8	I/O	TIM1_CH4	I/O	TIM1_CH1N
PB9	I/O	TIM1_CH1N	I/O	TIM1_CH2N
PB10	I/O	TIM1_CH2	I/O	TIM1_CH3N
PB11	I/O	TIM1_CH1	I/O	TIM1_CH4N
PB12 ⁽²⁾⁽³⁾	I	TIM1_BKIN	I/O	TIM1_CH3
PB13 ⁽²⁾⁽⁴⁾	I	TIM1_BKIN2	I/O	TIM1_CH4
PB14 ⁽²⁾	I/O	TIM1_CH3N	O	-
PB15 ⁽²⁾	I/O	TIM1_CH4N	O	-

1. This I/O is able to be configured in open-drain.
2. This I/O is able to be configured as analog (mixedI/O).
3. This I/O is shared with OSC32_OUT (low speed clock oscillator pin).
4. This I/O is shared with OSC32_IN (low speed clock oscillator pin).

Note: AF5, AF6, AF7 alternate functions:

PA2: SWDIO (AF5, AF7)

PA3: SWCLK (AF5, AF7)

PB14: USART_RX (AF7)

PB15: USART_TX (AF7)

Note: The STM32WB07xC and STM32WB06xC are provided with the RADIO_TX_SEQUENCE and RADIO_RX_SEQUENCE signals which alert, respectively, transmission and reception activities. A signal can be enabled for TX and RX on two pins, through alternate functions:

• RADIO_TX_SEQUENCE is available on PA10 (AF2) or PB15 (AF1)
• RADIO_RX_SEQUENCE is available on PA8 (AF2) or PA11 (AF2)

The signal is high when radio is in TX (or RX), low otherwise.

The signals can be used to control external antenna switching and support coexistence with other wireless technologies.

Note: Concerning the ADC block present in the STM32WB07xC and STM32WB06xC devices:

• The eight ADC channels are available on PA12, PA13, PA14, PA15, PB0, PB1, PB2, PB3
• The two analog microphone pins are available on PB4 and PB5.

The ADC features on those pins are available if the associated pin is configured in analog mode (see Section 7.3.1: General-purpose I/O (GPIO) for more details)

The table below shows the mapping associated to analog configuration (for pins which can support analog mode).
In Table 9. I/O analog feature mapping .

Note: Programming an alternate function sets the output value of the pin: I2C_SDA, I2C_SCL, I2C_SMBA set to 1, SPI_SCK, SPI_NSS, SPI_MISO, SPI_MOSI, SPI_MCK set to 0, UART_RX set to 0 and UART_TX set to 1.

Note: Refer to device the datasheet for details about the available pin for each supported device package.

Table 9. I/O analog feature mapping

Pin name	Analog feature	Pin name	Analog feature	Parallel analog feature
Port A		Port B
PA0	N/A ⁽¹⁾	PB0	ADC_VINM1	N/A ⁽¹⁾
PA1	N/A ⁽¹⁾	PB1	ADC_VINP1	N/A ⁽¹⁾
PA2	N/A ⁽¹⁾	PB2	ADC_VINM0	PGA_CAP0 ⁽²⁾
PA3	N/A ⁽¹⁾	PB3	ADC_VINP0	PGA_CAP1 ⁽²⁾
PA4	N/A ⁽¹⁾	PB4	PGA_VIN	N/A ⁽¹⁾
PA5	N/A ⁽¹⁾	PB5	PGA_VBIAS_MIC ⁽³⁾	N/A ⁽¹⁾
PA6	N/A ⁽¹⁾	PB6	N/A ⁽¹⁾	N/A ⁽¹⁾
PA7	N/A ⁽¹⁾	PB7	N/A ⁽¹⁾	N/A ⁽¹⁾
PA8	N/A ⁽¹⁾	PB8	N/A ⁽¹⁾	N/A ⁽¹⁾
PA9	N/A ⁽¹⁾	PB9	N/A ⁽¹⁾	N/A ⁽¹⁾
PA10	N/A ⁽¹⁾	PB10	N/A ⁽¹⁾	N/A ⁽¹⁾
PA11	N/A ⁽¹⁾	PB11	N/A ⁽¹⁾	N/A ⁽¹⁾
PA12	ADC_VINM3	PB12	N/A ⁽¹⁾	RCC_OSC32_OUT ⁽⁴⁾
PA13	ADC_VINP3	PB13	N/A ⁽¹⁾	RCC_OSC32_IN ⁽⁴⁾
PA14	ADC_VINM2	PB14	N/A ⁽¹⁾	PVD input voltage
PA15	ADC_VINP2	PB15	N/A ⁽¹⁾	N/A

1. N/A means not applicable as the associated I/O does not support analog option.
2. The selection between ADC_VINx0 and PGA_CAPx is done through a register in the SYSCFG block. See Section 8.2.11: I/O analog switch control register (GPIO_SWA_CTRL) .
3. This pin is not 5 V tolerant. All other 31 pins are 5 V tolerant.
4. The parallel analog feature is obtained by setting the RCC_CR.LSEON bit in the RCC registers. Then the PB12 and PB13 are forced by hardware to manage the LSE through RCC_OSC32_OUT / RCC_OSC32_IN whatever the selected mode in the associated GPIO_MODERx register.