2. System and memory overview

2.1 System architecture

The main system consists of a 32-bit multilayer AHB bus matrix that interconnects:

• • Three masters:
  • – CPU (Cortex®-M0+) core S-bus
  • – DMA1
  • – Radio system
• • Nine slaves:
  • – Internal flash memory on CPU (Cortex®-M0+) S bus
  • – Internal SRAM0 (16 Kbytes)
  • – Internal SRAM1 (16 Kbytes)
  • – Internal SRAM2 (16 Kbytes)
  • – Internal SRAM3 (16 Kbytes)
  • – APB0 peripherals (through an AHB to APB bridge)
  • – APB1 peripherals (through an AHB to APB bridge)
  • – AHB0 peripherals
  • – AHBRF including AHB to APB bridge and radio peripherals (connected to APB2)

The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even when several high-speed peripherals work simultaneously. This architecture is shown in Figure 1. STM32WB07xC and STM32WB06xC system architecture .

The system consists of a Cortex®-M0+ “Radio protocol and application” processor with its radio sub-system.

There is a single Flash memory to be used by the CPU for both Bluetooth protocol and application management.

The peripherals are located on the different system buses (AHB, APB0, APB1, APB2 for the radio system). There are 4 SRAM banks, an SRAM0 always power supplied and three SRAM (SRAM1, SRAM2 and SRAM3) that can be programmed to be always on or switchable. For more information see Section 5.7.2: Control register 2 (PWRC_CR2) .

2.1.1 S0: CPU (Cortex ^® -M0+) S-bus

This bus connects the system bus of the CPU core to the BusMatrix. This bus is used by the core to fetch instructions, for literal load and debug access, and access data located in a peripheral or SRAM area. The targets of this bus are all the possible peripherals (the internal flash and SRAM memories, the AHB0, APB0, APB1 and APB2 peripherals).

2.1.2 S1: DMA-bus

This bus connects the AHB master interface of the DMA to the BusMatrix. The targets of this bus are the four banks of SRAM and the APB1 peripheral.

2.1.3 S2: Radio system-bus

This bus connects the AHB master interface of the radio system to the BusMatrix. The targets of this bus are the four banks of SRAM and the APB2 peripherals (internal APB blocks of the MR_BLE/Radio sub-system IP).

2.1.4 BusMatrix

The BusMatrix manages the access arbitration between masters. The arbitration uses a "Round Robin" algorithm. The BusMatrix is composed of three masters (CPU, DMA1-bus and radio system-bus) and nine slaves (FLASH, SRAM0, SRAM1, SRAM2 & SRAM3, APB0 and APB1, AHB0 and AHBRF).

AHB/APB bridges

The two bridges AHB to APB0 and AHB to APB1 provide full synchronous connections between the AHB and the two APB buses.

The bridge AHB to APB2 provides synchronous connections between the AHB and the APB bus. Two blocks are added to the AHB/APB path to manage potential prescaled MR_BLE frequency versus the system frequency:

• • AHB up converter is used for the MR_BLE AHB master transactions towards the SRAM
• • AHB down converter is used for the CPU AHB master transactions towards the MR_BLE APB registers.

Refer to Section 2.2.2: Memory map and register boundary addresses for the address mapping of the peripherals connected to this bridge.

After each device reset, all peripheral clocks are disabled (except for the SRAM and Flash memory interface). Before using a peripheral the user has to enable its clock in the RCC_AHBxENR and the RCC_APBxENR registers.

Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

2.2 Memory organization

2.2.1 Introduction

Program memory, data memory and registers are organized within the same linear 4-Gbyte address space.

These bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word least significant byte and the highest numbered byte the most significant.

Figure 2. Memory map

DT/00198

All the memory areas that are not allocated to on-chip memories and peripherals are considered “Reserved”. For the detailed mapping of available memory and registers areas, refer to Section 2.2.2: Memory map and register boundary addresses and to each peripheral register map section.

2.2.2 Memory map and register boundary addresses

Table 3. STM32WB07xC and STM32WB06xC memory map and peripheral register boundary addresses gives the boundary addresses of the peripherals available in the device.

Table 3. STM32WB07xC and STM32WB06xC memory map and peripheral register boundary addresses

1. 1. This area is a mirroring area. The CPU accesses are redirected to other memory map depending on REMAP and PREMAP bits located in the Flash controller CONFIG register. See Table 5. Address remapping depending on REMAP bit for remapping detail.

SRAM0 memory locations from 0x2000 0000 to 0x2000 0017 are reserved for system use and users are not allowed to use these locations for their application.

2.3 Arm ^® Cortex ^® -M0+

The Arm ^® Cortex ^® -M0+ processor was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The embedded Cortex-M0+ embeds:

• • four breakpoints
• • two watchpoints
• • an MPU (memory protection unit) providing eight unified protection regions
• • a SysTick running only with the system clock (external clock option not supported)

2.3.1 CPU memory remap

Following a CPU boot the application software can modify the memory map at address 0x0000 0000. This modification is performed by programming the REMAP bit in the flash controller (see Section 9.4.2: Configuration register (CONFIG) ).

The following memory can be remapped:

• • Main flash memory
• • SRAM0 memory

Embedded boot loader

ST provides a boot loader executed after each CPU reboot. This boot loader has its own documentation.

Note: The STM32WB07xC and STM32WB06xC device latches the PA8 / PA9 / PA10 / PA11 pads value at POR. The information is available in the PWRC_SR2 register (see Section 5.7.6: Status register 2 (PWRC_SR2) ). One of those four I/Os can be used by the boot loader as boot indication between a normal boot or a boot on serial interface.

2.3.2 Interrupts

Interrupts are handled by the Cortex-M0+ nested vector interrupt controller (NVIC). The NVIC controls specific Cortex-M0+ interrupts (address 0x00 to 0x3C) as well as 32 user interrupts (address 0x40 to 0xBC). In the STM32WB07xC and STM32WB06xC devices, the user interrupts have been connected to the interrupt signals of the different peripherals (GPIO, Flash controller, timers, UART,...). These interrupts can be controlled using the ISER, ICER, ISPR and ICOR registers.

Vector table

On reset, the Cortex-M0+ vector table is fixed at address 0x0000_0000. The software may relocate the vector table address to a different memory location, in a range 0x0000_0000 to 0xFFFF_FF80 in multiples of 256 bytes through the vector table offset register (VTOR) located in the Cortex-M0+ registers area.

The interrupt mapping for the vector table of the STM32WB07xC and STM32WB06xC devices is described in Table 6. Interrupt vectors.

Table 6. Interrupt vectors

1. 1. Some specific cares are needed at SW level to clear the interrupt: see Warning for interrupt clearance when system clock is faster than MR_BLE clock .

Interrupt activation sequence

Safely activating a peripheral interrupt requires the following steps:

• • make sure the interrupt is disabled and cleared on the peripheral side (this prevents receiving an interrupt due to a previous event)
• • clear pending requests for this interrupt on the Cortex-M0+ side using the NVIC ICPR register
• • set the priority using the NVIC IPR0-IPR7 registers
• • activate on the Cortex-M0+ side using the NVIC ISER register
• • activate on the peripheral side

Note that most peripherals require clearing interrupt requests on the peripheral side when handling interrupt service requests to prevent triggering continuous interrupts for the same event.

For more details on the Cortex-M0+ exception model, see “ARMv6-M Architecture Reference Manual”, §B1.5.

For more details on the Cortex-M0+ NVIC behavior and registers, see “ARMv6-M Architecture Reference Manual”, §B3.4.