27. Device electronic signature (DESIG)

The device electronic signature is stored in the System memory area of the flash memory module, and can be read using the debug interface or by the CPU. It contains factoryprogrammed identification and calibration data that allow the user firmware or other external devices to automatically match the characteristics of the microcontroller.

27.1 DESIG registers

27.1.1 DESIG ADC trimming max diff (DESIG_ADCMAXDIFF)

Address offset: 0x000

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:16]
												r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET[19:16]				GAIN[11:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:20	Reserved, must be kept at reset value.
Bits 19:12	OFFSET[19:12] : ADC trimming offset maximum differential (ADC_VINP - ADC_VINM at 1.2 V).
Bits 11:0	GAIN[11:0] : ADC trimming gain maximum differential (ADC_VINP - ADC_VINM at 1.2 V).

27.1.2 DESIG ADC trimming max negative (DESIG_ADCMAXNEG)

Address offset: 0x004

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:16]
												r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET[19:16]				GAIN[11:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:20	Reserved, must be kept at reset value.
Bits 19:12	OFFSET[19:12] : ADC trimming offset maximum negative (ADC_VINM at 1.2 V).
Bits 11:0	GAIN[11:0] : ADC trimming gain maximum negative (ADC_VINM at 1.2 V).

27.1.3 DESIG ADC trimming max positive (DESIG_ADCMAXPOS)

Address offset: 0x008

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:16]
												r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET[19:16]				GAIN[11:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:20	Reserved, must be kept at reset value.
Bits 19:12	OFFSET[19:12] : ADC trimming offset maximum positive (ADC_VINP at 1.2 V).
Bits 11:0	GAIN[11:0] : ADC trimming gain maximum positive (ADC_VINP at 1.2 V).

27.1.4 DESIG ADC trimming mean diff (DESIG_ADCMEANDIFF)

Address offset: 0x00C

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:16]
												r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET[19:16]				GAIN[11:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:20	Reserved, must be kept at reset value.
Bits 19:12	OFFSET[19:12] : ADC trimming offset mean differential (ADC_VINP - ADC_VINM at 2.4 V).
Bits 11:0	GAIN[11:0] : ADC trimming gain mean differential (ADC_VINP - ADC_VINM at 2.4 V).

27.1.5 DESIG ADC trimming mean negative (DESIG_ADCMEANNEG)

Address offset: 0x010

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:16]
												r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET[19:16]					GAIN[11:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:20	Reserved, must be kept at reset value.
Bits 19:12	OFFSET[19:12] : ADC trimming offset mean negative (ADC_VINM at 2.4 V).
Bits 11:0	GAIN[11:0] : ADC trimming gain mean negative (ADC_VINM at 2.4 V).

27.1.6 DESIG ADC trimming max positive (DESIG_ADCMEANPOS)

Address offset: 0x000

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:16]
												r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET[19:16]					GAIN[11:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:20	Reserved, must be kept at reset value.
Bits 19:12	OFFSET[19:12] : ADC trimming offset mean positive (ADC_VINP at 2.4 V).
Bits 11:0	GAIN[11:0] : ADC trimming gain mean positive (ADC_VINP at 2.4 V).

27.1.7 DESIG ADC trimming min diff (DESIG_ADCMINDIFF)

Address offset: 0x018

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:16]
												r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET[19:16]				GAIN[11:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:20	Reserved, must be kept at reset value.
Bits 19:12	OFFSET[19:12] : ADC trimming offset minimum differential (ADC_VINP - ADC_VINM at 3.6 V).
Bits 11:0	GAIN[11:0] : ADC trimming gain minimum differential (ADC_VINP - ADC_VINM at 3.6 V).

27.1.8 DESIG ADC trimming min negative (DESIG_ADCMINNEG)

Address offset: 0x01C

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:16]
												r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET[19:16]				GAIN[11:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:20	Reserved, must be kept at reset value.
Bits 19:12	OFFSET[19:12] : ADC trimming offset minimum negative (ADC_VINM at 3.6 V).
Bits 11:0	GAIN[11:0] : ADC trimming gain minimum negative (ADC_VINM at 3.6 V).

27.1.9 DESIG ADC trimming min positive (DESIG_ADCMINPOS)

Address offset: 0x020

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:16]
												r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET[19:16]				GAIN[11:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:20	Reserved, must be kept at reset value.
Bits 19:12	OFFSET[19:12] : ADC trimming offset minimum positive (ADC_VINP at 3.6 V).
Bits 11:0	GAIN[11:0] : ADC trimming gain minimum positive (ADC_VINP at 3.6 V).

27.1.10 DESIG reference temperature register (DESIG_TSREFR)

Address offset: 0x05C

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TS_REF[31:16]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TS_REF[15:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:0

TS_REF[31:0] : reference temperature for ADC at 30°C.

27.1.11 DESIG temperature calibration register (DESIG_TSCAL1R)

Address offset: 0x060

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TS_CAL[31:16]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TS_CAL[15:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:0

TS_CAL[31:0] : temperature measurement calibration for ADC at 30°C.

27.1.12 DESIG package data register (DESIG_PKGR)

Address offset: 0x0EC

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PKG[31:16]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PKG[15:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:0

TS_REF[31:0]:
Package type:
0x5F325F32: VFQFPN32
0xAC36AC36: WLCSP36

27.1.13 DESIG 64-bit unique device identifier register 1 (DESIG_UID64R1)

Address offset: 0x0F0

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UID[31:16]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UID[15:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:0

UID[31:0]: unique serial number (first 4 bytes)

27.1.14 DESIG 64-bit unique device identifier register 2 (DESIG_UID64R2)

Address offset: 0x0F4

Reset value: 0xXXXX XXXX (X is factory-programmed)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UID[63:48]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UID[47:32]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:0

UID[63:32]: unique serial number (last 4 bytes)

27.1.15 DESIG register map

STMicroelectronics logo

Table 286. PWRC register map

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x000	DESIG_ADCMA XDIFF	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:12]																				GAIN[11:0]
0x000	Reset value													X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
0x004	DESIG_ADCMA XNEG	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:12]																			GAIN[11:0]
0x004	Reset value													X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
0x008	DESIG_ADCMA XPOS	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:12]																			GAIN[11:0]
0x008	Reset value													X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
0x00C	DESIG_ADCME ANDIFF	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:12]																			GAIN[11:0]
0x00C	Reset value													X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
0x010	DESIG_ADCME ANNNEG	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:12]																			GAIN[11:0]
0x010	Reset value													X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
0x014	DESIG_ADCME ANPOS	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:12]																			GAIN[11:0]
0x014	Reset value													X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
0x018	DESIG_ADCMI NDIFF	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:12]																			GAIN[11:0]
0x018	Reset value													X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
0x01C	DESIG_ADCMI NNEG	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:12]																			GAIN[11:0]
0x01C	Reset value													X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
0x020	DESIG_ADCMI NPOS	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OFFSET[19:12]																			GAIN[11:0]
0x020	Reset value													X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X
0x024 - 0x5B	Reserved	Res.
0x05C	DESIG_TSREF R	TS_REF[31:0]
0x05C	Reset value	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
0x060	DESIG_TSCAL 1R	PKG [31:0]

STMicroelectronics logo

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x060	Reset value	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
0x064 0xE8	Reserved	Res.
0x0EC	DESIG_PKGR	PKG[31:0]
0x0EC	Reset value	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
0x0F0	DESIG_UID64R 1	UID[31:0]
0x0F0	Reset value	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
0x0F4	DESIG_UID64R 2	UID[63:32]
0x0F4	Reset value	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses.

Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST product(s) identified in this documentation may be certified by various security certification bodies and/or may implement our own security measures as set forth herein. However, no level of security certification and/or built-in security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the customer needs both in relation to the ST product alone, as well as when combined with other components and/or software for the customer end product or application. In particular, take note that:

• ST products may have been certified by one or more security certification bodies, such as Platform Security Architecture ( www.psacertified.org ) and/or Security Evaluation standard for IoT Platforms ( www.trustcb.com ). For details concerning whether the ST product(s) referenced herein have received security certification along with the level and current status of such certification, either visit the relevant certification standards website or go to the relevant product page on www.st.com for the most up to date information. As the status and/or level of security certification for an ST product can change from time to time, customers should re-check security certification status/level as needed. If an ST product is not shown to be certified under a particular security standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST products. These certification bodies are therefore independently responsible for granting or revoking security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations, assessments, testing, or other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard technologies which may be used in conjunction with an ST product are based on standards which were not developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open technologies or for any methods which have been or may be developed to bypass, decrypt or crack such algorithms or technologies.
• While robust security testing may be done, no level of certification can absolutely guarantee protections against all attacks, including, for example, against advanced attacks which have not been tested for, against new or unidentified forms of attack, or against any form of attack when using an ST product outside of its specification or intended use, or in conjunction with other components or software which are used by customer to create their end product or application. ST is not responsible for resistance against such attacks. As such, regardless of the incorporated security features and/or any information or support that may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for meets their needs, both in relation to the ST product alone and when incorporated into a customer end product or application.
• All security features of ST products (inclusive of any hardware, software, documentation, and the like), including but not limited to any enhanced security features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the applicable written and signed contract terms specifically provide otherwise.

Revision history

Table 287. Document revision history

Date	Version	Changes
25-Jun-2024	1	Initial release.
20-Nov-2024	2	Updated: Section 7.3.2: I/O pin alternate function multiplexer and mapping (EVENTOUT description) Table 18. GPIO register map and reset values (typo in register name @0x18) Table 22. Command list available for customer Section 11.5.1: DMAMUX request line multiplexer channel x configuration register (DMAMUX_CxCR) Figure 22. ADC top level diagram Section 12.2.1: Temperature sensor subsystem Figure 23. ADC sampling time Tsw and sampling period Ts Section 12.5.1: ADC mode overview Added: Section 12.2.2: Battery sensor Section 12.2.6: Calibration points Cross-reference note to DESIG registers in Section 12.6.8: ADC gain and offset correction 1 register (COMP_1) through Section 12.6.11: ADC gain and offset correction 4 register (COMP_4). Removed ADC TIMER_CONF register.
4-Apr-2025	3	Added correct references to Deepstop mode Updated referenced to Bluetooth standard Updated Section 6.6: RCC registers Updated Section 9.5.5: Enabling protection example Updated Section 21: Inter-integrated circuit (I2C) interface
22-Oct-2025	4	Updated: Section 12.5.1: ADC mode overview Section 12.6.3: ADC control register (CTRL) Section 25.9.3: Wakeup management

Contents

1	Documentation conventions . . . . .	2
1.1	General information . . . . .	2
1.2	List of abbreviations for registers . . . . .	2
1.3	Glossary . . . . .	2
1.4	Availability of peripherals . . . . .	3
1.5	Acronyms . . . . .	3
2	System and memory overview . . . . .	6
2.1	System architecture . . . . .	6
2.1.1	S0: CPU (Cortex®-M0+) S-bus . . . . .	7
2.1.2	S1: DMA-bus . . . . .	7
2.1.3	S2: radio system-bus . . . . .	7
2.1.4	BusMatrix . . . . .	7
2.2	Memory organization . . . . .	7
2.2.1	Introduction . . . . .	7
2.2.2	Memory map and register boundary addresses . . . . .	9
2.3	Arm® Cortex®-M0+ . . . . .	10
2.3.1	CPU memory remap . . . . .	11
2.3.2	Interrupts . . . . .	11
3	AHB up/down converter . . . . .	14
3.1	AHB up/down converter description . . . . .	14
4	I/O operating modes . . . . .	16
5	Power controller (PWRC) . . . . .	20
5.1	Features . . . . .	20
5.2	Power supply domains . . . . .	20
5.3	Power voltage supervisor . . . . .	21
5.3.1	Power-on reset POR / power-down reset (PDR) / Brownout Reset (BOR) . . . . .	21
5.3.2	Power voltage detection (PVD) . . . . .	22
5.4	Operating modes . . . . .	22
5.4.1	Run mode . . . . .	22
5.4.2	Deepstop mode . . . . .	23
5.4.3	Shutdown mode . . . . .	25
5.4.4	Operating mode transition management . . . . .	26
5.5	SMPS step-down regulator . . . . .	27
5.6	I/O pull-ups/pull-downs during low power mode . . . . .	29
5.7	PWRC registers . . . . .	30

5.7.1	Control register 1 (PWRC_CR1) . . . . .	30
5.7.2	Control register 2 (PWRC_CR2) . . . . .	31
5.7.3	Control register 3 (PWRC_CR3) . . . . .	32
5.7.4	Control register 4 (PWRC_CR4) . . . . .	34
5.7.5	Status register 1 (PWRC_SR1) . . . . .	35
5.7.6	Status register 2 (PWRC_SR2) . . . . .	37
5.7.7	Control register 5 (PWRC_CR5) . . . . .	39
5.7.8	I/O port A pull-up control register (PWRC_PUCRA) . . . . .	41
5.7.9	I/O port A pull-down control register (PWRC_PDCRA) . . . . .	42
5.7.10	I/O port B pull-up control register (PWRC_PUCRB) . . . . .	43
5.7.11	I/O port B pull-down control register (PWRC_PDCRB) . . . . .	45
5.7.12	Control register 6 (PWRC_CR6) . . . . .	47
5.7.13	Control register 7 (PWRC_CR7) . . . . .	48
5.7.14	Status register 3(PWRC_SR3) . . . . .	49
5.7.15	Debug register (PWRC_DBGR) . . . . .	50
5.7.16	Extended status and reset register (PWRC_EXTSRR) . . . . .	51
5.7.17	PWRC register map . . . . .	52
5.8	Programmer model . . . . .	55
5.8.1	Reset reason management . . . . .	55
5.8.2	SMPS output level re-programming . . . . .	55
6	Reset and clock controller (RCC) . . . . .	57
6.1	Reset management. . . . .	57
6.1.1	General description. . . . .	57
6.1.2	Power reset. . . . .	58
6.1.3	Watchdog reset. . . . .	58
6.1.4	LOCKUP reset . . . . .	58
6.1.5	System reset request . . . . .	58
6.1.6	Deepstop exit . . . . .	58
6.2	Clock management . . . . .	58
6.2.1	System clock details . . . . .	59
6.2.2	Peripheral clock details . . . . .	60
6.2.3	Slow clock frequency details . . . . .	61
6.3	System frequency switch while MR_BLE is used . . . . .	61
6.4	Clock observation on external pad . . . . .	62
6.5	Miscellaneous . . . . .	62
6.5.1	IO BOOSTER . . . . .	62
6.6	RCC registers . . . . .	63
6.6.1	Clock source control register (RCC_CR) . . . . .	63

6.6.2	Clocks configuration register (RCC_CFGR) . . . . .	65
6.6.3	Clocks Sources Software Calibration register (RCC_CSSWCR) . . . . .	67
6.6.4	Clock interrupt enable register (RCC_CIER) . . . . .	69
6.6.5	Clock interrupt flag register (RCC_CIFR) . . . . .	70
6.6.6	Clock switch command register (RCC_CSCMDR) . . . . .	71
6.6.7	AHB0 macro cells reset register (RCC_AHBRSTR) . . . . .	73
6.6.8	APB0 macro cells reset register (RCC_APB0RSTR) . . . . .	73
6.6.9	APB1 macro cells reset register (RCC_APB1RSTR) . . . . .	74
6.6.10	APB2 macro cells reset register (RCC_APB2RSTR) . . . . .	76
6.6.11	AHB0 macro cells clock enable register (RCC_AHBENR) . . . . .	76
6.6.12	APB0 macro cell clock enable register (RCC_APB0ENR) . . . . .	77
6.6.13	APB1 macro cells clock enable register (RCC_APB1ENR) . . . . .	78
6.6.14	APB2 macro cells clock enable register (RCC_APB2ENR) . . . . .	80
6.6.15	V33 reset status register (RCC_CSR) . . . . .	81
6.6.16	RF software high speed external register (RCC_RFSWHSECR) . . . . .	82
6.6.17	RF high speed external register (RCC_RFHSECR) . . . . .	83
6.6.18	RCC register map . . . . .	84
6.7	Programmer model . . . . .	88
6.7.1	Switch the system on the PLL64M clock tree . . . . .	88
6.7.2	Use the direct HSE instead of the RC64MPLL block . . . . .	88
6.7.3	Changing the system clock frequency while the MR_BLE is enabled . . . . .	89
7	General-purpose I/O (GPIO) . . . . .	90
7.1	Introduction . . . . .	90
7.2	GPIO main features . . . . .	90
7.3	GPIO functional description . . . . .	90
7.3.1	General-purpose I/O (GPIO) . . . . .	92
7.3.2	I/O pin alternate function multiplexer and mapping . . . . .	93
7.3.3	I/O port control registers . . . . .	93
7.3.4	I/O port data registers . . . . .	93
7.3.5	I/O data bitwise handling . . . . .	94
7.3.6	GPIO locking mechanism . . . . .	94
7.3.7	I/O alternate function input/output . . . . .	94
7.3.8	External interrupt/wakeup lines . . . . .	94
7.3.9	Input configuration . . . . .	94
7.3.10	Output configuration . . . . .	95
7.3.11	Alternate function configuration . . . . .	96
7.3.12	Analog configuration . . . . .	96
7.3.13	Using the LSE oscillator pins as GPIOs . . . . .	97

7.4	GPIO registers . . . . .	98
7.4.1	GPIOA port mode register (GPIOA_MODER) . . . . .	98
7.4.2	GPIOB port mode register (GPIOB_MODER) . . . . .	98
7.4.3	GPIOA port output type register (GPIOA_OTYPER) . . . . .	99
7.4.4	GPIOB port output type register (GPIOB_OTYPER) . . . . .	99
7.4.5	GPIOA port output speed register (GPIOA_OSPEEDR) . . . . .	100
7.4.6	GPIOB port output speed register (GPIOB_OSPEEDR) . . . . .	100
7.4.7	GPIOA port pull-up/pull-down register (GPIOA_PUPDR) . . . . .	101
7.4.8	GPIOB port pull-up/pull-down register (GPIOB_PUPDR) . . . . .	101
7.4.9	GPIOA port input data register (GPIOA_IDR) . . . . .	102
7.4.10	GPIOB port input data register (GPIOB_IDR) . . . . .	102
7.4.11	GPIOA port output data register (GPIOA_ODR) . . . . .	103
7.4.12	GPIOB port output data register (GPIOB_ODR) . . . . .	103
7.4.13	GPIOA port bit set/reset register (GPIOA_BSRR) . . . . .	104
7.4.14	GPIOB port bit set/reset register (GPIOB_BSRR) . . . . .	104
7.4.15	GPIOA port configuration lock register (GPIOA_LCKR) . . . . .	105
7.4.16	GPIOB port configuration lock register (GPIOB_LCKR) . . . . .	105
7.4.17	GPIOA alternate function low register (GPIOA_AFRL) . . . . .	107
7.4.18	GPIOB alternate function low register (GPIOB_AFRL) . . . . .	107
7.4.19	GPIOA alternate function high register (GPIOA_AFRH) . . . . .	108
7.4.20	GPIOB alternate function high register (GPIOB_AFRH) . . . . .	108
7.4.21	GPIOA port bit reset register (GPIOA_BRR) . . . . .	108
7.4.22	GPIOB port bit reset register (GPIOB_BRR) . . . . .	109
7.4.23	GPIO register map . . . . .	110
8	System controller (SYSCFG) . . . . .	113
8.1	SYSCFG main features . . . . .	113
8.2	System controller registers. . . . .	113
8.2.1	Die ID register (DIE_ID) . . . . .	113
8.2.2	JTAG ID register (JTAG_ID) . . . . .	114
8.2.3	I2C Fast-Mode Plus pin capability control register (I2C_FMP_CTRL) . . . . .	115
8.2.4	I/O interrupt detection type register (IO_DTR) . . . . .	116
8.2.5	I/O interrupt edge register (IO_IBER) . . . . .	117
8.2.6	I/O interrupt polarity event register (IO_IEVR) . . . . .	118
8.2.7	I/O interrupt enable register (IO_IER) . . . . .	119
8.2.8	I/O Interrupt status and clear register (IO_ISCR) . . . . .	120
8.2.9	Power controller interrupt enable register (PWRC_IER) . . . . .	121
8.2.10	Power controller interrupt status and clear register (PWRC_ISCR) . . . . .	122
8.2.11	MR_BLE RX or TX sequence information detection type register (BLERXTX_DTR) . . . . .	123

8.2.12	MR_BLE RX or TX sequence information detection type register (BLERXTX_IBER) . . .	124
8.2.13	MR_BLE RX or TX sequence information detection event register (BLERXTX_IEVR) . . .	125
8.2.14	MR_BLE RX or TX sequence information detection interrupt enable register (BLERXTX_IER) . . . . .	126
8.2.15	MR_BLE RX or TX sequence information detection status and clear register (BLERXTX_ISCR) . . . . .	127
8.2.16	System controller register map . . . . .	128
9	Embedded Flash memory . . . . .	131
9.1	Flash main features . . . . .	131
9.2	Description . . . . .	131
9.3	Flash controller register map . . . . .	132
9.4	Flash controller registers . . . . .	133
9.4.1	Command register (COMMAND) . . . . .	133
9.4.2	Configuration register (CONFIG) . . . . .	134
9.4.3	Interrupt status register (IRQSTAT) . . . . .	135
9.4.4	Interrupt mask register (IRQMASK) . . . . .	136
9.4.5	Raw status register (IRQRAW) . . . . .	137
9.4.6	SIZE register . . . . .	138
9.4.7	Address register (ADDRESS) . . . . .	139
9.4.8	Linear feedback shift register (LFSRVAL) . . . . .	140
9.4.9	Main Flash page protection registers (PAGEPROTx) . . . . .	140
9.4.10	Data registers (DATA0-DATA3) . . . . .	142
9.5	Programmer model . . . . .	143
9.5.1	General information . . . . .	143
9.5.2	Read function examples . . . . .	144
9.5.3	Erase function examples . . . . .	144
9.5.4	Write function examples . . . . .	145
9.5.5	Enabling protection example . . . . .	146
9.5.6	OTP function example . . . . .	146
9.5.7	Write page protection example . . . . .	148
10	DMA controller (DMA) . . . . .	149
10.1	DMA introduction . . . . .	149
10.2	DMA main features . . . . .	149
10.3	DMA functional description . . . . .	149
10.3.1	DMA transactions . . . . .	149
10.3.2	Arbiter . . . . .	150
10.3.3	DMA channels . . . . .	150
10.3.4	Programmable data width, data alignment and endians . . . . .	151

10.3.5	Error management . . . . .	152
10.3.6	Interrupts. . . . .	152
10.3.7	DMA request mapping . . . . .	152
10.4	DMA registers . . . . .	153
10.4.1	DMA interrupt status register (DMA_ISR) . . . . .	153
10.4.2	DMA interrupt flag clear register (DMA_IFCR) . . . . .	154
10.4.3	DMA channel x configuration register (DMA_CCRx) (x = 1..8, where x = channel number) . . . . .	155
10.4.4	DMA channel x number of data register (DMA_CNDTRx) (x = 1..8, where x = channel number). . . . .	157
10.4.5	DMA channel x peripheral address register (DMA_CPARx) (x = 1..8, where x = channel number). . . . .	158
10.4.6	DMA channel x memory address register (DMA_CMARx) (x = 1..8, where x = channel number). . . . .	159
10.4.7	DMA register map . . . . .	160
11	DMA request multiplexer (DMAMUX) . . . . .	164
11.1	Introduction . . . . .	164
11.2	DMAMUX main features. . . . .	164
11.3	DMAMUX implementation . . . . .	164
11.3.1	DMAMUX instantiation . . . . .	164
11.3.2	DMAMUX mapping . . . . .	165
11.4	DMAMUX functional description . . . . .	165
11.4.1	DMAMUX block diagram. . . . .	165
11.4.2	DMAMUX channels. . . . .	166
11.4.3	DMAMUX request line multiplexer. . . . .	166
11.5	DMAMUX registers . . . . .	167
11.5.1	DMAMUX request line multiplexer channel x configuration register (DMAMUX_CxCR) . . . . .	167
11.5.2	DMAMUX register map . . . . .	168
12	Analog digital converter (ADC). . . . .	170
12.1	Features . . . . .	170
12.2	ADC presentation . . . . .	170
12.2.1	Temperature sensor subsystem . . . . .	171
12.2.2	Battery sensor. . . . .	172
12.2.3	ADC input mode conversion . . . . .	172
12.2.4	Steady-state input impedance. . . . .	172
12.2.5	Input signal sampling transient response . . . . .	172
12.2.6	Calibration points . . . . .	173
12.2.7	Down sampler (DS). . . . .	174
12.3	Interrupts . . . . .	175

12.4	DMA interface	175
12.5	ADC mode	175
12.5.1	ADC mode overview	175
12.6	ADC registers	177
12.6.1	Version register (VERSION_ID)	177
12.6.2	ADC configuration register (CONF)	177
12.6.3	ADC control register (CTRL)	179
12.6.4	ADC input voltage switch selection register (SWITCH)	180
12.6.5	Down sampler configuration register (DS_CONF)	181
12.6.6	ADC sequence programming 1 register (SEQ_1)	182
12.6.7	ADC sequence programming 2 register (SEQ_2)	183
12.6.8	ADC gain and offset correction 1 register (COMP_1)	184
12.6.9	ADC gain and offset correction 2 register (COMP_2)	185
12.6.10	ADC gain and offset correction 3 register (COMP_3)	185
12.6.11	ADC gain and offset correction 4 register (COMP_4)	186
12.6.12	ADC gain and offset selection register (COMP_SEL)	187
12.6.13	ADC watchdog threshold register (WD_TH)	188
12.6.14	ADC watchdog configuration register (WD_CONF)	189
12.6.15	Down sampler data out register (DS_DATAOUT)	189
12.6.16	ADC interrupt status register (IRQ_STATUS)	190
12.6.17	ADC interrupt enable register (IRQ_ENABLE)	191
12.6.18	ADC register map	192
13	Public key accelerator (PKA)	195
13.1	Introduction	195
13.2	PKA main features	195
13.3	PKA functional description	195
13.3.1	Enabling/disabling PKA	196
13.3.2	PKA RAM	197
13.3.3	Executing a PKA operation	197
13.3.4	Security level	197
13.3.5	PKA error management	197
13.4	Operating modes	198
13.4.1	Compute Montgomery parameter	199
13.4.2	Compute modular exponentiation	200
13.4.3	Compute the ECC scalar multiplication	201
13.4.4	Point check	202
13.4.5	ECDSA sign	203
13.4.6	ECDSA verification	204

13.4.7	RSA CRT exponentiation . . . . .	205
13.4.8	Modular reduction . . . . .	205
13.4.9	Arithmetic addition . . . . .	206
13.4.10	Arithmetic Subtraction . . . . .	207
13.4.11	Comparison . . . . .	208
13.4.12	Arithmetic multiplication . . . . .	208
13.4.13	Modular addition . . . . .	209
13.4.14	Modular inversion . . . . .	209
13.4.15	Modular subtraction. . . . .	210
13.4.16	Montgomery multiplication. . . . .	210
13.5	Processing time . . . . .	211
13.5.1	PKA interrupts. . . . .	213
13.6	PKA registers. . . . .	214
13.6.1	PKA control register (PKA_CR). . . . .	214
13.6.2	PKA status register (PKA_SR) . . . . .	216
13.6.3	PKA clear flag register (PKA_CLRFR) . . . . .	217
13.6.4	PKA RAM memory . . . . .	218
13.6.5	PKA register map . . . . .	219
14	Random number generator (RNG). . . . .	220
14.1	Features . . . . .	220
14.2	RNG registers . . . . .	221
14.2.1	RNG configuration register (RNG_CR) . . . . .	221
14.2.2	RNG status flag register (RNG_SR) . . . . .	222
14.2.3	RNG value register (RNG_VAL) . . . . .	222
14.2.4	RNG register map . . . . .	223
15	Cyclic redundancy check calculation unit (CRC) . . . . .	224
15.1	Introduction . . . . .	224
15.2	CRC main features . . . . .	224
15.3	CRC functional description. . . . .	224
15.3.1	CRC block diagram. . . . .	224
15.3.2	CRC operation . . . . .	225
15.4	CRC registers . . . . .	226
15.4.1	Data register (CRC_DR) . . . . .	226
15.4.2	Independent data register (CRC_IDR) . . . . .	226
15.4.3	Control register (CRC_CR) . . . . .	227
15.4.4	Initial CRC value (CRC_INIT) . . . . .	227
15.4.5	CRC polynomial (CRC_POL) . . . . .	228

15.4.6	CRC register map . . . . .	229
16	General purpose timer (TIM2) . . . . .	230
16.1	TIM2 introduction. . . . .	230
16.2	TIM2 main features . . . . .	230
16.3	TIM2 functional description . . . . .	231
16.3.1	Time-base unit . . . . .	231
16.3.2	Counter modes . . . . .	233
16.3.3	Repetition counter. . . . .	241
16.3.4	External trigger input. . . . .	242
16.3.5	Clock selection . . . . .	242
16.3.6	Capture/compare channels . . . . .	244
16.3.7	Input capture mode . . . . .	246
16.3.8	PWM input mode . . . . .	246
16.3.9	Forced output mode . . . . .	248
16.3.10	Output compare mode . . . . .	248
16.3.11	PWM mode . . . . .	249
16.3.12	Asymmetric PWM mode . . . . .	251
16.3.13	Combined PWM mode . . . . .	252
16.3.14	Clearing the OCxREF signal on an external event . . . . .	253
16.3.15	One-pulse mode . . . . .	254
16.3.16	Retriggerable one-pulse mode (OPM). . . . .	255
16.3.17	Encoder interface mode . . . . .	255
16.3.18	UIF bit remapping . . . . .	258
16.3.19	Timer input XOR function. . . . .	258
16.3.20	DMA burst mode . . . . .	258
16.4	TIM2 registers . . . . .	260
16.4.1	TIM2 control register 1 (TIMx_CR1) . . . . .	260
16.4.2	TIM2 control register 2 (TIMx_CR2) . . . . .	262
16.4.3	TIM2 slave mode control register (TIMx_SMCR). . . . .	263
16.4.4	TIM2 DMA/interrupt enable register (TIMx_DIER). . . . .	265
16.4.5	TIM2 status register (TIMx_SR) . . . . .	266
16.4.6	TIM2 event generation register (TIMx_EGR). . . . .	267
16.4.7	TIM2 capture/compare mode register 1 (TIMx_CCMR1). . . . .	268
16.4.8	TIM2 capture/compare mode register 2 (TIMx_CCMR2). . . . .	272
16.4.9	TIM2 capture/compare enable register (TIMx_CCER). . . . .	274
16.4.10	TIM2 counter (TIMx_CNT) . . . . .	275
16.4.11	TIM2 prescaler (TIMx_PSC) . . . . .	275
16.4.12	TIM2 auto-reload register (TIMx_ARR) . . . . .	276

16.4.13	TIM2 repetition counter register (TIMx_RCR) . . . . .	276
16.4.14	TIM2 capture/compare register 1 (TIMx_CCR1) . . . . .	276
16.4.15	TIM2 capture/compare register 2 (TIMx_CCR2) . . . . .	277
16.4.16	TIM2 capture/compare register 3 (TIMx_CCR3) . . . . .	277
16.4.17	TIM2 capture/compare register 4 (TIMx_CCR4) . . . . .	278
16.4.18	TIM2 DMA control register (TIM2_DCR) . . . . .	279
16.4.19	TIM2 DMA address for full transfer (TIM2_DMAR) . . . . .	280
16.4.20	TIM2 input selection register (TIM2_TISEL) . . . . .	280
16.4.21	TIM2 register map. . . . .	281
17	General purpose timer (TIM16/17) . . . . .	285
17.1	TIM16/17 introduction. . . . .	285
17.2	TIM16 and TIM17 main features . . . . .	285
17.3	TIM16/17 functional description. . . . .	286
17.3.1	Time-base unit . . . . .	286
17.3.2	Counter modes . . . . .	287
17.3.3	Repetition counter. . . . .	290
17.3.4	Clock selection . . . . .	291
17.3.5	Capture/compare channels. . . . .	291
17.3.6	Input capture mode. . . . .	293
17.3.7	Forced output mode . . . . .	294
17.3.8	Output compare mode . . . . .	294
17.3.9	PWM mode . . . . .	295
17.3.10	Complementary outputs and deadtime insertion . . . . .	296
17.3.11	Using the break function . . . . .	297
17.3.12	Bidirectional break inputs . . . . .	299
17.3.13	One-pulse mode . . . . .	300
17.3.14	UIF bit remapping . . . . .	301
17.3.15	DMA burst mode. . . . .	301
17.4	TIM16/17 registers . . . . .	303
17.4.1	TIM16/17 control register 1 (TIMx_CR1) . . . . .	304
17.4.2	TIM16/17 control register 2 (TIMx_CR2) . . . . .	306
17.4.3	TIM16/17 DMA/interrupt enable register (TIMx_DIER) . . . . .	307
17.4.4	TIM16/17 status register (TIMx_SR) . . . . .	308
17.4.5	TIM16 and 17 event generation register (TIMx_EGR) . . . . .	309
17.4.6	TIM16/17 capture/compare mode register 1 (TIMx_CCMR1) . . . . .	310
17.4.7	TIM16/17 capture/compare enable register (TIMx_CCER) . . . . .	313
17.4.8	TIM16/17 counter (TIMx_CNT) . . . . .	315
17.4.9	TIM16/17 prescaler (TIMx_PSC) . . . . .	316

17.4.10	TIM16/17 auto-reload register (TIMx_ARR) . . . . .	317
17.4.11	TIM16/17 repetition counter register (TIMx_RCR). . . . .	318
17.4.12	TIM16/17 capture/compare register 1 (TIMx_CCR1). . . . .	319
17.4.13	TIM16/17 break and deadtime register (TIMx_BDTR). . . . .	320
17.4.14	TIM16/17 DMA control register (TIMx_DCR). . . . .	323
17.4.15	TIM16/17 DMA address for full transfer (TIMx_DMAR). . . . .	324
17.4.16	TIM17 option register 1 (TIM17_OR1). . . . .	325
17.4.17	TIM16/17 alternate function register 1(TIMx_AF1) . . . . .	326
17.4.18	TIM16/17 input selection register (TIM16_TISEL). . . . .	328
17.4.19	TIM16/17 register map . . . . .	329
18	Infrared interface (IRTIM) . . . . .	332
19	Real-time clock (RTC). . . . .	333
19.1	Introduction . . . . .	333
19.2	RTC main features . . . . .	333
19.3	RTC functional description. . . . .	334
19.3.1	RTC block diagram . . . . .	334
19.3.2	Clock and prescalers. . . . .	334
19.3.3	Real-time clock and calendar . . . . .	335
19.3.4	Programmable alarm. . . . .	335
19.3.5	Periodic auto-wakeup . . . . .	335
19.3.6	RTC initialization and configuration. . . . .	336
19.3.7	Reading the calendar . . . . .	337
19.3.8	Resetting the RTC. . . . .	337
19.3.9	RTC synchronization. . . . .	337
19.3.10	RTC smooth digital calibration. . . . .	338
19.3.11	Calibration clock output. . . . .	339
19.3.12	Alarm output . . . . .	340
19.4	RTC low-power modes . . . . .	340
19.5	RTC interrupts . . . . .	340
19.6	RTC registers. . . . .	341
19.6.1	RTC time register (RTC_TR). . . . .	341
19.6.2	RTC date register (RTC_DR) . . . . .	342
19.6.3	RTC control register (RTC_CR) . . . . .	343
19.6.4	RTC initialization and status register (RTC_ISR). . . . .	345
19.6.5	RTC prescaler register (RTC_PRER) . . . . .	347
19.6.6	RTC wakeup timer register (RTC_WUTR). . . . .	347
19.6.7	RTC alarm A register (RTC_ALRMAR) . . . . .	348

19.6.8	RTC write protection register (RTC_WPR) . . . . .	349
19.6.9	RTC sub-second register (RTC_SSR) . . . . .	349
19.6.10	RTC shift control register (RTC_SHIFTR) . . . . .	350
19.6.11	RTC calibration register (RTC_CALR) . . . . .	351
19.6.12	RTC alarm A sub second register (RTC_ALRMASSR) . . . . .	352
19.6.13	RTC backup registers (RTC_BKPxR) . . . . .	353
19.6.14	RTC register map . . . . .	354
20	Independent watchdog (IWDG) . . . . .	356
20.1	Introduction . . . . .	356
20.2	IWDG main features . . . . .	356
20.3	IWDG functional description . . . . .	356
20.3.1	Window option . . . . .	356
20.3.2	Register access protection . . . . .	357
20.3.3	Debug mode . . . . .	357
20.4	IWDG registers . . . . .	357
20.4.1	Key register (IWDG_KR) . . . . .	357
20.4.2	Prescaler register (IWDG_PR) . . . . .	358
20.4.3	Reload register (IWDG_RLR) . . . . .	358
20.4.4	Status register (IWDG_SR) . . . . .	359
20.4.5	Window register (IWDG_WINR) . . . . .	360
20.4.6	IWDG register map . . . . .	361
21	Inter-integrated circuit (I ²C) interface . . . . .	362
21.1	Introduction . . . . .	362
21.2	I ²C main features . . . . .	362
21.3	I ²C implementation . . . . .	363
21.4	I ²C functional description . . . . .	363
21.4.1	I ²C block diagram . . . . .	363
21.4.2	I ²C clock requirements . . . . .	364
21.4.3	Mode selection . . . . .	364
21.4.4	I ²C initialization . . . . .	365
21.4.5	Software reset . . . . .	368
21.4.6	Data transfer . . . . .	369
21.4.7	I ²C target mode . . . . .	370
21.4.8	I ²C controller mode . . . . .	375
21.4.9	I ²C_TIMINGR register configuration examples . . . . .	386
21.4.10	SMBus specific features . . . . .	386
21.4.11	SMBus initialization . . . . .	388

21.4.12	SMBus: I2C_TIMEOUTR register configuration examples . . . . .	390
21.4.13	SMBus target mode . . . . .	390
21.4.14	Error conditions. . . . .	395
21.4.15	DMA requests . . . . .	396
21.5	I2C interrupts . . . . .	397
21.6	I2C registers. . . . .	399
21.6.1	Control register 1 (I2C_CR1). . . . .	399
21.6.2	Control register 2 (I2C_CR2). . . . .	402
21.6.3	Own address 1 register (I2C_OAR1). . . . .	405
21.6.4	Own address 2 register (I2C_OAR2). . . . .	406
21.6.5	Timing register (I2C_TIMINGR). . . . .	407
21.6.6	Timeout register (I2C_TIMEOUTR). . . . .	408
21.6.7	Interrupt and status register (I2C_ISR) . . . . .	409
21.6.8	Interrupt clear register (I2C_ICR) . . . . .	411
21.6.9	PEC register (I2C_PECR). . . . .	412
21.6.10	Receive data register (I2C_RXDR). . . . .	413
21.6.11	Transmit data register (I2C_TXDR). . . . .	414
21.6.12	I2C register map . . . . .	415
22	Universal synchronous asynchronous receiver transmitter (USART) . . . . .	417
22.1	USART introduction . . . . .	417
22.2	USART main features. . . . .	417
22.3	USART extended features . . . . .	418
22.4	USART implementation . . . . .	418
22.5	USART functional description . . . . .	419
22.5.1	USART character description . . . . .	420
22.5.2	FIFOs and thresholds . . . . .	421
22.5.3	Transmitter . . . . .	422
22.5.4	Receiver . . . . .	425
22.5.5	Baud rate generation. . . . .	429
22.5.6	Tolerance of the USART receiver to clock deviation . . . . .	430
22.5.7	Auto baud rate detection. . . . .	431
22.5.8	Multiprocessor communication . . . . .	432
22.5.9	Modbus communication . . . . .	433
22.5.10	Parity control. . . . .	434
22.5.11	LIN (local interconnection network) mode . . . . .	434
22.5.12	USART synchronous mode. . . . .	436
22.5.13	Single-wire half-duplex communication . . . . .	439
22.5.14	Receiver timeout. . . . .	440

22.5.15	Smartcard mode . . . . .	440
22.5.16	IrDA SIR ENDEC block . . . . .	443
22.5.17	Continuous communication using DMA . . . . .	445
22.5.18	RS232 hardware flow control and RS485 driver enable . . . . .	447
22.6	USART interrupts . . . . .	449
22.7	USART registers . . . . .	450
22.7.1	Control register 1 (USARTx_CR1) . . . . .	450
22.7.2	Control register 2 (USARTx_CR2) . . . . .	453
22.7.3	Control register 3 (USARTx_CR3) . . . . .	457
22.7.4	Baud rate register (USARTx_BRR) . . . . .	461
22.7.5	Guard Time and prescaler register (USARTx_GTPR) . . . . .	462
22.7.6	Receiver timeout register (USARTx_RTOR) . . . . .	463
22.7.7	Request register (USARTx_RQR) . . . . .	464
22.7.8	Interrupt and status register (USARTx_ISR) . . . . .	465
22.7.9	Interrupt flag clear register (USART_ICR) . . . . .	470
22.7.10	Receive data register (USART_RDR) . . . . .	472
22.7.11	Transmit data register (USART_TDR) . . . . .	473
22.7.12	Prescaler register (USARTx_PRESC) . . . . .	474
22.7.13	USART register map . . . . .	475
23	Universal Asynchronous Receiver Transmitter (LPUART) . . . . .	477
23.1	LPUART introduction . . . . .	477
23.2	LPUART main features . . . . .	477
23.3	LPUART functional description . . . . .	478
23.3.1	LPUART character description . . . . .	480
23.3.2	FIFOs and thresholds . . . . .	481
23.3.3	Transmitter . . . . .	482
23.3.4	Receiver . . . . .	485
23.3.5	Baud rate generation . . . . .	487
23.3.6	Multiprocessor communication . . . . .	488
23.3.7	Parity control . . . . .	490
23.3.8	Single-wire half-duplex communication . . . . .	490
23.3.9	Continuous communication using DMA . . . . .	491
23.3.10	RS232 hardware flow control and RS485 driver enable . . . . .	493
23.3.11	Wakeup from Deepstop mode . . . . .	495
23.4	LPUART interrupts . . . . .	496
23.5	LPUART registers . . . . .	497
23.5.1	Control register 1 (LPUART_CR1) . . . . .	497
23.5.2	Control register 2 (LPUART_CR2) . . . . .	500

23.5.3	Control register 3 (LPUART_CR3) . . . . .	502
23.5.4	Baud rate register (LPUART_BRR) . . . . .	505
23.5.5	Request register (LPUART_RQR) . . . . .	505
23.5.6	Interrupt and status register (LPUART_ISR) . . . . .	506
23.5.7	Interrupt flag clear register (LPUART_ICR) . . . . .	510
23.5.8	Receive data register (LPUART_RDR) . . . . .	510
23.5.9	Transmit data register (LPUART_TDR) . . . . .	511
23.5.10	Prescaler register (LPUART_PRESC) . . . . .	512
23.5.11	LPUART register map . . . . .	513
24	Serial peripheral interface / inter-IC sound (SPI/I2S) . . . . .	515
24.1	Introduction . . . . .	515
24.2	SPI main features . . . . .	515
24.3	I2S main features . . . . .	515
24.4	SPI/I2S implementation . . . . .	516
24.5	SPI functional description . . . . .	516
24.5.1	General description . . . . .	516
24.5.2	Communications between one master and one slave . . . . .	517
24.5.3	Standard multi-slave communication . . . . .	519
24.5.4	Slave select (NSS) pin management . . . . .	520
24.5.5	Communication formats . . . . .	521
24.5.6	Configuration of SPI . . . . .	523
24.5.7	Procedure to enable SPI . . . . .	524
24.5.8	Data transmission and reception procedures . . . . .	524
24.5.9	SPI status flags . . . . .	531
24.5.10	SPI error flags . . . . .	532
24.5.11	NSS pulse mode . . . . .	533
24.5.12	TI mode . . . . .	533
24.5.13	CRC calculation . . . . .	534
24.6	SPI interrupts . . . . .	535
24.7	I2S functional description . . . . .	535
24.7.1	I2S general description . . . . .	535
24.7.2	Supported audio protocols . . . . .	537
24.7.3	Clock generator . . . . .	542
24.7.4	I2S master mode . . . . .	546
24.7.5	I2S slave mode . . . . .	548
24.7.6	I2S error flags . . . . .	549
24.7.7	DMA features . . . . .	549

24.8	I2S interrupts .....	549
24.9	SPI and I ²S registers .....	550
24.9.1	SPI control register 1 (SPIx_CR1) .....	550
24.9.2	SPI control register 2 (SPIx_CR2) .....	553
24.9.3	SPI status register (SPIx_SR) .....	555
24.9.4	SPI data register (SPIx_DR) .....	557
24.9.5	SPI CRC polynomial register (SPIx_CRCPR) .....	558
24.9.6	SPI Rx CRC register (SPIx_RXCRCR) .....	559
24.9.7	SPI Tx CRC register (SPIx_TXCRCR) .....	560
24.9.8	SPIx_I2S configuration register (SPIx_I2SCFGR) .....	561
24.9.9	SPIx_I2S prescaler register (SPIx_I2SPR) .....	563
24.9.10	SPI/I2S register map .....	564
25	Radio IP .....	566
25.1	Overview .....	566
25.1.1	Architecture overview of the MR_BLE IP .....	566
25.1.2	Global scenario for Bluetooth® LE protocol usage .....	567
25.1.3	Miscellaneous features: RF activity monitoring .....	568
25.1.4	Bluetooth® LE standard 5.1 additional support .....	568
25.2	Interfacing with the MR_BLE IP .....	569
25.2.1	Interrupt lines to the CPU .....	569
25.2.2	Interface with the RAM embedded in the SoC .....	570
25.2.3	Interface with the power clock and reset controllers .....	570
25.3	Warning for users .....	571
25.4	Radio resource manager (RRM) .....	571
25.4.1	Semaphore .....	572
25.4.2	UDRA .....	572
25.4.3	Direct register access .....	575
25.4.4	RRM registers .....	575
25.5	Radio registers .....	579
25.5.1	Radio register list .....	579
25.5.2	Radio registers description .....	582
25.5.3	Trimming information .....	592
25.6	Radio FSM .....	592
25.6.1	Radio FSM sequences .....	592
25.6.2	Radio FSM states overview .....	594
25.6.3	Radio FSM interrupts .....	596
25.7	Radio controller .....	596

25.7.1	Slow clock measurement . . . . .	596
25.7.2	Radio FSM interrupt management . . . . .	596
25.7.3	Radio controller registers . . . . .	597
25.8	IP_BLE . . . . .	599
25.8.1	Overview . . . . .	599
25.8.2	Bluetooth LE link layer Sequencer . . . . .	599
25.8.3	IP_BLE interrupts . . . . .	610
25.8.4	IP_BLE RAM tables . . . . .	611
25.8.5	Complementary information . . . . .	637
25.8.6	Angle of arrival (AoA) and angle of departure (AoD) . . . . .	643
25.8.7	AES . . . . .	649
25.8.8	MSB first feature . . . . .	650
25.8.9	IP_BLE registers . . . . .	651
25.9	Wakeup block . . . . .	662
25.9.1	Time features management . . . . .	662
25.9.2	Sleep feature management . . . . .	663
25.9.3	Wakeup management . . . . .	663
25.9.4	CPU wakeup management . . . . .	664
25.9.5	wakeup block registers . . . . .	664
26	Debug support (DBG) . . . . .	668
26.1	SWD debug features . . . . .	668
27	Device electronic signature (DESIG) . . . . .	669
27.1	DESIG registers . . . . .	669
27.1.1	DESIG ADC trimming max diff (DESIG_ADCMAXDIFF) . . . . .	669
27.1.2	DESIG ADC trimming max negative (DESIG_ADCMAXNEG) . . . . .	669
27.1.3	DESIG ADC trimming max positive (DESIG_ADCMAXPOS) . . . . .	670
27.1.4	DESIG ADC trimming mean diff (DESIG_ADCMEANDIFF) . . . . .	670
27.1.5	DESIG ADC trimming mean negative (DESIG_ADCMEANNEG) . . . . .	671
27.1.6	DESIG ADC trimming max positive (DESIG_ADCMEANPOS) . . . . .	671
27.1.7	DESIG ADC trimming min diff (DESIG_ADCMINDIFF) . . . . .	672
27.1.8	DESIG ADC trimming min negative (DESIG_ADCMINNEG) . . . . .	672
27.1.9	DESIG ADC trimming min positive (DESIG_ADCMINPOS) . . . . .	673
27.1.10	DESIG reference temperature register (DESIG_TSREFR) . . . . .	673
27.1.11	DESIG temperature calibration register (DESIG_TSCAL1R) . . . . .	674
27.1.12	DESIG package data register (DESIG_PKGR) . . . . .	674
27.1.13	DESIG 64-bit unique device identifier register 1 (DESIG_UID64R1) . . . . .	675
27.1.14	DESIG 64-bit unique device identifier register 2 (DESIG_UID64R2) . . . . .	675
27.1.15	DESIG register map . . . . .	676

Important security notice .....	678
Revision history .....	679

List of tables

Table 1.	List of abbreviations for registers . . . . .	2
Table 2.	Acronyms . . . . .	3
Table 3.	STM32WB05xZ memory map and peripheral register boundary addresses . . . . .	9
Table 4.	SRAM0 reserved locations . . . . .	10
Table 5.	Address remapping depending on REMAP bit . . . . .	10
Table 6.	Interrupt vectors. . . . .	12
Table 7.	GPIO alternate options AF0, AF1 and AF2 modes . . . . .	17
Table 8.	GPIOs AF3, AF4 and AF6 modes . . . . .	18
Table 9.	I/O analog feature mapping . . . . .	19
Table 10.	I/O additional function mapping . . . . .	19
Table 11.	SMPS BOM information . . . . .	28
Table 12.	PWRC register map . . . . .	52
Table 13.	Flags versus CPU reboot reason . . . . .	55
Table 14.	Wakeup reason flags . . . . .	55
Table 15.	CPU versus MR_BLE clock dependency. . . . .	61
Table 16.	RCC register map and reset values . . . . .	84
Table 17.	Port bit configuration . . . . .	92
Table 18.	GPIO register map and reset values. . . . .	110
Table 19.	SYSCFG register map and reset values . . . . .	128
Table 20.	Flash memory section address . . . . .	131
Table 21.	Flash APB registers . . . . .	132
Table 22.	Command list available for customer . . . . .	133
Table 23.	Flash size information. . . . .	138
Table 24.	System memory protection . . . . .	146
Table 25.	Programmable data width and endian behavior (when PINC=MINC=1 and NDT=4) . . . . .	151
Table 26.	DMA interrupt requests. . . . .	152
Table 27.	DMA register map and reset values . . . . .	160
Table 28.	DMAMUX instantiation . . . . .	164
Table 29.	DMAMUX map . . . . .	165
Table 30.	DMAMUX register map and reset values. . . . .	168
Table 31.	Calibration points. . . . .	174
Table 32.	ADC interrupt requests . . . . .	175
Table 33.	ADC mode summary . . . . .	175
Table 34.	ADC register map and reset values . . . . .	192
Table 35.	Operating modes . . . . .	198
Table 36.	Montgomery parameter input data . . . . .	199
Table 37.	Montgomery parameter output data . . . . .	199
Table 38.	Modular exponentiation input data . . . . .	200
Table 39.	Modular exponentiation output data . . . . .	200
Table 40.	ECC scalar multiplication input data . . . . .	201
Table 41.	ECC scalar multiplication output data . . . . .	201
Table 42.	Point check input data . . . . .	202
Table 43.	Point check output data . . . . .	202
Table 44.	ECDSA sign input data . . . . .	203
Table 45.	ECDSA sign output data . . . . .	203
Table 46.	ECDSA verification input data . . . . .	204
Table 47.	ECDSA verification output data . . . . .	204
Table 48.	RSA CRT exponentiation input . . . . .	205
Table 49.	RSA CRT exponentiation output data . . . . .	205
Table 50.	Modular reduction input data . . . . .	205
Table 51.	Modular reduction output data . . . . .	205
Table 52.	Arithmetic addition input data. . . . .	206
Table 53.	Arithmetic addition output data. . . . .	206

Table 54.	Arithmetic subtraction input data . . . . .	207
Table 55.	Arithmetic subtraction output data . . . . .	207
Table 56.	Comparison input data . . . . .	208
Table 57.	Comparison output data . . . . .	208
Table 58.	Arithmetic multiplication input data . . . . .	208
Table 59.	Arithmetic multiplication output data . . . . .	208
Table 60.	Modular addition input data . . . . .	209
Table 61.	Modular addition output data . . . . .	209
Table 62.	Modular inversion input data . . . . .	209
Table 63.	Modular inversion output data . . . . .	209
Table 64.	Modular subtraction input data . . . . .	210
Table 65.	Modular subtraction output data . . . . .	210
Table 66.	Montgomery multiplication input data . . . . .	210
Table 67.	Montgomery multiplication output data . . . . .	210
Table 68.	Modular exponentiation . . . . .	211
Table 69.	ECC scalar multiplication . . . . .	211
Table 70.	ECDSA signature average computation time . . . . .	211
Table 71.	ECDSA verification average computation times . . . . .	211
Table 72.	Montgomery parameters average computation times . . . . .	212
Table 73.	PKA interrupt requests . . . . .	213
Table 74.	PKA register map . . . . .	219
Table 75.	RNG register map and reset values . . . . .	223
Table 76.	CRC register map and reset values . . . . .	229
Table 77.	Counting direction versus encodersignals . . . . .	256
Table 78.	Output control bits for OCx channels . . . . .	275
Table 79.	TIM2 register map and reset values . . . . .	281
Table 80.	Break protection disarming conditions . . . . .	300
Table 81.	Output control bits for complementary OCx and OCxN channels with break feature . . . . .	314
Table 82.	TIM2 register map and reset values . . . . .	329
Table 83.	RTC register map and reset values . . . . .	354
Table 84.	IWDG register map . . . . .	361
Table 85.	STM32WB05xZ I ²C implementation . . . . .	363
Table 86.	I ²C-SMBUS specification data setup and hold times . . . . .	367
Table 87.	I ²C configurable table . . . . .	370
Table 88.	I ²C-SMBUS specification clock timings . . . . .	378
Table 89.	Examples of timings settings for f _I2CCLK= 16 MHz . . . . .	386
Table 90.	SMBus timeout specifications . . . . .	387
Table 91.	SMBUS with PEC configuration . . . . .	389
Table 92.	Examples of TIMEOUTA settings (max. t _TIMEOUT= 25 ms) . . . . .	390
Table 93.	Example of TIMEOUTB settings . . . . .	390
Table 94.	Examples of TIMEOUTA settings (max. t _IDLE= 50 µs) . . . . .	390
Table 95.	I ²C interrupt requests . . . . .	397
Table 96.	I ²C register map . . . . .	415
Table 97.	USART/LPUART features . . . . .	418
Table 98.	Noise detection from sampled data . . . . .	428
Table 99.	Tolerance of the USART receiver when BRR [3:0] = 0000 (high-density devices) . . . . .	430
Table 100.	Tolerance of the USART receiver when BRR[3:0] is different from 0000 (high-density devices) . . . . .	430
Table 101.	Frame formats . . . . .	434
Table 102.	USART interrupt requests . . . . .	449
Table 103.	USART register map . . . . .	475
Table 104.	Error calculation for programmed baud rates at f _ck=32.768 KHz . . . . .	487
Table 105.	Error calculation for programmed baud rates at f _ck=16 MHz . . . . .	488
Table 106.	Frame formats . . . . .	490
Table 107.	LPUART interrupts . . . . .	496

Table 108.	LPUART register map and reset values . . . . .	513
Table 109.	STM32WB05xZ SPI implementation. . . . .	516
Table 110.	SPI interrupts requests . . . . .	535
Table 111.	Audio frequency precision using I2SCLK = 64 MHz . . . . .	544
Table 112.	Audio frequency precision using I2SCLK = 32 MHz . . . . .	544
Table 113.	Audio frequency precision using I2SCLK = 16 MHz . . . . .	546
Table 114.	I ²S interrupt request . . . . .	549
Table 115.	Interrupt summary . . . . .	569
Table 116.	Command start list details . . . . .	573
Table 117.	UDRA command format in RAM. . . . .	574
Table 118.	RRM registers list . . . . .	575
Table 119.	UDRA_CTRL0 register description . . . . .	576
Table 120.	UDRA_IRQ_ENABLE register description . . . . .	576
Table 121.	UDRA_IRQ_STATUS register description . . . . .	576
Table 122.	UDRA_RADIO_CFG_PTR register description . . . . .	576
Table 123.	SEMA_IRQ_ENABLE register description . . . . .	576
Table 124.	SEMA_IRQ_STATUS register description . . . . .	577
Table 125.	BLE_IRQ_ENABLE register description . . . . .	577
Table 126.	BLE_IRQ_STATUS register description . . . . .	577
Table 127.	VP_CPU_CMD_BUS register description . . . . .	578
Table 128.	VP_CPU_SEMA_BUS register description . . . . .	578
Table 129.	VP_CPU_IRQ_ENABLE register description . . . . .	578
Table 130.	VP_CPU_IRQ_STATUS register description . . . . .	579
Table 131.	Radio register list. . . . .	580
Table 132.	AA0_DIG_USR register description . . . . .	582
Table 133.	AA1_DIG_USR register description . . . . .	582
Table 134.	AA2_DIG_USR register description . . . . .	582
Table 135.	AA3_DIG_USR register description . . . . .	582
Table 136.	DEM_MOD_DIG_USR register description . . . . .	582
Table 137.	RADIO_FSM_USR register description . . . . .	583
Table 138.	PHYCTRL_DIG_USR register description . . . . .	583
Table 139.	AFC1_DIG_ENG register description . . . . .	583
Table 140.	CR0_DIG_ENG register description . . . . .	583
Table 141.	CR0_LR register description . . . . .	584
Table 142.	VIT_CONF_DIG_ENG register description . . . . .	584
Table 143.	LR_PD_THR_DIG_ENG register description . . . . .	584
Table 144.	LR_RSSI_THR_DIG_ENG register description . . . . .	584
Table 145.	LR_AAC_THR_DIG_ENG register description . . . . .	584
Table 146.	SYNTHCAL0_DIG_ENG register description . . . . .	585
Table 147.	DTB5_DIG_ENG register description . . . . .	585
Table 148.	RXADC_ANA_USR register description . . . . .	585
Table 149.	LDO_ANA_ENG register description . . . . .	586
Table 150.	CBIAS0_ANA_ENG register description . . . . .	586
Table 151.	CBIAS1_ANA_ENG register description . . . . .	586
Table 152.	SYNTHCAL0_DIG_OUT register description . . . . .	586
Table 153.	SYNTHCAL1_DIG_OUT register description . . . . .	586
Table 154.	SYNTHCAL2_DIG_OUT register description . . . . .	586
Table 155.	SYNTHCAL3_DIG_OUT register description . . . . .	587
Table 156.	SYNTHCAL4_DIG_OUT register description . . . . .	587
Table 157.	. SYNTHCAL5_DIG_OUT register description . . . . .	587
Table 158.	FSM_STATUS_DIG_OUT register description . . . . .	588
Table 159.	RSSI0_DIG_OUT register description . . . . .	588
Table 160.	RSSI1_DIG_OUT register description . . . . .	588
Table 161.	AGC_DIG_OUT register description . . . . .	588
Table 162.	DEMOD_DIG_OUT register description . . . . .	589

Table 163.	AGC2_ANA_TST register description . . . . .	589
Table 164.	AGC0_DIG_ENG register description . . . . .	589
Table 165.	AGC1_DIG_ENG register description . . . . .	589
Table 166.	AGC10_DIG_ENG register description . . . . .	589
Table 167.	AGC11_DIG_ENG register description . . . . .	589
Table 168.	AGC12_DIG_ENG register description . . . . .	590
Table 169.	AGC13_DIG_ENG register description . . . . .	590
Table 170.	AGC14_DIG_ENG register description . . . . .	590
Table 171.	AGC15_DIG_ENG register description . . . . .	590
Table 172.	AGC16_DIG_ENG register description . . . . .	590
Table 173.	AGC17_DIG_ENG register description . . . . .	590
Table 174.	AGC18_DIG_ENG register description . . . . .	590
Table 175.	AGC19_DIG_ENG register description . . . . .	590
Table 176.	RXADC_HW_TRIM_OUT register description . . . . .	591
Table 177.	CBIAS0_HW_TRIM_OUT register description . . . . .	591
Table 178.	AGC_HW_TRIM_OUT register description . . . . .	591
Table 179.	ANTSW0_DIG_USR register description . . . . .	591
Table 180.	ANTSW1_DIG_USR register description . . . . .	591
Table 181.	ANTSW2_DIG_USR register description . . . . .	591
Table 182.	ANTSW3_DIG_USR register description . . . . .	592
Table 183.	Radio FSM states summary (including exit conditions and timings). . . . .	595
Table 184.	ACTIVE2 to Tx or Rx state duration . . . . .	595
Table 185.	Radio Controller registers list . . . . .	597
Table 186.	RADIO_CONTROL_ID register description . . . . .	597
Table 187.	CLK32COUNT_REG register description . . . . .	597
Table 188.	CLK32PERIOD_REG register description . . . . .	598
Table 189.	CLK32FREQUENCY_REG register description . . . . .	598
Table 190.	RADIO_CONTROL_IRQ_STATUS register description . . . . .	598
Table 191.	RADIO_CONTROL_IRQ_ENABLE register description . . . . .	599
Table 192.	Summary of flags and RAM table pointers behavior versus Tx Skip command . . . . .	609
Table 193.	Summary of flags and RAM table pointers behavior versus Rx Skip command . . . . .	609
Table 194.	GlobalStatMach RAM table . . . . .	613
Table 195.	GlobalStatMach RAM table register list . . . . .	615
Table 196.	GlobalStatMach.WORD0 register description . . . . .	615
Table 197.	GlobalStatMach.WORD1 register description . . . . .	615
Table 198.	GlobalStatMach.WORD2 register description . . . . .	616
Table 199.	GlobalStatMach.WORD3 register description . . . . .	617
Table 200.	GlobalStatMach.WORD4 register description . . . . .	617
Table 201.	GlobalStatMach.WORD5 register description . . . . .	618
Table 202.	GlobalStatMach.WORD6 register description . . . . .	619
Table 203.	StatMach RAM table . . . . .	620
Table 204.	StatMach RAM table register list . . . . .	622
Table 205.	StatMach.WORD0 register description . . . . .	623
Table 206.	StatMach.WORD1 register description . . . . .	625
Table 207.	StatMach.WORD2 register description . . . . .	625
Table 208.	StatMach.WORD3 register description . . . . .	625
Table 209.	StatMach.WORD4 register description . . . . .	626
Table 210.	StatMach.WORD5 register description . . . . .	626
Table 211.	StatMach.WORD6 register description . . . . .	626
Table 212.	StatMach.WORD7 register description . . . . .	626
Table 213.	StatMach.WORD8 register description . . . . .	627
Table 214.	StatMach.WORD9 register description . . . . .	628
Table 215.	StatMach.WORDA register description . . . . .	628
Table 216.	StatMach.WORDB register description . . . . .	629
Table 217.	StatMach.WORDC register description . . . . .	629

Table 218.	StatMach.WORDD register description . . . . .	629
Table 219.	StatMach.WORDE register description . . . . .	629
Table 220.	StatMach.WORDF register description . . . . .	630
Table 221.	StatMach.WORD10 register description . . . . .	630
Table 222.	StatMach.WORD11 register description . . . . .	630
Table 223.	StatMach.WORD12 register description . . . . .	630
Table 224.	StatMach.WORD13 register description . . . . .	630
Table 225.	StatMach.WORD14 register description . . . . .	630
Table 226.	StatMach.WORD15 register description . . . . .	631
Table 227.	StatMach.WORD16 register description . . . . .	631
Table 228.	StatMach.PaPower values . . . . .	632
Table 229.	TxRxPack RAM table . . . . .	633
Table 230.	TxRxPack . . . . .	634
Table 231.	TxRxPack.WORD0 register description. . . . .	634
Table 232.	TxRxPack.WORD1 register description. . . . .	634
Table 233.	TxRxPack.WORD2 register description. . . . .	636
Table 234.	TxRxPack.WORD3 register description. . . . .	636
Table 235.	Truth table to select the correct algorithm . . . . .	639
Table 236.	RAM table bit fields usage versus algorithm number. . . . .	640
Table 237.	Transmission sequence . . . . .	640
Table 238.	Reception sequence. . . . .	641
Table 239.	Delays for Sequencer 2 ^ndINIT step proposal. . . . .	642
Table 240.	Behavior versus CTEDisable and CTEAndSampling bits value . . . . .	645
Table 241.	IP_BLE controller registers list. . . . .	652
Table 242.	INTERRUPT 1REG register description . . . . .	652
Table 243.	INTERRUPT2REG register description . . . . .	654
Table 244.	TIMEOUTDESTREG register description . . . . .	655
Table 245.	TIMEOUTREG register description. . . . .	655
Table 246.	TIMERCAPTUREREG register description . . . . .	655
Table 247.	CMDREG register description . . . . .	655
Table 248.	STATUSREG register description. . . . .	656
Table 249.	INTERRUPT1ENABLEREG register description . . . . .	658
Table 250.	INTERRUPT1LATENCYREG register description. . . . .	659
Table 251.	MANAESKEY0REG register description . . . . .	659
Table 252.	MANAESKEY1REG register description . . . . .	659
Table 253.	MANAESKEY2REG register description . . . . .	659
Table 254.	MANAESKEY3REG register description . . . . .	659
Table 255.	MANAESCLEARTEXT0REG register description. . . . .	659
Table 256.	MANAESCLEARTEXT1REG register description. . . . .	659
Table 257.	MANAESCLEARTEXT2REG register description. . . . .	659
Table 258.	MANAESCLEARTEXT3REG register description. . . . .	660
Table 259.	MANAESCHIPHERTEXT0REG register description. . . . .	660
Table 260.	MANAESCHIPHERTEXT1REG register description. . . . .	660
Table 261.	MANAESCHIPHERTEXT2REG register description. . . . .	660
Table 262.	MANAESCHIPHERTEXT3REG register description. . . . .	660
Table 263.	MANAESCMDREG register description . . . . .	660
Table 264.	MANAESSTATREG register description . . . . .	660
Table 265.	AESLEPRIVPOINTERREG register description. . . . .	660
Table 266.	AESLEPRIVHASHREG register description . . . . .	660
Table 267.	AESLEPRIVPRANDREG register description . . . . .	661
Table 268.	AESLEPRIVCMDREG register description . . . . .	661
Table 269.	AESLEPRIVSTATREG register description . . . . .	661
Table 270.	STATUS2REG register description. . . . .	661
Table 271.	wakeup block register list . . . . .	664
Table 272.	WAKEUP_OFFSET register description . . . . .	665

Table 273. ABSOLUTE_TIME register description . . . . .	665
Table 274. MINIMUM_PERIOD_LENGTH register description. . . . .	665
Table 275. AVERAGE_PERIOD_LENGTH register description . . . . .	665
Table 276. MAXIMUM_PERIOD_LENGTH register description . . . . .	666
Table 277. STATISTIC_RESTART register description . . . . .	666
Table 278. BLUE_WAKEUP_TIME register description. . . . .	666
Table 279. BLUE_SLEEP_REQUEST_MODE register description. . . . .	666
Table 280. CM0_WAKEUP_TIME register description . . . . .	667
Table 281. CM0_SLEEP_REQUEST_MODE register description. . . . .	667
Table 282. WAKEUP_BLE_IRQ_ENABLE register description. . . . .	667
Table 283. WAKEUP_BLE_IRQ_STATUS register description. . . . .	667
Table 284. WAKEUP_CM0_IRQ_ENABLE register description . . . . .	667
Table 285. WAKEUP_CM0_IRQ_STATUS register description . . . . .	667
Table 286. PWRC register map . . . . .	676
Table 287. Document revision history . . . . .	679

List of figures

Figure 1.	STM32WB05xZ system architecture . . . . .	6
Figure 2.	Memory map . . . . .	8
Figure 3.	AHB up/down converter . . . . .	14
Figure 4.	Power supply domain overview . . . . .	21
Figure 5.	Power-on reset/power-down reset waveform . . . . .	21
Figure 6.	Power regulators and SMPS configuration in mode . . . . .	23
Figure 7.	Power regulators and SMPS configuration in Deepstop mode . . . . .	25
Figure 8.	Power regulators and SMPS configuration in Shutdown mode . . . . .	26
Figure 9.	PWRC state machine for operating modes transition . . . . .	27
Figure 10.	Power supply configuration . . . . .	28
Figure 11.	PWRC SMPS state machine overview . . . . .	28
Figure 12.	Reset generation . . . . .	57
Figure 13.	Clock tree generation . . . . .	59
Figure 14.	RCC_LCO / RCC_MCO output clocks . . . . .	62
Figure 15.	Basic structure of a mixed analog/digital five-volt tolerant I/O port bit . . . . .	91
Figure 16.	Basic structure of a digital only five-volt tolerant I/O port bit . . . . .	91
Figure 17.	Input floating/pull-up/pull-down configurations . . . . .	95
Figure 18.	Output configuration . . . . .	95
Figure 19.	Alternate function configuration . . . . .	96
Figure 20.	High impedance-analog configuration . . . . .	97
Figure 21.	DMAMUX block diagram . . . . .	165
Figure 22.	ADC top level diagram . . . . .	171
Figure 23.	ADC sampling time T _swand sampling period T _s. . . . .	173
Figure 24.	Effect of analog source resistance . . . . .	173
Figure 25.	Block diagram . . . . .	195
Figure 26.	CRC calculation unit block diagram . . . . .	224
Figure 27.	Advanced-control timer block diagram . . . . .	231
Figure 28.	Counter timing diagram with prescaler division change from 1 to 2 . . . . .	232
Figure 29.	Counter timing diagram with prescaler division change from 1 to 4 . . . . .	232
Figure 30.	Counter timing diagram, internal clock divided by 1 . . . . .	233
Figure 31.	Counter timing diagram, internal clock divided by 2 . . . . .	233
Figure 32.	Counter timing diagram, internal clock divided by 4 . . . . .	234
Figure 33.	Counter timing diagram, internal clock divided by N . . . . .	234
Figure 34.	Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .	234
Figure 35.	Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .	235
Figure 36.	Counter timing diagram, internal clock divided by 1 . . . . .	236
Figure 37.	Counter timing diagram, internal clock divided by 2 . . . . .	236
Figure 38.	Counter timing diagram, internal clock divided by 4 . . . . .	236
Figure 39.	Counter timing diagram, internal clock divided by N . . . . .	237
Figure 40.	Counter timing diagram, update event when repetition counter is not used . . . . .	237
Figure 41.	Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .	238
Figure 42.	Counter timing diagram, internal clock divided by 2 . . . . .	238
Figure 43.	Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .	239
Figure 44.	Counter timing diagram, internal clock divided by N . . . . .	239
Figure 45.	Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .	239
Figure 46.	Counter timing diagram, update event with ARPE=1 (counter overflow) . . . . .	240
Figure 47.	Update rate examples depending on mode and TIMx_RCR register settings . . . . .	241
Figure 48.	External trigger input block . . . . .	242
Figure 49.	Control circuit in normal mode, internal clock divided by 1 . . . . .	242
Figure 50.	TI2 external clock connection example . . . . .	243
Figure 51.	Control circuit in external clock mode 1 . . . . .	243
Figure 52.	External trigger input block . . . . .	244
Figure 53.	Control circuit in external clock mode 2 . . . . .	244

Figure 54.	Capture/compare channel (example: channel 1 input stage) . . . . .	245
Figure 55.	Capture/compare channel 1 main circuit . . . . .	245
Figure 56.	Output stage of capture/compare channel (channel 4, 3, 2 and 1) . . . . .	245
Figure 57.	PWM input mode timing . . . . .	247
Figure 58.	Output compare mode, toggle on OC1 . . . . .	249
Figure 59.	Edge-aligned PWM waveforms (ARR=8) . . . . .	250
Figure 60.	Center-aligned PWM waveforms (ARR=8) . . . . .	251
Figure 61.	Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .	252
Figure 62.	Combined PWM mode on channel 1 and 3 . . . . .	253
Figure 63.	Clearing TIMx_OCxREF . . . . .	253
Figure 64.	Example of one-pulse mode . . . . .	254
Figure 65.	Retriggerable one-pulse mode . . . . .	255
Figure 66.	Example of counter operation in encoder interface mode . . . . .	257
Figure 67.	Example of encoder interface mode with TI1FP1 polarity inverted . . . . .	257
Figure 68.	Measuring time interval between edges on 3 signals . . . . .	258
Figure 69.	TIM16 and TIM17 block diagram . . . . .	285
Figure 70.	Counter timing diagram with prescaler division change from 1 to 2 . . . . .	286
Figure 71.	Counter timing diagram with prescaler division change from 1 to 4 . . . . .	287
Figure 72.	Counter timing diagram, internal clock divided by 1 . . . . .	288
Figure 73.	Counter timing diagram, internal clock divided by 2 . . . . .	288
Figure 74.	Counter timing diagram, internal clock divided by 4 . . . . .	288
Figure 75.	Counter timing diagram, internal clock divided by N . . . . .	289
Figure 76.	Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .	289
Figure 77.	Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .	290
Figure 78.	Update rate examples depending on mode and TIMx_RCR register settings . . . . .	291
Figure 79.	Control circuit in normal mode, internal clock divided by 1 . . . . .	291
Figure 80.	Capture/compare channel (example: channel 1 input stage) . . . . .	292
Figure 81.	Capture/compare channel 1 main circuit . . . . .	292
Figure 82.	Output stage of capture/compare channel (channel 1) . . . . .	293
Figure 83.	Output compare mode, toggle on OC1 . . . . .	295
Figure 84.	Edge-aligned PWM waveforms (ARR=8) . . . . .	296
Figure 85.	Complementary output with deadtime insertion . . . . .	297
Figure 86.	Deadtime waveforms with delay greater than the negative pulse . . . . .	297
Figure 87.	Deadtime waveforms with delay greater than the positive pulse . . . . .	297
Figure 88.	Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .	299
Figure 89.	Output redirection . . . . .	300
Figure 90.	Example of one-pulse mode . . . . .	301
Figure 91.	IR internal hardware connections with TIM16 and TIM17 . . . . .	332
Figure 92.	RTC block diagram . . . . .	334
Figure 93.	Independent watchdog block diagram . . . . .	357
Figure 94.	I ²C block diagram . . . . .	363
Figure 95.	I ²C bus protocol . . . . .	365
Figure 96.	Setup and hold timings . . . . .	366
Figure 97.	I ²C initialization flowchart . . . . .	368
Figure 98.	Data reception . . . . .	369
Figure 99.	Data transmission . . . . .	369
Figure 100.	Target initialization flowchart . . . . .	372
Figure 101.	Transfer sequence flowchart for I2C target transmitter, NOSTRETCH=0 . . . . .	373
Figure 102.	Transfer sequence flowchart for I2C target transmitter, NOSTRETCH=1 . . . . .	373
Figure 103.	Transfer bus diagram for I2C target transmitter . . . . .	374
Figure 104.	Transfer sequence flowchart for target receiver with NOSTRETCH=0 . . . . .	374
Figure 105.	Transfer sequence flowchart for target receiver with NOSTRETCH=1 . . . . .	375
Figure 106.	Transfer bus diagrams for I2C target receiver . . . . .	375
Figure 107.	Controller clock generation . . . . .	377
Figure 108.	Controller initialization flowchart . . . . .	379

Figure 109.	10-bit address read access with HEAD10R=1. . . . .	379
Figure 110.	Transfer sequence flowchart for I2C controller transmitter for N ≤ 255 bytes . . . . .	380
Figure 111.	Transfer sequence flowchart for I2C controller transmitter for N > 255 bytes . . . . .	381
Figure 112.	Transfer bus diagrams for I2C controller transmitter. . . . .	382
Figure 113.	Transfer sequence flowchart for I ²C controller receiver for N > 255 bytes . . . . .	383
Figure 114.	Transfer sequence flowchart for I ²C controller receiver for N > 255 bytes . . . . .	384
Figure 115.	Transfer bus diagrams for I ²C controller receiver. . . . .	385
Figure 116.	Timeout intervals for t _LOW:SEXT, t _LOW:MEXT. . . . .	388
Figure 117.	Transfer sequence flowchart for SMBus target transmitter N bytes + PEC . . . . .	391
Figure 118.	Transfer bus diagrams for SMBus target transmitter (SBC=1). . . . .	391
Figure 119.	Transfer sequence flowchart for SMBus target receiver N bytes + PEC . . . . .	392
Figure 120.	Bus transfer diagrams for SMBus target receiver (SBC=1) . . . . .	393
Figure 121.	Bus transfer diagrams for SMBus controller transmitter . . . . .	394
Figure 122.	Bus transfer diagrams for SMBus controller receiver . . . . .	395
Figure 123.	I ²C interrupt mapping diagram . . . . .	398
Figure 124.	USART block diagram . . . . .	420
Figure 125.	Word length programming . . . . .	421
Figure 126.	Configurable stop bits . . . . .	422
Figure 127.	TC/TXE behavior when transmitting . . . . .	424
Figure 128.	Start bit detection when oversampling by 16 or 8. . . . .	425
Figure 129.	usart_ker_ck clock divider block diagram . . . . .	427
Figure 130.	Data sampling when oversampling by 16 . . . . .	428
Figure 131.	Data sampling when oversampling by 8 . . . . .	428
Figure 132.	Mute mode using Idle line detection. . . . .	432
Figure 133.	Mute mode using address mark detection . . . . .	433
Figure 134.	Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .	435
Figure 135.	Break detection in LIN mode vs. framing error detection. . . . .	436
Figure 136.	USART example of synchronous master transmission . . . . .	437
Figure 137.	USART data clock timing diagram M=0 . . . . .	437
Figure 138.	USART data clock timing diagram (M bits = 01) . . . . .	438
Figure 139.	RX data setup/hold time. . . . .	438
Figure 140.	ISO 7816-3 asynchronous protocol . . . . .	440
Figure 141.	Parity error detection using 1.5 stop bits. . . . .	442
Figure 142.	IrDA SIR ENDEC - block diagram . . . . .	445
Figure 143.	IrDA data modulation (3/16) - normal mode . . . . .	445
Figure 144.	Transmission using DMA . . . . .	446
Figure 145.	Reception using DMA . . . . .	447
Figure 146.	Hardware flow control between 2 USARTs . . . . .	447
Figure 147.	RS232 RTS flow control. . . . .	448
Figure 148.	RS232 CTS flow control. . . . .	448
Figure 149.	LPUART block diagram . . . . .	479
Figure 150.	LPUART word length programming . . . . .	481
Figure 151.	Configurable stop bits . . . . .	483
Figure 152.	TC/TXE behavior when transmitting . . . . .	484
Figure 153.	lpuart_ker_ck clock divider block diagram . . . . .	486
Figure 154.	Mute mode using idle line detection. . . . .	489
Figure 155.	Mute mode using address mark detection . . . . .	489
Figure 156.	Transmission using DMA . . . . .	491
Figure 157.	Reception using DMA . . . . .	492
Figure 158.	Hardware flow control between 2 LPUARTs . . . . .	493
Figure 159.	RS232 RTS flow control. . . . .	493
Figure 160.	RS232 CTS flow control. . . . .	494
Figure 161.	SPI block diagram. . . . .	517
Figure 162.	Full-duplex single master/single slave application . . . . .	518
Figure 163.	Half-duplex single master/single slave application . . . . .	518

Figure 164.	Simplex single master/single slave application (master in transmit-only/slave in receive-only mode) . . . . .	519
Figure 165.	Master and three independent slaves . . . . .	520
Figure 166.	Hardware/software slave select management. . . . .	521
Figure 167.	Data clock timing diagram . . . . .	522
Figure 168.	Data alignment when data length is not equal to 8-bit or 16-bit . . . . .	523
Figure 169.	Packing data in FIFO for transmission and reception . . . . .	526
Figure 170.	Master full-duplex communication . . . . .	528
Figure 171.	Slave full-duplex communication . . . . .	529
Figure 172.	Master full-duplex communication with CRC. . . . .	530
Figure 173.	Master full-duplex communication in packed mode . . . . .	531
Figure 174.	NSSP pulse generation in Motorola SPI master mode . . . . .	533
Figure 175.	TI mode transfer . . . . .	534
Figure 176.	I ²S block diagram . . . . .	536
Figure 177.	I ²S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0) . . . . .	537
Figure 178.	I ²S Philips standard waveforms (24-bit frame with CPOL = 0). . . . .	537
Figure 179.	Transmitting 0x8EAA33 . . . . .	538
Figure 180.	Receiving 0x8EAA33. . . . .	538
Figure 181.	I ²S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0). . . . .	538
Figure 182.	Example of 16-bit data frame extended to 32-bit channel frame . . . . .	538
Figure 183.	MSB justified 16-bit or 32-bit full-accuracy length with CPOL = 0. . . . .	539
Figure 184.	MSB justified 24-bit frame length with CPOL = 0 . . . . .	539
Figure 185.	MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .	539
Figure 186.	LSB justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . .	540
Figure 187.	LSB justified 24-bit frame length with CPOL = 0 . . . . .	540
Figure 188.	Operations required to transmit 0x3478AE . . . . .	540
Figure 189.	Operations required to receive 0x3478AE . . . . .	541
Figure 190.	LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .	541
Figure 191.	Example of 16-bit data frame extended to 32-bit channel frame (2) . . . . .	541
Figure 192.	PCM standard waveforms (16-bit). . . . .	542
Figure 193.	PCM standard waveforms (16-bit extended to 32-bit packet frame) . . . . .	542
Figure 194.	Audio sampling frequency definition . . . . .	543
Figure 195.	I ²S clock generator architecture . . . . .	543
Figure 196.	MR_BLE architecture overview . . . . .	567
Figure 197.	RRM overview . . . . .	571
Figure 198.	UDRA command list mapping in RAM (example). . . . .	573
Figure 199.	Radio FSM overview . . . . .	594
Figure 200.	Sequencer steps overview . . . . .	602
Figure 201.	Sequencer Initialization steps timings overview. . . . .	605
Figure 202.	Tx sequence . . . . .	606
Figure 203.	Rx sequence . . . . .	607
Figure 204.	RAM table dependency overview . . . . .	612
Figure 205.	Pointer management and packet counter increment algorithm . . . . .	638
Figure 206.	Bluetooth LE link layer channel management overview . . . . .	639
Figure 207.	Timings of an Rx sequence . . . . .	641
Figure 208.	Timings of a Tx sequence . . . . .	642
Figure 209.	MSBFirst feature principle overview. . . . .	651
Figure 210.	IP_BLE wakeup timing contributors . . . . .	664

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