23. Universal Asynchronous Receiver Transmitter (LPUART)

23.1 LPUART introduction

The low-power universal asynchronous receiver transmitter (LPUART) is a UART that allows bidirectional UART communications with a limited power consumption. Only 32.768 kHz LSE clock is required to allow UART communications up to 9600 baud/s. Higher baud rates can be reached when the LPUART is clocked by clock sources different from the LSE clock.

Even when the microcontroller is in Deepstop mode, the LPUART can wait for an incoming UART frame while having an extremely low energy consumption. The LPUART includes all the necessary hardware support to make asynchronous serial communications possible with minimum power consumption.

It supports half-duplex single wire communications and modem operations (CTS/RTS).

It also supports multiprocessor communications.

DMA (direct memory access) can be used for data transmission/reception.

23.2 LPUART main features

• • Full-duplex asynchronous communications
• • NRZ standard format (mark/space)
• • Programmable baud rate
• • From 300 baud/s to 9600 baud/s using a 32.768 kHz clock source
• • Higher baud rates can be achieved by using a higher frequency clock source
• • Two internal FIFOs to transmit and receive data
• • Each FIFO can be enabled/disabled by software and comes with status flags for FIFO states
• • Dual clock domain allowing
  • – UART functionality and wakeup from Deepstop mode
  • – Convenient baud rate programming independent from the PCLK reprogramming
• • Programmable data word length (7 or 8 or 9 bits)
• • Programmable data order with MSB-first or LSB-first shifting
• • Configurable stop bits (1 or 2 stop bits)
• • Single-wire half-duplex communications
• • Continuous communications using DMA
• • Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
• • Separate enable bits for transmitter and receiver
• • Separate signal polarity control for transmission and reception
• • Swappable Tx/Rx pin configuration
• • Hardware flow control for modem and RS-485 transceiver
• • Transfer detection flags:
  • – Receive buffer full
  • – Transmit buffer empty
  • – Busy and end of transmission flags
• • Parity control:
  • – Transmits parity bit
  • – Checks parity of received data byte
• • Four error detection flags:
  • – Overrun error
  • – Noise detection
  • – Frame error
  • – Parity error
• • Interrupt sources with flags
• • Multiprocessor communications

• • The LPUART enters mute mode if the address does not match
• • Wakeup from mute mode (by idle line detection or address mark detection).

23.3 LPUART functional description

Any LPUART bidirectional communication requires a minimum of two pins: Receive Data In (RX) and Transmit Data Out (TX):

• • RX: Receive Data Input. This is the serial data input
• • TX: Transmit Data Output
  When the transmitter is disabled, the output pin returns to its I/O port configuration. When the transmitter is enabled and nothing is to be transmitted, the TX pin is at high level. In single-wire mode, this I/O is used to transmit and receive the data.

Through these pins, serial data are transmitted and received in normal LPUART mode as frames comprising:

• • An Idle Line prior to transmission or reception
• • A start bit
• • A data word (7 or 8 or 9 bits) least significant bit first
• • 1, 2 Stop bits indicating that the frame is complete
• • The LPUART interface uses a baud rate generator
• • A status register (LPUART_ISR)
• • Receive and transmit data registers (LPUART_RDR, LPUART_TDR)
• • A baud rate register (LPUART_BRR).

Refer to Section 23.5: LPUART registers for the definitions of each bit. The following pins are required in RS232 hardware flow control mode:

• • nCTS: Clear To Send blocks the data transmission at the end of the current transfer when high
• • nRTS: Request to send indicates that the LPUART is ready to receive data (when low).

The following pin is required in RS485 hardware control mode:

• • DE: Driver enable activates the transmission mode of the external transceiver.

Note: DE and nRTS share the same pin.

Figure 149. LPUART block diagram

The simplified block diagram given in Figure 149 shows two fully independent clock domains:

• • The lpuart_pclk clock domain
  The lpuart_pclk clock signal feeds the peripheral bus interface. It must be active when access to the LPUART registers are required.
• • The lpuart_ker_ck kernel clock domain
  The lpuart_ker_ck is the LPUART clock source. It is independent of the lpuart_pclk and delivered by the RCC. So, the LPUART registers can be written/read even when the lpuart_ker_ck is stopped.

There is no constraint between lpuart_pclk and lpuart_ker_ck: lpuart_ker_ck can be faster or slower than lpuart_pclk, with no more limitation than the ability for the software to manage the communication fast enough.

23.3.1 LPUART character description

Word length may be selected as being either 7 or 8 or 9 bits by programming the M bits (M0: bit 12 and M1: bit 28) in the LPUART_CR1 register (see Figure 125. Word length programming ).

• • 7-bit character length: M[1:0] =10
• • 8-bit character length: M[1:0] =00
• • 9-bit character length: M[1:0] =01

In default configuration, the signal (TX or RX) is in low state during the start bit. It is in high state during the stop bit.

These values can be inverted, separately for each signal, through polarity configuration control.

An Idle character is interpreted as an entire frame of “1”s. (The number of “1”s includes the number of stop bits).

A break character is interpreted on receiving “0”s for a frame period. At the end of the break frame, the transmitter inserts 2 stop bits.

Transmission and reception are driven by a common baud rate generator, the clock for each is generated when the enable bit is set respectively for the transmitter and receiver.

The details of each block is given below.

Figure 150. LPUART word length programming

23.3.2 FIFOs and thresholds

The LPUART can operate in FIFO mode, with the FIFO buffers having a depth of 16 bytes. The LPUART comes with a transmit FIFO (TXFIFO) and a receive FIFO (RXFIFO). The FIFO mode is enabled by setting the bit 29 FIFOEN in the USARTx_CR1 register.

Being 9 bits the maximum data word length, the TXFIFO is 9-bits wide. However the RXFIFO is by default 12-bits wide. This is due to the fact that the receiver does not only put the data in the FIFO, but also the error flags associated to each character (Parity error, Noise error and Framing error flags).

Note: The received data is stored in the RXFIFO with its flags. But if RDR is read, just the data is read. The status flags are available in the LPUART_ISR register.

It is possible to define the TXFIFO and RXFIFO levels at which the Tx and RX interrupt are triggered. These thresholds are programmed through bit fields RXFTCFG and TXFTCFG in the LPUART_CR3 control register.

In this case:

• • The receive interrupt is generated when the number of received data in the RXFIFO reaches the threshold programmed in the RXFTCFG bit fields.
• • The transmit interrupt is generated when the number of empty locations in the TXFIFO reaches the threshold programmed in the TXFTCFG bit fields.

RXFIFO threshold

The RXFIFO threshold is configured using the RXFTCFG bit fields in the LPUART_CR3 register.

When the number of received data is equal to the programmed RXFTCFG, the flag RXFT in the LPUART_ISR register is set.

Having RXFT flag set means that there are RXFTCFG data received: 1 data in LPUART_RDR and (RXFTCFG - 1) data in the RXFIFO. So, when the RXFTCFG is programmed to «101», the RXFT flag is set when 16 data are received: 15 data in the RXFIFO and 1 data in the LPUART_RDR. Consequently, the 17th received data does not set the overrun flag.

23.3.3

Transmitter

The transmitter can send data words of either 7 or 8 or 9 bits depending on the M bit status. The transmit enable bit (TE) must be set in order to activate the transmitter function. The data in the transmit shift register is output on the TX pin.

Character transmission

During an LPUART transmission, data shifts out least significant bit first (default configuration) on the TX pin. In this mode, the LPUART_TDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 149. LPUART block diagram).

When FIFO mode is enabled, data written to the LPUART_TDR register is queued in the TXFIFO.

Every character is preceded by a start bit which is a logic level low for one bit period. The character is terminated by a configurable number of stop bits.

The following stop bits are supported by LPUART: 1 and 2 stop bits.

Note: The TE bit must be set before writing the data to be transmitted to the LPUART_TDR.

Note: The TE bit should not be reset during transmission of data. Resetting the TE bit during the transmission corrupts the data on the TX pin as the baud rate counters get frozen. The current data being transmitted is lost. An idle frame is sent after the TE bit is enabled.

Configurable stop bits

The number of stop bits to be transmitted with every character can be programmed in control register 2, bits 13,12.

• • 1 stop bit: This is the default value of the number of stop bits.
• • 2 stop bits: This is supported by normal LPUART, single-wire and modem modes. An idle frame transmission includes the stop bits.

A break transmission is 10 low bits (when M[1:0] = 00) or 11 low bits (when M[1:0] = 01) or 9 low bits (when M[1:0] = 10) followed by 2 stop bits. It is not possible to transmit long breaks (break of length greater than 9/10/11 low bits).

Figure 151. Configurable stop bits

Character transmission procedure

1. 1. Program the M bits in LPUART_CR1 to define the word length.
2. 2. Select the desired baud rate using the LPUART_BRR register.
3. 3. Program the number of stop bits in LPUART_CR2.
4. 4. Enable the LPUART by writing the UE bit in the LPUART_CR1 register to 1.
5. 5. Select DMA enable (DMAT) in LPUART_CR3 if multi-buffer communication is to take place. Configure the DMA register as explained in Section 23.3.6: Multiprocessor communication .
6. 6. Set the TE bit in LPUART_CR1 to send an idle frame as first transmission.
7. 7. Write the data to send in the LPUART_TDR register. Repeat this for each data to be transmitted in case of single buffer.
   • – When FIFO mode is disabled, writing a data in the LPUART_TDR clears the TXE flag.
   • – When FIFO mode is enabled, writing a data in the LPUART_TDR adds one data to the TXFIFO and write operations in the LPUART_TDR are made when TXFNF flag is set. This flag remains set until the TXFIFO is full.
8. 8. After writing the last data into the LPUART_TDR register, wait until TC=1. This indicates that the transmission of the last frame is complete. This is required for instance when the LPUART is disabled or enters the Halt mode to avoid corrupting the last transmission.
   • – When FIFO mode is disabled, this indicates that the transmission of the last frame is complete.
   • – When FIFO mode is enabled, this indicates that both TXFIFO and shift register are empty.

Single byte communication

• • When FIFO mode is disabled:

Clearing the TXE bit is always performed by a write to the transmit data register. The TXE flag is set by hardware and it indicates:

• • The data has been moved from the LPUART_TDR register to the shift register and the data transmission has started.
• • The LPUART_TDR register is empty.
• • The next data can be written in the LPUART_TDR register without overwriting the previous data.

This flag generates an interrupt if the TXEIE bit is set.

When a transmission is taking place, a write instruction to the LPUART_TDR register stores the data in the TDR register and is copied in the shift register at the end of the current transmission.

When no transmission is taking place, a write instruction to the LPUART_TDR register places the data in the shift register, the data transmission starts, and the TXE bit is set.

• • When FIFO mode is enabled, the TXFNF (TXFIFO Not Full) flag is set by hardware and it indicates:
  • – The TXFIFO is not full.
  • – The LPUART_TDR register is empty.
  • – The next data can be written in the LPUART_TDR register without overwriting the previous data. When a transmission is taking place, a write operation to the LPUART_TDR register stores the data in the TXFIFO. Data are copied from the TXFIFO into the shift register at the end of the current transmission.

When the TXFIFO is not full, the TXFNF flag stays at 1 even after a write in LPUART_TDR. It is cleared when the TXFIFO is full. This flag generates an interrupt if TXFNEIE bit is set.

Alternatively, interrupts can be generated and data can be written into TXFIFO when the TXFIFO threshold is reached. In this case, the CPU can write a block of data defined by the programmed threshold.

If a frame is transmitted (after the stop bit) and the TXE flag (TXFE in case of FIFO mode) is set, the TC bit goes high. An interrupt is generated if the TCIE bit is set in the LPUART_CR1 register.

After writing the last data in the LPUART_TDR register, it is mandatory to wait for TC=1 before disabling the LPUART or causing the microcontroller to enter the low-power mode (see Figure 152. TC/TXE behavior when transmitting).

Figure 152. TC/TXE behavior when transmitting

Note: When FIFO management is enabled, the TXFNF flag is used for data transmission.

Break characters

Setting the SBKRQ bit transmits a break character. The break frame length depends on the M bits (see Figure 120. Bus transfer diagrams for SMBus target receiver (SBC=1)).

If a '1' is written to the SBKRQ bit, a break character is sent on the TX line after completing the current character transmission. The SBKF bit is set by the write operation and it is reset by hardware when the break character is completed (during the stop bits after the break character). The LPUART inserts a logic 1 signal (STOP) for the duration of 2 bits at the end of the break frame to guarantee the recognition of the start bit of the next frame.

When the SBKRQ bit is set, the break character is sent at the end of the current transmission.

When FIFO mode is enabled, sending the break character has priority on sending data even if the TXFIFO is full.

Idle characters

Setting the TE bit drives the LPUART to send an idle frame before the first data frame.

23.3.4 Receiver

Receiver

The LPUART can receive data words of either 7 or 8 or 9 bits depending on the M bits in the LPUART_CR1 register.

Start bit detection

In LPUART, for START bit detection, a falling edge should be detected first on the Rx line, then a sample is taken in the middle of the start bit to confirm that it is still '0'. If the start sample is at '1', then the noise error flag (NF) is set, then the START bit is discarded and the receiver waits for a new START bit. Otherwise, the receiver continues to sample all incoming bits normally.

Character reception

During an LPUART reception, data shifts in least significant bit first (default configuration) through the RX pin. In this mode, the LPUART_RDR register consists of a buffer (RDR) between the internal bus and the received shift register.

Character reception procedure

1. 1. Program the M bits in LPUART_CR1 to define the word length.
2. 2. Select the desired baud rate using the baud rate register LPUART_BRR.
3. 3. Program the number of stop bits in LPUART_CR2.
4. 4. Enable the LPUART by writing the UE bit in the LPUART_CR1 register to 1.
5. 5. Select DMA enable (DMAR) in LPUART_CR3 if multi-buffer communication is to take place. Configure the DMA register as explained in Section 23.3.6: Multiprocessor communication .
6. 6. Set the RE bit LPUART_CR1. This enables the receiver which begins searching for a start bit.

When a character is received:

• • When FIFO mode is disabled, the RXNE bit is set. It indicates that the content of the shift register is transferred to the RDR. In other words, data has been received and can be read (as well as its associated error flags).
• • When FIFO mode is enabled, the RXFNE bit is set indicating that the RXFIFO is not empty. A read of LPUART_RDR gets the oldest entry in the RXFIFO. When a data is received, it is stored in the RXFIFO, with error bits associated with that data.
• • An interrupt is generated if the RXNEIE (RXFNEIE in case of FIFO mode) bit is set.
• • The error flags can be set if a frame error, noise or an overrun error has been detected during reception.
• • In multi-buffer communication:
  • – When FIFO mode is disabled, the RXNE flag is set after every byte received and is cleared by the DMA read of the Receive Data Register.
  • – When FIFO mode is enabled, the RXFNE flag is set when the RXFIFO is not empty. After every DMA request, a data is retrieved from the RXFIFO. DMA request is triggered by RXFIFO if not empty i.e. there is a data in the RXFIFO to be read.
• • In single buffer mode:
  • – When FIFO mode is disabled, clearing the RXNE bit is performed by a software read to the LPUART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register. The RXNE bit must be cleared before the end of the reception of the next character to avoid an overrun error.
  • – When FIFO mode is enabled, the RXFNE flag is set when the RXFIFO is not empty. After every read of the LPUART_RDR register, a data is retrieved from the RXFIFO. When the RXFIFO is empty, the RXFNE flag is cleared. The RXFNE flag can also be cleared by writing 1 to the RXFRQ bit in the LPUART_RQR register. When the RXFIFO is full, the first entry in the RXFIFO must be read before the end of the reception of the next character to avoid an overrun error. The RXFNE flag generates an interrupt if the RXFNEIE bit is set. Alternatively, interrupts can be generated and data can be read from RXFIFO when the RXFIFO threshold is reached. In this case, the CPU can read a block of data defined by the programmed threshold.

Break character

When a break character is received, the LPUART handles it as a framing error.

Idle character

When an idle frame is detected, the procedure is the same as for a received data character plus an interrupt if the IDLEIE bit is set.

Overrun error

• • FIFO mode disabled: An overrun error occurs when a character is received when RXNE has not been reset. Data can not be transferred from the shift register to the RDR register until the RXNE bit is cleared. The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set when the next data is received or the previous DMA request has not been serviced. When an overrun error occurs:
  • – The ORE bit is set
  • – The RDR content is not lost. The previous data is available when a read to LPUART_RDR is performed
  • – The shift register is overwritten. After that point, any data received during overrun is lost
  • – An interrupt is generated if either the RXNEIE bit is set or EIE bit is set.
• • FIFO mode enabled: An overrun error occurs when the shift register is ready to be transferred when the receive FIFO is full. Data cannot be transferred from the shift register to the LPUART_RDR register until there is one free location in the RXFIFO. The RXFNE flag is set when the RXFIFO is not empty. An overrun error occurs if the RXFIFO is full and the shift register is ready to be transferred. When an overrun error occurs:
  • – The ORE bit is set
  • – The first entry in the RXFIFO is not lost. It is available when a read to LPUART_RDR is performed
  • – The shift register is overwritten. After that point, any data received during overrun is lost
  • – An interrupt is generated if either the RXFNEIE bit is set or EIE bit is set.

The ORE bit is reset by setting the ORECF bit in the ICR register.

Note: The ORE bit, when set, indicates that at least 1 data has been lost.

Note: When the FIFO mode is disabled, there are two possibilities.

• • if RXNE=1, then the last valid data is stored in the receive register RDR and can be read
• • if RXNE=0, then it means that the last valid data has already been read and thus there is nothing to be read in the RDR. This can occur when the last valid data is read in the RDR at the same time as the new (and lost) data is received.

Selecting the clock source

The choice of the clock source is done through the clock control system (see Section 6: Reset and clock controller (RCC) ). The clock source must be chosen before enabling the LPUART (by setting the UE bit).

The choice of the clock source must be done according to two criteria:

• • Possible use of the LPUART in low-power mode
• • Communication speed.

The clock source frequency is lpuart_kern_ck.

When the dual clock domain and the wakeup from Deepstop mode features are supported, the lpuart_kern_ck clock source can be selected through Section 6: Reset and clock controller (RCC) . The lpuart_kern_ck can be divided by a programmable factor in the LPUARTx_PRESC register.

Figure 153. lpuart_ker_ck clock divider block diagram

graph LR
    subgraph ClockDivider [ ]
        direction LR
        A[LPUARTx_PRESC[3:0]] -- lpuart_ker_ck_pres --> B[LPUARTx_BRR register and oversampling]
    end
    lpuart_ker_ck --> A
    style ClockDivider fill:none,stroke:none
    style lpuart_ker_ck fill:none,stroke:none
  

Choosing lpuart_kern_ck as LSE clock source may allow the LPUART to receive data while the MCU is in low-power mode. Depending on the received data and wakeup mode selection, the LPUART wakes up the MCU, when needed, in order to transfer the received data by software reading the LPUART_RDR register or by DMA. For the other clock sources, the system must be active in order to allow LPUART communication.

When the LPUART clock source is configured to be LSE, it is possible to keep enabled this clock during Deepstop mode by setting the UCESM bit in the LPUART_CR3 control register.

The communication speed range (specially the maximum communication speed) is also determined by the clock source.

The receiver samples each incoming baud as close as possible to the middle of the baud-period. Only a single sample is taken of each of the incoming bauds.

Note: There is no noise detection for data.

Framing error

A framing error is detected when the stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise.

When the framing error is detected:

• • The FE bit is set by hardware
• • The invalid data is transferred from the Shift register to the LPUART_RDR register
• • No interrupt is generated in case of single byte communication. However this bit rises at the same time as the RXNE bit which itself generates an interrupt. In case of multi-buffer communication an interrupt is issued if the EIE bit is set in the LPUART_CR3 register.

The FE bit is reset by writing 1 to the FECF in the LPUART_ICR register.

Configurable stop bits during reception

The number of stop bits to be received can be configured through the LPUART_CR2 register control bits: it can be either 1 or 2 in normal mode.

• • 1 stop bit: Sampling for 1 stop bit is done on the 8 ^th , 9 ^th and 10 ^th samples.
• • 2 stop bits: Sampling for the 2 stop bits is done in the middle of the second stop bit. The RXNE and FE flags are set just after this sample, i.e. during the second stop bit. The first stop bit is not checked for framing error.

23.3.5 Baud rate generation

The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as programmed in the LPUART_BRR register.

LPUARTDIV is coded on the LPUART_BRR register.

Note: The baud counters are updated to the new value in the baud registers after a write operation to LPUART_BRR. Hence the baud rate register value should not be changed during communication. It is forbidden to write values less than 0x300 in the LPUART_BRR register. f _CK must be in the range (3 x baud rate) to (4096 x baud rate).

Table 104. Error calculation for programmed baud rates at f _ck =32.768 KHz

Table 105. Error calculation for programmed baudrates at \( f_{ck}=16 \) MHz

23.3.6 Multiprocessor communication

It is possible to perform multiprocessor communication with the LPUART (with several LPUARTs connected in a network). For instance one of the LPUARTs can be the master, its TX output connected to the RX inputs of the other LPUARTs. The others are slaves, their respective TX outputs are logically ANDed together and connected to the RX input of the master.

In multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant LPUART service overhead for all non addressed receivers.

The non addressed devices may be placed in mute mode by means of the muting function. In order to use the mute mode feature, the MME bit must be set in the LPUART_CR1 register.

Note: When FIFO management is enabled and MME is already set, MME bit must not be cleared and then set again quickly (within two UCLK cycles), otherwise mute mode might remain active.

In mute mode:

• • None of the reception status bits can be set
• • All the receive interrupts are inhibited
• • The RWU bit in the LPUART_ISR register is set to 1. RWU can be controlled automatically by hardware or by software, through the MMRQ bit in the LPUART_RQR register, under certain conditions.

The LPUART can enter or exit from mute mode using one of two methods, depending on the WAKE bit in the LPUART_CR1 register:

• • Idle line detection if the WAKE bit is reset
• • Address mark detection if the WAKE bit is set

Idle line detection (WAKE=0)

The LPUART enters mute mode when the MMRQ bit is written to 1 and the RWU is automatically set.

It wakes up when an Idle frame is detected. Then the RWU bit is cleared by hardware but the IDLE bit is not set in the LPUART_ISR register. An example of mute mode behavior using Idle line detection is given in Figure 154. Mute mode using idle line detection.

Figure 154. Mute mode using idle line detection

Note: If the MMRQ is set while the IDLE character has already elapsed, mute mode is not entered (RWU is not set). If the LPUART is activated while the line is IDLE, the idle state is detected after the duration of one IDLE frame (not only after the reception of one character frame).

4-bit/7-bit address mark detection (WAKE=1)

In this mode, bytes are recognized as addresses if their MSB is a '1', otherwise they are considered as data. In an address byte, the address of the targeted receiver is put in the 4 or 7 LSBs. The choice of 7 or 4 bit address detection is done using the ADDM7 bit. This 4-bit/7-bit word is compared by the receiver with its own address which is programmed in the ADD bits in the LPUART_CR2 register.

Note: In 7-bit and 9-bit data modes, address detection is done on 6-bit and 8-bit addresses (ADD[5:0] and ADD[7:0]) respectively.

The LPUART enters mute mode when an address character is received which does not match its programmed address. In this case, the RWU bit is set by hardware. The RXNE flag is not set for this address byte and no interrupt or DMA request is issued when the LPUART enters mute mode.

The LPUART also enters mute mode when the MMRQ bit is written to 1. The RWU bit is also automatically set in this case.

The LPUART exits from mute mode when an address character is received which matches the programmed address. Then the RWU bit is cleared and subsequent bytes are received normally. The RXNE/RXFNE bit is set for the address character since the RWU bit has been cleared.

Note: When FIFO management is enabled, when MMRQ bit is set while the receiver is sampling the last bit of a data; this data may be received before effectively entering in mute mode.

An example of mute mode behavior using address mark detection is given in Figure 155. Mute mode using address mark detection.

Figure 155. Mute mode using address mark detection

In this example, the current address of the receiver is 1 (programmed in the LPUART_CR2 register)

23.3.7 Parity control

Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the LPUART_CR1 register. Depending on the frame length defined by the M bits, the possible LPUART frame formats are as listed in Table 106. Frame formats .

Table 106. Frame formats

1. Legends: SB: start bit, STB: stop bit, PB: parity bit. In the data register the PB is always taking the MSB position (8 ^th or 7 ^th , depending on the M bit value).

2. In the data register, the PB is always taking the MSB position (8 ^th or 7 ^th , depending on the M bit value).

Even parity

The parity bit is calculated to obtain an even number of “1’s inside the frame, which is made of the 6, 7 or 8 LSB bits (depending on M bit values) and the parity bit.

As an example, if data=00110101, and 4 bits are set, then the parity bit is 0 if even parity is selected (PS bit in LPUART_CR1 = 0).

Odd parity

The parity bit is calculated to obtain an odd number of “1’s inside the frame made of the 6, 7 or 8 LSB bits (depending on M bit values) and the parity bit.

As an example, if data=00110101 and 4 bits set, then the parity bit is 1 if odd parity is selected (PS bit in LPUART_CR1 = 1).

Parity checking in reception

If the parity check fails, the PE flag is set in the LPUART_ISR register and an interrupt is generated if PEIE is set in the LPUART_CR1 register. The PE flag is cleared by software writing 1 to the PECF in the LPUART_ICR register.

Parity generation in transmission

If the PCE bit is set in LPUART_CR1 , then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit (even number of “1’s if even parity is selected (PS=0) or an odd number of “1’s if odd parity is selected (PS=1)).

23.3.8 Single-wire half-duplex communication

Single-wire half-duplex mode is selected by setting the HDSEL bit in the LPUART_CR3 register.

In this mode, the following bits must be kept cleared:

• • LINEN and CLKEN bits in the LPUART_CR2 register
• • SCEN and IREN bits in the LPUART_CR3 register

The LPUART can be configured to follow a single-wire half-duplex protocol where the TX and RX lines are internally connected. The selection between half- and full-duplex communication is made with a control bit HDSEL in LPUART_CR3 .

As soon as HDSEL is written to 1:

• • The TX and RX lines are internally connected
• • The RX pin is no longer used
• • The TX pin is always released when no data is transmitted. Thus, it acts as a standard I/O in idle or in reception. It means that the I/O must be configured so that TX is configured as alternate function open-drain with an external pull-up.

Apart from this, the communication protocol is similar to normal LPUART mode. Any conflicts on the line must be managed by software (by the use of a centralized arbiter, for instance). In particular, the transmission is never blocked by hardware and continues as soon as data is written in the data register while the TE bit is set.

Note: In LPUART, in the case of 1-STOP bit configuration, the RXNE flag is set in the middle of the STOP bit.

23.3.9 Continuous communication using DMA

The LPUART is capable of performing continuous communication using the DMA. The DMA requests for Rx buffer and Tx buffer are generated independently.

Note: Refer to Section 22.4: USART implementation to determine if the DMA mode is supported. If DMA is not supported, use the LPUART as explained in Section 23.3.4: Receiver to perform continuous communication. When FIFO is disabled, the TXE/ RXNE flags in the LPUART_ISR register can be cleared.

Transmission using DMA

DMA mode can be enabled for transmission by setting DMAT bit in the LPUART_CR3 register. Data is loaded from an SRAM area configured using the DMA peripheral, see Section 10: DMA controller (DMA), to the LPUART_TDR register whenever the TXE flag (TXFNF flag if FIFO mode is enabled) is set. To map a DMA channel for LPUART transmission, use the following procedure (x denotes the channel number):

1. 1. Write the LPUART_TDR register address in the DMA control register to configure it as the destination of the transfer. The data is moved to this address from memory after each TXE (or TXFNF if FIFO mode is enabled) event.
2. 2. Write the memory address in the DMA control register to configure it as the source of the transfer. The data is loaded into the LPUART_TDR register from this memory area after each TXE (or TXFNF if FIFO mode is enabled) event.
3. 3. Configure the total number of bytes to be transferred to the DMA control register.
4. 4. Configure the channel priority in the DMA register.
5. 5. Configure DMA interrupt generation after half/full transfer as required by the application.
6. 6. Clear the TC flag in the LPUART_ISR register by setting the TCCF bit in the LPUART_ICR register.
7. 7. Activate the channel in the DMA register.

When the number of data transfers programmed in the DMA controller is reached, the DMA controller generates an interrupt on the DMA channel interrupt vector.

In transmission mode, once the DMA has written all the data to be transmitted (the TCIF flag is set in the DMA_ISR register), the TC flag can be monitored to make sure that the LPUART communication is complete. This is required to avoid corrupting the last transmission before disabling the LPUART or entering Deepstop mode. Software must wait until TC=1. The TC flag remains cleared during all data transfers and it is set by hardware at the end of transmission of the last frame.

Figure 156. Transmission using DMA

Note: When FIFO management is enabled, the DMA request is triggered by transmit FIFO not full (i.e. TXFNF = 1).

Reception using DMA

DMA mode can be enabled for reception by setting the DMAR bit in the LPUART_CR3 register. Data is loaded from the LPUART_RDR register to an SRAM area configured using the DMA peripheral, refer to Section 10: DMA controller (DMA) whenever a data byte is received. To map a DMA channel for LPUART reception, use the following procedure:

1. 1. Write the LPUART_RDR register address in the DMA control register to configure it as the source of the transfer. The data is moved from this address to the memory after each RXNE (RXFNE in case FIFO mode is enabled) event.
2. 2. Write the memory address in the DMA control register to configure it as the destination of the transfer. The data is loaded from LPUART_RDR to this memory area after each RXNE (RXFNE in case FIFO mode is enabled) event.
3. 3. Configure the total number of bytes to be transferred to the DMA control register.
4. 4. Configure the channel priority in the DMA control register.
5. 5. Configure interrupt generation after half/full transfer as required by the application.
6. 6. Activate the channel in the DMA control register.

When the number of data transfers programmed in the DMA controller is reached, the DMA controller generates an interrupt on the DMA channel interrupt vector.

Figure 157. Reception using DMA

Note: When FIFO management is enabled, the DMA request is triggered by receive FIFO not empty (i.e. RXFNE = 1).

Error flagging and interrupt generation in multi-buffer communication

In multi-buffer communication, if any error occurs during the transaction the error flag is asserted after the current byte. An interrupt is generated if the interrupt enable flag is set. For framing error, overrun error and noise flag which are asserted with RXNE (RXFNE in case FIFO mode is enabled) in single-byte reception, there is a separate error flag interrupt enable bit (EIE bit in the LPUART_CR3 register), which, if set, enables an interrupt after the current byte if any of these errors occur.

23.3.10 RS232 hardware flow control and RS485 driver enable

It is possible to control the serial data flow between 2 devices by using the nCTS input and the nRTS output. Figure 158. Hardware flow control between 2 LPUARTs shows how to connect 2 devices in this mode:

Figure 158. Hardware flow control between 2 LPUARTs

RS232 RTS and CTS flow control can be enabled independently by writing the RTSE and CTSE bits respectively to 1 (in the LPUART_CR3 register).

RS232 RTS flow control

If the RTS flow control is enabled (RTSE=1), then nRTS is asserted (tied low) as long as the LPUART receiver is ready to receive a new data. When the receive register is full, nRTS is deasserted, indicating that the transmission is expected to stop at the end of the current frame. Figure 159. RS232 RTS flow control shows an example of communication with RTS flow control enabled.

Figure 159. RS232 RTS flow control

Note: When FIFO mode is enabled, nRTS is deasserted only when RXFIFO is full.

RS232 CTS flow control

If the CTS flow control is enabled (CTSE=1), then the transmitter checks the nCTS input before transmitting the next frame. If nCTS is asserted (tied low), then the next data is transmitted (assuming that data is to be transmitted, in other words, if TXE/TXFE=0), otherwise the transmission does not occur. When nCTS is deasserted during a transmission, the current transmission is completed before the transmitter stops.

When CTSE=1, the CTSIF status bit is automatically set by hardware as soon as the CTS input toggles. It indicates when the receiver becomes ready or not ready for communication.

An interrupt is generated if the CTSIE bit in the LPUART_CR3 register is set. Figure 160. RS232 CTS flow control shows an example of communication with CTS flow control enabled.

Figure 160. RS232 CTS flow control

Note: For a correct behavior, nCTS must be asserted at least 3 LPUART clock source periods before the end of the current character. In addition, it should be noted that the CTSCF flag may not be set for pulses shorter than 2 x PCLK periods.

RS485 driver enable

The driver enable feature is enabled by setting bit DEM in the LPUART_CR3 control register. This allows the user to activate the external transceiver control through the DE (DriverEnable) signal. The assertion time is the time between the activation of the DE signal and the beginning of the START bit. It is programmed using the DEAT [4:0] bit fields in the LPUART_CR1 control register. The deassertion time is the time between the end of the last stop bit, in a transmitted message, and the deactivation of the DE signal. It is programmed using the DEDT [4:0] bit fields in the LPUART_CR1 control register. The polarity of the DE signal can be configured using the DEP bit in the LPUART_CR3 control register.

In LPUART, the DEAT and DEDT are expressed in LPUART clock source ( \( f_{CK} \) ) cycles:

1. • • The driver enable assertion time=
     • – \( (1 + (DEAT \times P)) \times f_{CK} \) , if \( P \neq 0 \)
     • – \( (1 + DEAT) \times f_{CK} \) , if \( P = 0 \)
   • • The driver enable deassertion time=
     • – \( (1 + (DEDT \times P)) \times f_{CK} \) , if \( P \neq 0 \)
     • – \( (1 + DEDT) \times f_{CK} \) , if \( P = 0 \)
2. with \( P = BRR[20:11] \)

23.3.11 Wakeup from Deepstop mode

The LPUART is able to wake up the MCU from Deepstop mode when the UESM bit is set and the LPUART clock is set to LSE (refer to Section 6: Reset and clock controller (RCC) ).

When FIFO mode is disabled, the MCU wakeup from Deepstop mode can be done using the standard RXNE interrupt. In this case, the RXNEIE bit must be set before entering Deepstop mode.

When FIFO mode is enabled, the MCU wakeup from Deepstop mode can be done using the:

• • standard RXFIFO not empty interrupt. In this case, the RXFNEIE bit must be set before entering Deepstop mode
• • standard RXFIFO full interrupt. In this case, the RXFFIE bit must be set before entering Deepstop mode
• • standard TXFIFO empty interrupt. In this case, the TXFEIE bit must be set before entering Deepstop mode. This allows sending the data in the TXFIFO during Deepstop mode. When all data are sent (i.e. TXFIFO is empty), the MCU wakes up from Deepstop mode.

In order to avoid overrun/underrun errors and transmit/receive data in Deepstop mode, the MCU wakeup from Deepstop mode can be done also using the:

• • standard TXFIFO threshold interrupt
• • standard RXFIFO threshold interrupt

An application can set the threshold to the maximum RXFIFO size if the wakeup time is less than the time to receive a single byte across the line.

Using the RXFIFO full, TXFIFO empty, and RXFIFO/TXFIFO threshold interrupts to wake up the MCU from Deepstop mode allows doing as many USART transfers as possible during Deepstop mode with the benefit of optimizing consumption.

Alternatively, a specific interrupt may be selected through the WUS bit fields.

In order to be able to wake up the MCU from Deepstop mode, the UESM bit in the USART_CR1 control register must be set before entering Deepstop mode.

When the wakeup event is detected, the WUF flag is set by hardware and a wakeup interrupt is generated if the WUFIE bit is set.

Note: Before entering Deepstop mode, the user must ensure that the USART is not performing a transfer. BUSY flag cannot ensure that Deepstop mode is never entered during a running reception.

Note: The WUF flag is set when a wakeup event is detected, independently of whether the MCU is in Deepstop or in an active mode.

Note: When entering Deepstop mode just after having initialized and enabled the receiver, the REACK bit must be checked to ensure the USART is actually enabled.

Note: When DMA is used for reception, it must be disabled before entering Deepstop mode and re-enabled upon exit from Deepstop mode.

Note: The wakeup from Deepstop mode feature is not available for all modes. For example it doesn't work in SPI mode because the SPI operates in master mode only.

Note: When FIFO is enabled, the wakeup from Deepstop mode on address match is only possible when mute mode is enabled.

Using Mute mode with Deepstop mode

If the USART is put into Mute mode before entering Deepstop mode:

• • Wakeup from Mute mode on idle detection must not be used, because idle detection cannot work in Deepstop mode
• • If the wakeup from Mute mode on address match is used, then the source of wakeup from Deepstop mode must also be the address match. If the RXNE flag is set when entering the Deepstop mode, the interface remains in mute mode upon address match and wakeup from Deepstop.

Note: When FIFO management is enabled, mute mode is used with wakeup from Deepstop mode without any constraints (i.e. the two points mentioned above about mute and Deepstop mode are valid only when FIFO management is disabled).

23.4 LPUART interrupts

These events generate an interrupt if the corresponding enable control bit is set.

Table 107. LPUART interrupts

1. RXFF flag is asserted if the LPUART receives n+1 data (n being the RXFIFO size): n data in the RXFIFO and 1 data in LPUART_RDR. In DEESTOP mode, LPUART_RDR is not clocked. As a result, this register is not written and once n data are received and written in the RXFIFO, the RXFF interrupt is asserted (RXFF flag is not set).

2. The WUF interrupt is active only in low-power mode

23.5 LPUART registers

Refer to Section 1.5: Acronyms for a list of abbreviations used in register descriptions.

23.5.1 Control register 1 (LPUART_CR1)

Address offset: 0x00

Reset value: 0x0000

23.5.2 Control register 2 (LPUART_CR2)

Address offset: 0x04

Reset value: 0x0000

23.5.3 Control register 3 (LPUART_CR3)

Address offset: 0x08

Reset value: 0x0000

23.5.4 Baud rate register (LPUART_BRR)

This register can only be written when the LPUART is disabled (UE=0). It may be automatically updated by hardware in auto baud rate detection mode.

Address offset: 0x0C

Reset value: 0x0000

Note: It is forbidden to write values less than 0x300 in the LPUART_BRR register. Provided that LPUART_BRR must be >= 0x300 and LPUART_BRR is 20 bits, care should be taken when generating high baud rates using high f _ck values. f _ck must be in the range [3 x baud rate ..4096 x baud rate].

23.5.5 Request register (LPUART_RQR)

Address offset: 0x18

Reset value: 0x0000

23.5.6 Interrupt and status register (LPUART_ISR)

Address offset: 0x1C

Reset value: 0x00C0 (in case FIFO disabled)

Reset value: 0x08000C0 (in case FIFO enabled)

23.5.7 Interrupt flag clear register (LPUART_ICR)

Address offset: 0x20

Reset value: 0x0000

23.5.8 Receive data register (LPUART_RDR)

Address offset: 0x24

Reset value: undefined

23.5.9 Transmit data register (LPUART_TDR)

Address offset: 0x28

Reset value: undefined

23.5.10 Prescaler register (LPUART_PRESC)

This register can only be written when the USART is disabled (UE=0).

Address offset: 0x2C

Reset value: 0x0000

23.5.11 LPUART register map

The table below gives the LPUART register map and reset values.

Table 108. LPUART register map and reset values

Refer to Section 2.2.2: Memory map and register boundary addresses.