20. Independent watchdog (IWDG)

20.1 Introduction

The devices feature an embedded watchdog peripheral which offers a combination of high safety level, timing accuracy and flexibility of use. The independent watchdog peripheral serves to detect and resolves malfunctions due to software failure, and to trigger system reset when the counter reaches a given timeout value.

The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI) and thus remains active even if the main clock fails.

The IWDG is best suited to applications which require the watchdog to run as a totally independent process outside the main application, but have lower timing accuracy constraints.

20.2 IWDG main features

• • Free-running down-counter
• • Clocked from an independent RC oscillator (can operate in Deepstop mode)
• • Conditional Reset
  • – Reset (if watchdog activated) when the down-counter value becomes less than 000h
  • – Reset (if watchdog activated) if the down-counter is reloaded outside the window

20.3 IWDG functional description

Figure 93. Independent watchdog block diagram shows the functional blocks of the independent watchdog module.

When the independent watchdog is started by writing the value 0x0000 CCCC in the Key register (IWDG_KR), the counter starts counting down from the reset value of 0xFFF. When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset).

Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, the IWDG_RLR value is reloaded in the counter and the watchdog reset is prevented.

20.3.1 Window option

The IWDG can also work as a window watchdog by setting the appropriate window in the IWDG_WINR register. If the reload operation is performed while the counter is greater than the value stored in the window register (IWDG_WINR), then a reset is provided.

The default value of the IWDG_WINR is 0x0000 0FFF, so if it is not updated, the window option is disabled.

As soon as the window value is changed, a reload operation is performed in order to reset the down-counter to the IWDG_RLR value and ease the cycle number calculation to generate the next reload.

Configuring the IWDG when the window option is enabled

1. 1. Enable the IWDG by writing 0x0000 CCCC in the IWDG_KR register.
2. 2. Enable register access by writing 0x0000 5555 in the IWDG_KR register.
3. 3. Write the IWDG prescaler by programming IWDG_PR from 0 to 7.
4. 4. Write the reload register(IWDG_RLR).
5. 5. Wait for the registers to be updated (IWDG_SR = 0x00000000).
6. 6. Write to the window register IWDG_WINR. This automatically refreshes the counter value IWDG_RLR.

Note: Writing the window value allows the counter value to be refreshed by the RLR when IWDG_SR to set to 0x0000 0000.

Configuring the IWDG when the window option is disabled.

When the window option it is not used, the IWDG can be configured as follows:

1. 1. Enable register access by writing 0x0000 5555 in the IWDG_KR register.
2. 2. Write the IWDG prescaler by programming IWDG_PR from 0 to 7.
3. 3. Write the reload register (IWDG_RLR).
4. 4. Wait for the registers to be updated (IWDG_SR = 0x00000000).
5. 5. Refresh the counter value with IWDG_RLR (IWDG_KR = 0x0000AAAA).

1. Enable the IWDG by writing 0x0000 CCCC in the IWDG_KR.

20.3.2 Register access protection

Write access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers is protected. To modify them, you must first write the code 0x0000 5555 to the IWDG_KR register. A write access to this register with a different value breaks the sequence and register access is protected again. This implies that it is the case of the reload operation (writing 0x0000 AAAA).

A status register is available to indicate that an update of the prescaler or the down-counter reload value or the window value is on-going.

20.3.3 Debug mode

No specific debug mode implemented in the STM32WB05xZ. The timer goes on counting even when the CPU is halted by the debugger.

Figure 93. Independent watchdog block diagram

Note: The watchdog is implemented in the VDD12o power domain that is still functional in Deepstop mode.

20.4 IWDG registers

Refer to Table 2. Acronyms for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

20.4.1 Key register (IWDG_KR)

Address offset: 0x00

Reset value: 0x0000 0000

20.4.2 Prescaler register (IWDG_PR)

Address offset: 0x04

Reset value: 0x0000 0000

20.4.3 Reload register (IWDG_RLR)

Address offset: 0x08

Reset value: 0x0000 0FFF

20.4.4 Status register (IWDG_SR)

Address offset: 0x0C

Reset value: 0x0000 0000

20.4.5 Window register (IWDG_WINR)

Address offset: 0x10

Reset value: 0x0000 0FFF

Note:

If several reload, prescaler, or window values are used by the application, it is mandatory to wait for the RVU bit to be reset before changing the reload value, to wait for the PVU bit to be reset before changing the prescaler value, and to wait for the WVU bit to be reset before changing the window value. However, after updating the prescaler and/or the reload/window value it is not necessary to wait for RVU or PVU or WVU to be reset before continuing code execution except in case of low-power mode entry.

20.4.6 IWDG register map

The following table gives the IWDG register map and reset values.

Table 84. IWDG register map

Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses.