19. Real-time clock (RTC)

19.1 Introduction

The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-of-day clock/calendar with programmable alarm interrupt.

The RTC also includes a periodic programmable wakeup flag with interrupt capability. The RTC provides an automatic wakeup to manage all low-power modes.

Two 32-bit registers contain the seconds, minutes, hours (12- or 24-hour format), day (day of week), date (day of month), month, and year, expressed in binary coded decimal format (BCD). The sub-seconds value is also available in binary format.

Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed automatically. Daylight saving time compensation can also be performed.

Additional 32-bit registers contain the programmable alarm sub-seconds, seconds, minutes, hours, day, and date.

A digital calibration feature is available to compensate for any deviation in crystal oscillator accuracy.

After power-on reset, all RTC registers are protected against possible parasitic write accesses.

As long as the supply voltage remains in the operating range, the RTC never stops, regardless of the device status (run mode, low-power mode or under system reset).

Note: The RTC counter does not freeze when the CPU is halted by a debugger.

19.2 RTC main features

The RTC unit main features are the following (see Figure 92. RTC block diagram ):

• Calendar with sub-seconds, seconds, minutes, hours (12 or 24 format), day (day of week), date (day of month), month, and year.
• Daylight saving compensation programmable by software
• Programmable alarm with interrupt function. The alarm can be triggered by any combination of the calendar fields
• Automatic wakeup unit generating a periodic flag that triggers an automatic wakeup interrupt
• Digital calibration circuit (periodic counter correction): 0.95 ppm accuracy, obtained in a calibration window of several seconds
• Maskable interrupts/events:
- – Alarm A
- – wakeup interrupt.

19.3 RTC functional description

19.3.1 RTC block diagram

Figure 92. RTC block diagram

Figure 92. RTC block diagram. The diagram shows the internal architecture of the RTC. At the top, three clock sources are shown: LSE (32.768 Hz), 16 MHz/512, and LSI. These are multiplexed to form the RTCCLK. RTCCLK is connected to an RTC_CALR block (Smooth calibration) and an RTC_PRER block (Asynchronous 7-bit prescaler, default = 128). The output of the asynchronous prescaler is ck_apre (default 256 Hz). This clock is connected to another RTC_PRER block (Synchronous 15-bit prescaler, default = 256) and to a 1 Hz / 512 Hz divider. The output of the synchronous prescaler is ck_spre (default 1 Hz). This clock is connected to a Calendar block, which contains Shadow registers (RTC_TR, RTC_DR) and a Shadow register (RTC_SSR). The Calendar block is also connected to the RTC_CALIB and RTC_ALARM blocks. The RTC_CALIB block is connected to an Output control block, which outputs RTC_OUT. The RTC_ALARM block is connected to an Alarm A block (RTC_ALRMAR, RTC_ALMASSR). The Alarm A block is connected to an OR gate, which outputs ALRAF.

19.3.2 Clock and prescalers

The RTC clock source (RTCCLK) is selected through the clock controller among the LSE clock, the LSI oscillator clock, and an always 32 kHz equal to HSI_64M/2048 clock if HSESEL='0' else equal to HSE/1024 if HSESEL='1'. For more information on the RTC clock source configuration, refer to Section 6: Reset and clock controller (RCC) .

A programmable prescaler stage generates a 1 Hz clock which is used to update the calendar. To minimize power consumption, the prescaler is split into 2 programmable prescalers (see Figure 92. RTC block diagram ):

• A 7-bit asynchronous prescaler configured through the PREDIV_A bits of the RTC_PRER register
• A 15-bit synchronous prescaler configured through the PREDIV_S bits of the RTC_PRER register.

Note: When both prescalers are used, it is recommended to configure the asynchronous prescaler to a high value to minimize consumption.

The asynchronous prescaler division factor is set to 128, and the synchronous division factor to 256, to obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency of 32.768 kHz.

The minimum division factor is 1 and the maximum division factor is $2^{22}$ . This corresponds to a maximum input frequency of around 4 MHz. $f_{ck\_apre}$ is given by the following formula:

f_{CK\_APRE} = \frac{f_{RTCCLK}}{PREDIV\_A + 1} \quad (2)

The ck_apre clock is used to clock the binary RTC_SSR sub-seconds down-counter. When it reaches 0, RTC_SSR is reloaded with the content of PREDIV_S.

$f_{ck\_spre}$ is given by the following formula:

f_{CK\_SPRE} = \frac{f_{RTCCLK}}{(PREDIV\_S + 1) \times (PREDIV\_A + 1)} \quad (3)

The ck_spre clock can be used either to update the calendar or as timebase for the 16-bit wakeup auto-reload timer. To obtain short timeout periods, the 16-bit wakeup auto-reload timer can also run with the RTCCLK divided by the programmable 4-bit asynchronous prescaler (see Section 19.3.5: Periodic auto-wakeup ).

19.3.3 Real-time clock and calendar

The RTC calendar time and date registers are accessed through shadow registers which are synchronized with PCLK (APB clock). They can also be accessed directly in order to avoid waiting for the synchronization duration.

• RTC_SSR for the sub-seconds
• RTC_TR for the time
• RTC_DR for the date

Every two RTCCLK periods, the current calendar value is copied into the shadow registers, and the RSF bit of the RTC_ISR register is set (see Section 19.6.4: RTC initialization and status register (RTC_ISR) ).

The copy is not performed in Deepstop mode. When exiting these modes, the shadow registers are updated after up to 2 RTCCLK periods.

When the application reads the calendar registers, it accesses the content of the shadow registers. It is possible to make a direct access to the calendar registers by setting the BYPSHAD control bit in the RTC_CR register. By default, this bit is cleared, and the user accesses the shadow registers.

When reading the RTC_SSR, RTC_TR or RTC_DR registers in BYPSHAD=0 mode, the frequency of the APB clock ( $f_{APB}$ ) must be at least 7 times the frequency of the RTC clock ( $f_{RTCCLK}$ ).

The shadow registers are reset by system reset.

19.3.4 Programmable alarm

The RTC unit provides programmable alarm: Alarm A. The programmable alarm function is enabled through the ALRAE bit in the RTC_CR register. The ALRAF is set to 1 if the calendar subseconds, seconds, minutes, hours, date or day match the values programmed in the alarm registers RTC_ALRMASSR and RTC_ALRMAR. Each calendar field can be independently selected through the MSKx bits of the RTC_ALRMAR register, and through the MASKSSx bits of the RTC_ALRMASSR register. The alarm interrupt is enabled through the ALRAIE bit in the RTC_CR register.

Caution: If the seconds field is selected (MSK0 bit reset in RTC_ALRMAR), the synchronous prescaler division factor set in the RTC_PRER register must be at least 3 to ensure correct behavior.

Alarm A (if enabled by bits OSEL[0:1] in RTC_CR register) can be routed to the RTC_ALARM output. RTC_ALARM output polarity can be configured through bit POL in the RTC_CR register.

19.3.5 Periodic auto-wakeup

The periodic wakeup flag is generated by a 16-bit programmable auto-reload down-counter. The wakeup timer range can be extended to 17 bits.

The wakeup function is enabled through the WUTE bit in the RTC_CR register. The wakeup timer clock input can be:

• RTC clock (RTCCLK) divided by 2, 4, 8, or 16.
When RTCCLK is LSE (32.768 kHz), this allows the wakeup interrupt period to be configured from 122 $\mu s$ to 32 s, with a resolution down to 61 $\mu s$ .
• ck_spre (usually 1 Hz internal clock)
When ck_spre frequency is 1 Hz, this allows a wakeup time to be achieved from 1 s to around 36 hours with one-second resolution. This large programmable time range is divided in 2 parts:
- – from 1 s to 18 hours when WUCKSEL [2:1] = 10
- – and from around 18 h to 36 h when WUCKSEL[2:1] = 11. In this last case $2^{16}$ is added to the 16-bit counter current value. When the initialization sequence is complete (see Section 19.3.6: RTC initialization and configuration ), the timer starts counting down. When the wakeup function is enabled, the down-counting remains active in low-power modes. In addition, when it reaches 0, the WUTF flag is set in the RTC_ISR register, and the wakeup counter is automatically reloaded with its reload value (RTC_WUTR register value).

The WUTF flag must then be cleared by software.

When the periodic wakeup interrupt is enabled by setting the WUTIE bit in the RTC_CR2 register, it can exit the device from low-power modes.

The periodic wakeup flag can be routed to the RTC_ALARM output provided it has been enabled through bits OSEL[0:1] of the RTC_CR register. RTC_ALARM output polarity can be configured through the POL bit in the RTC_CR register.

System reset, as well as low-power mode (Deepstop) have no influence on the wakeup timer.

19.3.6 RTC initialization and configuration

RTC register access

The RTC registers are 32-bit registers. The APB interface introduces 2 wait-states in RTC register accesses except on read accesses to calendar shadow registers when BYPSHAD=0.

RTC register write protection

After power-on reset, all the RTC registers are write-protected. Writing to the RTC registers is enabled by writing a key into the write protection register, RTC_WPR.

The following steps are required to unlock the write protection on all the RTC registers except for RTC_ISR[13:8], and RTC_BKPxR.

1. Write '0xCA' into the RTC_WPR register.
2. Write '0x53' into the RTC_WPR register.

Writing a wrong key reactivates the write protection.

The protection mechanism is not affected by system reset.

Calendar initialization and configuration

To program the initial time and date calendar values, including the time format and the prescaler configuration, the following sequence is required:

1. Set INIT bit to 1 in the RTC_ISR register to enter initialization mode. In this mode, the calendar counter is stopped and its value can be updated.
2. Poll INITF bit in the RTC_ISR register. The initialization phase mode is entered when INITF is set to 1. It takes around 2 RTCCLK clock cycles (due to clock synchronization).
3. To generate a 1 Hz clock for the calendar counter, program both the prescaler factors in RTC_PRER register.
4. Load the initial time and date values in the shadow registers (RTC_TR and RTC_DR), and configure the time format (12 or 24 hours) through the FMT bit in the RTC_CR register.
5. Exit the initialization mode by clearing the INIT bit. The actual calendar counter value is then automatically loaded and the counting restarts after 4 RTCCLK clock cycles.

When the initialization sequence is complete, the calendar starts counting.

Note: 1. After a system reset, the application can read the INITS flag in the RTC_ISR register to check if the calendar has been initialized or not. If this flag equals 0, the calendar has not been initialized since the year field is set at its power-on reset default value (0x00).

Note: 2. To read the calendar after initialization, the software must first check that the RSF flag is set in the RTC_ISR register.

Daylight saving time

The daylight saving time management is performed through bits SUB1H, ADD1H, and BKP of the RTC_CR register.

Using SUB1H or ADD1H, the software can subtract or add one hour to the calendar in one single operation without going through the initialization procedure.

In addition, the software can use the BKP bit to memorize this operation.

Programming the alarm

A similar procedure must be followed to program or update the programmable alarms.

1. Clear ALRAE in RTC_CR to disable Alarm A
2. Program the Alarm A registers (RTC_ALRMASSR/RTC_ALRMAR)
3. Set ALRAE in the RTC_CR register to enable alarm A again.

Note: Each change of the RTC_CR register is taken into account after around 2 RTCCLK clock cycles due to clock synchronization.

Programming the wakeup timer

The following sequence is required to configure or change the wakeup timer auto-reload value (WUT[15:0] in RTC_WUTR):

1. Clear WUTE in RTC_CR to disable the wakeup timer.
2. Poll WUTWF bit until it is set in RTC_ISR register to make sure the access to wake up auto-reload counter and to WUCKSEL[2:0] bits is allowed. It takes around 2 RTCCLK clock cycles (due to clock synchronization).
3. Program the wakeup auto-reload value WUT[15:0], and the wakeup clock selection (WUCKSEL[2:0] bits in RTC_CR). Set WUTE in RTC_CR to enable the timer again. The wakeup timer restarts down-counting.

19.3.7 Reading the calendar

• When BYPSHAD control bit is cleared in the RTC_CR register:

To read the RTC calendar registers (RTC_SSR, RTC_TR and RTC_DR) properly, the APB1 clock frequency (fPCLK) must be equal to or greater than seven times the fRTCCLKRTC clock frequency. This ensures a secure behavior of the synchronization mechanism.

If the APB0 clock frequency is less than seven times the RTC clock frequency, the software must read the calendar time and date registers twice. If the second read of the RTC_TR gives the same result as the first read, this ensures that the data is correct. Otherwise a third read access must be done. In any case the APB0 clock frequency must never be lower than the RTC clock frequency.

The RSF bit is set in the RTC_ISR register each time the calendar registers are copied into the RTC_TR and RTC_DR shadow registers. The copy is performed every two RTCCLK cycles. To ensure consistency between the 3 values, reading either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read. In case the software makes read accesses to the calendar in a time interval smaller than 2 RTCCLK periods: RSF must be cleared by software after the first calendar read, and then the software must wait until RSF is set before reading again the RTC_SSR, RTC_TR and RTC_DR registers.

After waking up from low-power mode (Deepstop), RSF must be cleared by software. The software must then wait until it is set again before reading the RTC_SSR, RTC_TR and RTC_DR registers.

The RSF bit must be cleared after wakeup and not before entering low-power mode.

After a system reset, the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers. Indeed, a system reset resets the shadow registers to their default values.

After an initialization, (refer to Calendar initialization and configuration in Section 19.3.6: RTC initialization and configuration ), the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers.

After synchronization (refer to Section 19.3.9: RTC synchronization ), the software must await until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers.

• When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow registers)

Reading the calendar registers gives the values from the calendar counters directly, thus eliminating the need to wait for the RSF bit to be set. This is especially useful after exiting from low-power mode (Deepstop), since the shadow registers are not updated during these modes.

When the BYPSHAD bit is set to 1, the results of the different registers might not be coherent with each other if an RTCCLK edge occurs between two read accesses to the registers. Additionally, the value of one of the registers may be incorrect if an RTCCLK edge occurs during the read operation. The software must read all the registers twice, and then compare the results to confirm that the data is coherent and correct. Alternatively, the software can just compare the two results of the least-significant calendar register.

Note: While BYPSHAD=1, instructions which read the calendar registers require one extra APB cycle to complete.

19.3.8 Resetting the RTC

The calendar shadow registers (RTC_SSR, RTC_TR and RTC_DR) and the RTC status register (RTC_ISR) are reset to their default values by all available system reset sources.

On the contrary, the following registers are reset to their default values by a power-on reset and are not affected by a system reset: the RTC current calendar registers, the RTC control register (RTC_CR), the prescaler register (RTC_PRER), the RTC calibration register (RTC_CALR), the RTC shift register (RTC_SHIFTR), the RTC backup registers (RTC_BKPxR), the wakeup timer register (RTC_WUTR), the Alarm A registers (RTC_ALRMASSR/RTC_ALRMAR).

In addition, the RTC keeps on running under system reset if the reset source is different from the power-on reset one. When a power-on reset occurs, the RTC is stopped and all the RTC registers are set to their reset values.

19.3.9 RTC synchronization

The RTC can be synchronized to a remote clock with a high degree of precision. After reading the sub-second field (RTC_SSR or RTC_TSSSR), a calculation can be made of the precise offset between the times being maintained by the remote clock and the RTC. The RTC can then be adjusted to eliminate this offset by “shifting” its clock by a fraction of a second using RTC_SHIFTR.

RTC_SSR contains the value of the synchronous prescaler counter. This allows to calculate the exact time being maintained by the RTC down to a resolution of $1 / ( PREDIV\_S + 1 )$ seconds. As a consequence, the resolution can be improved by increasing the synchronous prescaler value (PREDIV_S[14:0]). The maximum resolution allowed (30.52 µs with a 32768 Hz clock) is obtained with PREDIV_S set to 0x7FFF.

However, increasing PREDIV_S means that PREDIV_A must be decreased in order to maintain the synchronous prescaler's output at 1 Hz. In this way, the frequency of the asynchronous prescaler's output increases, which may increase the RTC dynamic consumption.

The RTC can be finely adjusted using the RTC shift control register (RTC_SHIFTR). Writing to RTC_SHIFTR can shift (either delay or advance) the clock by up to a second with a resolution of $1 / (PREDIV\_S + 1)$ seconds. The shift operation consists of adding the SUBFS[14:0] value to the synchronous prescaler counter SS[15:0]: this delays the clock. If at the same time the ADD1S bit is set, this results in adding one second and at the same time subtracting a fraction of a second, so this advances the clock.

Caution: Before initiating a shift operation, the user must check that SS[15] = 0 in order to ensure that no overflow occurs.

As soon as a shift operation is initiated by a write to the RTC_SHIFTR register, the SHPF flag is set by hardware to indicate that a shift operation is pending. This bit is cleared by hardware as soon as the shift operation has completed.

19.3.10 RTC smooth digital calibration

The RTC frequency can be digitally calibrated with a resolution of about 0.954 ppm with a range from -487.1 ppm to +488.5 ppm. The correction of the frequency is performed using a series of small adjustments (adding and/or subtracting individual RTCCLK pulses). These adjustments are fairly well distributed so that the RTC is well calibrated even when observed over short durations of time.

The smooth digital calibration is performed during a cycle of about 220 RTCCLK pulses, or 32 seconds when the input frequency is 32768 Hz. This cycle is maintained by a 20-bit counter, calib_cnt[19:0], clocked by RTCCLK.

The smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles to be masked during the 32-second cycle:

• Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during the 32-second cycle
• Setting CALM[1] to 1 causes two additional cycles to be masked
• Setting SMC[2] to 1 causes four additional cycles to be masked
• and so on up to SMC[8] set to 1 which causes 256 clocks to be masked

Note: CALM[8:0] (RTC_CALR) specifies the number of RTCCLK pulses to be masked during the 32-second cycle. Setting the bit CALM[0] to '1' causes exactly one pulse to be masked during the 32-second cycle at the moment when cal_cnt[19:0] is 0x80000; CALM[1]=1 causes two other cycles to be masked (when cal_cnt is 0x40000 and 0xC0000); SMC[2]=1 causes four other cycles to be masked (cal_cnt = 0x20000/0x60000/0xA0000/ 0xE0000); and so on up to SMC[8]=1 which causes 256 clocks to be masked (cal_cnt = 0xXX800).

While CALM allows the RTC frequency to be reduced by up to 487.1 ppm ( $$ 511/(220+511) $$ ) with fine resolution, the bit CALP can be used to increase the frequency by 488.5 ppm ( $$ 512/(220+512) $$ ). Setting CALP to '1' effectively inserts an extra RTCCLK pulse every 211 RTCCLK cycles, which means that 512 clocks are added during every 32-second cycle.

Using CALM together with CALP, an offset ranging from -511 to +512 RTCCLK cycles can be added during the 32-second cycle, which translates to a calibration range of -487.1 ppm to +488.5 ppm with a resolution of about 0.954 ppm.

The formula to calculate the effective calibrated frequency (FCAL) given the input frequency (FRTCCLK) is as follows:

F_{CAL} = F_{RTCCLK} \times [ 1 + (CALP \times 512 - CALM) / (2^{20} + CALM - CALP \times 512) ]

Calibration when PREDIV_A < 3

The CALP bit can not be set to 1 when the asynchronous prescaler value (PREDIV_A bits in RTC_PRER register) is less than 3. If CALP was already set to 1 and PREDIV_A bits are set to a value less than 3, CALP is ignored and the calibration operates as if CALP was equal to 0.

To perform a calibration with PREDIV_A less than 3, the synchronous prescaler value (PREDIV_S) should be reduced so that each second is accelerated by 8 RTCCLK clock cycles, which is equivalent to adding 256 clock cycles every 32 seconds. As a result, between 255 and 256 clock pulses (corresponding to a calibration range from 243.3 to 244.1 ppm) can effectively be added during each 32-second cycle using only the CALM bits.

With a nominal RTCCLK frequency of 32768 Hz, when PREDIV_A equals 1 (division factor of 2), PREDIV_S should be set to 16379 rather than 16383 (4 less). The only other interesting case is when PREDIV_A equals 0, PREDIV_S should be set to 32759 rather than 32767 (8 less).

If PREDIV_S is reduced in this way, the formula giving the effective frequency of the calibrated input clock is as follows:

F_{CAL} = F_{RTCCLK} \times [ 1 + (256 - CALM) / (2^{20} + CALM - 256) ]

In this case, CALM[7:0] equals 0x100 (the midpoint of the CALM range) is the correct setting if RTCCLK is exactly 32768.00 Hz.

Note: The case PREDIV_A=2 (asynchronous prescaler divides by 3) seems unlikely to be useful unless the nominal input frequency is a multiple of 3. For example, if RTCCLK is nominally 98304 Hz (32768 Hz x 3), setting PREDIV_S to 32759 rather than 32767 (8 less) would render the above formula valid.

Verifying the RTC calibration

RTC precision is ensured by measuring the precise frequency of RTCCLK and calculating the correct CALM value and CALP values. An optional 1 Hz output is provided to allow applications to measure and verify the RTC precision.

Measuring the precise frequency of the RTC over a limited interval can result in a measurement error of up to 2 RTCCLK clock cycles over the measurement period, depending on how the digital calibration cycle is aligned with the measurement period.

However, this measurement error can be eliminated if the measurement period is the same length as the calibration cycle period. In this case, the only error observed is the error due to the resolution of the digital calibration.

By default, the calibration cycle period is 32 seconds.

Using this mode and measuring the accuracy of the 1 Hz output over exactly 32 seconds guarantees that the measure is within 0.477 ppm (0.5 RTCCLK cycles over 32 seconds, due to the limitation of the calibration resolution).

CALW16 bitof the RTC_CALR register can be set to 1 to force a 16- second calibration cycle period.

In this case, the RTC precision can be measured during 16 seconds with a maximum error of 0.954 ppm (0.5 RTCCLK cycles over 16 seconds). However, since the calibration resolution is reduced, the long term RTC precision is also reduced to 0.954 ppm: CALM[0] bit is stuck at 0 when CALW16 is set to 1.

CALW8 bit of the RTC_CALR register can be set to 1 to force a 8-second calibration cycle period.

In this case, the RTC precision can be measured during 8 seconds with a maximum error of 1.907 ppm (0.5 RTCCLK cycles over 8 s). The long term RTC precision is also reduced to 1.907 ppm: CALM[1:0] bits are stuck at 00 when CALW8 is set to 1.

Re-calibration on-the-fly

The calibration register (RTC_CALR) can be updated on-the-fly while RTC_ISR/INITF=0, by using the following process:

Poll the RTC_ISR/RECALPF (re-calibration pending flag).
If it is set to 0, write a new value to RTC_CALR, if necessary. RECALPF is then automatically set to 1.
Within three ck_apre cycles after the write operation to RTC_CALR, the new calibration settings take effect.

Note: RECALPF then becomes '0' automatically. Note that RECALPF can stay at '1' for as long as 4 ck_apre cycles plus 2 system clock cycles after writing to RTC_CALR. During initialization mode (RTC_ISR/INIT=1), RECALPF can stay at '1' indefinitely.

19.3.11 Calibration clock output

When the COE bit is set to 1 in the RTC_CR register, a reference clock is provided on the RTC_CALIB device output.

Note: This RTC_CALIB information is output on the RTC_OUT I/O signal if the I/O is programmed with the associated AFx mode, see Section 5: Power controller (PWRC).

If the COSEL bit in the RTC_CR register is reset and PREDIV_A = 0x7F, the RTC_CALIB frequency is $f_{RTCCLK}/64$ . This corresponds to a calibration output at 512 Hz for an $f_{RTCCLK}$ frequency at 32.768 kHz. The RTC_CALIB duty cycle is irregular: there is a light jitter on falling edges. It is therefore recommended to use rising edges.

When COSEL is set and "PREDIV_S+1" is a non-zero multiple of 256 (i.e.: PREDIV_S[7:0] = 0xFF), the RTC_CALIB frequency is $f_{RTCCLK}/(256 * (PREDIV_A+1))$ . This corresponds to a calibration output at 1 Hz for prescaler default values (PREDIV_A = 0x7F, PREDIV_S = 0xFF), with an $f_{RTCCLK}$ frequency at 32.768 kHz.

19.3.12 Alarm output

The OSEL[1:0] control bits in the RTC_CR register are used to activate the alarm alternate function output RTC_ALARM, and to select the function which is output. These functions reflect the contents of the corresponding flags in the RTC_ISR register. The polarity of the output is determined by the POL control bit in RTC_CR so that the opposite of the selected flag bit is output when POL is set to 1.

Note: The RTC_ALARM is output on the RTC_OUT I/O signal if the I/O is programmed with the associated AFx mode, see Section 5: Power controller (PWRC) .

Note: Once the RTC_ALARM output is enabled, it has priority over RTC_CALIB (COE bit must be kept cleared, which means the RTC_OUT I/O outputs the RTC_ALARM).

19.4 RTC low-power modes

The RTC is able to run in Deepstop mode and generate a wakeup event to wake the device through RTC alarm and RTC wakeup root cause.

Note: The software has to clear the RTC_ISR.WUTF flag in the RTC after a wakeup, otherwise it prevents from going into low-power again. The PWRC block only mirrors the RTC wakeup signal in its own wakeup flag register.

19.5 RTC interrupts

All RTC interrupts are combined and connected to the NVIC controller. Refer to Section 2.3.2: Interrupts .

To enable the RTC alarm interrupt, the following sequence is required:

1. Configure and enable the RTC_ALARM IRQ channel in the NVIC
2. Configure the RTC to generate RTC alarms (alarm A)

To enable the wakeup timer interrupt, the following sequence is required:

1. Configure and enable the RTC IRQ channel in the NVIC
2. Configure the RTC to detect the WUT event

19.6 RTC registers

Refer to Section 1.5: Acronyms of the reference manual for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by words (32-bit).

19.6.1 RTC time register (RTC_TR)

The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Section 19.3.7: Reading the calendar .

This register is write protected. The write access procedure is described in Section 19.3.6: RTC initialization and configuration .

Address offset: 0x00

Power-on reset value: 0x0000 0000

System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	PM	HT[1:0]		HU[3:0]
									rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	MNT[2:0]			MNU[3:0]				Res.	ST[2:0]		SU[3:0]
	rw	rw	rw	rw	rw	rw	rw		rw	rw	rw	rw	rw	rw	rw

Bits 31-23	Reserved, must be kept at reset value.
Bit 22	PM: AM/PM notation 0: AM or 24-hour format 1: PM
Bits 21:20	HT[1:0]: Hour tens in BCD format
Bit 16:16	HU[3:0]: Hour units in BCD format
Bit 15	Reserved, must be kept at reset value.
Bits 14:12	MNT[2:0]: Minute tens in BCD format
Bit 11:8	MNU[3:0]: Minute units in BCD format
Bit 7	Reserved, must be kept at reset value.
Bits 6:4	ST[2:0]: Second tens in BCD format
Bit 3:0	SU[3:0]: Second units in BCD format

19.6.2 RTC date register (RTC_DR)

The RTC_DR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Section 19.3.7: Reading the calendar .

This register is write protected. The write access procedure is described in Section 19.3.6: RTC initialization and configuration .

Address offset: 0x04

Power-on reset value: 0x0000 2101

System reset: 0x0000 2101 when BYPSHAD = 0. Not affected when BYPSHAD = 1.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	YT[3:0]				YU[3:0]
								rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDU[2:0]			MT	MU[3:0]				Res.	Res.	DT[1:0]		DU[3:0]
rw	rw	rw	rw	rw	rw	rw	rw			rw	rw	rw	rw	rw	rw

Bits 31:24	Reserved, must be kept at reset value.
Bits 23:20	YT[3:0] : Year tens in BCD format.
Bits 19:16	YU[3:0] : Year units in BCD format.
Bits 15:13	WDU[2:0] : Week day units. 000: forbidden 001: Monday ... 111: Sunday
Bit 12	MT : Month tens in BCD format.
Bits 11:8	MU : Month units in BCD format.
Bits 7:6	Reserved, must be kept at reset value.
Bits 5:4	DT[1:0] : Date tens in BCD format.
Bits 3:0	DU[3:0] : Date units in BCD format.

19.6.3 RTC control register (RTC_CR)

Address offset: 0x08

Power-on reset value: 0x0000 0000

System reset: not affected

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	COE	OSEL[1:0]		POL	COSEL	BKP	SUB1H	ADD1H
								rw	rw	rw	rw	rw	rw	w	w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	WUTIE	Res.	ALRAIE	Res.	WUTE	Res.	ALRAE	Res.	FMT	BYPS HAD	Res.	Res.	WUCKSEL[2:0]
	rw		rw		rw		rw		rw	rw			rw	rw	rw

Bits 31:25	Reserved, must be kept at reset value.
Bit 23	COE: Calibration output enable. This bit enables the RTC_CALIB output. 0: Calibration output disabled 1: Calibration output enabled
Bits 22:21	OSEL[1:0]: Output selection. These bits are used to select the flag to be routed to RTC_OUT output. 00: Output disabled 01: Alarm A output enabled 10: 11: Wakeup output enabled
Bit 20	POL: Output polarity. This bit is used to configure the polarity of RTC_ALARM output. 0: The pin is high when ALRAF/WUTF is asserted (depending on OSEL[1:0]) 1: The pin is low when ALRAF/WUTF is asserted (depending on OSEL[1:0])
Bit 19	COSEL : Calibration output selection. When COE=1, this bit selects which signal is output on RTC_CALIB. 0: Calibration output is 512 Hz 1: Calibration output is 1 Hz These frequencies are valid for $R_{TCLK}$ at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255). Refer to Section 19.3.11: Calibration clock output .
Bit 18	BKP: Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not.
Bit 17	SUB1H: Subtract 1 hour (winter time change). When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0. 0: No effect 1: Subtracts 1 hour to the current time. This can be used for winter time change.
Bit 16	ADD1H: Add 1 hour (summer time change). When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0. 0: No effect 1: Adds 1 hour to the current time. This can be used for summer time change.

Bit 15	Reserved, must be kept at reset value.
Bit 14	WUTIE: Wakeup timer interruptenable. 0: Wakeup timer interrupt disabled 1: Wakeup timer interrupt enabled
Bit 13	Reserved, must be kept at reset value.
Bit 12	ALRAIE: Alarm A interrupt enable 0: Alarm A interrupt disabled 1: Alarm A interrupt enabled
Bit 11	Reserved, must be kept at reset value.
Bit 10	WUTE: Wakeup timer enable. 0: Wakeup timer disabled 1: Wakeup timer enabled
Bit 9	Reserved, must be kept at reset value.
Bit 8	ALRAE: Alarm A enable. 0: Alarm A disabled 1: Alarm A enabled
Bit 7	Reserved, must be kept at reset value.
Bit 6	FMT: Hour format. 0: 24 hour/day format 1: AM/PM hour format
Bit 5	BYPSHAD: Bypass the shadow registers. 0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken by the shadow registers, which are updated once every two RTCCLK cycles 1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly by the calendar counters Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to '1'.
Bit 4	Reserved, must be kept at reset value.
Bit 3	Reserved, must be kept at reset value.
Bits 2:0	WUCKSEL[2:0]: wakeup clock selection 000: RTC/16 clock is selected. 001: RTC/8 clock is selected 010: RTC/4 clock is selected 011: RTC/2 clock is selected 10x: ck_spre (usually 1 Hz) clock is selected 11x: ck_spre (usually 1 Hz) clock is selected and 2 ¹⁶is added to the WUT counter value (see note below)

Note:
1. 1. Bits 7, 6 and 4 of this register can be written in initialization mode only ( RTC_ISR/INITF = 1).
2. 2. WUT = wakeup unit counter value. WUT = (0x0000 to 0xFFFF) + 0x10000 added when WUCKSEL[2:1] = 11.
3. 3. Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1.
4. 4. It is recommended not to change the hour during the calendar hour increment as it could mask the incrementation of the calendar hour.
5. 5. ADD1H and SUB1H changes are effective in the next second.
6. 6. This register is write protected. The write access procedure is described in RTC registers.

19.6.4 RTC initialization and status register (RTC_ISR)

This register is write protected (except for RTC_ISR[-17:8] bits).

The write access procedure is described in Section 19.6.3: RTC control register (RTC_CR) .

Address offset: 0x0C

Reset value: 0x0000 0007

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	RECAL PF
															r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	WUTF	Res.	ALRAF	INIT	INITF	RSF	INITS	SHPF	WUTWF		ALRAW F
					rc_w0		rc_w0	nw	r	rc_w0	r	rc_w0	r		r

Bits 31:18	Reserved, must be kept at reset value.
Bit 16	RECALPF : Recalibration pending Flag. The RECALPF status flag is automatically set to '1' when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to '0'.
Bit 15	Reserved, must be kept at reset value.
Bit 14	Reserved, must be kept at reset value.
Bit 13	Reserved, must be kept at reset value.
Bit 12	Reserved, must be kept at reset value.
Bit 11	Reserved, must be kept at reset value.
Bit 10	WUTF : wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. This flag is cleared by software by writing 0. This flag must be cleared by software at least 1.5 $R_{TCCLK}$ periods before WUTF is set to 1 again.
Bit 9	Reserved, must be kept at reset value.
Bit 8	ALRAF : Alarm A flag. This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the alarm A register (RTC_ALRMAR). This flag is cleared by software by writing 0.
Bit 7	INIT : Initialization mode. 0: Free running mode 1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.
Bit 6	INITF : Initialization flag. When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated. 0: Calendar registers update is not allowed 1: Calendar registers update is allowed
Bit 5	RSF : Register synchronization flag. This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow register mode (BYPSHAD=1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode. 0: Calendar shadow registers not yet synchronized

	1: Calendar shadow registers synchronized
Bit 4	INITS: Initialization status flag. This bit is set by hardware when the calendar year field is different from 0 (power-on reset state). 0: Calendar has not been initialized 1: Calendar has been initialized
Bit 3	SHPF: Shift operation pending. 0: No shift operation is pending 1: A shift operation is pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect.
Bit 2	WUTWF: wakeup timer write flag. This bit is set by hardware when the wakeup timer values can be changed, after the WUTE bit has been set to 0 in RTC_CR. 0: wakeup timer configuration update not allowed 1: wakeup timer configuration update allowed
Bit 0	ALRAWF: Alarm A write flag. This bit is set by hardware when alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode. 0: Alarm A update not allowed 1: Alarm A update allowed

Note: The bits ALRAF, WUTF are cleared 2 APB clock cycles after programming them to 0.

19.6.5 RTC prescaler register (RTC_PRER)

This register must be written in initialization mode only. The initialization must be performed in two separate write accesses.

This register is write protected. The write access procedure is described in RTC registers.

Address offset: 0x10

Power-on reset value: 0x007F 00FF

System reset: not affected

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	PREDIV_A[6:0]
									rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	PREDIV_S[14:0]
	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:23	Reserved, must be kept at reset value.
Bits 22:16	PREDIV_A[6:0] : Asynchronous prescaler factor. This is the asynchronous division factor: $ck\_apre\ frequency = RTCCLK\ frequency / (PREDIV\_A + 1)$
Bit 15	Reserved, must be kept at reset value.
Bits 14:0	PREDIV_S[14:0] : Synchronous prescaler factor. This is the synchronous division factor: $ck\_spre\ frequency = ck\_apre\ frequency / (PREDIV\_S + 1)$

19.6.6 RTC wakeup timer register (RTC_WUTR)

This register can be written only when WUTWF is set to 1 in RTC_ISR.

This register is write protected. The write access procedure is described in Section 19.6: RTC registers .

Address offset: 0x14

Power-on reset value: 0x0000 FFFF

System reset: not affected

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WUT[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:16

Reserved, must be kept at reset value.

Bits 15:0

WUT[15:0] : wakeup auto-reload value bits.
When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register.
When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer.
The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] = 011 (RTCCLK/2) is forbidden.

19.6.7 RTC alarm A register (RTC_ALRMAR)

This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode.

This register is write protected. The write access procedure is described in Section 19.6: RTC registers .

Address offset: 0x1C

Power-on reset value: 0x0000 0000

System reset: not affected

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MSK4	WDSEL	DT[1:0]		DU[3:0]			MSK3		PM	HT[1:0]		HU[3:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSK2	MNT[2:0]			MNU[3:0]			MSK1		ST[2:0]		SU[3:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31	MSK4: Alarm A date mask 0: Alarm A set if the date/day match 1: Date/day do not care in Alarm A comparison
Bit 30	WDSEL: Week day selection 0: DU[3:0] represents the date units 1: DU[3:0] represents the week day. Do not care DT[1:0]
Bits 29:28	DT[1:0]: Date tens in BCD format
Bits 27:24	DU[3:0]: Date units or day in BCD format
Bit 23	MSK3: Alarm A hours mask 0: Alarm A set if the hours match 1: Hours do not care in Alarm A comparison
Bit 22	PM: AM/PM notation 0: AM or 24-hour format 1: PM
Bits 21:20	HT[1:0]: Hour tens in BCD format
Bits 19:16	HU[3:0]: Hour units in BCD format
Bit 15	MSK2: Alarm A minutes mask 0: Alarm A set if the minutes match 1: Minutes do not care in Alarm A comparison
Bits 14:12	MNT[2:0]: Minute tens in BCD format
Bits 11:8	MNU[3:0]: Minute units in BCD format
Bit 7	MSK1: Alarm A seconds mask 0: Alarm A set if the seconds match 1: Seconds do not care in Alarm A comparison
Bits 6:4	ST[2:0]: Second tens in BCD format
Bits 3:0	SU[3:0]: Second units in BCD format

19.6.8 RTC write protection register (RTC_WPR)

Address offset: 0x24

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	KEY[7:0]
								w	w	w	w	w	w	w	w

Bits 31:8	Reserved, must be kept at reset value.
Bits 7:0	KEY[7:0]: Write protection key. This byte is written by software. Reading this byte always returns 0x00. Refer to Section 19.6: RTC registers for a description of how to unlock RTC register write protection.

19.6.9 RTC sub-second register (RTC_SSR)

Address offset: 0x28

Power-on reset value: 0x0000 0000

System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS[15:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:16	Reserved, must be kept at reset value.
Bits 15:0	SS: Sub-second value. SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: $\text{Second fraction} = ( \text{PREDIV\_S} - \text{SS} ) / ( \text{PREDIV\_S} + 1 )$ Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR.

19.6.10 RTC shift control register (RTC_SHIFTR)

This register is write protected. The write access procedure is described in Section 19.6.8: RTC write protection register (RTC_WPR) .

Address offset: 0x2C

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD1S	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	SUBFS[14:0]
	w	w	w	w	w	w	w	w	w	w	w	w	w	w	w

Bit 31

ADD1S: Add one second.

0: No effect

1: Add one second to the clock/calendar

This bit is "write" only and is always "read" as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR).

This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation.

Bits 31:15

Reserved, must be kept at reset value.

Bits 14:0

SUBFS: Subtract a fraction of a second.

These bits are "write" only and are always "read" as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR).

The value which is written to SUBFS is added to the synchronous prescaler's counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by:

Delay (seconds) = SUBFS / ( PREDIV_S + 1 )

A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by :

Advance (seconds) = ( 1 - ( SUBFS / ( PREDIV_S + 1 ) ) ) .

Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be sure that the shadow registers have been updated with the shifted time.

Refer to Section 19.3.9: RTC synchronization .

19.6.11 RTC calibration register (RTC_CALR)

This register is "write" protected. The write access procedure is described in Section 19.6.8: RTC write protection register (RTC_WPR) .

Address offset: 0x3C

Power-on reset value: 0x0000 0000

System reset: not affected

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALP	CALW8	CALW 16	Res.	Res.	Res.	Res.	CALM[8:0]
rw	rw	rw					rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31:16	Reserved, must be kept at reset value.
Bit 15	CALP: Increase frequency of RTC by 488.5 ppm 0: No RTCCLK pulses are added 1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency increased by 488.5 ppm). This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: $$ (512 * CALP) - CALM $$ . Refer to Section 19.3.10: RTC smooth digital calibration .
Bit 14	CALW8: Use an 8-second calibration cycle period. When CALW8 is set to '1', the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at "00" when CALW8 ='1'. Refer to Section 19.3.10: RTC smooth digital calibration .
Bit 13	CALW16: Use a 16-second calibration cycle period. When CALW16 is set to '1', the 16-second calibration cycle period is selected. This bit must not be set to '1' if CALW8=1. Note: CALM[0] is stuck at '0' when CALW16 ='1'. Refer to Section 19.3.10: RTC smooth digital calibration .
Bits 12:9	Reserved, must be kept at reset value.
Bits 8:0	CALM[8:0]: Calibration minus The frequency of the calendar is reduced by masking CALM out of $2^{20}$ RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See Section 19.3.10: RTC smooth digital calibration .

19.6.12 RTC alarm A sub second register (RTC_ALRMASSR)

This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.

This register is "write" protected. The write access procedure is described in Section 19.6.8: RTC write protection register (RTC_WPR) .

Address offset: 0x44

Power-on reset value: 0x0000 0000

System reset: not affected

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	MASKSS[3:0]				Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
				rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	SS[14:0]
	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	w	rw	rw

Bit 31:28	Reserved, must be kept at reset value.
Bit 27:24	MASKSS[3:0]: Mask the most-significant bits starting at this bit 0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is incremented (assuming that the rest of the fields match). 1: SS[14:1] are "do not care" in Alarm A comparison. Only SS[0] is compared. 2: SS[14:2] are "do not care" in Alarm A comparison. Only SS[1:0] are compared. 3: SS[14:3] are "do not care" in Alarm A comparison. Only SS[2:0] are compared. ... 12: SS[14:12] are "do not care" in Alarm A comparison. SS[11:0] are compared. 13: SS[14:13] are "do not care" in Alarm A comparison. SS[12:0] are compared. 14: SS[14] is "do not care" in Alarm A comparison. SS[13:0] are compared. 15: All 15 SS bits are compared and must match to activate alarm The overflow bits of the synchronous counter (bits 15) are never compared. This bit can be different from 0 only after a shift operation.
Bit 23:15	Reserved, must be kept at reset value.
Bit 14:0	SS[14:0]: Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if Alarm A is to be activated. Only bits 0 up to MASKSS-1 are compared.

19.6.13 RTC backup registers (RTC_BKPxR)

Address offset: 0x50 to 0x54

Power-on reset value: 0x0000 0000

System reset: not affected

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP[31:16]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	w	rw	rw

Bits 31:0

BKP[31:0]

The application can write or read data to and from these registers.

They are powered-on by VDD12 _oso they are retained during Deepstop mode.

The application can write or read data to and from these registers. This register is reset on PORESET _nonly.

19.6.14 RTC register map

Table 83. RTC register map and reset values

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x00	RTC_TR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	PM	HT [1:0]		HU[3:0]			Res.	MNT[2:0]		MNU[3:0]			Res.	ST[2:0]		SU[3:0]
0x00	Reset value										0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x04	RTC_DR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	YT[3:0]			YU[3:0]			WDU[2:0]		MT	MU[3:0]			Res.	Res.	DT [1:0]		DU[3:0]
0x04	Reset value									0	0	0	0	0	0	0	0	0	1	0	0	0	0	1	0	0	0	0	0	0	0	1
0x08	RTC_CR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	COE	OSEL [1:0]		POL	COSEL	BKP	SUB1H	ADD1H	Res.	WUTIE	Res	ALRAIE	Res	WUTE	Res	ALRAIE	Res.	FMT	BYPSHAD	Res.	Res.	WUCKSE L[2:0]
0x08	Reset value									0	0	0	0		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x0C	RTC_ISR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	RECALPF	Res.	Res	Res.	Res.	Res.	WUTF	Res.	ALRAF	INIT	INITF	RSF	INITS	SHPF	WUT WF	ALRAWF
0x0C	Reset value																0						0		0	0	0	0	0	0	1	1
0x10	RTC_PRER	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	PREDIV_A[6:0]						Res.	PREDIV_S[14:0]
0x10	Reset value										1	1	1	1	1	1	1	0	0	0	0	0	0	0	0	1	1	1	1	1	1	1
0x14	RTC_WUTR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	WUT[15:0]
0x14	Reset value																	1	1	1	1	1	1	1	1	1	1	1	1	1	1
0x1C	RTC_ALRMAR	MSK4	WDSEL	DT [1:0]		DU[3:0]			MSK3	PM	HT [1:0]		HU[3:0]			MSK2	MNT[2:0]		MNU[3:0]			MSK1	ST[2:0]		SU[3:0]
0x1C	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x24	RTC_WPR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	KEY[7:0]
0x24	Reset value																									0	0	0	0	0	0	0
0x28	RTC_SSR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	SS[15:0]

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Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x28	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x2C	RTC_SHIFTR	ADD1S	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	SUBFS[14:0]
0x2C	Reset value	0																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x3C	RTC_CALR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CALP	CALW8	CALW16	Res.	Res.	Res.	Res.	CALM[8:0]
0x3C	Reset value																	0	0	0					0	0	0	0	0	0	0	0	0
0x40	Reserved
0x44	RTC_ALRMASSR	Res.	Res.	Res.	Res.	MASKSS[3:0]				Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	SS[14:0]
0x44	Reset value					0	0	0	0										0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x50	RTC_BKP0R	BKP[31:0]
0x50	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x54	RTC_BKP1R	BKP[31:0]
0x54	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses.

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