17. General purpose timer (TIM16/17)

17.1 TIM16/17 introduction

The TIM16/17 timers consist of a 16-bit auto-reload counter driven by a programmable prescaler.

They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with deadtime insertion).

Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers. TIM16/17 timers are completely independent, and do not share any resources.

17.2 TIM16 and TIM17 main features

TIM16 and TIM17 timers include:

• 16-bit auto-reload upcounter
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535
• One channel for:
- – Input capture
- – Output compare
- – PWM generation (edge-aligned mode)
- – One-pulse mode output
• Complementary outputs with programmable deadtime
• Repetition counter to update the timer registers only after a given number of cycles of the counter
• Break input to put the timer output signals in the reset state or a known state
• Interrupt/DMA generation on the following events:
- – Update: counter overflow
- – Trigger event (counter start, stop, initialization or count by internal/external trigger), only interrupt
- – Input capture
- – Output compare
- – Break input

Figure 69. TIM16 and TIM17 block diagram

Block diagram of TIM16 and TIM17 showing internal components and signal flow.

The block diagram illustrates the internal architecture of the TIM16 and TIM17 general-purpose timers. Key components and signal paths include:

Clocking: The internal clock (CK_INT) is connected to an AND gate. One input of the AND gate comes from the TIMx_BKIN pin (after a BRK block), and the other comes from the CK_PSC output of the PSC Prescaler. The output of this AND gate drives the CNT counter and the Capture/Compare 1 register.
Input Path (TIMx_CH1): The TIMx_CH1 pin is connected to an Input filter & Edge detector. Its output (TI1) is divided by a Prescaler (IC1) to produce IC1PS, which then feeds into the Capture/Compare 1 register.
Counter and Registers:
- The CNT counter is a 16-bit upcounter with 'Stop, clear or up/down' control inputs.
- The Auto-reload register (ARR) provides the reload value for the counter. It has a 'U' (update) input.
- The Capture/Compare 1 register (CCR1) is used for input capture or output compare. It has a 'U' (update) input and an OC1REF output.
- The Repetition counter (RCR) receives inputs from the ARR and CNT registers and has 'U' (update) inputs.
- DTG registers are connected to the OC1REF signal.
Output Path: The output control block takes inputs from the DTG registers, the OC1REF signal, and the TIMx_BKIN pin (via a BI input). It generates the TMx_CH1 and TMx_CH1N output signals.
Break Input (TIMx_BKIN): This pin is connected to a BRK block, which also receives a 'Clock failure event from clock controller'. The output of the BRK block is connected to the AND gate for clocking and to the output control block.

Notes:

Reg : Preload registers transferred to active registers on U event according to control bit
U : interrupt & DMA output

Block diagram of TIM16 and TIM17 showing internal components and signal flow.

17.3 TIM16/17 functional description

17.3.1 Time-base unit

The main block of the programmable advanced-control timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler.

The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

• Counter register(TIMx_CNT)
• Prescaler register(TIMx_PSC)
• Auto-reload register(TIMx_ARR)
• Repetition counter register(TIMx_RCR)

The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The contents of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The update event is sent when the counter reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration.

The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in the TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling).

Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register.

Prescaler description

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on-the-fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event.

Figure 70. Counter timing diagram with prescaler division change from 1 to 2 and Figure 71. Counter timing diagram with prescaler division change from 1 to 4 give some examples of the counter behavior when the prescaler ratio is changed on-the-fly.

Figure 70. Counter timing diagram with prescaler division change from 1 to 2

Timing diagram showing the relationship between CK_PSC, CEN, Timer clock (CK_CNT), Counter register, Update event (UEV), Prescaler control register, Write to TIMx_PSC, Prescaler buffer, and Prescaler counter. It illustrates a change in prescaler division from 1 to 2.

The diagram shows the following signals and states over time:

CK_PSC: A periodic square wave representing the prescaler input clock.
CEN: Counter Enable bit. It is initially low and goes high at the start of the diagram.
Timer clock = CK_CNT: The output of the prescaler. It is initially a high-frequency square wave (division 1). After the prescaler control register is updated, its frequency halves (division 2).
Counter register: Shows hexadecimal values: F7, F8, F9, FA, FB, FC, 00, 01, 02, 03. It overflows from FC to 00.
Update event (UEV): A pulse generated when the counter overflows (from FC to 00).
Prescaler control register: Initially contains '0'. It is updated to '1' at the time of the UEV. An arrow points to the write operation.
Write a new value in TIMx_PSC: The action of writing '1' to the prescaler control register.
Prescaler buffer: A shadow register that initially contains '0'. It updates to '1' at the next UEV after the control register is changed.
Prescaler counter: A 16-bit counter that counts the CK_PSC clock. It is initially '0'. After the prescaler buffer updates to '1', it counts every two CK_PSC cycles, shown as a sequence of 0, 1, 0, 1, 0, 1, 0, 1.

Timing diagram showing the relationship between CK_PSC, CEN, Timer clock (CK_CNT), Counter register, Update event (UEV), Prescaler control register, Write to TIMx_PSC, Prescaler buffer, and Prescaler counter. It illustrates a change in prescaler division from 1 to 2.

Figure 71. Counter timing diagram with prescaler division change from 1 to 4

The timing diagram shows the following signals and states over time:

CK_PSC : A periodic clock signal.
CEN : Counter Enable signal, which goes high to enable the counter.
Timer clock = CK_CNT : The clock for the counter, derived from CK_PSC. Its frequency changes when the prescaler division changes.
Counter register : Shows values F7, F8, F9, FA, FB, FC, followed by a reset to 00, and then 01.
Update event (UEV) : A pulse generated when the counter overflows (from FC to 00).
Prescaler control register : Initially set to 0. At the time of the first UEV, it is changed to 3.
Write a new value in TIMx_PSC : An arrow indicates the write operation to the control register.
Prescaler buffer : Initially 0. It is updated to 3 at the second UEV.
Prescaler counter : Counts from 0 to 3. The sequence 0, 1, 2, 3 is shown twice, corresponding to the two periods where the division is 4.

Timing diagram showing the relationship between CK_PSC, CEN, Timer clock (CK_CNT), Counter register, Update event (UEV), Prescaler control register, Write to TIMx_PSC, Prescaler buffer, and Prescaler counter. The diagram illustrates a change in prescaler division from 1 to 4.

17.3.2 Counter modes

Up-counting mode

In up-counting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

If the repetition counter is used, the update event (UEV) is generated after up-counting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR). Otherwise, the update event is generated at each counter overflow.

Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event.

The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in the TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit):

• The repetition counter is reloaded with the content of the TIMx_RCR register
• The auto-reload shadow register is updated with the preload value (TIMx_ARR)
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register).

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36.

Figure 72. Counter timing diagram, internal clock divided by 1

Timing diagram for internal clock divided by 1. It shows the relationship between CK_PSC, CNT_EN, Timer clock (CK_CNT), Counter register values, Counter overflow, Update event (UEV), and Update interrupt flag (UIF).

This timing diagram illustrates the operation of a counter with an internal clock divided by 1. The signals shown are:

CK_PSC : Prescaler clock signal, shown as a continuous square wave.
CNT_EN : Counter enable signal, which goes high to start counting.
Timer clock = CK_CNT : The clock signal for the counter, which is the CK_PSC signal divided by 1.
Counter register : Shows the sequence of values: 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07.
Counter overflow : A pulse generated when the counter reaches its maximum value (36) and rolls over to 00.
Update event (UEV) : A pulse generated at the time of counter overflow.
Update interrupt flag (UIF) : A flag that is set when an update event occurs.

Timing diagram for internal clock divided by 1. It shows the relationship between CK_PSC, CNT_EN, Timer clock (CK_CNT), Counter register values, Counter overflow, Update event (UEV), and Update interrupt flag (UIF).

Figure 73. Counter timing diagram, internal clock divided by 2

Timing diagram for internal clock divided by 2. It shows the relationship between CK_PSC, CNT_EN, Timer clock (CK_CNT), Counter register values, Counter overflow, Update event (UEV), and Update interrupt flag (UIF).

This timing diagram illustrates the operation of a counter with an internal clock divided by 2. The signals shown are:

CK_PSC : Prescaler clock signal, shown as a continuous square wave.
CNT_EN : Counter enable signal, which goes high to start counting.
Timer clock = CK_CNT : The clock signal for the counter, which is the CK_PSC signal divided by 2.
Counter register : Shows the sequence of values: 0034, 0035, 0036, 0000, 0001, 0002, 0003.
Counter overflow : A pulse generated when the counter reaches its maximum value (0036) and rolls over to 0000.
Update event (UEV) : A pulse generated at the time of counter overflow.
Update interrupt flag (UIF) : A flag that is set when an update event occurs.

Timing diagram for internal clock divided by 2. It shows the relationship between CK_PSC, CNT_EN, Timer clock (CK_CNT), Counter register values, Counter overflow, Update event (UEV), and Update interrupt flag (UIF).

Figure 74. Counter timing diagram, internal clock divided by 4

Timing diagram for internal clock divided by 4. It shows the relationship between CK_PSC, CNT_EN, Timer clock (CK_CNT), Counter register values, Counter overflow, Update event (UEV), and Update interrupt flag (UIF).

This timing diagram illustrates the operation of a counter with an internal clock divided by 4. The signals shown are:

CK_PSC : Prescaler clock signal, shown as a continuous square wave.
CNT_EN : Counter enable signal, which goes high to start counting.
Timer clock = CK_CNT : The clock signal for the counter, which is the CK_PSC signal divided by 4.
Counter register : Shows the sequence of values: 0035, 0036, 0000, 0001.
Counter overflow : A pulse generated when the counter reaches its maximum value (0036) and rolls over to 0000.
Update event (UEV) : A pulse generated at the time of counter overflow.
Update interrupt flag (UIF) : A flag that is set when an update event occurs.

Timing diagram for internal clock divided by 4. It shows the relationship between CK_PSC, CNT_EN, Timer clock (CK_CNT), Counter register values, Counter overflow, Update event (UEV), and Update interrupt flag (UIF).

Figure 75. Counter timing diagram, internal clock divided by N

The diagram shows the relationship between the prescaler clock (CK_PSC) and the counter clock (CK_CNT). CK_PSC is a square wave. CK_CNT is derived from CK_PSC and is shown as a series of pulses. The counter register starts at 1F, increments to 20, and then overflows to 00. The counter overflow signal is a pulse that goes high when the counter reaches 00. The update event (UEV) is a pulse that goes high when the counter overflows. The update interrupt flag (UIF) is a high pulse that goes high when the counter overflows and remains high until it is cleared.

Timing diagram for internal clock divided by N. It shows CK_PSC (square wave), Timer clock = CK_CNT (derived from CK_PSC), Counter register (values 1F, 20, 00), Counter overflow (pulse), Update event (UEV) (pulse), and Update interrupt flag (UIF) (high pulse).

Figure 76. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)

The diagram shows the relationship between the prescaler clock (CK_PSC), the counter enable (CEN), and the counter clock (CK_CNT). CK_PSC is a square wave. CEN is a signal that goes high to enable the counter. CK_CNT is a square wave that is active when CEN is high. The counter register starts at 31, increments through 32, 33, 34, 35, 36, overflows to 00, and then continues to increment through 01, 02, 03, 04, 05, 06, 07. The counter overflow signal is a pulse that goes high when the counter reaches 00. The update event (UEV) is a pulse that goes high when the counter overflows. The update interrupt flag (UIF) is a high pulse that goes high when the counter overflows and remains high until it is cleared. The auto-reload register starts at FF and is updated to 36. An arrow points to the transition in the auto-reload register with the text 'Write a new value in TIMx_ARR'.

Timing diagram for update event when ARPE=0. It shows CK_PSC (square wave), CEN (counter enable), Timer clock = CK_CNT (square wave), Counter register (values 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07), Counter overflow (pulse), Update event (UEV) (pulse), Update interrupt flag (UIF) (high pulse), and Auto-reload register (values FF, 36). An arrow points to the transition in the Auto-reload register with the text 'Write a new value in TIMx_ARR'.

Figure 77. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)

Timing diagram for a counter with ARPE=1. It shows the relationship between CK_PSC, CEN, Timer clock (CK_CNT), Counter register values, Counter overflow, Update event (UEV), Update interrupt flag (UIF), Auto-reload preload register, and Auto-reload shadow register. The counter register shows values F0, F1, F2, F3, F4, F5, 00, 01, 02, 03, 04, 05, 06, 07. The auto-reload preload register is updated with a new value (36) while the shadow register holds the previous value (F5) until the next overflow.

The timing diagram illustrates the operation of a counter when ARPE=1. The signals shown are:

CK_PSC : Prescaler clock signal, a periodic square wave.
CEN : Counter Enable signal, which goes high to start counting.
Timer clock = CK_CNT : The clock signal for the counter, derived from CK_PSC.
Counter register : Shows the sequence of values: F0, F1, F2, F3, F4, F5, 00, 01, 02, 03, 04, 05, 06, 07. The values F0 through F5 are highlighted in yellow.
Counter overflow : A pulse generated when the counter reaches its maximum value (07) and rolls over to 00.
Update event (UEV) : A pulse generated when the counter overflows and ARPE=1.
Update interrupt flag (UIF) : A flag that is set when an update event occurs.
Auto-reload preload register : Shows the value F5 being updated to 36. An arrow points to the update with the text "Write a new value in TIMx_ARR".
Auto-reload shadow register : Shows the value F5 being updated to 36. This register is updated when an update event occurs.

Timing diagram for a counter with ARPE=1. It shows the relationship between CK_PSC, CEN, Timer clock (CK_CNT), Counter register values, Counter overflow, Update event (UEV), Update interrupt flag (UIF), Auto-reload preload register, and Auto-reload shadow register. The counter register shows values F0, F1, F2, F3, F4, F5, 00, 01, 02, 03, 04, 05, 06, 07. The auto-reload preload register is updated with a new value (36) while the shadow register holds the previous value (F5) until the next overflow.

17.3.3 Repetition counter

Section 17.3.1: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows. It is actually generated only when the repetition counter has reached zero. This can be useful when generating PWM signals.

This means that data are transferred from the preload registers to the shadow registers (TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx capture/compare registers in compare mode) every N counter overflow, where N is the value in the TIMx_RCR repetition counter register.

The repetition counter is decremented at each counter overflow.

The repetition counter is an auto-reload type; the repetition rate is maintained as defined by the TIMx_RCR register value (refer to Figure 78. Update rate examples depending on mode and TIMx_RCR register settings).

When the update event is generated by software (by setting the UG bit in the TIMx_EGR register) or by hardware through the slave mode controller, it occurs immediately whatever the value of the repetition counter is and the repetition counter is reloaded with the content of the TIMx_RCR register.

Figure 78. Update rate examples depending on mode and TIMx_RCR register settings

Edge-aligned mode
Upcounting

Counter TIMx_CNT

TIMx_RCR = 0 UEV

TIMx_RCR = 1 UEV

TIMx_RCR = 2 UEV

TIMx_RCR = 3 UEV

TIMx_RCR = 3 and re-synchronization UEV (by SW)

UEV Update Event: Preload registers transferred to active registers and update interrupt generated.
MS31084V2

Timing diagram showing update rate examples for Edge-aligned mode and Upcounting. It displays the Counter TIMx_CNT (a sawtooth wave) and Update Events (UEV) for different TIMx_RCR settings: 0, 1, 2, 3, and 3 with re-synchronization. The diagram shows how the update rate decreases as the TIMx_RCR value increases. The re-synchronization example shows a manual update event generated by software (SW).

17.3.4 Clock selection

The counter clock can be provided by the following clock sources:

Internal clock (CK_INT)

Internal clock source (CK_INT)

The CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are control bits and can be changed only by software (except UG, which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.

Figure 79. Control circuit in normal mode, internal clock divided by 1 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.

Figure 79. Control circuit in normal mode, internal clock divided by 1

Internal clock

CEN=CNT_EN

CNT_INIT

Counter clock = CK_CNT = CK_PSC

Counter register

Timing diagram for the control circuit in normal mode with internal clock divided by 1. It shows the Internal clock, CEN=CNT_EN, UG, CNT_INIT, Counter clock = CK_CNT = CK_PSC, and Counter register. The counter register shows a sequence of values: 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07.

17.3.5 Capture/compare channels

Each capture/compare channel is built around a capture/compare register (including a shadow register), an input stage for capture (with digital filter, multiplexing, and prescaler) and an output stage (with comparator and output control).

Figure 80. Capture/compare channel (example: channel 1 input stage) to Figure 82. Output stage of capture/compare channel (channel 1) give an overview of one capture/compare channel.

The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS).

Figure 80. Capture/compare channel (example: channel 1 input stage)

Figure 80: Capture/compare channel (example: channel 1 input stage) block diagram. The diagram shows the input stage starting with TI1 input, which passes through a filter downcounter (controlled by ICF[3:0] from TIMx_CCMR1) to produce TI1F. This signal then goes through an Edge Detector (controlled by CC1P/CC1NP from TIMx_CCER) to produce TI1F_Rising and TI1F_Falling signals. These signals are combined with TI2F signals (rising and falling from channel 2) via multiplexers to produce TI1FP1 and TI2FP1 signals. TI1FP1 is connected to an OR gate to produce TI1F_ED, which is sent to the slave mode controller. TI2FP1 is connected to a multiplexer (controlled by TRC from slave mode controller) to produce IC1. IC1 is then passed through a divider (/1, /2, /4, /8) controlled by CC1S[1:0] and ICPS[1:0] from TIMx_CCMR1 and CC1E from TIMx_CCER to produce IC1PS.

The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain.

Figure 81. Capture/compare channel 1 main circuit

Figure 81: Capture/compare channel 1 main circuit block diagram. This diagram shows the main circuitry of the capture/compare channel. It includes an APB Bus connected to an MCU-peripheral interface. The interface controls a Capture/compare preload register and a Capture/compare shadow register. The preload register is loaded from the APB Bus via write CCR1H and write CCR1L signals. The shadow register is loaded from the preload register via capture_transfer and compare_transfer signals. The shadow register is connected to a Counter and a Comparator. The Counter is controlled by CC1G from TIMx_EGR. The Comparator compares the Counter value (CNT) with the CCR1 value. The output of the Comparator is connected to an output mode multiplexer (controlled by CC1S[1] and CC1S[0]) to produce OC1PE. The output mode multiplexer is also controlled by UEV from the time base unit and OC1PE from TIMx_CCMR1. The output stage also includes a capture/compare shadow register and a capture/compare preload register. The preload register is loaded from the APB Bus via write CCR1H and write CCR1L signals. The shadow register is loaded from the preload register via capture_transfer and compare_transfer signals. The shadow register is connected to a Counter and a Comparator. The Counter is controlled by CC1G from TIMx_EGR. The Comparator compares the Counter value (CNT) with the CCR1 value. The output of the Comparator is connected to an output mode multiplexer (controlled by CC1S[1] and CC1S[0]) to produce OC1PE. The output mode multiplexer is also controlled by UEV from the time base unit and OC1PE from TIMx_CCMR1.

Figure 82. Output stage of capture/compare channel (channel 1)

The diagram illustrates the signal path for timer channel 1. It starts with inputs CNT>CCR1 , CNT=CCR1 , and OC2REF entering an Output mode controller . This feeds into an Output selector , which also receives OC1REF . The output OC1REF is sent to the master mode controller and a Dead-time generator . The dead-time generator produces OC1_DT and OC1N_DT . These signals pass through multiplexers controlled by CC1P and CC1NP bits. Finally, Output enable circuits (controlled by MOE , OSSI , OSSR , CC1E , and CC1NE ) drive the OC1 and OC1N output pins. Control registers involved include TIMx_CCMR1 , TIMx_BDTR , and TIMx_CCER .

Block diagram of the output stage of capture/compare channel 1.

The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register.

In capture mode, captures are actually done in the shadow register, which is copied into the preload register.

In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter.

17.3.6 Input capture mode

In input capture mode, the capture/compare registers (TIMx_CCR _x) are used to latch the value of the counter after a transition detected by the corresponding IC _xsignal. When a capture occurs, the corresponding CC _xIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CC _xIF flag was already high, then the overcapture flag CC _xOF (TIMx_SR register) is set. CC _xIF can be cleared by software by writing it to '0' or by reading the captured data stored in the TIMx_CCR _xregister. CC _xOF is cleared when it is written to '0'.

The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure:

• Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input and the TIMx_CCR1 register becomes read-only.
• Program the input filter duration needed with respect to the signal connected to the timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Imagine that, when toggling, the input signal is not stable during, at most, 5 internal clock cycles. A filter duration longer than these 5 clock cycles must be programmed. A transition on TI1 can be validated when 8 consecutive samples with the new level have been detected (sampled at $f_{DTS}$ frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register.
• Select the edge of the active transition on the TI1 channel by writing CC1P and CC1NP bits to 0 in the TIMx_CCER register.
• Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to '00' in the TIMx_CCMR1 register).
• Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register.
• If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the TIMx_DIER register.

When an input capture occurs:

– The TIMx_CCR1 register gets the value of the counter on the active transition.
– CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared.
– An interrupt is generated depending on the CC1IE bit.
– A DMA request is generated depending on the CC1DE bit.

In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data.

Note: IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register.

17.3.7 Forced output mode

In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter.

To force an output compare signal (OCxREF/OCx) to its active level, 101 needs to be written in the OCxM bits in the corresponding TIMx_CCMRx register. Thus, OCxREF is forced high (OCxREF is always active high) and OCx gets an opposite value to CCxP polarity bit.

For example: CCxP=0 (OCx active high) => OCx is forced to high level.

The OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register.

Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the output compare mode section below.

17.3.8 Output compare mode

This function is used to control an output waveform or indicate when a period of time has elapsed.

When a match is found between the capture/compare register and the counter, the output compare function:

• Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCxM=0000), be set active (OCxM=0001), be set inactive (OCxM=0010) or can toggle (OCxM=0011) on match.
• Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).
• Generates an interrupt if the corresponding interrupt mask is set (CCxIE bit in the TIMx_DIER register).
• Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection).

The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register.

In output compare mode, the update event UEV has no effect on OCxREF and OCx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in one-pulse mode).

Procedure:

1. Select the counter clock (internal, external, prescaler).
2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3. Set the CCxIE bit if an interrupt request is to be generated.
4. Select the output mode. For example:
1. a. Write OCxM = 0011 to toggle OCx output pin when CNT matches CCRx
2. b. Write OCxPE = 0 to disable preload register
3. c. Write CCxP = 0 to select active high polarity
4. d. Write CCxE = 1 to enable the output
5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.

The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE='0', otherwise the TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 83. Output compare mode, toggle on OC1

Figure 83. Output compare mode, toggle on OC1

Timing diagram for Output compare mode, toggle on OC1. The diagram shows three horizontal timelines. The top timeline, TIMx_CNT, shows counter values: 0039, 003A, 003B, followed by a dashed section, then B200, and B201. The middle timeline, TIMx_CCR1, shows the compare register value 003A. An arrow points from the text 'Write B201h in the CC1R register' to the value B201 in the TIMx_CCR1 register. The bottom timeline, oc1ref=OC1, shows a signal that is initially high, then goes low at the match point (003A), and then goes high again at the reload point (B201). Below the OC1 signal, text indicates 'Match detected on CCR1' and 'Interrupt generated if enabled'.

17.3.9 PWM mode

Pulse width modulation mode allows the user to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.

PWM mode can be selected independently on each channel (one PWM per OCx output) by writing '110' (PWM mode 1) or '111' (PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. The user must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in up-counting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.

As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, all the registers must be initialized by setting the UG bit in the TIMx_EGR register.

OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by a combination of the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers). Refer to the TIMx_CCER register description for more details.

In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether $TIMx\_CCRx \leq TIMx\_CNT$ or $TIMx\_CNT \leq TIMx\_CCRx$ (depending on the direction of the counter).

The TIM16/17 is able to upcount only. Refer to the up-counting mode.

In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as $TIMx\_CNT < TIMx\_CCRx$ , otherwise it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR), then OCxREF is held at '1'. If the compare value is 0, then OCxRef is held at '0'.

Figure 84. Edge-aligned PWM waveforms (ARR=8) shows some edge-aligned PWM waveforms in an example where TIMx_ARR=8.

Figure 84. Edge-aligned PWM waveforms (ARR=8)

Timing diagram showing edge-aligned PWM waveforms for different CCRx values. The diagram includes a counter register sequence (0-8, 0, 1), OCXREF signals, and CCxIF flags for CCRx=4, CCRx=8, CCRx>8, and CCRx=0. For CCRx=4, the OCXREF signal is high from counter 0 to 4. For CCRx=8, it is high from 0 to 8. For CCRx>8, it is always high ('1'). For CCRx=0, it is always low ('0'). CCxIF flags are shown as pulses at the end of each PWM period.

17.3.10 Complementary outputs and deadtime insertion

The TIM16/17 general-purpose timers can output one complementary signal and manage the switching-off and the switching-on instants of the outputs.

This time is generally known as the deadtime and it has to be adjusted depending on the devices connected to the outputs and their characteristics (intrinsic delays of level-shifters, delays due to power switches...).

The user can select the polarity of the outputs (main output OCx or complementary OCxN) independently for each output. This is done by writing to the CCxP and CCxNP bits in the TIMx_CCER register.

The complementary signals OCx and OCxN are activated by a combination of several control bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx, OISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers.

Refer to Table 81. Output control bits for complementary OCx and OCxN channels with break feature for more details. In particular, the deadtime is activated when switching to the idle-state (MOE falling down to 0).

The deadtime insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. There is one 10-bit deadtime generator for each channel. From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high:

• The OCx output signal is the same as the reference signal except for the rising edge, which is delayed relative to the reference rising edge
• The OCxN output signal is the opposite of the reference signal except for the rising edge, which is delayed relative to the reference falling edge

If the delay is greater than the width of the active output (OCx or OCxN) then the corresponding pulse is not generated.

The following figures show the relationships between the output signals of the deadtime generator and the reference signal OCxREF (we suppose CCxP=0, CCxNP=0, MOE=1, CCxE=1 and CCxNE=1 in these examples).

Figure 85. Complementary output with deadtime insertion

Timing diagram for Figure 85 showing complementary output with deadtime insertion. The diagram shows three waveforms: OCxREF, OCx, and OCxN. OCxREF is a reference signal. OCx and OCxN are complementary outputs. Deadtime is indicated by double-headed arrows labeled 'delay' between the transitions of OCx and OCxN.

Figure 86. Deadtime waveforms with delay greater than the negative pulse

Timing diagram for Figure 86 showing deadtime waveforms where the delay is greater than the negative pulse. The diagram shows three waveforms: OCxREF, OCx, and OCxN. OCxREF is a reference signal. OCx and OCxN are complementary outputs. Deadtime is indicated by a double-headed arrow labeled 'delay' between the transitions of OCx and OCxN.

Figure 87. Deadtime waveforms with delay greater than the positive pulse

Timing diagram for Figure 87 showing deadtime waveforms where the delay is greater than the positive pulse. The diagram shows three waveforms: OCxREF, OCx, and OCxN. OCxREF is a reference signal. OCx and OCxN are complementary outputs. Deadtime is indicated by a double-headed arrow labeled 'delay' between the transitions of OCx and OCxN.

The deadtime delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 17.4.13: TIM16/17 break and deadtime register (TIMx_BDTR) for delay calculation.

Re-directing OCxREF to OCx or OCxN

In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx output or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER register.

This allows a specific waveform (such as PWM or static active level) to be sent on one output while the complementary remains in its inactive level. Other alternative possibilities are to have both outputs at inactive level or both outputs active and complementary with deadtime.

Note: When OCxN is enabled (CCxE=0, CCxNE=1) only, it is not complemented and becomes active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes active when OCxREF is high whereas OCxN is complemented and becomes active when OCxREF is low.

17.3.11 Using the break function

The purpose of the break function is to protect power switches driven by PWM signals generated with the TIM16/17 timers. The two break inputs are usually connected to fault outputs of power stages and 3-phase inverters. When activated, the break circuitry shuts down the PWM outputs and forces them to a predefined safe state.

When the break function is used, the output enable signals and inactive levels are modified according to additional control bits (MOE, OSSI and OSSR bits in the TIMx_BDTR register, OISx and OISxN bits in the TIMx_CR2 register). In any case, the OCx and OCxN outputs cannot be set both to active level at a given time. Refer to Table 81. Output control bits for complementary OCx and OCxN channels with break feature for more details.

When exiting from reset, the break circuit is disabled and the MOE bit is low. The user can enable the break function by setting the BKE and BKE2 bits in the TIMx_BDTR register. The break input global polarity can be selected by configuring the BKP bit in the same register. BKEx and BKP can be modified at the same time. When the BKEx and BKPx bits are written, a delay of 1 APB clock cycle is applied before the writing is effective. Consequently, it is necessary to wait for 1 APB clock period to correctly read back the bit after the write operation. Because MOE falling edge can be asynchronous, a resynchronization circuit has been inserted between the actual signal (acting on the outputs) and the synchronous control bit (accessed in the TIMx_BDTR register). It results in some delays between the asynchronous and the synchronous signals. In particular, if MOE is written to 1 whereas it was low, a delay (dummy instruction) must be inserted before reading it correctly. This is because the asynchronous signal is written and the synchronous signal is read.

The break is generated by the BRK inputs which have:

• Programmable polarity (BKP bit in the TIMx_BDTR register)
• Programmable enable bit (BKE bit in the TIMx_BDTR register)

Note: An asynchronous (clockless) operation is only guaranteed when the programmable filter is disabled.

When a break occurs (selected level on the break input):

• The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or even releasing the control to the AFIO controller (selected by the OSSI bit). This feature functions even if the MCU oscillator is off.
• Each output channel is driven with the level programmed in the OISx bit in the TIMx_CR2 register as soon as MOE=0. If OSSI=0, the timer releases the output control (taken over by the AFIO controller) or else the enable output remains high.
• When complementary outputs are used:
- – The outputs are first put in reset state, inactive state (depending on the polarity). This is done asynchronously so that it works even if no clock is provided to the timer.
- – If the timer clock is still present, then the deadtime generator is reactivated in order to drive the outputs with the level programmed in the OISx and OISxN bits after a deadtime. Even in this case, OCx and OCxN cannot be driven to their active level together. Note that because of the resynchronization on MOE, the deadtime duration is a bit longer than usual (around 2 ck_tim clock cycles).
- – If OSSI=0 then the timer releases the enable outputs (taken over by the AFIO controller which forces a Hi-Z state) or else the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high.
• The break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be generated if the BIE bit in the TIMx_DIER register is set. A DMA request can be sent if the BDE bit in the TIMx_DIER register is set.
• If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again at the next update event UEV. This can be used to perform a regulation, for instance. Otherwise, MOE remains low until it is written to '1' again. In this case, it can be used for security and the break input can be connected to an alarm from power drivers, thermal sensors or any security components.

Note: The break inputs is acting on level. Thus, the MOE cannot be set while the break input is active (neither automatically nor by software). In the meantime, the status flag BIF cannot be cleared.

The break can be generated by the BRK input which has a programmable polarity and an enable bit BKE in the TIMx_BDTR register.

In addition to the break input and the output management, a write protection has been implemented inside the break circuit to safeguard the application. It allows the user to freeze the configuration of several parameters (deadtime duration, OCx/OCxN polarities and state when disabled, OCxM configurations, break enable and polarity). The user can choose from 3 levels of protection selected by the LOCK bits in the TIMx_BDTR register. Refer to TIM16&TIM17 break and deadtime register (TIMx_BDTR). The LOCK bits can be written only once after an MCU reset.

The figure below shows an example of behavior of the outputs in response to a break.

Figure 88. Various output behavior in response to a break event on BRK (OSSI = 1)

Timing diagram showing various output behaviors (OCxREF, OCx, OCxN) in response to a break event on BRK (MOE = 1). The diagram illustrates how different output configurations (e.g., OCxN not implemented, CCxP=0, OISx=1) affect the output state and delay after a break event. The break event is indicated by a vertical dashed line labeled 'BREAK (MOE = 1)'.

17.3.12 Bidirectional break inputs

The TIM16/TIM17 feature bidirectional break I/Os, as represented in Figure 89. Output redirection.

They allow:

• A board-level global break signal available for signaling faults to external MCUs or gate drivers, with a unique pin being both an input and an output status pin
• Internal break sources and multiple external open drain comparator outputs ORed together to trigger a unique break event, when multiple internal and external break sources must be merged

The break input is configured in bidirectional mode using the BKBID bit in the TIMxBDTR register. The BKBID programming bit can be locked in read-only mode using the LOCK bits in the TIMxBDTR register (in LOCK level 1 or above).

The bidirectional mode requires the I/O to be configured in open-drain mode with active low polarity (using BKINP and BKP bits). Any break request coming from break inputs forces a low level on the break input to signal the fault event. The bidirectional mode is inhibited if the polarity bits are not correctly set (active high polarity), for safety purposes.

The break software event (BG) also causes the break I/O to be forced to '0' to indicate to the external components that the timer has entered in break state. However, this is valid only if the break is enabled (BKE = 1). When a software break event is generated with BKE = 0, the outputs are put in safe state and the break flag is set, but there is no effect on the break I/O.

A safe disarming mechanism prevents the system from being definitively locked-up (a low level on the break input triggers a break which enforces a low level on the same input).

When the BKDSRM bit is set to 1, this releases the break output to clear a fault signal and to give the possibility to re-arm the system.

At no point can the break protection circuitry be disabled:

• The break input path is always active: a break event is active even if the BKDSRM bit is set and the open drain control is released. This prevents the PWM output from re-starting as long as the break condition is present.
• The BKDSRM bit cannot disarm the break protection as long as the outputs are enabled (MOE bit is set).

See the table below:

Table 80. Break protection disarming conditions

MOE	BKDIR	BKDSRM	Break protection state
0	0	X	Armed
0	1	0	Armed
0	1	1	Disarmed
1	X	X	Armed

Arming and re-arming break circuitry

The break circuitry (in input or bidirectional mode) is armed by default (peripheral reset configuration).

The following procedure must be followed to re-arm the protection after a break event:

• The BKDSRM bit must be set to release the output control
• The software must poll the BKDSRM bit until it is cleared by hardware (when the application break condition disappears)

From this point, the break circuitry is armed and active, and the MOE bit can be set to reenable the PWM outputs.

Figure 89. Output redirection

The diagram illustrates the internal logic for output redirection and break protection. On the left, a 'Bidirectional Break I/O' is connected to an 'AF input (active low)' which passes through an inverter to an 'AF Controller'. Below the input, an 'AF output (open drain)' is connected to the 'AF Controller' and pulled down to 'Vss'. The 'AF Controller' provides 'BKIN inputs from AF controller' to a logic block. This logic block also receives 'BKP' and 'BKE' signals. A 'Software break requests: BG' signal is also input to this logic. The logic block generates a 'BRK request' signal. To the right, the 'BRK request' signal is ANDed with a constant '1' to produce a 'BIF flag' and a 'BRK request' output. Below the main logic, 'Bidirectional Mode Control Logic' is shown, which is connected to 'MOE', 'BKBID', and 'BKDSRM' registers and also connected to 'Vss'.

Figure 89. Output redirection diagram showing the internal logic for break protection. It includes a Bidirectional Break I/O, AF input (active low), AF output (open drain), AF Controller, Bidirectional Mode Control Logic, BKIN inputs, BKP, BKE, and a BRK request logic block.

17.3.13 One-pulse mode

One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.

The waveform can be generated in output compare mode or PWM mode. The user selects one-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV.

A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting, the configuration must be:

• $CNT < CCRx \leq ARR$ (in particular, $$ 0 < CCRx $$ )

Figure 90. Example of one-pulse mode

Timing diagram for one-pulse mode. The diagram shows four waveforms over time (t). 1. TI1: A single positive pulse. 2. OC1REF: A signal that goes high when TI1 is high and returns low when the counter reaches TIMx_ARR. 3. OC1: A signal that goes high when the counter reaches TIMx_CCR1 and returns low when the counter reaches TIMx_ARR. 4. Counter: A staircase waveform starting at 0 and increasing until it reaches TIMx_ARR, at which point it resets to 0. The time interval from the rising edge of TI1 to the rising edge of OC1 is labeled t_DELAY. The time interval from the rising edge of OC1 to the falling edge of OC1REF is labeled t_PULSE.

For example, the user may want to generate a positive pulse on OC1 with a length of $t_{PULSE}$ and after a delay of $t_{DELAY}$ .

The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler).

• The $t_{DELAY}$ is defined by the value written in the TIMx_CCR1 register
• The $t_{PULSE}$ is defined by the difference between the auto-reload value and the compare value ( $TIMx\_ARR - TIMx\_CCR1$ )
• Target: to build a waveform with a transition from '0' to '1' when a compare match occurs and a transition from '1' to '0' when the counter reaches the auto-reload value. To do this, enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1 register. The user can optionally enable the preload registers by writing OC1PE='1' in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case the compare value must be written in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register. Generate an update by setting the UG bit and wait for external trigger event on TI1. CC1P is written to '0' in this example.

Only 1 pulse is wanted, so write '1' in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0).

Particular case: OCx fast enable:

In one-pulse mode, the edge detection on TIx input sets the CEN bit, which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. Several clock cycles are needed for these operations. The minimum delay $t_{DELAY}$ is the minimum we can get.

If it is necessary to output a waveform with the minimum delay, the user can set the OCxFE bit in the TIMx_CCMRx register. Then OCxRef (and OCx) is forced in response to the stimulus, without taking the comparison into account. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.

17.3.14 UIF bit remapping

The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the update interrupt flag UIF into the timer counter register bit 31 (TIMxCNT[31]). This allows both the counter value and a potential roll-over condition signaled by the UIFCPY flag to be read in an atomic way. In particular cases, it can ease the calculations by avoiding race conditions, caused for instance by a processing shared between a background task (counter reading) and an interrupt (update interrupt). There is no latency between the UIF and UIFCPY flags assertion.

17.3.15 DMA burst mode

The TIMx timers have the capability to generate multiple DMA requests on a single event.

The main purpose is to be able to re-program several timer registers multiple times without software overhead, but it can also be used to read several registers in a row, at regular intervals.

The DMA controller destination is unique and must point to the virtual register TIMx_DMAR.

On a given timer event, the timer launches a sequence of DMA requests (burst). Each write into the TIMx_DMAR register is actually redirected to one of the timer registers.

The DBL[4:0] bits in the TIMx_DCR register set the DMA burst length. The timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers (either in half-words or in bytes).

The DBA[4:0] bits in the TIMx_DCR registers define the DMA base address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register.

Example:

00000: TIMx_CR1

00001: TIMx_CR2

For example, the timer DMA burst feature could be used to update the contents of the CCRx registers (x = 2, 3, 4) on an update event, with the DMA transferring half words into the CCRx registers.

This is done in the following steps:

1. Configure the corresponding DMA channel as follows:
1. a. DMA channel peripheral address is the DMAR register address
2. b. DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into the CCRx registers
3. c. Number of data to transfer = 3
4. d. Circular mode disabled
2. Configure the DCR register by configuring the DBA and DBL bit fields as follows: DBL = 3 transfers, DBA = 0xE
3. Enable the TIMx update DMA request (set the UDE bit in the DIER register)
4. Enable TIMx
5. Enable the DMA channel

This example is for the case where every CCRx register is to be updated once. If every CCRx register is to be updated twice for example, the number of data to transfer should be 6. We can take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and data6. The data is transferred to the CCRx registers as follows: on the first update DMA request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4.

17.4 TIM16/17 registers

Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions.

17.4.1 TIM16/17 control register 1 (TIMx_CR1)

Address offset: 0x04

Reset value: 0x0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.				UIFREMAP	Res.	CKD[1:0]		ARPE	Res.			OPM	URS	UDIS	CEN
				rw		rw	rw	rw				rw	rw	rw	rw

Bits 15:12	Reserved, must be kept at reset value.
Bit 11	UIFREMAP : UIF status bit remapping 0: No remapping. UIF status bit is not copied to TIMx_CNT register bit 31 1: Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31
Bits 10	Reserved, must be kept at reset value.
Bit 9:8	CKD[1:0] : Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the dead-time and sampling clock (tDTS) used by the dead-time generators and the digital filters (TIx), 00: $t_{DTS} = t_{CK\_INT}$ 01: $t_{DTS} = 2 \times t_{CK\_INT}$ 10: $t_{DTS} = 4 \times t_{CK\_INT}$ 11: Reserved, do not program this value
Bit 7	ARPE : Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered
Bit 6:4	Reserved, must be kept at reset value
Bit 3	OPM : One pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN)
Bit 2	URS : Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
Bit 1	UDIS : Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: Counter overflow/underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values.

	1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
Bit 0	CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock and gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.

17.4.2 TIM16/17 control register 2 (TIMx_CR2)

Address offset: 0x04

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	OIS1N	OIS1	Res.	Res.	Res.	Res.	CCDS	CCUS	Res.	CCPC
						rW	rW					rW	rW		rW

Bits 15:10	Reserved, must be kept at reset value.
Bit 9	OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BKR register).
Bits 8	OIS1: Output Idle state 1 (OC1 output) 0: OC1N=0 after a dead-time if OC1N is implemented) when MOE=0 1: OC1=1 after a dead-time if OC1N is implemented) when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BKR register).
Bit 7:4	Reserved, must be kept at reset value
Bit 3	CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs
Bit 2	CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only. Note: This bit acts only on channels that have a complementary output.
Bit 1	Reserved, must be kept at reset value
Bit 0	CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. Note: This bit acts only on channels that have a complementary output.

17.4.3 TIM16/17 DMA/interrupt enable register (TIMx_DIER)

Address offset: 0x0C

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	CC1DE	UDE	BIE	Res.	COMIE	Res.	Res.	Res.	CC1IE	UIE
						rw	rw	rw		rw				rw	rw

Bits 15:13	Reserved, must be kept at reset value.
Bit 12:10	Reserved, must be kept at reset value.
Bit 9	CC1DE : Capture/compare 1 DMA request enable 0: CC1 DMA request disabled 1: CC1 DMA request enabled
Bit 8	UDE : update DMA request enable 0: Update DMA request disabled 1: Update DMA request enabled
Bit 7	BIE : Break interrupt enable 0: Break interrupt disabled 1: Break interrupt enabled
Bit 6	Reserved, must be kept at reset value
Bit 5	COMIE : COM interrupt enable 0: COM interrupt disabled 1: COM interrupt enabled
Bit 4:2	Reserved, must be kept at reset value
Bit 1	CCIE : Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled
Bit 0	UIE : Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled

17.4.4 TIM16/17 status register (TIMx_SR)

Address offset: 0x10

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	CC1OF	Res.	BIF	Res.	COMIF	Res.	Res.	Res.	CC1IF	UIF
						rc_w0		rc_w0		rc_w0				rc_w0	rc_w0

Bits 15:10	Reserved, always read as 0.
Bit 9	CC1OF : Capture/compare 1 overcapture flag. This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to '0'. 0: No overcapture has been detected 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
Bit 8	Reserved, must be kept at reset value
Bit 7	BIF : Break interrupt flag. This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred 1: An active level has been detected on the break input
Bit 6	Reserved, must be kept at reset value
Bit 5	COMIF : COM interrupt flag This flag is set by hardware on a COM event (once the capture/compare control bits –CCxE, CCxNE, OCxM– have been updated). It is cleared by software. 0: No COM event occurred 1: COM interrupt pending
Bit 4:2	Reserved, must be kept at reset value.
Bit 1	CC1IF : Capture/compare 1 interrupt flag. If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by software. 0: No match 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in up-counting and up/down-counting modes) or underflow (in down-counting mode). If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred 1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1 which matches the selected polarity)
Bit 0	UIF : Update interrupt flag. This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow regarding the repetition counter value (update if repetition counter = 0) and if the UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register.

17.4.5 TIM16 and 17 event generation register (TIMx_EGR)

Address offset: 0x14

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG		COMG				CC1G	UG
								w		w				w	w

Bits 15:8	Reserved, must be kept at reset value
Bit 7	BG: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled
Bit 6	Reserved, must be kept at reset value
Bit 5	COMG: Capture/Compare control update generation. This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits. Note: This bit acts only on channels that have a complementary output.
Bits 4:2	Reserved, must be kept at reset value
Bit 1	CC1G: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action. 1: A capture/compare event is generated on channel 1: if channel CC1 is configured as output: CC1IF flag is set. Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input. The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high.
Bit 0	UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected).

17.4.6 TIM16/17 capture/compare mode register 1 (TIMx_CCMR1)

Address offset: 0x18

Reset value: 0x0000

The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So you must take care that the same bit can have a different meaning for the input stage and for the output stage.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OC1M[3]
															Res.
															rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OC1M[2:0]			OC1PE	OC1FE	CC1S[1:0]
									IC1F[3:0]			IC1PSC[1:0]
								rw	rw	rw	rw	rw	rw	CC1S[1:0]		rw	rw

Output compare mode:

Bits 31:17	Reserved, always read as 0.
Bit 6	OC1M[3]: Output compare 1 mode - bit 3 OC1M[2:0]: Output compare 1 mode (bits 2 to 0) These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 0000: Frozen - the comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 0001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 0011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 0100: Force inactive level - OC1REF is forced low. 0101: Force active level - OC1REF is forced high. 0110: PWM mode 1 - Channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive 0111: PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active All other values: Reserved Note 1: These bits cannot be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in output). Note 2: In PWM mode, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from "frozen" mode to "PWM" mode.
Bit 3	OC1PE: Output compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken into account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note 1: These bits cannot be modified as long as LOCK level 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S='00' (the channel is configured in output). Note 2: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in TIMx_CR1 register). Otherwise the behavior is not guaranteed.

Bit 2

OC1FE : Output compare 1 fast enable

This bit is used to accelerate the effect of an event on the trigger in input on the CC output.

0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles.

1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode.

Bits 1:0

CC1S : Capture/compare 1 selection.

This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output

01: CC1 channel is configured as input, IC1 is mapped on TI1

10: CC1 channel is configured as input, IC1 is mapped on TI2

11: Reserved

Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER).

Input capture mode

Bits 31:8	Reserved, always read as 0.
Bits 7:4	IC1F[3:0] : Input capture 1 filter. This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at $f_{DTS}$ 0001: $f_{SAMPLING}=f_{CK\_INT}$ , N=2 0010: $f_{SAMPLING}=f_{CK\_INT}$ , N=4 0011: $f_{SAMPLING}=f_{CK\_INT}$ , N=8 0100: $f_{SAMPLING}=f_{DTS}/2$ , N=6 0101: $f_{SAMPLING}=f_{DTS}/2$ , N=8 0110: $f_{SAMPLING}=f_{DTS}/4$ , N=6 0111: $f_{SAMPLING}=f_{DTS}/4$ , N=8 1000: $f_{SAMPLING}=f_{DTS}/8$ , N=6 1001: $f_{SAMPLING}=f_{DTS}/8$ , N=8 1010: $f_{SAMPLING}=f_{DTS}/16$ , N=5 1011: $f_{SAMPLING}=f_{DTS}/16$ , N=6 1100: $f_{SAMPLING}=f_{DTS}/16$ , N=8 1101: $f_{SAMPLING}=f_{DTS}/32$ , N=5 1110: $f_{SAMPLING}=f_{DTS}/32$ , N=6 1111: $f_{SAMPLING}=f_{DTS}/32$ , N=8
Bits 3:2	IC1PSC : Input capture 1 prescaler. This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E='0' (TIMx_CCER register). 00: No prescaler, capture is done each time an edge is detected on the capture input 01: Capture is done once every 2 events 10: Capture is done once every 4 events 11: Capture is done once every 8 events
Bits 1:0	CC1S : Capture/compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input.

00: CC1 channel is configured as output

01: CC1 channel is configured as input, IC1 is mapped on TI1

10: CC1 channel is configured as input, IC1 is mapped on TI2

11: Reserved.

Note: CC1S bits are writable only when the channel is OFF (CC1E = '0' in TIMx_CCER).

17.4.7 TIM16/17 capture/compare enable register (TIMx_CCER)

Address offset: 0x20

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CC1NP	CC1NE	CC1P	CC1E
												rW	rW	rW	rW

Bits 15:4	Reserved, always read as 0.
Bit 3	CC1NP: Capture/compare 1 output polarity. CC1 channel configured as output: 0: OC1N active high 1: OC1N active low CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to the description of CC1P. Note 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register) and CC1S="00" (the channel is configured in output). 2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the preloaded bit only when a commutation event is generated.
Bit 2	CC1NE: Capture/compare 1 output enable 0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits 1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
Bit 1	CC1P: Capture/compare 1 output polarity. CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for trigger or capture operations. 00: Non-inverted/rising edge. The circuit is sensitive to TIxFP1 rising edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode). 01: Inverted/falling edge. The circuit is sensitive to TIxFP1 falling edge (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is inverted (trigger operation in gated mode). 10: Reserved, do not use this configuration. 11: Non-inverted/both edges. The circuit is sensitive to both TIxFP1 rising and falling edges (capture or trigger operations in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger operation in gated mode). Notes: 1. This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register). 2. On channels that have a complementary output, this bit is preloaded. If the CCPC bit is set in the TIMx_CR2 register then the CC1P active bit takes the new value from the preloaded bit only when a Commutation event is generated.
Bit 0	CC1E: Capture/Compare 1 output enable CC1 channel configured as output: 0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. 1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not.

0: Capture disabled

1: Capture enabled

Table 81. Output control bits for complementary OCx and OCxN channels with break feature

Control bits					Output states ⁽¹⁾
MOEbit	OSSI bit	OSSR bit	CCxE bit	CCxNE bit	OCx output state	OCxN output state
1	X	X	0	0	Output disabled (not driven by the timer: Hi-Z) OCx=0 OCxN=0, OCxN_EN=0
		0	0	1	Output disabled (not driven by the timer: Hi-Z) OCx=0	OCxREF +polarity OCxN=OCxREF XOR CCxNP
		0	1	0	OCxREF +polarity OCx=OCxREF XOR CCxP	Output disabled (not driven by the timer: Hi-Z) OCxN=0
		X	1	1	OCREF+ polarity + dead- time	Complementary to OCREF (not OCREF) + polarity + dead-time
		1	0	1	Off-state (output enabled with inactive state) OCx=CCxP	OCxREF +Polarity OCxN=OCxREF XOR CCxNP
		1	1	0	OCxREF +polarity OCx=OCxREF XOR CCxP, OCx_EN=1	Off-State (output enabled with inactive state) OCxN=CCxNP, OCxN_EN=1
0	0	X	X	X	Output disabled (not driven by the timer: Hi-Z) OCx=CCxP, OCxN=CCxNP
	1		0	0
			0	1	Off-state (output enabled with inactive state) asynchronously: OCx=CCxP, OCxN=CCxNP Then if the clock is present: OCx=OISx and OCxN=OISxN after a dead-time, assuming that OISx and OISxN do not correspond to OCx and OCxN both in active state
			1	0
			1	1

1. When both outputs of a channel are not used (control taken over by GPIO controller), the OISx, OISxN, CCxP and CCxNP bits must be kept cleared.

Note: The state of the external I/O pins connected to the complementary OCx and OCxN channels depends on the OCx and OCxN channel state and AFIO registers.

17.4.8 TIM16/17 counter (TIMx_CNT)

Address offset: 0x24

Reset value: 0x0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31	UIFCPY: UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0.
Bits 30:16	Reserved, always read as 0.
Bits 15:0	CNT[15:0]: Counter value

17.4.9 TIM16/17 prescaler (TIMx_PSC)

Address offset: 0x28

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits
15:0

PSC[15:0]: Prescaler value

The counter clock frequency (CK_CNT) is equal to $f_{CK\_PSC} / (PSC[15:0] + 1)$ .

PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in "reset mode").

17.4.10 TIM16/17 auto-reload register (TIMx_ARR)

Address offset: 0x2C

Reset value: 0xFFFF

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0

ARR[15:0]: Prescaler value
ARR is the value to be loaded in the actual auto-reload register.
Refer to Section 17.3.1: Time-base unit for more details about ARR update and behavior.
The counter is blocked while the auto-reload value is null.

17.4.11 TIM16/17 repetition counter register (TIMx_RCR)

Address offset: 0x30

Reset value: 0x0000

7	6	5	4	3	2	1	0
REP[7:0]
rw	rw	rw	rw	rw	rw	rw	rw

Bits
7:0

REP[7:0]: Repetition counter value.

These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enabled, as well as the update interrupt generation rate, if this interrupt is enabled.

Each time the REP_CNT related down-counter reaches zero, an update event is generated and it restarts counting from REP value. As REP_CNT is reloaded with REP value only at the repetition update event U_RC, any write to the TIMx_RCR register is not taken into account until the next repetition update event.

It means in PWM mode (REP+1) corresponds to the number of PWM periods in edge-aligned mode .

17.4.12 TIM16/17 capture/compare register 1 (TIMx_CCR1)

Address offset: 0x34

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0

CCR1[15:0]: Capture/compare 1 value.

If channel CC1 is configured as output:

CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Otherwise the preload value is copied in the active capture/compare 1 register when an update event occurs.

The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output.

If channel CC1 is configured as input:

CCR1 is the counter value transferred by the last input capture 1 event (IC1).

17.4.13 TIM16/17 break and deadtime register (TIMx_BDTR)

Address offset: 0x44

Reset value: 0x0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	BKBID	Res.	BKDSRM	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
			rw		rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK[1:0]		DTG[7:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Note: As the BKBID, BKDSRM, AOE, BKP, BKE, OSSI, OSSR, and DTG[7:0] bits and all used bits of TIMx_AF1 register may be write-locked depending on the LOCK configuration, it may be necessary to configure all of them during the first write access to the TIMx_BDTR register.

Bits 31:29	Reserved, must be kept at reset value
Bit 28	BKBID : Break bidirectional 0: Break input BRK in input mode 1: Break input BRK in bidirectional mode In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input mode and in open drain output mode. Any active break event asserts a low logic level on the Break input to indicate an internal break event to external devices. Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 27	Reserved, must be kept at reset value
Bit 26	BKDSRM : Break disarm 0: Break input BRK is armed 1: Break input BRK is disarmed This bit is cleared by hardware when no break source is active. The BKDSRM bit must be set by software to release the bidirectional output control (open drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the fault condition has disappeared. Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bits 25:16	Reserved, must be kept at reset value
Bit 15	MOE : Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output. 0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit. 1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register) See OC/OCN enable description for more details Section 17.4.7: TIM16/17 capture/compare enable register (TIMx_CCER)
Bit 14	AOE : Automatic output enable 0: MOE can be set by software only 1: MOE can be set by software or automatically at the next update event (if the break input is not be active) Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Bit 13	BKP : Break polarity

	0: Break input BRK is active low 1: Break input BRK is active high Note: 1. This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective
Bit 12	BKE: Break enable 0: Break inputs (BRK) disabled 1: Break inputs (BRK) enabled Note: 1. This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register). 2. Any write operation to this bit takes a delay of 1 APB clock cycle to become effective
Bit 11	OSSR: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer. See OC/OCN enable description for more details Section 17.4.7: TIM16/17 capture/compare enable register (TIMx_CCER) 0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the AFIO logic, which forces a Hi-Z state) 1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer). Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
Bit 10	OSSI: Off-state selection for idle mode This bit is used when MOE=0 on channels configured as outputs. See OC/OCN enable description for more details Section 17.4.7: TIM16/17 capture/compare enable register (TIMx_CCER) 0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0) 1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or CCxNE=1. OC/OCN enable output signal=1 Note: This bit cannot be modified when LOCK level 2 has been programmed (LOCK bits in TIMx_BDTR register).
Bit 9:8	LOCK[1:0]: Lock configuration These bits offer a write protection against software errors. 00: LOCK OFF - No bit is write protected 01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register, BKE/BKP/AOE/BKBID/BKDSRM bits in TIMx_BDTR register and all used bits in TIMx_AF1 register can no longer be written. 10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. 11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register has been written, their content is frozen until the next reset.
Bits 7:0	DTG[7:0]: Deadtime generator setup. This bit-field defines the duration of the deadtime inserted between the complementary outputs. DT matches this duration. DTG[7:5]=0xx => DT=DTG[7:0]x $t_{dtg}$ with $t_{dtg}=t_{DTS}$ . DTG[7:5]=10x => DT=(64+DTG[5:0])x $t_{dtg}$ with $T_{dtg}=2xT_{DTS}$ . DTG[7:5]=110 => DT=(32+DTG[4:0])x $t_{dtg}$ with $T_{dtg}=8xT_{DTS}$ . DTG[7:5]=111 => DT=(32+DTG[4:0])x $t_{dtg}$ with $T_{dtg}=16xT_{DTS}$ . Example if $T_{DTS} = 125$ ns (8 MHz), deadtime possible values are: 0 to 15875 ns by 125 ns steps, 16 µs to 31750 ns by 250 ns steps, 32 µs to 63 µs by 1 µs steps, 64 µs to 126 µs by 2 µs steps

Note: This bit-field cannot be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).

17.4.14 TIM16/17 DMA control register (TIMx_DCR)

Address offset: 0x48

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	DBL[4:0]				Res.	Res.	Res.	DBA[4:0]
			rW	rW	rW	rW	rW				rW	rW	rW	rW	rW

Bits 15:13	Reserved, must be kept at reset value
Bits 12:8	DBL[4:0]: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers. Transfers can be in half-words or in bytes (see example below). 00000: 1 transfer 00001: 2 transfers 00010: 3 transfers ... 10001: 18 transfers.
Bits 7:5	Reserved, must be kept at reset value
Bits 4:0	DBA[4:0]: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1 00001: TIMx_CR2 00010: Reserved ... Example: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.

17.4.15 TIM16/17 DMA address for full transfer (TIMx_DMAR)

Address offset: 0x4C

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0

DMAB[15:0]: DMA register for burst accesses

A read or write operation to the DMAR register accesses the register located at the address (TIM2_CR1 address) + (DBA + DMA index) x 4 where TIM2_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIM2_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIM2_DCR).

17.4.16 TIM17 option register 1 (TIM17_OR1)

Address offset: 0x50

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	TI1_RMP[1:0]
														rw	rw

Bits 1:0

TI1_RMP[1:0]: Timer 17 input 1 connection
This bit is set and cleared by software.
00: TIM17 TI1 is connected to GPIO
01: TIM17 TI1 is connected to RCC_LCO
1x: TIM17 TI1 is connected to RCC_MCO

17.4.17 TIM16/17 alternate function register 1(TIMx_AF1)

Address offset: 0x60

Reset value: 0x0001

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	BKCMP2P	BKCMP1P	BKINP	Res.						BKCMP2E	BKCMP1E	BKINE
				rw	rw	rw							rw	rw	rw

Bits 31:22	Reserved, must be kept at reset value.
Bit 11	BKCMP2P: BRK COMP2 input polarity. This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP2 input is active low. 1: COMP2 input is active high. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)
Bit 10	BKCMP1P: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP1 input is active low. 1: COMP1 input is active high. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)
Bit 9	BKINP: BRK BKIN input polarity This bit selects the BKIN alternate function input sensitivity. It must be programmed together with the BKP polarity bit. 0: BKIN input is active low. 1: BKIN input is active high. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)
Bits 8:3	Reserved, must be kept at reset value.
Bit 2	BKCMP2E: BRK COMP2 enable. This bit enables the COMP2 for the timer's BRK input. COMP2 output is ORed with the other enabled BRK sources. 0: COMP2 input disabled. 1: COMP2 input enabled. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)
Bit 1	BKCMP1E: BRK COMP1 enable This bit enables the COMP1 for the timer's BRK input. COMP1 output is ORed with the other enabled BRK sources. 0: COMP1 input disabled. 1: COMP1 input enabled. Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)
Bit 0	BKINE: BRK BKIN enable. This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is ORed with the other enabled BRK sources.

0: BKIN input disabled.

1: BKIN input enabled.

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register)

17.4.18 TIM16/17 input selection register (TIM16_TISEL)

Address offset: 0x68

Reset value: 0x0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	TI1SEL[3:0]
												rw	rw	rw	rw

Bit 31:14	Reserved, must be kept at reset value.
Bits 3:0	TI1SEL[3:0] : selects TI1[0] to TI1[15] input 0000: TIMx_CH1 input Others: Reserved

17.4.19 TIM16/17 register map

TIM16/17 registers are mapped as 16-bit addressable registers as described in the table below:

Table 82. TIM2 register map and reset values

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x00	TIMx_CR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIFREMAP	Res.	CKD [1:0]		ARPE	Res.	Res.	Res.	OPM	URS	UDIS	CEN
0x00	Reset value																					0		0	0	0				0	0	0	0
0x04	TIMx_CR2	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OIS1N	OIS1	Res.	Res.	Res.	Res.	CCDS	CCUS	Res.	CCPC
0x04	Reset value																							0	0					0	0		0
0x0C	TIMx_DIER	Res	Res	Res	Res	Res	Res	Res	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CC1DE	UDE	BIE	Res.	COMIE	Res.	Res.	Res.	CC1IE	UIE
0x0C	Reset value																										0		0	0	0	0	0
0x10	TIMx_SR	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res.	Res.	Res	Res	Res	Res.	Res.	Res.	CC1OF	Res.	BIF	Res.	COMIF	Res.	Res.	Res.	CC1IF	UIF
0x10	Reset value																							0		0		0			0	0
0x14	TIMx_EGR	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res.	BG	Res.	COMIG	Res.	Res.	Res.	CC1IG	UG
0x14	Reset value																									0		0				0	0
0x18	TIMx_CCMR1	Res	Res	Res	Res	Res	Res	Res	Res.	Res	Res	Res	Res	Res	Res	Res	OC1M[3]	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OC1M [2:0]	OC1PE	OC1FE	CC1S [1:0]
	Output Compare mode																											OC1M [2:0]	OC1PE	OC1FE	CC1S [1:0]
	Reset value																0										0	0	0	0	0
	TIMx_CCMR1 Input Capture mode	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	IC1F[3:0]	IC1PSC [1:0]	CC1S [1:0]
	Reset value																	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	0	0	0	0	0	0	0
0x20	TIMx_CCER	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res.	Res.	Res	Res	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CC1NP	CC1NE	CC1P	CC1E

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Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x20	Reset value																													0	0	0	0
0x24	TIMx_CNT	UIFCPY	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	CNT[15:0]
0x24	Reset value	0																0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x28	TIMx_PSC	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	PSC[15:0]
0x28	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x2C	TIMx_ARR	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	ARR[15:0]
0x2C	Reset value																	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1
0x30	TIMx_RCR	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	REP[7:0]
0x30	Reset value																									0	0	0	0	0	0	0
0x34	TIMx_CCR1	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	CCR1[15:0]
0x34	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x44	TIMx_BDTR	Res	Res	Res	BKBID	Res	BKDSRM	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	MOE	AOE	BKP	BKE	OSSR	OSSI	LOCK [1:0]	DT[7:0]
0x44	Reset value				0		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x48	TIMx_DCR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	DBL[4:0]					Res.	Res.	Res.	DBA[4:0]
0x48	Reset value																				0	0	0	0					0	0	0	0
0x4C	TIMx_DMAR	Res	Res	Res	Res	Res	Res	Res	Res.	Res	Res	Res	Res	Res	Res	Res	Res.	DMAB[15:0]
0x4C	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x50	TIM17_OR1																															TI1_RMP [1:0]
0x50	Reset value																															0
0x60	TIMx_AF1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	BKCOMP2P	BKCOMP1P	BKINP	Res.	Res.	Res.	Res.	Res.	Res.	BKCOMP2E	BKCOMP1E	BKINE

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x60	Reset value																					0	0	0							0	0	1
0x68	TIMx_TISEL	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	TI1SEL[3:0]
0x68	Reset value																													0	0	0	0

Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses.

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