14. Random number generator (RNG)

The RNG is a random number generator based on a continuous analog noise that provides a 16-bit value to the host when read.

14.1 Features

• • AHB slave peripheral
• • Deliver 16-bit random number produced by an analog generator
• • Minimum period of 1.25 µs (corresponding to 20 RNGCLK cycles) between two consecutive random numbers. This is automatically managed by a pulling spacer counter that adds wait-state on the AHB bus when reading occurs too closely to the previous one
• • Monitoring of the entropy of the RNG to flag abnormal behavior (generation of stable values or stable sequence of values)
• • 2 clock domains:
  • – RNGCLK: 16 MHz for the normalization and shifter (specific serial to 16-bit parallel conversion)
  • – HCLK: AHB clock (16 MHz, 32 MHz or 64 MHz) for the AHB interface
• • Can be disabled to reduce power consumption.

Power consumption and RNG

The internal free-running oscillators are quite power consuming. It is possible to stop them when the RNG is not used

• • After a PORESETn, the internal free-running oscillators are stopped by default to limit consumption
• • When the RNG clock tree is enabled through the RCC after a PORESETn, the oscillators are automatically restarted
• • If the SW enables the RNG clock tree through the RCC, it does not stop the internal oscillator. The SW has to first set the RNG_CR[2] = RNG_DIS to stop them.
• • On the other side, the SW has to restart them by clearing the RNG_DIS bit once the RNG clock tree is re-enabled.

14.2 RNG registers

Refer to Memory map and register boundary addresses for the register boundary addresses.

Note: Despite RNG registers being addressed through the AHB, only 32-bit accesses are allowed. Any 8-bit or 16-bit access generates an AHB error leading to a hard fault on Cortex-M0+.

14.2.1 RNG configuration register (RNG_CR)

Address offset: 0x00

Reset value: 0x0000

This register configures the RNG.

14.2.2 RNG status flag register (RNG_SR)

Address offset: 0x04

Reset value: 0x0000

This register provides status flags of the RNG.

14.2.3 RNG value register (RNG_VAL)

Address offset: 0x08

Reset value: 0xXXXX

This register delivers a 16-bit random value when read. After being read, this register delivers a new random value only after 20 cycles of RNGCLK. If the host performs a new read before the period has elapsed, the RNG inserts a wait-state on the AHB bus.

14.2.4 RNG register map

Table 75. RNG register map and reset values