11. DMA request multiplexer (DMAMUX)

11.1 Introduction

A peripheral indicates a request for DMA transfer by setting its DMA request signal. The DMA request is pending until it is served by the DMA controller which generates a DMA acknowledge signal and the corresponding DMA request signal is deasserted.

For simplicity, the functional description of the DMA request/acknowledge protocol and its associated control signals are abstracted in this document and globally named as DMA request lines. The DMA controller response signals are not shown in figures nor described in the text.

The DMAMUX request multiplexer allows routing a DMA request line between the peripherals and the DMA controller of the product. The routing function is ensured by a programmable multi-channel DMA request line multiplexer. Each channel selects a unique DMA request line.

11.2 DMAMUX main features

11.3 DMAMUX implementation

11.3.1 DMAMUX instantiation

DMAMUX is instantiated with the following hardware configuration parameters.

Table 28. DMAMUX instantiation

FeatureDMAMUX
Number of DMAMUX output request channels8
Number of DMAMUX request generator channels1
Number of DMAMUX request trigger inputs2
Number of DMAMUX synchronization inputs2
Number of DMAMUX peripheral request inputs25

11.3.2 DMAMUX mapping

The mapping of resources to DMAMUX is hardwired.

Table 29. DMAMUX map

DMA request MUX inputResourceDMA request MUX inputResource
1Reserved14LPUART_RX
2SPI3_RX15LPUART_TX
3SPI3_TX16ADC_CH0 (DS channel)
4Reserved17Reserved
5Reserved18TIM2_CH1
6Reserved19TIM2_CH2
7Reserved20TIM2_CH3
8I2C1_RX21TIM2_CH4
9I2C1_TX22TIM2_UP
10Reserved23TIM16_CH1
11Reserved24TIM16_UP
12USART_RX25TIM17_CH1
13USART_TX26TIM17_UP

11.4 DMAMUX functional description

11.4.1 DMAMUX block diagram

Figure 21. DMAMUX block diagram shows the DMAMUX block diagram.

DMAMUX block diagram showing internal architecture including AHB Slave Interface, Request Multiplexer with channels 0 to M, and synchronization inputs.

Figure 21. DMAMUX block diagram

The diagram illustrates the internal structure of the DMAMUX block. On the left, DMA requests from peripherals (labeled dmamux_req_inx ) enter through a multiplexer (inputs P, 1, 0). The output of this multiplexer is labeled dmamux_reqx . This signal enters the 'Request Multiplexer' block, which contains multiple channels (Channel 0, Channel 1, ..., Channel M). Each channel has its own control register (e.g., DMAMUX_C0CR, DMAMUX_C1CR, DMAMUX_CMCR). Inside each channel, there is a 'Channel Select' multiplexer (inputs P+N+2, N+2, N+1, N, ..., 1, 0) and a 'Sync' block. The outputs of the channels are labeled dmamux_req_outx and are connected to DMA controllers. Below the channels, there is a 'Sync' block with inputs S, ..., 1, 0, which are connected to synchronization inputs (labeled none ). The entire DMAMUX block is connected to a 32-bit AHB Bus via an 'AHB Slave Interface'. The interface has a signal labeled dmamux_hclk .

DMAMUX block diagram showing internal architecture including AHB Slave Interface, Request Multiplexer with channels 0 to M, and synchronization inputs.

The implementation assigns:

11.4.2 DMAMUX channels

A DMAMUX channel is a DMAMUX request multiplexer channel which may include, depending on the selected input of the request multiplexer.

A DMAMUX request multiplexer channel is connected and dedicated to one single DMA controller(s) channel.

Channel configuration procedure

The following sequence should be followed to configure both a DMAMUX x channel and the related DMA channel y:

  1. 1. Set and configure completely the DMA channel y, except enabling the channel y.
  2. 2. Set and configure completely the related DMAMUX y channel.
  3. 3. Activate the DMA channel y by setting the EN bit in the DMA y channel register.

11.4.3 DMAMUX request line multiplexer

The DMAMUX request multiplexer with its multiple channels ensures the actual routing of DMA request/acknowledge control signals, named as DMA request lines.

Each DMA request line is connected in parallel to all the channels of the DMAMUX request line multiplexer.

A DMA request is sourced from the peripherals.

The DMAMUX request line multiplexer channel x selects the DMA request line number as configured by the 8-bit DMAREQ_ID field in the DMAMUX_CxCR register.

Note: The null value in the field DMAREQ_ID corresponds to no DMA request line selected. A same non-null DMA_REQ_ID value shall not be programmed to different x and y DMAMUX request multiplexer channels (via DMAMUX1_CxCR and DMAMUX CyCR). It is not allowed to configure a same non-null DMAREQ_ID to two different channels of the DMAMUX request line multiplexer.

On top of the DMA request selection, the synchronization mode and/or the event generation may be configured and enabled, if required.

11.5 DMAMUX registers

Refer to the table about register boundary addresses for the DMAMUX base address. The registers can only be accessed by words (32-bits).

11.5.1 DMAMUX request line multiplexer channel x configuration register (DMAMUX_CxCR)

Address offset: 0x04 * x (x = 0 to 7)

Reset value: 0x0000 0000

31302928272625242322212019181716
RESERVED
1514131211109876543210
RESERVEDDMAREQ_ID[4:0]
rw
Bits 31:5Reserved, must be kept at reset value.
Bits 4:0DMAREQ_ID[4:0]: DMA request identification.
Selects the input DMA request. DMAMUX table about assignments of multiplexer inputs to resources.

11.5.2 DMAMUX register map

The following table summarizes the DMAMUX registers and reset values. Refer to the register boundary address table for the DMAMUX register base address.

Table 30. DMAMUX register map and reset values

OffsetRegister313029282726252423222120191817161514131211109876543210
0x000DMAMUX_C0CRRes.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.DMAREQ_ID[4:0]
Reset value00000
0x004DMAMUX_C1CRRes.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.DMAREQ_ID[4:0]
Reset value00000
0x008DMAMUX_C2CRRes.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.DMAREQ_ID[4:0]
Reset value00000
0x00CDMAMUX_C3CRRes.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.DMAREQ_ID[4:0]
Reset value00000
0x010DMAMUX_C4CRRes.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.DMAREQ_ID[4:0]
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OffsetRegister313029282726252423222120191817161514131211109876543210
0x010Reset value00000
0x014DMAMUX_C5CRRes.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.DMAREQ_ID[4:0]
Reset value00000
0x018DMAMUX_C6CRRes.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.DMAREQ_ID[4:0]
Reset value00000
0x01CDMAMUX_C7CRRes.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.DMAREQ_ID[4:0]
Reset value00000
0x020
0x3E8
ReservedRes.
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