8. System controller (SYSCFG)

The system controller is a set of registers (configuration, control and status) linked to system features of the STM32WB05xZ device.

8.1 SYSCFG main features

The system controller set of registers are mainly linked to:

• • Provide the JTAG_ID, Die ID and cut version
• • Manage the interrupts linked to GPIO feature
• • Manage the interrupts linked to the power controller (PWRC)
• • Manage the interrupt linked to MR_BLE reception and transmission sequences
• • Enable/disable I ² C fast-mode plus driving capability on some I/Os

Note: This peripheral is in the non-retained power domain so all settings done in the associated registers are lost after a Deepstop.

8.2 System controller registers

8.2.1 Die ID register (DIE_ID)

This register provides the device version and cut information.

Address offset: 0x00

Reset value: 0x0000 0120

8.2.2 JTAG ID register (JTAG_ID)

This register provides the JTAG ID of the STM32WB05xZ.

Note: The same information is also available through direct SWD access to test registers.

Address offset: 0x04

Reset value: 0x0202 8041

8.2.3 I2C Fast-Mode Plus pin capability control register (I2C_FMP_CTRL)

This register allows activating the fast-mode Plus driving capability on I ² C open-drain pads.

Address offset: 0x08

Reset value: 0x0000 0000

8.2.4 I/O interrupt detection type register (IO_DTR)

Address offset: 0x0C

Reset value: 0x0000 0000

8.2.5 I/O interrupt edge register (IO_IBER)

Address offset: 0x10

Reset value: 0x0000 0000

8.2.6 I/O interrupt polarity event register (IO_IEVR)

Address offset: 0x14

Reset value: 0x0000 0000

8.2.7 I/O interrupt enable register (IO_IER)

Address offset: 0x18

Reset value: 0x0000 0000

8.2.8 I/O Interrupt status and clear register (IO_ISCR)

Address offset: 0x1C

Reset value: 0x0000 0000

8.2.9 Power controller interrupt enable register (PWRC_IER)

This register allows control of the enable or mask on the interrupt sources of the power controller (PWRC) block.

Address offset: 0x20

Reset value: 0x0000 0000

8.2.10 Power controller interrupt status and clear register (PWRC_ISCR)

This register allows status checking, and clearing of the power controller (PWRC) block interrupt sources .

Address offset: 0x24

Reset value: 0x0000 0000

8.2.11 MR_BLE RX or TX sequence information detection type register (BLERXTX_DTR)

This register allows selecting the type of detection (level or edge) on RADIO_RX_SEQUENCE and RADIO_TX_SEQUENCE coming from the MR_BLE IP.

Address offset: 0x2C

Reset value: 0x0000 0000

8.2.12 MR_BLE RX or TX sequence information detection type register (BLERXTX_IBER)

This register is used to activate RADIO_RX_SEQUENCE and RADIO_TX_SEQUENCE signal detection on single edge or both edges when edge detection type is active.

Address offset: 0x30

Reset value: 0x0000 0000

8.2.13 MR_BLE RX or TX sequence information detection event register (BLERXTX_IEVR)

This register defines the polarity of the RADIO_RX_SEQUENCE and RADIO_TX_SEQUENCE signals detection.

Address offset: 0x34

Reset value: 0x0000 0000

8.2.14 MR_BLE RX or TX sequence information detection interrupt enable register (BLERXTX_IER)

This register defines the interrupt enable of the RADIO_RX_SEQUENCE and RADIO_TX_SEQUENCE signals.

Address offset: 0x38

Reset value: 0x0000 0000

8.2.15 MR_BLE RX or TX sequence information detection status and clear register (BLERXTX_ISCR)

This register allows checking the status and clear the interrupt linked to the RADIO_RX_SEQUENCE and RADIO_TX_SEQUENCE information provided by the MR_BLE IP.

Address offset: 0x3C

Reset value: 0x0000 0000

8.2.16 System controller register map

Refer to Table 3. STM32WB05xZ memory map and peripheral register boundary addresses for the system controller base address location in the STM32WB05xZ.

Table 19. SYSCFG register map and reset values