5. Power controller (PWRC)

The power controller block controls the analog supplies block and manages the startup, active and low-power phase of the device including the transition from one state to another.

5.1 Features

The power controller block supports the following features:

• • Low-power mode choice and entry/exit sequences
• • Flash memory power (ON/OFF) and the power-down sequence
• • RAM banks retention control
• • Power monitoring:
  • – POR/PDR reset on rising/falling VDDIO voltage
  • – Programmable voltage detector (PVD) monitoring of the VDDIO with programmable threshold or of an external analog input voltage (compared to the internal VBG)
• • I/Os pull-up/down during low-power mode
• • wakeup I/O configuration.

5.2 Power supply domains

The STM32WB05xZ embeds three power domains:

• • VDD33 aka VDDIO or VDD:
  • – the voltage range is between 1.7 V and 3.6 V,
  • – it supplies a part of the I/O ring, the embedded regulators and the system analog IPs such as power management block and embedded oscillators
• • VDD12o:
  • – always-on digital power domain
  • – this domain is generally supplied at 1.2 V during active phase of the device
  • – this domain is supplied at 1.0 V during low-power mode (Deepstop)
• • VDD12i:
  • – interruptible digital power domain
  • – this domain is generally supplied at 1.2 V during active phase of the device
  • – this domain is shut down during low-power mode (Deepstop)

The digital power supplies are provided by different regulators:

• – a main LDO(MLDO):
  • ◦ providing the 1.2 V from a 1.4-3.3 V input voltage
  • ◦ supplies both VDD12i and VDD12o when the device is active
  • ◦ is disabled during the low-power mode (Deepstop)
• – a low-power LDO(LPREG):
  • ◦ stays enabled during both active and low-power phases
  • ◦ provides a 1.0 V voltage
  • ◦ is not connected to the digital domain when the device is active
  • ◦ is connected to the VDD12o domain during low-power mode (Deepstop)
• – a dedicated LDO (RFLDO) to provide a 1.2 V to the analog RF block.

An embedded SMPS step-down converter is available (inserted between the external power and the LDOs).

Figure 4. Power supply domain overview shows an overview of the different regulators and connections between the power supply domains.

Figure 4. Power supply domain overview

5.3 Power voltage supervisor

The BlueNRG-LPS devices embed several power voltage monitorings:

• • Power-on reset (POR) / power-down reset (PDR) / Brownout Reset (BOR)
• • Power voltage detector (PVD)

5.3.1 Power-on reset POR / power-down reset (PDR) / Brownout Reset (BOR)

The device has an integrated power-on reset / power-down reset, coupled with a Brownout Reset circuitry. During the power-on, the device remains in reset mode as long as \( V_{DDIO} \) is below a \( V_{POR} \) threshold (typically 1.60 V).

During power-down, the PDR puts the device under reset when the supply voltage ( \( V_{DD} \) ) drops below the \( V_{PDR} \) threshold (around 20 mV below \( V_{POR} \) ). The PDR feature is always enabled.

Figure 5. Power-on reset/power-down reset waveform

With typical values as follows:

• • \( V_{POR} \) : 1.60 V
• • Hysteresis: 20 mV (so \( V_{PDR} \) : 1.58 V)
• • \( T_{TEMPO} \) : 600 \( \mu \) s

The Brownout Reset (BOR) generates a device reset when the power supply (VDD) drops under \( V_{PDR} \) .

This feature is always active except during shutdown mode where the software can decide to enable it or not (through PWRC_CR1.ENSDNBOR bit).

5.3.2 Power voltage detection (PVD)

The PVD can be used to monitor:

• • the VDDIO:
  • – an external analog signal is compared to an internal VBGP (at 1.0 V) voltage
  • – the feature is selected through PWRC_CR2.PVDLS[2:0] bit field
• • an external analog input signal:
  • – an external analog signal is compared to an internal VBGP (at 1.0 V) voltage
  • – the feature is selected through PWRC_CR2.PVDLS[2:0] bit field

The PVD can be enabled or disabled through the PWRC_CR2.PVDE bit.

When the feature is enabled and the PVD measures a voltage below the comparator, a status flag is raised in the SYSCFG block that can generate an interrupt to the CPU if unmasked (see Section 8.2.10: Power controller interrupt status and clear register (PWRC_ISCR) ).

5.4 Operating modes

The STM32WB05xZ supports 3 main operating modes:

• • Run mode
• • Deepstop mode
• • Shutdown mode

The transition from one mode to another is managed through a PMU state machine.

5.4.1 Run mode

In Run mode:

• • both regulators (MLDO and LPREG) are enabled
• • MLDO provides the power supply for both VDD12i and VDD12o
• • System clock and bus clock are running
• • the CPU and the radio can be used

The power consumption may be reduced by gating the clock of the unused peripherals through the RCC clock enable registers (see Section 6.6.18: RCC register map ).

Figure 6. Power regulators and SMPS configuration in mode shows the regulators and SMPS configuration in mode with a product with only 24 Kbytes of RAM.

Figure 6. Power regulators and SMPS configuration in mode

5.4.2

Deepstop mode

The Deepstop is the only low-power mode of the STM32WB05xZ in order to restart from a saved context environment and go on running the application at wakeup.

The conditions to enter Deepstop mode are:

• • Radio (MR_BLE) is sleeping
• • CPU is sleeping (WFI with SLEEPDEEP information active)
• • No unmasked wakeup sources are active (including those from a previous wakeup sequence for which the software did not clear the associated flag after wakeup)
• • System is clocked on RC64MPLL (HSI or pll locked mode)
• • PWRC_CR1.LPMS bit is equal to 0
• • If PWRC_CR1.APC = 1, the I/O pull-ups/pull-downs are controlled by the PWRC_PUCRx/PWRC_PDCRx registers.
• • Set GPIORET bit to enable GPIOs configuration retention for all I/Os (If DEEPSTOP2 bit is set, GPIORET must be reset, because SWJTAG must be available).

Note: If the MR_BLE is not used at all by the SoC (or not yet started), the following steps need to be performed after any reset to allow low-power modes (Deepstop and Shutdown):

• • Enable the MR_BLE clock by setting the RCC_APB2ENR.MRBLEEN bit
• • Set the BLUE_SLEEP_REQUEST_MODE.FORCE_SLEEPING bit inside the wakeup block of the MR_BLE to have the MR_BLE IP requesting low-power mode to the SoC
• • Gate again the MR_BLE clock by clearing the RCC_APB2ENR.MRBLEEN bit

In Deepstop mode:

• • the system and bus clocks are stopped as the RC64MPLL block is OFF
• • the VDD12i power domain is switched off
• • the VDD12o power domain is ON and supplied at 1.0 V
• • the RAM0 bank is kept in retention
• • if PWRC_CR1.APC = 1, the I/Os pull-up/down are controlled by the PWRC_PUCRx/PWRC_PDCRx during Deepstop mode
• • the other RAM banks are in retention or not, depending on software choice in PWRC_CR2 register
• • the slow clock can be running or stopped, depending on the software configuration present before Deepstop entry:
  • – ON or OFF
  • – LSE or LSI source
• • RTC, IWDG and LPUART stay active (if enabled and one slow clock source is ON)
• • MR_BLE wakeup block including its timer stays active (if enabled and one slow clock source is ON)
• • All I/Os configurations can be retained and are able to be configured:
  • – In output:
    1. 1. driving either a static low or high level if Section 7.4: GPIO registers properly programmed
    2. 2. driving the slow clock information RCC_LCO on PA10 only if LCOEN bit is set
    3. 3. driving the RTC_OUT on PA8 only if Section 19.6.3: RTC control register (RTC_CR) properly programmed and AF1 selected
  • – In input if Section 7.4: GPIO registers is properly programmed

A version of Deepstop mode called DEEPSTOP2 has been implemented to emulate Deepstop mode without losing the debugger connection and breakpoints or watchpoints.

• • This variant can be selected by setting the PWRC_DBGR.DEEPSTOP2 bit
• • In this case, the Deepstop mode sequence (entry and exit) is done without shutting down the VDD12i power domain

Possible wakeup sources:

• • the MR_BLE block is able to generate two events to wake up the system through its embedded wakeup timer running on slow clock:
  • – BLE IP wakeup time is reached
• • the RTC is able to generate a wakeup event
• • the IWDG is able to generate a reset event
• • the LPUART is able to generate a wakeup event
• • All I/Os are able to wake up the system.

After wakeup from Deepstop, all the I/Os are in retention mode (except PA2 and PA3 in order to have SWD available again); if DBGRET bit was set, before entering Deepstop mode, then at wakeup also PA2 and PA3 are in retention mode and SWD is not available. To change I/Os configuration, when exiting Deepstop, it is necessary to reset GPIORET bit after having re-configured GPIO registers through Section 7.4: GPIO registers (this GPIO configuration can be the same before entering Deepstop, or a new one). At wakeup, the hardware resources located in the VDD12i power domain are reset, the CPU reboots. The wakeup reason is visible in a PWRC register (see Section 5.7.5: Status register 1 (PWRC_SR1) for details).

Figure 7. Power regulators and SMPS configuration in Deepstop mode shows the regulators and SMPS configuration in Deepstop mode, with a configuration requesting retention only on RAM0 and RAM1 banks.

Figure 7. Power regulators and SMPS configuration in Deepstop mode

Note: Strikethrough text indicates that the feature is OFF in Deepstop mode.

5.4.3 Shutdown mode

Shutdown mode is the least power consuming mode.

The conditions to enter Shutdown mode are the same conditions needed to enter Deepstop mode except that the PWRC_CR1.LPMS bit must be equal to 1 and the PWRC_DBGR.DEEPSTOP2 bit must be maintained equal to 0. In Shutdown mode:

• • The system is powered down as both regulators are OFF (so both VDD12i and VDD12o power domains are OFF)
• • Only the VDDIO power domain is ON
• • All clocks are OFF (system and slow clock tree) as RC64MPLL, LSI and LSE are OFF,
• • If PWRC_CR1.APC = 1, the I/O pull-ups/pull-down are controlled by the PWRC_PUCRx/PWRC_PDCRx registers
• • The only wakeup source is a low pulse on the RSTN pad

A Shutdown exit is similar to a POR startup of the board. The associated reset reason is the PORRSTF flag (see Section 6.6.15: V33 reset status register (RCC_CSR) for reset reason flag detail).

The BOR feature may be enabled or disabled during Shutdown through the PWRC_CR1.ENSDNBOR bit.

Figure 8. Power regulators and SMPS configuration in Shutdown mode shows the regulators and SMPS configuration in Shutdown mode, configured with the BOR reset disabled.

Figure 8. Power regulators and SMPS configuration in Shutdown mode

Note: Strikethrough text indicates that the feature is OFF in Shutdown mode.

5.4.4 Operating mode transition management

The PWRC block manages the switches from an operating mode to another through a state machine.

Figure 9. PWRC state machine for operating modes transition

stateDiagram-v2
    [*] --> START
    START --> RUN : RESETn
    RUN --> SHUTDOWN : CSTOP & RF OFF & CR1.LPMS = SHUTDOWN
    RUN --> DEEPSTOP : CSTOP & RF OFF & CR1.LPMS = DEEPSTOP
    DEEPSTOP --> RUN : wakeup
    DEEPSTOP --> SHUTDOWN : CSTOP & RF OFF & CR1.LPMS = SHUTDOWN
  

5.5 SMPS step-down regulator

The STM32WB05xZ SMPS is a 20 mA output step-down SMPS (switch mode power supply) converter. The SMPS output voltage can be programmed from 1.2 V to 1.90 V. It is internally clocked at 4 MHz or 8 MHz. The SMPS can be in different configurations:

• • ON:
  • – the \( V_{FBSD} \) pin of the SMPS outputs a regulated voltage (from 1.2 V to 1.9 V)
  • – the SMPS needs a clock
• • OFF:
  • – the \( V_{FBSD} \) pin has to be forced externally with VDDIO
  • – the SMPS does not need a clock
• • PRECHARGE (aka BYPASS):
  • – the \( V_{FBSD} \) pin outputs the VDDIO without regulation
  • – the SMPS does not need a clock
  • – the SMPS current can be limited programming control register 5 (PWRC_CR5)
• • OPEN:
  • – the \( V_{FBSD} \) pin is floating
  • – the SMPS does not need a clock

Except for the configuration SMPS OFF, an L/C BOM must be present on the board and connected to the \( V_{FBSD} \) pad (see Figure 10. Power supply configuration).

Figure 10. Power supply configuration

The user must configure the PWRC_CR5.SMPSBOMSEL[1:0] according to the BOM implemented on their board. The value to program is indicated in Table 11. SMPS BOM information.

Table 11. SMPS BOM information

The SMPS is managed by the PWRC through a state machine shown in Figure 11. PWRC SMPS state machine overview.

Figure 11. PWRC SMPS state machine overview

After a power-on reset sequence, the SMPS FSM always goes up to Run state. From there, the SMPS FSM can stay in three states (others are transition states):

• Run:
  • the SMPS is ON in a Run mode
  • the SMPS clock is running
  • the VFBSD is regulated and voltage amplitude is the one programmed in the PWRC_CR5.SMPSLVL bit field
  • the L/C BOM is present on the board and is connected on the VFBSD pad of the STM32WB05xZ (see Figure 10. Power supply configuration)

• • NOSMPS (if the software configures PWRC_CR5.NOSMPS=1):
  • – the SMPS is OFF
  • – the SMPS clock is stopped
  • – the \( V_{FBSD} \) is directly connected to the VDDIO through the \( V_{FBSD} \) pad of the STM32WB05xZ (see Figure 10. Power supply configuration )
  • – the PWRC does not control any specific sequencing on the SMPS during low-power entry/exit phases
• • PRECHARGE aka BYPASS (if the software configures PWRC_CR5.SMPSFBYP=1):
  • – the SMPS is ON in a precharge mode
  • – the SMPS clock is stopped
  • – the \( V_{FBSD} \) is the VDDIO voltage crossing the SMPS block
  • – the PWRC does not control any specific sequencing on the SMPS during low-power entry/exit phases
  • – this mode is compliant with an L/C BOM connected on the \( V_{FBSD} \) pad of the STM32WB05xZ

When the device enters Deepstop mode, the PWRC automatically switches the SMPS from Run to Deepstop mode which can be:

• – if PWRC_CR5.SMPSLPOPEN = 0: SMPS output is the VDDIO (as in PRECHARGE FSM state)
• – if PWRC_CR5.SMPSLPOPEN = 1: the SMPS output is floating

5.6 I/O pull-ups/pull-downs during low power mode

When PWRC_CR1.APC is set (default configuration), the pull-up/pull-down of the IOs is controlled by the PWRC_PUCRx and PWRC_PDCRx registers of the PWRC block, instead of GPIOx_PUPDR register of the GPIO block. This feature avoids glitches on the lines by keeping the same pull-up/pull-down configuration during all the supported operating modes.

5.7 PWRC registers

All PWRC APB registers are only 16-bit registers. The 16 most-significant bits are always stuck to 0.

5.7.1 Control register 1 (PWRC_CR1)

This register controls the BOR in Shutdown, the low-power mode selection and the IO control owner.

Address offset: 0x00

Reset value: 0x0000 0114

Note: It is mandatory to ensure that PWRC_DBGR.DEEPSTOP2 bit is reset when LPMS bit is set before entering in Shutdown.

5.7.2 Control register 2 (PWRC_CR2)

Address offset: 0x04

Reset value: 0x0000 0000

Note: it is mandatory to ensure GPIORET bit is set before entering Deepstop unless DEEPSTOP2 bit is set.

5.7.3 Control register 3 (PWRC_CR3)

This register manages the selection of the wakeup sources to get out of Deepstop mode.

Note: All wakeup sources are disabled by default after reset.

Address offset: 0x08

Reset value: 0x0000 0000

5.7.4 Control register 4 (PWRC_CR4)

This register manages the polarity for the I/Os wakeup sources to get out of Deepstop mode.

Note: The wakeup events are edge detection only, not level detection.

Address offset: 0x0C

Reset value: 0x0000 0000

5.7.5 Status register 1 (PWRC_SR1)

This register provides the information concerning which source woke up the device after a Deepstop.

Address offset: 0x10

Reset value: 0x0000 0000

5.7.6 Status register 2 (PWRC_SR2)

This register provides some status flags related to the power voltage detector and the SMPS blocks.

Address offset: 0x14

Reset value: 0x0000 -306

1. • 1: SMPS regulator is in PRECHARGE mode (VSMPS connected to VDDIO)

5.7.7 Control register 5 (PWRC_CR5)

This register is used to configure the SMPS.

Address offset: 0x1C

Reset value: 0x0000 6014

5.7.8 I/O port A pull-up control register (PWRC_PUCRA)

This register is used to control the pull-up for the PA0 to PA15 I/O when the PWRC_CR1.APC bit is set.

Caution: If both pull-up and pull-down are enabled in the PWRC_PUCRA and PWRC_PDCRA registers for an I/O, then pull-down is applied.

The user must take care to disable the pull-on I/O programmed in analog mode.

Address offset: 0x20

Reset value: 0x0000 0F07

5.7.9 I/O port A pull-down control register (PWRC_PDCRA)

This register is used to control the pull-down for the PA0 to PA15 I/O when the PWRC_CR1.APC bit is set.

Caution: If both pull-up and pull-down are enabled in the PWRC_PUCRA and PWRC_PDCRA registers for an I/O, then pull-down is applied.

The user must take care to disable the pull-on I/O programmed in analog mode.

Address offset: 0x24

Reset value: 0x0000 0008

5.7.10 I/O port B pull-up control register (PWRC_PUCRB)

This register is used to control the pull-up for the PB0 to PB15 I/O when the PWRC_CR1.APC bit is set.

Caution: If both pull-up and pull-down are enabled in the PWRC_PUCRA and PWRC_PDCRA registers for an I/O, then pull-down is applied.

The user must take care to disable the pull-on I/O programmed in analog mode.

Address offset: 0x28

Reset value: 0x0000 F0FF

5.7.11 I/O port B pull-down control register (PWRC_PDCRB)

This register is used to control the pull-down for the PB0 to PB15 I/O when the PWRC_CR1.APC bit is set.

Caution: If both pull-up and pull-down are enabled in the PWRC_PUCRA and PWRC_PDCRA registers for an I/O, then pull-down is applied.

The user must take care to disable the pull-on I/O programmed in Analog mode.

Address offset: 0x2C

Reset value: 0x0000 F0FF

5.7.12 Control register 6 (PWRC_CR6)

This register manages the selection of the wakeup sources to get out of Deepstop mode.

Note: All wakeup sources are disabled by default after reset.

Address offset: 0x30

Reset value: 0x0000 0000

5.7.13 Control register 7 (PWRC_CR7)

This register manages the polarity for the I/Os wakeup sources to get out of Deepstop mode.

Note: The wakeup events are only edge detection, not level detection.

Address offset: 0x34

Reset value: 0x0000 0000

5.7.14 Status register 3(PWRC_SR3)

This register provides some information about which source woke up the device after a Deepstop.

Address offset: 0x38

Reset value: 0x0000 0000

5.7.15 Debug register (PWRC_DBGR)

This register is used for debug features.

Address offset: 0x84

Reset value: 0x0000 0000

5.7.16 Extended status and reset register (PWRC_EXTSRR)

This register provides flags about Bluetooth activity start and Deepstop sequence occurrence or not.

Address offset: 0x88

Reset value: 0x0000 0000

5.7.17 PWRC register map

Refer to Table 3. STM32WB05xZ memory map and peripheral register boundary addresses for the PWRC base address location in the STM32WB05xZ.

Note: All the PWRC registers are retained during Deepstop mode. The grey cells indicate the bit fields located in the VDD33 power domain. This implies the associated feature is applied even during Shutdown state (but are lost at Shutdown mode exit as a PORESETn is generated).

Table 12. PWRC register map

5.8 Programmer model

5.8.1 Reset reason management

The CPU has many reasons to be reset and executes its reset handler. Table 13. Flags versus CPU reboot reason provides an overview of the flags that can help the embedded software to get the root cause of the CPU reset.

Table 13. Flags versus CPU reboot reason

If the reboot reason is a wakeup from Deepstop, then the wakeup source(s) can be read in the PWRC_SR1 register as shown in Table 14. Wakeup reason flags.

Table 14. Wakeup reason flags

Note: If several (enabled) wakeup events occur, several bits are high in the PWRC_SR1. The wakeup flags are set as soon as a wakeup event (enabled in PWRC_CR3 register) occurs; the associated flag is set in the PWRC_SR1 register even if the device is in active mode or in the sleep exit sequence (initiated by another wakeup source).
Caution: Those flags have to be cleared by software knowing a Deepstop entry sequence cannot happen if a wakeup flag is already active when the system requests a Deepstop mode.

5.8.2 SMPS output level re-programming

The SMPS output voltage cannot be modified on-the-fly when the SMPS is in use for more than one step. When the software needs to re-program the SMPS output voltage to another value, the following sequence must be respected:

• • Set PWRC_CR5.SMPSBYP =1
• • Wait for PWRC_SR2.SMPSRDY =0
• • Program the new targeted value in PWRC_CR5.SMPSLVL[3:0]
• • Clear PWRC_CR5.SMPSBYP =0
• • Wait for PWRC_SR2.SMPSRDY =1

Caution: This sequence must be launched when no radio activity only / RF transfer is on-going.