4. I/O operating modes

The STM32WB05xZ device proposes up to 20 programmable I/Os (on all packages).

Each I/O can be programmed in several modes:

• • Input mode
• • General purpose output mode
• • Alternate function
• • Analog mode (when available Table 9. I/O analog feature mapping )

The STM32WB05xZ device supports six alternate modes called AFx (x = 0 to 4 and 6). The configuration of each I/O for those alternate modes is detailed in Table 7. GPIO alternate options AF0, AF1 and AF2 modes and Table 8. GPIOs AF3, AF4 and AF6 modes .

Note: I/Os features presented in Table 7. GPIO alternate options AF0, AF1 and AF2 modes and Table 8. GPIOs AF3, AF4 and AF6 modes are valid only when the associated I/O is programmed as alternate function.

Refer to Section 7: General-purpose I/O (GPIO) for more details on all configurations.

The number of I/Os available in the STM32WB05xZ device depends on the package:

• • 20 I/Os in VFQFPN32
• • 20 I/Os in WLCSP36

Type acronyms correspond to:

• • I: input
• • O: output
• • I/O: input output
• • OD: open drain

Table 7. GPIO alternate options AF0, AF1 and AF2 modes

1. This I/O is able to be configured in open-drain.

2. This I/O is shared with RCC_OSC32_OUT (low speed clock oscillator pin).

3. This I/O is shared with RCC_OSC32_IN (low speed clock oscillator pin).

Table 8. GPIOs AF3, AF4 and AF6 modes

1. 1. This I/O is able to be configured in open-drain.
2. 2. This I/O is shared with RCC_OSC32_OUT (low speed clock oscillator pin).
3. 3. This I/O is shared with RCC_OSC32_IN (low speed clock oscillator pin).

Note: Concerning the ADC block present in the STM32WB05xZ device:

• • The eight ADC channels are available on PA2, PA3, PB0, PB1, PB2, PB3, PB4, PB5

The ADC features on those pins are available if the associated pin is configured in analog mode (see Section 7: General-purpose I/O (GPIO) for more details)

The Table 9. I/O analog feature mapping shows the mapping associated to analog configuration (for pins which can support analog mode).

Table 9. I/O analog feature mapping

1. N/A means not applicable as the associated I/O does not support analog option.

Table 10. I/O additional function mapping

1. The additional functions for LSE oscillator are obtained by setting the RCC_CR.LSEON bit in the RCC registers. Then the PB12 and PB13 are forced by hardware to manage the LSE through RCC_OSC32_OUT/RCC_OSC32_IN whatever the selected mode in the associated GPIOx_MODER register, but if PWRC_CR1.APC bit is set, it is necessary to disable PUB12, PUB13, PDB12, PDB13 in PWRC registers.

Note: For the additional functions like Wakeup I/O, LSE oscillator, RCC_LCO configure the required function in the related PWRC, RCC, RTC registers. These functions have priority over the configuration in the standard GPIO registers.