1. Documentation conventions
1.1 General information
For information on the Arm ® Cortex ® -M0+ core, refer to the Cortex ® -M0+ technical reference manual, available from the www.arm.com website.
For information on Bluetooth ® refer to www.bluetooth.com website.
Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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1.2 List of abbreviations for registers
The following abbreviations are used in register descriptions:
Table 1. List of abbreviations for registers
| read/write (rw or R/W) | Software can read and write to these bits |
| read-only (r or R) | Software can only read these bits |
| write-only (w or W) | Software can only write to this bit. Reading the bit returns the reset value |
| read/write-once (RWOnce) | Software can read these bits but write is only allowed once |
| read/clear (rc_w1 or RWC1) | Software can read as well as clear this bit by writing 1. Writing '0' has no effect on the bit value |
| read/clear (rc_w0 or RWC0) | Software can read as well as clear this bit by writing 0. Writing '1' has no effect on the bit value |
| read/clear by read (rc_r or RC) | Software can read this bit. Reading this bit automatically clears it to '0'. Writing '0' has no effect on the bit value |
| read/set (rs or RWS1) | Software can read as well as set this bit. Writing '0' has no effect on the bit value |
| read-only write trigger (rt_w or RWH) | Software can read this bit. Writing '0' or '1' triggers an event but has no effect on the bit value |
| toggle (t or RWT1) | Software can only toggle this bit by writing '1'. Writing '0' has no effect |
| Reserved (Res.) | Reserved bit, must be kept at reset value |
1.3 Glossary
This section gives a brief definition of the abbreviations used in this document:
The SoC integrates the SWD debug port (SWD-DP) which provides a 2-pin (clock and data) interface based on the serial wire debug (SWD) protocol.
- • Word: data/instruction of 32-bit length
- • Half word: data/instruction of 16-bit length
- • Byte: data of 8-bit length
- • Double word: data of 64-bit length
- • AHB: advanced high-performance bus
- • APB: advanced peripheral bus
- • CPU: refers to the Cortex ® -M0+core
1.4 Availability of peripherals
For availability of peripherals and their number across all sales types, refer to the particular device datasheet.
1.5 Acronyms
Table 2. Acronyms
| Acronym | Description |
|---|---|
| ADC | Analog to digital converter |
| AES | Advanced encryption standard hardware accelerator |
| AGC | Automatic gain control |
| AoA | Angle of arrival |
| AoD | Angle of departure |
| AHB | Advanced high-performance bus |
| APB | Advanced peripheral bus |
| BOR | Brown-out reset |
| BPU | Breakpoint unit (ARM debug component) |
| CPU | Central processor unit |
| CRC | Cyclic redundancy check |
| CTE | Constant tone extension |
| CTI | Cross trigger interface (ARM debug component) |
| DBG | DeBuG |
| DMA | Direct memory access |
| DMAMUX | Direct memory access multiplexer |
| DWT | Data watchpoint and trace (ARM debug component) |
| FSM | Finite state machine |
| GPIO | General purpose input output |
| HSE | High speed external clock oscillator |
| HSI | High speed internal clock oscillator |
| HW | Hardware |
| I2C | Inter integrated circuit (communication standard) |
| I2S | Inter integrated (communication standard) |
| IRQ | Interrupt request |
| ITM | Instrumentation trace macrocell (ARM debug component) |
| IWDG | Independent watchdog |
| JTAG | Joint test access group (test interface standard) |
| LDO | Low-dropout |
| LP | Low power |
| LPUART | Universal asynchronous receiver transmitter (communication standard) |
| LSB | Least significant byte |
| LSE | Low speed external clock oscillator |
| LSI | Low speed internal clock oscillator |
| MCU | Micro controller unit |
| Acronym | Description |
|---|---|
| MPU | Memory protection unit |
| MR_BLE | Radio sub-system |
| MSB | Most significant byte |
| NVIC | Nested vector interrupt controller |
| OBL | Option byte loading |
| OSC | Oscillator |
| OTP | One time programmable |
| PA | Power amplifier |
| PDR | Power-down reset |
| PDM | Pulse density modulation |
| PKA | Public key accelerator |
| PLL | Phase locked loop |
| POR | Power-on reset |
| PVD | Programmable voltage detector |
| PVM | Peripheral voltage monitoring |
| PWR | Power controller |
| RC | Resistor capacitor oscillator |
| RCC | Reset and clock controller |
| RF | Radio frequency |
| RF2G4 | Analog radio block used with the MR_BLE IP |
| RNG | True random number Generator |
| ROM | Read-only memory |
| RRM | Radio resource manager |
| RTC | Real-time clock |
| Rx | Reception |
| SMPS | Switch mode power supply |
| SoC | System-on-chip |
| SPI | Serial peripheral interface (communication standard) |
| SRAM | Static random access memory |
| SW | Software |
| SWD | Single-wire debug |
| SWJ-DP | Single-wire joint test access group - debug port (ARM debug component) |
| SYSCFG | System configuration |
| TIM | Timer |
| Tx | Transmission |
| UDRA | Unified direct register access (part of the RRM block) |
| USART | Universal synchronous asynchronous receiver transmitter (communication standard) |
| V bat | Battery voltage. Voltage used for the part of the design that is always on |
| VCO | Voltage controlled oscillator |
| VREF | Voltage reference |
| WFI | Wait for instruction (ARM instruction entering low-power mode) |
| Acronym | Description |
|---|---|
| WKUP | Wakeup |
| WRP | Write protection |
| WWDG | Window watchdog |
Note: For information about MR_BLE/Radio sub-system refer to Section 25: Radio IP.