41. Debug support (DBG)

41.1 DBG introduction and main features

A comprehensive set of debug features is provided to support software development and system integration:

• • Breakpoint debugging of the CPU core in the system
• • Code execution tracing
• • Software instrumentation

The debug features can be controlled via a JTAG/serial-wire debug access port, using industry-standard debugging tools. A trace port allows data to be captured for logging and analysis.

The following debug features are based on Arm ^® CoreSight ^™ components.

• • General features:
  • – SWJ-DP: JTAG/serial-wire debug port
  • – AP access ports
  • – ROM tables
  • – System control space (SCS)
  • – Breakpoint unit (BPU)
  • – Data watchpoint and trace unit (DWT)
  • – Instrumentation trace macrocell (ITM)
  • – Embedded trace macrocell (ETM)
  • – Trace port interface unit (TPIU)
  • – Cross-trigger interface (CTI)

The debug features are accessible by the debugger via the debug AP access ports.

Additional information can be found in the Arm ^® documents referenced in Section 41.12 .

The following debug features are based on STMicroelectronics components

• • System debug features:
  • – Debug MCU controller (DBGMCU).

41.2 DBG functional description

41.2.1 DBG block diagram

Figure 379. Block diagram of debug support infrastructure

41.2.2 DBG pins and internal signals

Table 400. JTAG/serial-wire debug port pins

1. Debug access port JTDO and trace port TRACESWO are multiplexed on a single device GPIO pin.

Table 401. Single-wire trace port pins

1. TRACESWO is multiplexed with JTDO. This means that single-wire trace is only available when using the serial-wire debug interface, and not when using JTAG.

41.2.3 DBG reset and clocks

The debug port (SWJ-DP) is reset by a power-on reset and when waking up from Standby mode.

The debugger supplies the clock for the debug port via the debug interface pin JTCK/SWCLK. This clock is used to register the serial input data in both serial-wire and JTAG modes, as well as to operate the state machines and internal logic of the debug port. This clock must therefore continue to toggle for several cycles after the end of an access, to ensure that the debug port returns to the idle state.

The SWJ-DP contains an asynchronous interface to the DAPCLK domain, which covers the rest of the SWJ-DP.

The DAPCLK is a gated version of the CPU bus clock hclk1.

The DAPCLK domain is enabled by the debugger using the CDBGPWRUPREQ bit in the DP_CTRLSTATR register. The clock must be enabled before the debugger can access any of the debug features on the device. The availability of the clock is reflected in the CDBGPWRUPACK bit in the DP_CTRLSTATR register. DAPCLK is disabled at power-up, after OBL, and after a wake-up from Standby. DAPCLK must be disabled when the debugger is disconnected to avoid wasting energy.

The debug components included in the processor are clocked with the processor core clock hclk1.

41.2.4 DBG power domains

The debug components are located in the core power domain. This means that debugger connection is not possible in Standby modes. To avoid losing the connection when the device enters Standby mode, the power to the core can be maintained by setting a bit in the debug unit (DBGMCU). This also keeps the processor clocks active and hold off the reset, so that the debug session is maintained.

41.2.5 DBG low-power modes

The devices include power-saving features that allow the core power domain to be switched off or clocks to be stopped when not required. If the power is switched off, all the debug components are inaccessible to the debugger. When the core is not clocked, all the debug components except the DBGMCU are inaccessible to the debugger. To avoid this, low-power mode emulation is implemented. If emulation is enabled, the device still enters low-power mode, but the clocks and power are maintained. In other words, the device

behaves similarly to when it is in low-power mode, but the debugger does not lose the connection to the CPU.

The low-power emulation mode is programmed in the DBGMCU. For more information refer to Section 41.13.4: Low-power mode emulation .

41.2.6 Security

The trace and debug components allow a high degree of access to the processor and system during product development. In order to protect user code and ensure that the debug features cannot be used to alter or compromise the normal operation of the finished product, these features can be disabled or limited in scope. For example, secure software debug and trace can be disabled without preventing the debug of nonsecure code.

The following authentication signals are used by the system to determine which debug features are enabled or disabled:

• • dbgen : global enable for all debug features
  • 0: All debug features are disabled.
  • 1: Debug features in nonsecure state are enabled. Debug features in secure state are dependent on the state of the spiden signal.
• • spiden : enables debug in secure state when dbgen = 1.
  • 0: Debug features are disabled in secure state.
  • 1: Debug features are enabled in secure state.
• • niden : enables trace and performance monitoring (noninvasive debug).
  • 0: Trace generation is disabled.
  • 1: Trace generation in nonsecure state is enabled. Trace generation in secure state is dependent on the state of the spniden signal.
• • spniden : enables trace and performance monitoring in secure state when niden = 1.
  • 0: Trace generation is disabled in secure state.
  • 1: Trace generation is enabled in secure state.

For detailed information on the behavior of each component according to the state of the authentication signals, refer to the relevant component section or to the relevant Arm technical documentation.

The state of the signals is set according to the readout protection (RDP) level (see Section 7.6.2: Readout protection (RDP) ), as shown in the table below:

Table 403. Authentication signal states

Note: Security features are only relevant when the option bit TZEN = 1. If security features are disabled, the authentication signals are still set according to the RDP level, but since the processor and all memories are nonsecure, spniden and spiden are redundant.

The state of the authentication signals can be read from DAUTHSTATUS register in the system control space (SCS) of the Cortex-M33.

The debugger access to secure memory (when permitted) must be performed using secure transactions on the debug AHB, that is, with PROT[6] set in AP_CSWR.

The debugger access is disabled while the processor is booting from system flash memory (RSS), whatever the RDP level, if security features are enabled (TZEN = 1).

41.2.7 Serial-wire and JTAG debug port

The serial-wire and JTAG debug port (SWJ-DP) is a CoreSight component that implements an external access port for connecting debugging equipment.

The two following types of interface can be configured:

• • A 5-pin standard JTAG interface (JTAG-DP)
• • A 2-pin (clock + data) serial-wire debug port (SW-DP)

The two modes are mutually exclusive since they share the same I/O pins.

By default the JTAG-DP is selected after a system or a power-on reset. The five I/O pins are configured by hardware in debug alternative function mode.

The SWJ-DP incorporates pull-up resistors on JTDI, JTMS/SWDIO and nJTRST, as well as a pull-down resistor on JTCK/SWCLK.

A debugger can select the SW-DP by transmitting the following serial data sequence on JTMS/SWDIO:

... (50 or more ones) ..., 0, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 1, ... (50 or more ones) ...
JTCK/SWCLK must be cycled for each data bit.

In SW-DP mode, the unused JTAG pins JTDI, JTDO, and nJTRST can be used for other functions.

Note: All SWJ port I/Os can be reconfigured to other functions by software but debugging is no longer possible.

41.2.8 JTAG debug port

The JTAG debug port (JTAG-DP) implements a TAP state machine (TAPSM) based on IEEE Std 1149.1-1990. The state machine controls two scan chains, one associated with an instruction register (IR) and the other one with a number of data registers (DR).

Figure 380. JTAG TAP state machine

stateDiagram-v2
    [*] --> Test-Logic-Reset : JTMS=1
    Test-Logic-Reset --> Run-Test/Idle : JTMS=0
    Run-Test/Idle --> Select-DR-Scan : JTMS=1
    Run-Test/Idle --> Select-IR-Scan : JTMS=1
    Select-DR-Scan --> Capture-DR : JTMS=0
    Select-IR-Scan --> Capture-IR : JTMS=0
    Capture-DR --> Shift-DR : JTMS=0
    Capture-IR --> Shift-IR : JTMS=0
    Shift-DR --> Shift-DR : JTMS=0
    Shift-DR --> Exit1-DR : JTMS=1
    Shift-IR --> Shift-IR : JTMS=0
    Shift-IR --> Exit1-IR : JTMS=1
    Exit1-DR --> Pause-DR : JTMS=0
    Exit1-IR --> Pause-IR : JTMS=0
    Pause-DR --> Pause-DR : JTMS=0
    Pause-DR --> Exit2-DR : JTMS=1
    Pause-IR --> Pause-IR : JTMS=0
    Pause-IR --> Exit2-IR : JTMS=1
    Exit2-DR --> Update-DR : JTMS=1
    Exit2-IR --> Update-IR : JTMS=1
    Update-DR --> Run-Test/Idle : JTMS=0
    Update-IR --> Run-Test/Idle : JTMS=0
  

The operation of the JTAG-DP is as follows:

1. 1. When the TAPSM goes through the Capture-IR state, 0b0001 is transferred onto the instruction register (IR) scan chain. The IR scan chain is connected between JTDI and JTDO.
2. 2. While the TAPSM is in the Shift-IR state, the IR scan chain shifts one bit for each rising edge of JTCK. This means that, on the first tick:
   • – The LSB of the IR scan chain is output on JTDO.
   • – Bit[n] of the IR scan chain is transferred to bit[n-1].
   • – The value on JTDI is transferred to the MSB of the IR scan chain.
3. 3. When the TAPSM goes through the Update-IR state, the value scanned into the IR scan chain is transferred into the instruction register.
4. 4. When the TAPSM goes through the Capture-DR state, a value is transferred from one of the data registers onto one of the DR scan chains, connected between JTDI and JTDO.
5. 5. The value held in the instruction register determines which data register and associated DR scan chain are selected.
6. 6. This data is then shifted while the TAPSM is in the Shift-DR state, in the same manner as the IR shift in the Shift-IR state.
7. 7. When the TAPSM goes through the Update-DR state, the value scanned into the DR scan chain is transferred into the selected data register.
8. 8. When the TAPSM is in the Run-Test/Idle state, no special actions occur. The IDCODE instruction is loaded in the instruction register.

When active, the nJTRST signal resets the state machine asynchronously to the Test-Logic-Reset state.

The data registers corresponding to the 4-bit IR instructions are listed in Table 404 .

Table 404. JTAG-DP data registers

Table 404. JTAG-DP data registers (continued)

Data registers are described in more detail in the Arm® Debug Interface Architecture Specification [1].

41.2.9 Serial-wire debug port

The serial-wire debug (SWD) protocol uses the two following pins:

• • SWCLK: clock from host to target
• • SWDIO: bidirectional serial data

Serial data is transferred LSB first, synchronously with the clock.

A transfer comprises three phases:

1. 1. Packet request (8-bit) transmitted by the host (see Table 405 )
2. 2. Acknowledge response (3-bit) transmitted by the target (see Table 406 )
3. 3. Data transfer (33-bit) transmitted by the host (in case of a write) or target (in case of a read) (see Table 407 )

The data transfer only occurs if the acknowledge response is OK.

Between each phase, if the direction of the data is reversed, a single clock cycle turn-around time is inserted.

Table 405. Packet request

Table 406. ACK response

Table 407. Data transfer

In the case of a FAULT or WAIT ACK response from the target, the data transfer phase is canceled, unless overrun detection is enabled: in this case the data is ignored by the target (in the case of a write), or not driven (in the case of a read).

A line reset must be generated by the host when it is first connected, or following a protocol error. The line reset consists in 50 or more SWCLK cycles with SWDIO high, followed by two SWCLK cycles with SWDIO low.

For more details on the serial-wire debug protocol, refer to the Arm ^® Debug Interface Architecture Specification [1] .

Note: The SWJ-DP implements SWD protocol version 2.

41.3 Debug port registers

Both SW-DP and JTAG-DP access the debug port (DP) registers listed in Table 408 .

The debugger accesses the DP registers as follows:

1. 1. If using JTAG, program the A[3:2] field in the DPACC register with the register address within the bank. Program the RnW bit to select a read or write. In the case of a write, program the DATA field with the write data. If using SWD, the A[3:2] and RnW fields are

part of the packet request word sent to the SW-DP with the APnDP bit reset (see Table 405 ). The write data are sent in the data phase.

1. To access one of the banked DP registers at address 0x4, the register number must first be written to the DP_SELECTR register at address 0x8. Any subsequent read or write to address 0x4 accesses the register corresponding to the content of the DP_SELECTR register.

41.3.1 DP identification register [alternate] (DP_PIDR)

Address offset: 0x00

Reset value: 0x0BE0 2477 (SW-DP), 0x0BE0 1477 (JTAG-DP)

Read only

Bits 31:28 REVISION[3:0] : Revision code

0x0 (JTAG-DP)

0x0 (SW-DP)

Bits 27:20 PARTNO[7:0] : Part number for the debug port

0xBE

Bits 19:17 Reserved, must be kept at reset value.

Bit 16 MIN : Minimal debug port (MINDP) implementation

0x1 MINDP not implemented (transaction counter and pushed operations are supported)

Bits 15:12 VERSION[3:0] : DP architecture version

0x1 (JTAG-DP)

0x2 (SW-DP)

Bits 11:1 DESIGNER[10:0] : JEDEC designer identity code

0x23B Arm® JEDEC code

Bit 0 Reserved, must be kept at reset value.

41.3.2 DP abort register [alternate] (DP_ABORTR)

Address offset: 0x00

Reset value: 0x0000 0000

Write only

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 ORUNERRCLR : Overrun error clear

0: No effect

1: Clear STICKYORUN bit in DP_CTRLSTATR

Bit 3 WDERCLR : Write data error clear

0: No effect

1: Clear WDATAERR bit in DP_CTRLSTATR

Bit 2 STKERCLR : Sticky error clear

0: No effect

1: Clear STICKYERR bit in DP_CTRLSTATR

Bit 1 Reserved, must be kept at reset value.

Bit 0 DAPABORT : Data AP abort

Aborts current AP transaction if an excessive number of WAIT responses are returned, indicating that the transaction is stalled.

0: No effect

1: Aborts the transaction.

41.3.3 DP control and status register (DP_CTRLSTATR)

Address offset: 0x04

This register is accessible when DP_SELECTR.DPBANKSEL = 0x0

Reset value: 0x0000 0000

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 CDBGPWRUPACK : See description in Section 41.2.6

0 = DAPCLK gated
1 = DAPCLK enabled

Bit 28 CDBGPWRUPREQ : Control of DAPCLK enable request signal

0 = Requests DAPCLK gating
1 = Requests DAPCLK enabled

Bits 27:8 Reserved, must be kept at reset value.

Bit 7 WDATAERR : Write data error (read only) in SW-DP

There is a parity or framing error on the data phase of a write, or a write that has been accepted by the DP is then discarded without being submitted to the AP.

This bit is reset by writing 1 to the DP_ABORTR.WDERRCLR bit.

0: No error

1: An error occurred.

This bit is reserved in JTAG-DP.

Bit 6 READOK : AP read response (read only) in SW-DP

Indicates the response to the last AP read access.

0: Read not OK

1: Read OK

This bit is reserved in JTAG-DP.

Bit 5 STICKYERR : Transaction error (read only in SW-DP, R/W in JTAG-DP)

Indicates that an error occurred in an AP transaction.

0: No error

1: An error occurred.

In SW-DP, STICKYERR bit is read only, reset by writing 1 to the DP_ABORTR.STKERRCLR bit.

In JTAG-DP, STICKYERR bit is read, cleared by writing a 1 to it.

Bits 4:2 Reserved, must be kept at reset value.

Bit 1 STICKYORUN : Overrun (read only in SW-DP, R/W in JTAG-DP)

Indicates that an overrun occurred (new transaction received before previous transaction completed). This bit is only set if the ORUNDETECT bit is set.

0: No overrun

1: An overrun occurred.

In SW-DP, STICKYORUN bit is read only, reset by writing 1 to the DP_ABORTR.ORUNERRCLR bit.

In JTAG-DP, STICKYORUN bit is read, cleared by writing a 1 to it.

Bit 0 ORUNDETECT : Overrun detection mode enable

0: Overrun detection disabled

1: Overrun detection enabled

In the event of an overrun, the STICKYORUN bit is set and subsequent transactions are blocked until the STICKYORUN bit is cleared.

41.3.4 DP data link control register (DP_DLCR)

Address offset: 0x04

This register is accessible when DP_SELECTR.DPBANKSEL = 0x1

Reset value: 0x0000 0000

Bits 31:10 Reserved, must be kept at reset value.

Bits 9:8 TURNROUND[1:0] : Tristate period for SWDIO

• 0x0: 1 data bit period
• 0x1: 2 data bit periods
• 0x2: 3 data bit periods
• 0x3: 4 data bit periods

Bits 7:6 WIREMODE[1:0] : SW-DP SWDIO

• 0x0: Synchronous
• Others: Reserved

Bits 5:0 Reserved, must be kept at reset value.

41.3.5 DP target identification register (DP_TARGETIDR)

Address offset: 0x04

This register is accessible when DP_SELECTR.DPBANKSEL = 0x2

Reset value: 0x14B2 0041

Bits 31:28 TREVISION[3:0] : Target revision

• 0x1: Revision A

Bits 27:12 TPARTNO[15:0] : Target part number

• 0x4B20: STM32WBA2xxx

Bits 11:1 TDESIGNER[10:0] : Target designer JEDEC code.

• 0x020: STMicroelectronics

Bit 0 Reserved, must be kept at reset value.

41.3.6 DP data link protocol identification register (DP_DLPIDR)

Address offset: 0x04

This register is accessible when DP_SELECTR.DPBANKSEL = 0x3

Reset value: 0x0000 0001

Bits 31:28 TINSTANCE[3:0] : Target instance number

Defines the instance number for this device in a multi-drop system.

0x0: Instance number 0

Bits 27:4 Reserved, must be kept at reset value.

Bits 3:0 PROTSVN[3:0] : Serial-wire debug protocol version

0x1: Version 2

41.3.7 DP resend register (DP_EVENSTATR)

Address offset: 0x04

This register is accessible when DP_SELECTR.DPBANKSEL = 0x4

Reset value: 0x0000 0001

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 EA : Event status flag

0: Cortex-M33 processor halted

1: Cortex-M33 processor not halted.

41.3.8 DP resend register (DP_RESENR)

Address offset: 0x08

Reset value: 0x0000 0000

Bits 31:0 RESEND[31:0] : Value returned by the last AP read or DP_RDBUFR read.
Used in the event of a corrupted read transfer.

41.3.9 DP access port select register (DP_SELECTR)

Address offset: 0x08

Reset value: 0xXXXX XXXX

Bits 31:28 APSEL[3:0] : Access port selection

Selects the access port for the next transaction.

0x0: AP0 - System debug access port

0x1: AP1 - Cortex-M33 debug access port

Others: reserved

Bits 27:8 Reserved, must be kept at reset value.

Bits 7:4 APBANKSEL[3:0] : AP register bank selection

Selects the 4-word register bank on the active AP for the next transaction.

Bits 3:0 DPBANKSEL[3:0] : DP register bank selection

Selects the register at address 0x4 of the debug port.

0x0: DP_CTRLSTATR

0x1: DP_DLCR

0x2: DP_TARGETIDR

0x3: DP_DLPIDR

0x4: DP_EVENTSTAT

Others: reserved

41.3.10 DP read buffer register (DP_BUFFR)

Address offset: 0x0C

Reset value: 0x0000 0000

Bits 31:0 RDBUFF[31:0] : Contains the value returned by the last AP read access.

The value returned by an AP read access can either be obtained using a second read access to the same address, which initiates a new transaction on the corresponding bus, or else it can be read from this register, in which case no new AP transaction occurs.

41.3.11 DP register map and reset values

These registers are not on the CPU memory bus and are only accessed through SW-DP and JTAG-DP debug interface.

The debug port address is 2-bit wide, defined in the JTAG-DP register DPACC or SW-DP packet request A[3:2] field.

Table 408. DP register map and reset values

Table 408. DP register map and reset values (continued)

1. 1. DP_SELECTR.DPBANKSEL = 0x0.
2. 2. DP_SELECTR.DPBANKSEL = 0x1.
3. 3. DP_SELECTR.DPBANKSEL = 0x2.
4. 4. DP_SELECTR.DPBANKSEL = 0x3.
5. 5. DP_SELECTR.DPBANKSEL = 0x4

41.4 Access port

There are two access ports (AP) attached to the DP.

• • AP0, system debug access port: enables access to the system debug features integrated at device level.
• • AP1, Cortex-M33 processor core access port: enables access to the debug and trace features integrated in the Cortex-M33 processor core.

41.4.1 Access port registers

The access ports are of MEM-AP type: the debug and trace component registers are mapped in the address space of the associated bus.

An AP is seen by the debugger as a set of 32-bit registers organized in banks of four registers each. Some of these registers are used to configure or monitor the AP itself, while others are used to perform a transfer on the bus. The AP registers are listed in Table 409 .

The address of the AP registers is composed of the following fields:

• • Bits [7:4]: content of the APBANKSEL[3:0] field in the DP_SELECTR register
• • Bits [3:2]: content of the A[3:2] field of the APACC data register in the JTAG-DP or of the SW-DP packet request, depending on the debug interface used
• • Bits [1:0]: always set to 0

The content of the APSEL[3:0] defines which MEM-AP is being accessed.

The debugger can access the AP registers as follows:

1. 1. Program in the APSEL[3:0] field to choose the AP and the APBANKSEL[3:0] field to select the register bank to be accessed.
2. 2. If using JTAG, program the A[3:2] field in the APACC register, with the register address within the bank. Program the RnW bit to select a read or write. In the case of a write, program the DATA field with the write data. If using SWD, the A[3:2] and RnW fields are part of the packet request word sent to the SW-DP with the APnDP bit set (see Table 405 ). The write data is sent in the data phase.

The debugger can access the memory-mapped debug component registers through the MEM-AP registers (using the above AP register access procedure) as follows:

1. 1. Program the transaction target address in the AP_TAR register.
2. 2. If necessary, program the AP_CSWR register with the transfer parameters (AddrInc for example).
3. 3. Write to or read from the AP_DRWR register to initiate a bus transaction at the address held in the AP_TAR register. Alternatively, a read or write to the AP_BDxR register triggers an access to address \( AP\_TAR[31:4] + x \) (allowing up to four consecutive addresses to be accessed without changing the address in the AP_TAR register).

For more detailed information on the MEM-AP, refer to the Arm® Debug Interface Architecture Specification [1] .

41.4.2 AP control/status word register (APx_CSWR) (x = 0 to 1)

Address offset: 0x00

Reset value: 0x0100 00X0

Bit 31 Reserved, must be kept at reset value.

Bit 30 PROT6 : secure transfer protection bit [6]

This field sets protection attribute HPROT[6] of the AP bus transfer.

0: Secure transfer

1: Nonsecure transfer

Bits 29:28 Reserved, must be kept at reset value.

Bits 27:24 PROT[3:0] : Bus transfer protection

This field sets protection attribute HPROT[3:0] of the AP bus transfer.

0bXXX1: Data transfer

0bXX0X: Unprivileged transfer

0bXX1X: Privileged transfer

0bX0XX: Non-bufferable

0bX1XX: Bufferable

0b0XXX: Non-sharable, no look-up non-modifiable

0b1XXX: Sharable, look-up, modifiable

Bits 23:7 Reserved, must be kept at reset value.

Bit 6 DBGSTATUS : Device enable (DEVICEEN) status

Indicates whether the Cortex-M33 AP bus can be accessed by the debugger. This bit reflects the state of dbgen.

0: AP AHB bus transfers blocked.

1: AP AHB bus transfers granted.

Bits 5:4 ADDRINC[1:0] : Auto-increment mode

Defines whether AP_TAR address is automatically incremented after a transaction.

0x0: No auto-increment

0x1: Address is incremented by the size in bytes of the transaction (SIZE field).

Others: Reserved

Bit 3 Reserved, must be kept at reset value.

Bits 2:0 SIZE[2:0] : Size of next memory access transaction

0x0: Byte (8-bit)

0x1: Halfword (16-bit)

0x2: Word (32-bit)

Others: Reserved

41.4.3 AP transfer address register (APx_TAR) (x = 0 to 1)

Address offset: 0x04

Reset value: 0xXXXX XXXX

Bits 31:0 TA[31:0] : Address of current transfer

41.4.4 AP data read/write register (APx_DRWR) (x = 0 to 1)

Address offset: 0x0C

Reset value: 0xXXXX XXXX

Bits 31:0 TD[31:0] : Data of current transfer

41.4.5 AP banked data registers y (APx_BDyR) (x = 0 to 1)

Address offset: 0x10 + 0x4 * y, (y = 0 to 3)

Reset value: 0x0000 0000

Bits 31:0 TBD[31:0] : Banked data of current transfer to address in AP_TAR

AP_TAR + AP_BDnR address [3:2] + 0b00

The auto address incrementing is not performed on AP_BD[3:0]R.

Banked transfers are only supported for word transfers.

41.4.6 AP configuration register (APx_CFGR) (x = 0 to 1)

Address offset: 0xF4

Reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 LD : Large data

0: Data not longer than 32-bits supported.

Bit 1 LA : Long address

0: Physical addresses not longer than 32-bits supported.

Bit 0 BE : Big-endian

0: Only little-endian supported.

41.4.7 AP base address register (APx_BASER) (x = 0 to 1)

Address offset: 0xF8

Reset value: Block 0: 0xE008 0003

Reset value: Block 1: 0xE00F E003

Bits 31:12 BASEADDR[31:12] : Base address (bits 31 to 12) of ROM table for the AP

The 12 LSBs are zero since the ROM table must be aligned on a 4-Kbyte boundary.

AP0: 0xE0080 (system ROM table)

AP1: 0xE00FE (MCU ROM table)

Bits 11:2 Reserved, must be kept at reset value.

Bit 1 FORMAT : Base address register format

1: Arm ^® debug interface v5

Bit 0 ENTRYPRESENT : Debug components presence

Indicates that debug components are present on the access port bus.

1: Debug components are present

41.4.8 AP identification register (APx_IDR) (x = 0 to 1)

Address offset: 0xFC

Reset value: 0x1477 0015

Bits 31:28 REVISION[3:0] : Revision

0x1: r0p1

Bits 27:24 JEDECBANK[3:0] : JEDEC bank

0x4: Arm ^®

Bits 23:17 JEDECCODE[6:0] : JEDEC code

0x3B: Arm ^®

Bits 16:13 CLASS[3:0] : Memory access port

0x8: MEM_AP Standard register map

Bits 12:8 Reserved, must be kept at reset value.

Bits 7:4 VARIANT[3:0] : AP variant

0x1: AHB-AP

Bits 3:0 TYPE[3:0] : AP type

0x5: AHB5

41.4.9 Access port register map and reset values

These registers are not on the CPU memory bus and are only accessed through SW-DP and JTAG-DP debug interface.

The access port address is 8-bit wide, defined by DP_SELECTR.APBANKSEL[3:0] field and by JTAG-DP register DPACC or SW-DP packet request A[3:2] field.

Table 409. AP register map and reset values

41.5 System debug AP0 features

The system debug subsystem integrates the following features accessible through the AP0:

• • System ROM table
• • Debug MCU controller (DBGMCU)

41.5.1 System debug ROM table

The system debug ROM table is a CoreSight component that contains the base addresses of all the debug components accessible via the AP0. This table allows a debugger to discover the topology of the debug system automatically.

There is one ROM table in the system debug subsystem.

1. 1. The system debug ROM table is pointed to by the AP0_BASER register. It contains the base-address pointer for the DBGMCU.

The system debug ROM table (see Table 410 ) occupies a 4-Kbyte, 32-bit wide chunk of address space, from 0xE008 0000 to 0xE008 0FFC.

Table 410. System debug ROM table

The CoreSight topology for the debug components in the system debug subsystem is shown in Figure 381 .

Figure 381. AP0: CoreSight topology

41.5.2 System debug memory type register (SYSROM_MEMTYPER)

Address offset: 0xFCC

Reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 SYSTMEM : system memory

0: No system memory present on this bus

41.5.3 System debug CoreSight peripheral identity register 4 (SYSROM_PIDR4)

Address offset: 0xFD0

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 F4KCOUNT[3:0] : Register file size

0x0: Register file occupies a single 4-Kbyte region.

Bits 3:0 JEP106CON[3:0] : JEP106 continuation code

0x0: STMicroelectronics JEDEC continuation code

41.5.4 System debug CoreSight peripheral identity register 0 (SYSROM_PIDR0)

Address offset: 0xFE0

Reset value: 0x0000 00B2

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PARTNUM[7:0] : Part number bits [7:0]

0xB2: STM32WBA2xxx

41.5.5 System debug CoreSight peripheral identity register 1 (SYSROM_PIDR1)

Address offset: 0xFE4

Reset value: 0x0000 0004

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 JEP106ID[3:0] : JEP106 identity code bits [3:0]

0x0: STMicroelectronics JEDEC code

Bits 3:0 PARTNUM[11:8] : Part number bits [11:8]

0x4: STM32WBA2xxx

41.5.6 System debug CoreSight peripheral identity register 2 (SYSROM_PIDR2)

Address offset: 0xFE8

Reset value: 0x0000 000A

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 REVISION[3:0] : Component revision number

0x0: Rev r0p0

Bit 3 JEDEC : JEDEC assigned value

1: Designer ID specified by JEDEC

Bits 2:0 JEP106ID[6:4] : JEP106 identity code bits [6:4]

0x2: STMicroelectronics JEDEC code

41.5.7 System debug CoreSight peripheral identity register 3 (SYSROM_PIDR3)

Address offset: 0xFEC

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 REVAND[3:0] : Metal fix version

0x0: No metal fix

Bits 3:0 CMOD[3:0] : Customer modified

0x0: No customer modifications

41.5.8 System debug CoreSight component identity register 0 (SYSROM_CIDR0)

Address offset: 0xFF0

Reset value: 0x0000 000D

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PREAMBLE[7:0] : Component ID bits [7:0]

0x0D: Common ID value

41.5.9 System debug CoreSight peripheral identity register 1 (SYSROM_CIDR1)

Address offset: 0xFF4

Reset value: 0x0000 0010

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 CLASS[3:0] : Component ID bits [15:12] - component class

0x1: ROM table component

Bits 3:0 PREAMBLE[11:8] : Component ID bits [11:8]

0x0: Common ID value

41.5.10 System debug CoreSight component identity register 2 (SYSROM_CIDR2)

Address offset: 0xFF8

Reset value: 0x0000 0005

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PREAMBLE[19:12] : Component ID bits [23:16]

0x05: Common ID value

41.5.11 System debug CoreSight component identity register 3 (SYSROM_CIDR3)

Address offset: 0xFFC

Reset value: 0x0000 00B1

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PREAMBLE[27:20] : Component ID bits [31:24]

0xB1: Common ID value

41.5.12 System debug ROM table register map and reset values

Refer to Section 41.5: System debug AP0 features for the register boundary addresses.

41.6 Cortex-M33 AP1 features

The Cortex-M33 subsystem integrates the following features accessible through the AP1:

• • MCU and processor ROM tables
• • System control space (SCS)
• • Breakpoint unit (FPB)
• • Data watchpoint and trace unit (DWT)
• • Instrumental trace macrocell (ITM)
• • Embedded trace macrocell (ETM)
• • Trace port interface unit (TPIU)
• • Cross-trigger interface (CTI)

41.6.1 CPU ROM tables

The ROM tables are CoreSight components that contain the base addresses of all the debug components accessible via the AP1. These tables allow the debugger to discover the CoreSight topology of the system automatically.

There are two ROM tables on AP1 in the Cortex-M33 subsystem.

1. 1. The MCU ROM table is pointed to by the AP_BASER register in the AP1. It contains the base-address pointers for the processor ROM table and for the TPIU and DBGMCU.
2. 2. The processor ROM table contains the base-address pointer for the system control space (SCS) registers that allows the debugger to identify the CPU core, as well as for the BPU, ITM, and CTI.

The MCU ROM table occupies a 4-Kbyte, 32-bit wide chunk of address space, at base address 0xE00F E000.

Table 411. MCU ROM table

The processor ROM table occupies a 4-Kbyte, 32-bit wide chunk of address space, at base address 0xE00F F000.

Table 412. Processor ROM table

The CoreSight topology for the debug components in the CPU subsystem is shown in Figure 382.

Figure 382. CPU CoreSight topology

MSv77291V1

41.6.2 MCU and processor ROM memory type register (ROM_MEMTYPE)

Address offset: 0xFCC

Reset value: 0x0000 0001

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 SYSTM : System memory

1: System memory present on this bus

41.6.3 MCU and processor ROM CoreSight peripheral identity register 4 (ROM_PIDR4)

Address offset: 0xFD0

Reset value: 0x0000 0000 (MCU ROM)

Reset value: 0x0000 0004 (processor ROM)

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 F4KCOUNT[3:0] : Register file size

0x0: Register file occupies a single 4-Kbyte region.

Bits 3:0 JEP106CON[3:0] : JEP106 continuation code

MCU ROM:

0x0: STMicroelectronics JEDEC continuation code

Processor ROM:

0x4: Arm ^® JEDEC continuation code

41.6.4 MCU and processor ROM CoreSight peripheral identity register 0 (ROM_PIDR0)

Address offset: 0xFE0

Reset value: 0x0000 00B2 (MCU ROM)

Reset value: 0x0000 00C9 (processor ROM)

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PARTNUM[7:0] : Part number bits [7:0]

MCU ROM:

0xB2: STM32WBA2

processor ROM:

0xC9: Cortex-M33

41.6.5 MCU and processor ROM CoreSight peripheral identity register 1 (ROM_PIDR1)

Address offset: 0xFE4

Reset value: 0x0000 0004 (MCU ROM)

Reset value: 0x0000 00B4 (processor ROM)

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 JEP106ID[3:0] : JEP106 identity code bits [3:0]

0x0: MCU ROM: STMicroelectronics JEDEC code

0xB: Processor ROM: Arm® JEDEC code

Bits 3:0 PARTNUM[11:8] : Part number bits [11:8]

0x4: MCU ROM: STM32WBA2

0x4: Processor ROM: Cortex-M33

41.6.6 MCU and processor ROM CoreSight peripheral identity register 2 (ROM_PIDR2)

Address offset: 0xFE8

Reset value: 0x0000 000A (MCU ROM)

Reset value: 0x0000 000B (processor ROM)

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 REVISION[3:0] : Component revision number

0x0: Rev r0p0

Bit 3 JEDEC : JEDEC assigned value

1: Designer ID specified by JEDEC

Bits 2:0 JEP106ID[6:4] : JEP106 identity code bits [6:4]

MCU ROM:

0x2: STMicroelectronics JEDEC code

Processor ROM:

0x3: Arm® JEDEC code

41.6.7 MCU and processor ROM CoreSight peripheral identity register 3 (ROM_PIDR3)

Address offset: 0xFEC

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 REVAND[3:0] : Metal fix version

0x0: No metal fix

Bits 3:0 CMOD[3:0] : Customer modified

0x0: No customer modifications

41.6.8 MCU and processor ROM CoreSight component identity register 0 (ROM_CIDR0)

Address offset: 0xFF0

Reset value: 0x0000 000D

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PREAMBLE[7:0] : Component ID bits [7:0]

0x0D: Common ID value

41.6.9 MCU and processor ROM CoreSight peripheral identity register 1 (ROM_CIDR1)

Address offset: 0xFF4

Reset value: 0x0000 0010

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 CLASS[3:0] : Component ID bits [15:12] - component class

0x1: ROM table component

Bits 3:0 PREAMBLE[11:8] : Component ID bits [11:8]

0x0: Common ID value

41.6.10 MCU and processor ROM CoreSight component identity register 2 (ROM_CIDR2)

Address offset: 0xFF8

Reset value: 0x0000 0005

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PREAMBLE[19:12] : Component ID bits [23:16]

0x05: Common ID value

41.6.11 MCU and processor ROM CoreSight component identity register 3 (ROM_CIDR3)

Address offset: 0xFFC

Reset value: 0x0000 00B1

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PREAMBLE[27:20] : Component ID bits [31:24]

0xB1: Common ID value

41.6.12 MCU and processor ROM tables register map and reset values

Table 413. ROM table register map and reset values

41.7 Data watchpoint and trace unit (DWT)

The DWT provides four comparators that can be used as one of the following function:

• • Watchpoint
• • PC sampling trigger
• • Data address sampling trigger
• • Data comparator (comparator 1 only)
• • Clock cycle counter comparator (comparator 0 only)

It also contains counters for:

• • Clock cycles
• • Folded instructions
• • Load store unit (LSU) operations
• • Sleep cycles
• • Number of cycles per instruction
• • Interrupt overhead

A DWT comparator compares the value held in its DWT_COMPxR registers with one of the following:

• • A data address
• • An instruction address
• • A data value
• • The cycle count value, for comparator 0 only.

For address matching, the comparator can use a mask, so it matches a range of addresses.

On a successful match, the comparator generates one of the following:

• • One or more DWT data trace packets, containing one or more of:
  • – The address of the instruction that caused a data access
  • – An address offset, bits[15:0] of the data access address
  • – The matched data value
• • A watchpoint debug event, on either the PC value or the accessed data address
• • A CMPMATCH[N] event that signals the match outside the DWT unit

A watchpoint debug event either generates a DebugMonitor exception or causes the processor to halt execution and enter Debug state.

For more details on how to use the DWT, refer to the Arm ^® v8-M Architecture Reference Manual [4].

41.7.1 DWT control register (DWT_CTRLR)

Address offset: 0x000

Reset value: 0x4000 0000

Bits 31:28 NUMCOMP[3:0] : Number of comparators implemented (read only)

0x4: Four comparators

Bit 27 NOTRCPKT : Trace sampling and exception tracing support (read only)

0: Supported

Bit 26 NOEXTTRIG : External match signal, CMPMATCH support (read only)

0: Supported

Bit 25 NOCYCCNT : Cycle counter support (read only)

0: Supported

Bit 24 NOPRFCNT : Profiling counter support (read only)

0: Supported

Bit 23 CYCDISS : Cycle counter disable secure

Controls whether the cycle counter is disabled in secure mode

0: No effect

1: Disabled incrementing the cycle counter when the processor is in secure mode

Bit 22 CYCEVTENA : Enable for POSTCNT underflow event counter packet generation

0: Disabled

1: Enabled

Bit 21 FOLDEVTENA : Enable for folded instruction counter overflow event generation

0: Disabled

1: Enabled

Bit 20 LSUEVTENA : Enable for LSU counter overflow event generation

0: Disabled

1: Enabled

Bit 19 SLEEPVTENA : Enable for sleep counter overflow event generation

0: Disabled

1: Enabled

Bit 18 EXCEVTENA : Enable for exception overhead counter overflow event generation

0: Disabled

1: Enabled

• Bit 17 CPIEVTPENA : Enable for CPI counter overflow event generation

  • 0: Disabled
  • 1: Enabled

• Bit 16 EXCTRCENA : Enable for exception trace generation

  • 0: Disabled
  • 1: Enabled

• Bits 15:13 Reserved, must be kept at reset value.

• Bit 12 PCSAMPLENA : Enable for POSTCNT counter used as a timer for periodic PC sample packet generation

  • 0: Disabled
  • 1: Enabled

• Bits 11:10 SYNCTAP[1:0] : Synchronization packet counter tap

  Selects the position of the synchronization packet counter tap on the CYCCNT counter. This determines the synchronization packet rate.

  • 00: Disabled. No synchronization packets
  • 01: Tap at CYCCNT[24]
  • 10: Tap at CYCCNT[26]
  • 11: Tap at CYCCNT[28]

• Bit 9 CYCTAP : Selects the position of the POSTCNT tap on the CYCCNT counter.

  • 0: Tap at CYCCNT[6]
  • 1: Tap at CYCCNT[10]

• Bits 8:5 POSTINIT[3:0] : Initial value of the POSTCNT counter

  Writes to this field are ignored if POSTCNT counter is enabled (CYCEVTENA or PCSAMPLENA must be reset prior to writing POSTINIT).

• Bits 4:1 POSTPRESET[3:0] : Reloads value of the POSTCNT counter.

• Bit 0 CYCCNTENA : Enable for CYCCNT counter

  • 0: Disabled
  • 1: Enabled

41.7.2 DWT cycle count register (DWT_CYCCNTR)

Address offset: 0x004

Reset value: 0x0000 0000

Bits 31:0 CYCCNT[31:0] : Processor clock cycle counter

41.7.3 DWT CPI count register (DWT_CPICNTR)

Address offset: 0x008

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 CPICNT[7:0] : CPI counter

Counts additional cycles required to execute multi-cycle instructions (except those recorded by DWT_LSUCNTR) and counts any instruction fetch stalls.

41.7.4 DWT exception count register (DWT_EXCCNTR)

Address offset: 0x00C

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 EXCCNT[7:0] : Exception overhead cycle counter

Counts the number of cycles spent in exception processing.

41.7.5 DWT sleep count register (DWT_SLPCNTR)

Address offset: 0x010

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 SLEEPcnt[7:0] : Sleep cycle counter

Counts the number of cycles spent in sleep mode (WFI, WFE, sleep-on-exit).

41.7.6 DWT LSU count register (DWT_LSUCNTR)

Address offset: 0x014

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 LSUCNT[7:0] : load store counter

Counts additional cycles required to execute load and store instructions.

41.7.7 DWT fold count register (DWT_FOLDCNTR)

Address offset: 0x018

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 FOLDCNT[7:0] : Folded instruction counter

Increments on each instruction that takes 0 cycles.

41.7.8 DWT program counter sample register (DWT_PCSR)

Address offset: 0x01C

Reset value: 0x0000 0000

Bits 31:0 EIASAMPLE[31:0] : Executed Instruction Address sample value
Samples the current value of the program counter.

41.7.9 DWT comparator register x (DWT_COMPxR)

Address offset: 0x020 + 0x10 * x, (x = 0 to 3)

Reset value: 0x0000 0000

Bits 31:0 COMP[31:0] : Reference value for comparison

41.7.10 DWT function register 0(DWT_FUNCTR0)

Address offset: 0x028

Reset value: 0x5800 0000