15. Peripherals interconnect matrix

15.1 Introduction

Several peripherals have direct connections between them, enabling autonomous communication and/or synchronization between them. This saves CPU resources and power consumption. Additionally, these hardware connections remove software latency and result in a more predictable system design.

Depending on the peripherals, these interconnections can operate in Run, Sleep, Stop 0, Stop 1, and Stop 2 modes.

15.2 Connection summary

Table 129. Peripherals interconnect matrix ^{(1) (2)}

1. The numbers in this table are links to the corresponding subsections of Section 15.3 .

2. The “-” symbol in grayed cells means no interconnect.

15.3 Interconnection details

15.3.1 Master to slave interconnection for timers

From timer (TIM2/TIM16/TIM17) to timer (TIM2).

Purpose

Some timers are linked together internally for timer synchronization or chaining.

When one timer is configured in master mode, it can reset, start, stop, or clock the counter of another timer configured in slave mode.

The synchronization modes are detailed in:

• • Section 28.4.23: Timer synchronization and Section 28.4.22: Timers and external trigger synchronization for general-purpose timers (TIM2)

Triggering signals

The output from the master timer is on signal tim_trgo for TIM2, and tim_oc for TIM16 and TIM17, following a configurable timer event. The input to the slave timer is on signals tim_itr.

The possible master/slave connections are given in:

• • Table 255: TIMx internal trigger connection for TIM2

Active power modes

Run and Sleep.

15.3.2 Triggers to ADC4

From EXTI and timers (TIM2) and (LPTIM1) to ADC4.

Purpose

The timers TIM2 can be used to generate the ADC4 trigger event through the timer outputs tim_oc or tim_trgo. The low-power timer LPTIM1 can be used to generate the ADC4 trigger

event through output lptim1_ch1. In addition, GPIO pin 15 via EXTI channel can be used to generate an ADC4 trigger event.

Triggering signals

The input trigger signal list and the description of the interconnection between ADC4 and timers and EXTI is given in:

• • Table 167: ADC interconnection
• • Section 22.4.16: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) .
• • Section 22.4.21: Example timing diagrams (single/continuous modes hardware/software triggers)

Active power modes

Run, Sleep, and for LPTIM also in Stop 0, 1, and 2 modes, and EXTI in all Stop modes.

15.3.3 ADC4 analog watchdog as trigger to timer

From ADC4 to TIM2.

Purpose

The internal analog watchdog output signals from ADC4 are connected to timers. ADC4 can provide trigger events through watchdog signals to the timer (TIM2) to reset, start, stop, or enable the counting.

Setting descriptions of the ADC analog watchdog and timer trigger are provided in:

• • Section 28.4.2: TIM2 pins and internal signals for TIM2
• • Table 256: Interconnect to the tim_etr input multiplexer for TIM2

Triggering signals

The output from ADC4 is on signals adc_awa (three watchdogs on ADC4) and the input to timer on signal tim_etr.

Active power modes

Run, Sleep, and an ADC4 conversion in autonomous mode in Stop 0, 1, and 2 modes can generate a wake-up interrupt and desired trigger action to timers.

15.3.4 Clock source to timer

From HSE32, HSI16, LSE, LSI, and MCO to timer (TIM2/TIM16/TIM17) and low-power timer (LPTIM1/LPTIM2).

Purpose

A timer input or clock can receive different clock sources and can be used, for example, to calibrate internal oscillators and a reference clock.

External clocks (HSE32, LSE), internal clocks (HSI16, LSI), and microcontroller output clock (MCO) can be used as input to timer.

• • HSI16 and LSE are assigned to timer TIM2 as external input signals (tim_etr4/tim_etr11). HSI/LSE can be selected as a counter clock provided by

an external clock source in mode2: external trigger input. Inputs assignment and clock selection description are detailed in Section 28.4.5: Clock selection .

• • HSE32, HSI16, LSE, and LSI are assigned to general-purpose timers TIM16 and TIM17 as an input multiplexer input signal (tim_ti1_in3/tim_ti1_in5/tim_ti1_in6/tim_ti1_in9). HSI16/LSE/LSI can be selected as a counter clock provided by an external clock source in mode1: input multiplexer input. Inputs assignment and clock selection description are detailed in Section 28.4.5: Clock selection .
• • MCO is connected as external input to general-purpose timers TIM16 and TIM17, making possible the calibration of the HSI16 system clock with LSE or LSI with HSE system clock. This feature is detailed in Section 28.4.5: Clock selection .
• • LSE and LSI can be selected as input capture 2 (lptim_ic2_mux1/lptim_ic2_mux2) to LPTIM1. This feature is detailed in Section 28.4.7: Input capture mode .
• • HSI16/256 can be selected as input capture 2 (lptim_ic2_mux1) to LPTIM2. This feature is detailed in Section 28.4.7: Input capture mode .

Triggering signals

The input to the timer is on signals tim_etr or tim_ti1_in, and for low-power timer on signals lptim_ic2_mux.

The possible connections are given in:

• • Table 256: Interconnect to the tim_etr input multiplexer for TIM2
• • Table 251: Interconnect to the tim_ti1 input multiplexer for TIM16 and TIM17
• • Table 287: LPTIM1/2 input 2 connections for LPTIM1/LPTIM2

Active power modes

Run and Sleep.

15.3.5 Triggers to low-power timer

From RTC wake-up, RTC alarm, TAMP, LPDMA1, and LPTIM_ETR to low-power timer (LPTIM1/LPTIM2).

Purpose

Low-power timer counters may be started after the detection of an active edge on a trigger input (lptim_ext_trig0 to 5). This feature is detailed in Section 30.4.7: Trigger multiplexer .

Triggering signals

The input to low-power timer on signals lptim_ext_trig.

The possible connections are given in Table 285: LPTIM1/2 external trigger connections .

Active power modes

Run, Sleep, and Stop 0, and for RTC and TAMP also in Stop 1 and Stop 2 modes.

15.3.6 Internal analog signals to analog peripheral

From internal analog source to analog peripheral (ADC4).

Purpose

The internal reference voltage ( \( V_{REFINT} \) ), the internal temperature sensor ( \( V_{SENSE} \) ), and digital core voltage ( \( V_{CORE} \) ) monitoring signals are connected to analog peripheral (ADC4), as described in:

• • Section 22.4.9: Channel selection (CHSEL, SCANDIR, CHSELRMOD)
• • Section 22.4.27: Temperature sensor and internal reference voltage

Input signals

The input to analog peripheral on signals \( V_{IN} \) .

The possible connections are given in Table 167: ADC interconnection .

Active power modes

Run, Sleep, Stop 0, and Stop 1.

15.3.7 System errors as break signals to timers

From system errors to timers (TIM16/TIM17).

Purpose

HSE32 clock security, CPU lockup, SRAM2 parity error, FLASH ECC double error detection, and PVD can generate system errors in the form of timer break toward timers (TIM16/TIM17).

The purpose of the break function is to protect power switches driven by PWM signals generated by the timers. This feature is detailed in:

• • Section 29.4.13: Using the break function for TIM16 and TIM17

Break signals

The input to the timer on signals \( tim\_sys\_brk \) .

The possible connections are given in:

• • Table 271: Timer break interconnect for TIM16 and TIM17

Active power modes

Run and Sleep.

15.3.8 Triggers to LPDMA1

From GPIO pin EXTI, RTC, TAMP, timers (TIM2), low-power timer (LPTIM1/LPTIM2), LPDMA1, ADC4 to LPDMA1.

Purpose

An LPDMA trigger can be assigned to an LPDMA channel x. A programmed LPDMA transfer can be triggered by a rising/falling edge of a selected input trigger event. The trigger mode can also be programmed to condition the linked-list item transfer.

More details are given in:

• • Section 16.3.5: LPDMA triggers
• • Section 16.4.12: LPDMA triggered transfer

Triggering signals

Trigger mapping is specified in Table 16.3.5: LPDMA triggers .

Active power modes

Run and Sleep, and for peripherals supporting autonomous mode also in Stop 0 and Stop 1.

15.3.9 Internal tamper sources

From LSE clock security, RTC, Debug, ADC4, AES, PKA, TRNG, and IWDG to TAMP

Purpose

To detect any abnormal activity or tentative to corrupt the device, tampers are introduced and alert the system to such undesired events. Different actions can be taken in consequence. More details are given in Section 34: Tamper and backup registers (TAMP) .

Resources

Table 314: TAMP interconnection presents a list of tamper sources.

Active power modes

These interconnections are active in all power modes if the tamper source is active.

15.3.10 Triggers to communication peripherals

From LP timers (LPTIM1/LPTIM2), LPDMA1 transfer complete, EXTI GPIOs, RTC alarm and RTC wake-up to I2C1, I2C3, USART1, LPUART1, and SPI3.

Purpose

LP timer (LPTIM1) output channels (lptim1_ch1 and lptim2_ch1), EXTI GPIOs, RTC alarm and RTC wake-up, can be used as trigger to start a communication on the selected I2C, USART, LPUART, and SPI peripheral.

An LPDMA1 transfer complete can trigger both the LPDMA1 regular or linked-list new transfers and communication on the selected communication peripheral.

These features are detailed in:

• • Section 35.4.16: Autonomous mode I2C
• • Section 36.5.22: USART autonomous mode USART
• • Section 37.4.15: LPUART autonomous mode LPUART
• • Section 38.4.15: Autonomous mode SPI

Triggering signals

The outputs from triggers are directly connected to peripheral trigger inputs.

The selection of input triggers is detailed in:

• • Table 326: I2C1 interconnection and Table 327: I2C3 interconnection
• • Table 346: USART interconnection (USART1)
• • Table 358: LPUART interconnections (LPUART1)
• • Table 368: SPI interconnection (SPI3)

Active power mode

These interconnections remain active in Run, Sleep, and Stop modes if both the source and communication line are autonomous in this mode. Refer to:

• • Section 36.6: USART in low-power modes
• • Section 35.5: I2C in low-power modes
• • Section 38.6: SPI in low-power modes

15.3.11 Output from tamper

From TAMP to RTC.

Purpose

The RTC can timestamp a tamper event to retrieve history in time of such detection. The RTC can also control RTC_OUT and send tamp status tamp_evt outside the MCU. More details are given in Section 33.3.3: GPIOs controlled by the RTC and TAMP .

Active power mode

This interconnection remains active in all power modes.

15.3.12 Timers generating IRTIM signal

From timer (TIM16/TIM17) to IRTIM.

Purpose

Timers (TIM16/TIM17) output channels timx_oc1 are used to generate the waveform of infrared signal output IRTIM. The functionality is detailed in Section 31: Infrared interface (IRTIM) .

Active power mode

Run and Sleep.