10. PTA converter (PTACONV)

10.1 PTACONV introduction

The PTA converter is used to convert the PTA information coming from the 2.4 GHz RADIO into the PTA protocol used on the PTA controller GPIOs.

10.2 PTACONV main features

10.3 PTACONV functional description

The PTA converter adapts the PTA protocol to the various external PTA controllers. It supports a grant or deny signaling on the PTA_GRANT signal, and the following protocols:

When the request to cease an ongoing transmission occurs near the end of the 2.4 GHz RADIO packet, PTA_ACTIVE is deactivated at the end of the packet, before the expiration of T4.

10.3.1 PTACONV block diagram

Figure 26 shows the PTA converter block diagram and the interface to the 2.4 GHz RADIO.

Block diagram of PTACONV showing internal control blocks (ACTIVE, PRIORITY, STATUS, GRANT, ABORT) and their connections to external pins (PTA_ACTIVE, PTA_PRIORITY, PTA_STATUS, PTA_GRANT) and internal signals (ptaconv_active, ptaconv_priority, etc.).

Figure 26. PTACONV block diagram

The diagram shows the internal architecture of the PTACONV block. A 32-bit AHB bus is connected to the top. Inside the block, there are five control units: ACTIVE control, PRIORITY control, STATUS control, GRANT control, and ABORT control. The ACTIVE control takes ptaconv_active, ptaconv_packet_detect, and ptaconv_status_ms as inputs and outputs PTA_ACTIVE. The PRIORITY control takes ptaconv_priority and ptaconv_status_txrx as inputs and outputs PTA_PRIORITY. The STATUS control takes ptaconv_status_ms and ptaconv_status_txrx as inputs and outputs PTA_STATUS. The GRANT control takes ptaconv_ngrant and ptaconv_ker_ck as inputs and outputs PTA_GRANT. The ABORT control is connected to the ACTIVE and PRIORITY controls. A multiplexer selects between the outputs of the PRIORITY and STATUS controls for the PTA_STATUS pin. The reference MSV76712V1 is noted in the bottom right.

Block diagram of PTACONV showing internal control blocks (ACTIVE, PRIORITY, STATUS, GRANT, ABORT) and their connections to external pins (PTA_ACTIVE, PTA_PRIORITY, PTA_STATUS, PTA_GRANT) and internal signals (ptaconv_active, ptaconv_priority, etc.).

The PTACONV is clocked by the 2.4 GHz RADIO kernel clock, independently from the hclk for the AHB interface used to access the PTACONV configuration registers.

10.3.2 PTACONV pins and internal signals

Table 86. 2.4 PTACONV input/output pins

Pin nameSignal typeDescription
PTA_ACTIVEOutputPTA 2.4 GHz RADIO packet activation request
PTA_PRIORITYOutputPTA 2.4 GHz RADIO packet priority
PTA_STATUSOutputPTA 2.4 GHz RADIO packet type
PTA_GRANTInputPTA grant medium to 2.4 GHz RADIO

Table 87. PTACONV internal input/output signals

Pin nameSignal typeDescription
ptaconv_activeInput2.4 GHz RADIO packet activation request
ptaconv_priorityInput2.4 GHz RADIO packet priority
ptaconv_status_txrxInput2.4 GHz RADIO packet type Tx or Rx
ptaconv_status_msInput2.4 GHz RADIO packet type maser or slave
ptaconv_packet_detectInput2.4 GHz RADIO packet detect
ptaconv_ngrantOutputPTA active low medium granted

Table 87. PTACONV internal input/output signals (continued)

Pin nameSignal typeDescription
ptaconv_ker_ckInputKernel clock
AHBInput/outputAHB bus interface

10.3.3 PTACONV protocols

The PTA grant protocol, the PTA deny protocol, and the 3-wire PTA_STATUS time-multiplexed priority and status transmit receive information are detailed in this section.

PTA grant protocol

The 4-wire PTA grant protocol uses PTA_ACTIVE, PTA_STATUS, PTA_PRIORITY, and PTA_GRANT signals, as shown in Figure 27.

Figure 27. 4-wire PTA grant protocol

Timing diagram for the 4-wire PTA grant protocol showing signal transitions for packet, ptaconv_packet_detect, ptaconv_ngrant, PTA_ACTIVE, PTA_PRIORITY, PTA_STATUS, and PTA_GRANT across TX, RX master, TX aborted, RX slave, and TX denied scenarios. Timing intervals T1, T2, and T4 are marked.

The diagram shows the interaction of seven signals over five scenarios: TX, RX master, TX aborted, RX slave, and TX denied.

In the 'TX aborted' case, PTA_ACTIVE is pulled low early, and the packet is truncated after a delay T4. In 'TX denied', PTA_GRANT remains low, and no packet is sent.

Timing diagram for the 4-wire PTA grant protocol showing signal transitions for packet, ptaconv_packet_detect, ptaconv_ngrant, PTA_ACTIVE, PTA_PRIORITY, PTA_STATUS, and PTA_GRANT across TX, RX master, TX aborted, RX slave, and TX denied scenarios. Timing intervals T1, T2, and T4 are marked.

Timing parameters:

Time instances:

Receive packets are always granted and reception always proceeds. Receive packets use the PTA protocol to request the reservation of the medium for high priority receive packets.

PTA deny protocol

The PTA deny protocol uses PTA_ACTIVE, PTA_STATUS, PTA_PRIORITY and PTA_DENY signals, as shown in Figure 28.

Figure 28. 4-wire PTA deny protocol

Timing diagram for the 4-wire PTA deny protocol showing signal transitions for packet types TX, RX master, TX aborted, RX slave, and TX denied across signals like ptaconv_packet_detect, ptaconv_ngrant(deny), PTA_ACTIVE, PTA_PRIORITY, PTA_STATUS, and PTA_GRANT(DENY).

The diagram illustrates the timing of the 4-wire PTA deny protocol across five packet scenarios: TX, RX master, TX aborted, RX slave, and TX denied. The signals shown are:

Timing parameters are defined as:

Timing diagram for the 4-wire PTA deny protocol showing signal transitions for packet types TX, RX master, TX aborted, RX slave, and TX denied across signals like ptaconv_packet_detect, ptaconv_ngrant(deny), PTA_ACTIVE, PTA_PRIORITY, PTA_STATUS, and PTA_GRANT(DENY).

Timing parameters:

Time instances:

Receive packets are always granted and reception always proceeds. Receive packets use the PTA protocol to request the reservation of the medium for high priority receive packets.

3-wire time shared PTA_STATUS

The 3-wire PTA protocol does not use the PTA_PRIORITY signal. The priority and transmit receive packet status information is time-multiplexed on the PTA_STATUS signal, as shown in Figure 29.

Figure 29. 3-wire time-multiplexed PTA_STATUS

Timing diagram for 3-wire time-multiplexed PTA_STATUS. The diagram shows four signal lines over time. The top line is labeled 'packet' and shows a packet starting at t3. The second line is PTA_ACTIVE, which goes high at t1 and low at t3. The third line is PTA_STATUS, which is time-multiplexed: it shows 'priority' from t1 to t1.1, and 'status' from t1.1 to t3. The fourth line is PTA_GRANT, which goes high at t1 and low at t2. Time intervals are marked: T3 from t1 to t1.1, T1 from t1.1 to t2, and T2 from t2 to t3. A small text 'MSV56217V2' is in the bottom right corner of the diagram area.
Timing diagram for 3-wire time-multiplexed PTA_STATUS. The diagram shows four signal lines over time. The top line is labeled 'packet' and shows a packet starting at t3. The second line is PTA_ACTIVE, which goes high at t1 and low at t3. The third line is PTA_STATUS, which is time-multiplexed: it shows 'priority' from t1 to t1.1, and 'status' from t1.1 to t3. The fourth line is PTA_GRANT, which goes high at t1 and low at t2. Time intervals are marked: T3 from t1 to t1.1, T1 from t1.1 to t2, and T2 from t2 to t3. A small text 'MSV56217V2' is in the bottom right corner of the diagram area.

Timing parameters:

Time instances:

PTA timing parameters

Table 88. 2.4 PTACONV timing parameters

SymbolParameterMinTypMaxUnit
T1, T 1_PTAPTA_ACTIVE setup time20-150µs
T 1_PTA_jitterPTA_ACTIVE setup time jitter-2-2
T2, T 2_PTAPTA_GRANT setup time5--
T3, T 3_PTAPTA_STATUS priority valid time8-20
T4, T 4_PTATransmit packet abort delay5-10

10.3.4 PTACONV interface with the 2.4 GHz RADIO

The 2.4 GHz RADIO provides the following signals:

10.4 PTACONV low-power modes

The PTACONV supports operation in low power modes as shown in the table below:

Table 89. Effect of low-power modes on the PTACONV
ModeDescription
SleepNo effect. PTACONV remains operational.
Stop 0 voltage scaling range 1 and 1.5No effect. PTACONV remains operational.
Stop 0 voltage range 2 and Stop 1The PTACONV register context is kept, PTA signals keep their values.
Stop 2, Stop 3The PTACONV is powered down, PTA signals keep their values when enabled in register PWR_S2RETR.
Standby retention, StandbyThe PTACONV is powered down, PTA signals keep their values when enabled in register PWR_IORETENRx.

10.5 PTACONV registers

10.5.1 PTACONV active control register (PTACONV_ACTCR)

Address offset: 0x000

Reset value: 0x00005 0014

Access: no wait state; word, half-word, and byte access

31302928272625242322212019181716
Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.ABORT
DIS
TABORT[3:0]
rwrwrwrwrw

1514131211109876543210
ACTPOLRes.Res.Res.Res.Res.Res.Res.TACTIVE[7:0]
rwrwrwrwrwrwrwrwrw

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 ABORTDIS : Disable PTA_ACTIVE deny to abort an ongoing transmission

Set and cleared by software to define if PTA_ACTIVE aborts an ongoing transmission.

0: PTA_ACTIVE deny aborts an ongoing transmission

1: PTA_ACTIVE deny does not abort an ongoing transmission

Bits 19:16 TABORT[3:0] : PTA_ACTIVE delay to cease an ongoing transmission in µs

Set and cleared by software to define transmit packet abort delay and signaling on PTA_ACTIVE.

0x5 to 0xA: transmit packet PTA_ACTIVE abort delay time: \( T_{4\_PTA} = TABORT \times 1 \mu s \)

Others: Reserved, must no be used.

Bit 15 ACTPOL : PTA_ACTIVE polarity

Set and cleared by software to define PTA_ACTIVE signal polarity.

0: PTA_ACTIVE active high

1: PTA_ACTIVE active low

Bits 14:8 Reserved, must be kept at reset value.

Bits 7:0 TACTIVE[7:0] : PTA_ACTIVE setup time in µs

Set and cleared by software to define PTA_ACTIVE setup time.

0x14 to 0x96: PTA_ACTIVE setup time: \( T_{1\_PTA} = TACTIVE \times 1 \mu s \)

Others: Reserved, must no be used.

10.5.2 PTACONV priority control register (PTACONV_PRICR)

Address offset: 0x004

Reset value: 0x0000 000A

Access: no wait state; word, half-word, and byte access

31302928272625242322212019181716
Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.
1514131211109876543210
PRIPOLRes.Res.Res.Res.Res.Res.Res.Res.Res.Res.TPRIORITY[4:0]
rwrwrwrwrwrw

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 PRIPOL : Priority polarity

Set and cleared by software to define PTA_PRIORITY and time-multiplexed priority on PTA_STATUS signal polarity.
0: priority on PTA_PRIORITY or PTA_STATUS not inverted
1: inverted priority on PTA_PRIORITY or PTA_STATUS

Bits 14:5 Reserved, must be kept at reset value.

Bits 4:0 TPRIORITY[4:0] : Priority valid time in \( \mu s \)

Set and cleared by software to define PTA_STATUS signal priority valid time.
0x00: no time-multiplexed priority information on PTA_STATUS
0x08 to 0x14: priority information multiplexed on PTA_STATUS with valid time:
\( T_{3\_PTA} = TPRIORITY \times 1 \mu s \)
Others: Reserved, must no be used.

10.5.3 PTACONV control register (PTACONV_CR)

Address offset: 0x008

Reset value: 0x0000 0000

Access: no wait state; word, half-word, and byte access

31302928272625242322212019181716
GRANT
POL
Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.
rw
1514131211109876543210
TXRX
POL
Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.Res.
rw

Bit 31 GRANTPOL : PTA_GRANT polarity

Set and cleared by software to define PTA_GRANT signal polarity.
0: PTA_GRANT active low
1: PTA_GRANT active high

Bits 30:16 Reserved, must be kept at reset value.

Bit 15 TXRXPOL : PTA_STATUS transmit and receive polarity

Set and cleared by software to define PTA_STATUS signal polarity for transmit and receive information.

0: PTA_STATUS receive = 0, transmit = 1

1: PTA_STATUS receive = 1, transmit = 0

Bits 14:0 Reserved, must be kept at reset value.

10.5.4 PTACONV register map

Table 90. PTACONV register map and reset values

OffsetRegister313029282726252423222120191817161514131211109876543210
0x000PTACONV_ACTCRResResResResResResResResResResResABORTDISTABORT[3:0]ACTPOLResResResResResResResResTACTIVE[7:0]
Reset value00101000010100
0x004PTACONV_PRIORResResResResResResResResResResResResResResResResPRIPOLResResResResResResResResResResTPRIORITY[4:0]
Reset value001010
0x008PTACONV_CRGRANTPOLResResResResResResResResResResResResResResResTXRPOLResResResResResResResResResResResResResResRes
Reset value00
0x00C to 0x3FCReservedReserved

Refer to Section 2.3: Memory organization for the register boundary addresses.