5. Global TrustZone® controller (GTZC)

5.1 Introduction

This section describes the global TrustZone controller (GTZC) block, containing the following subblocks:

• • TZSC: TrustZone security controller
  This subblock defines the secure/privileged state of slave peripherals. It also controls the subregions size and properties for the watermark memory protection controller (MPCWM). The TZSC informs some peripherals (such as RCC or GPIOs) about the secure status of each securable peripheral.
• • MPCBB: memory protection controller - block based
  This subblock configures the internal RAM in a TrustZone-system product having segmented SRAM (pages of 512 bytes) with programmable-security and privileged attributes.
• • TZIC: TrustZone illegal access controller
  This subblock gathers all illegal access events in the system and generates a secure interrupt towards NVIC.

These subblocks are used to configure TrustZone system security in a product having bus agents with programmable-security and privileged attributes such as:

• • On-chip RAM with programmable secure and/or privileged blocks (pages)
• • AHB and APB peripherals with programmable security and/or privileged access
• • Off-chip memories with secure and/or privileged areas

5.2 GTZC main features

The GTZC main features are listed below:

• • Independent 32-bit AHB interface for TZSC, TZIC, and MPCBB
• • TZIC accessible only with secure transactions
• • Secure and nonsecure access supported for privileged and unprivileged part of TZSC and MPCBB
• • Set of registers to define product security settings:
  • – Secure/privileged blocks for internal SRAM
  • – Secure/privileged regions for external memories
  • – Secure/privileged access mode for securable peripherals

GTZC TrustZone system architecture

The Armv8-M supports security per TrustZone-M model with isolation between:

• • A secure world, where usually security sensitive applications are run and critical resources are located
• • A nonsecure or public world (such as usual nonsecure operating system and user space)

The TrustZone architecture is extended beyond AHB and Armv8-M with:

• • AHB/APB bridge used as a secure gate to block or propagate secure/nonsecure and privileged/unprivileged transaction towards APB agents
• • PPC (peripheral protection controller) used as a secure gate to block or propagate secure/nonsecure and privileged/unprivileged transaction towards AHB agents
• • TrustZone block-based MPC firewalls used as secure gates to filter secure/nonsecure, privileged/unprivileged access towards internal SRAMs
• • TrustZone watermark MPC firewalls used as secure gates to filter secure/nonsecure, privileged/unprivileged access towards external memories

AHB and APB peripherals can be categorized as:

• • Privileged: peripherals protected by an AHB/APB firewall stub that is controlled from TZSC to define privilege properties
• • Secure: peripherals are always protected by an AHB/APB firewall stub. These peripherals are always secure (such as TZIC)
• • Securable: peripherals protected by an AHB/APB firewall stub that is controlled from TZSC to define security properties (optional)
• • Nonsecure and unprivileged: peripherals connected directly to AHB/APB interconnect without any secure gate
• • TrustZone-aware: peripherals connected directly to AHB or APB bus and implementing a specific TrustZone behavior (such as a subset of registers being secure). TrustZone-aware AHB masters always drive HNONSEC signal according to their security mode (such as Armv8-M core or DMA)

Application information

The TZSC (MPCWM), TZIC, and MPCBB can be used in one of the following ways:

• • Programmed during secure boot only, locked and not changed afterwards
• • Dynamically reprogrammed when using specific application code or secure kernel (microvisor). When not locked, MPCWM regions and MPCBB secure blocks can be changed by secure software executing from the secure FLASH region or secure SRAM. The same remark applies to the GTZC1_TZSC_SECCFGRn/PRIVCFGRn registers that define the secure/privileged state of each peripheral.

The Armv8-M security architecture with secure, securable, and TrustZone-aware peripherals is shown in the figure below.

Figure 13. GTZC in Armv8-M subsystem block diagram

5.3 GTZC implementation

The devices embed the following GTZC features.

Table 25. GTZC features

The tables below show the GTZC subblocks address offset versus GTZC base address (refer to Section 2.3.2: Memory map and register boundary addresses for GTZC base address).

Table 26. GTZC sub-blocks address offset

The table below describes the characteristics of the available MPCWM.

Table 27. MPCWM resource assignment

The table below describes the characteristics of the available MPCBB.

Table 28. MPCBB resource assignment

5.4 GTZC functional description

5.4.1 GTZC block diagram

Figure 14 describes the combined feature of TZSC (MPCWM), TZIC, and MPCBB. Each subblock is controlled by its own AHB configuration port.

The TZSC defines which peripheral is secured and/or privileged. The privileged configuration bit of a peripheral can be modified by a secure privileged transaction when the peripheral is configured as secure. Otherwise, a privileged transaction (nonsecure) is sufficient.

On the opposite, the secure configuration bit of a peripheral can be modified only with a secure privileged transaction if the peripheral is configured as privileged. Otherwise, a secure transaction (unprivileged) is sufficient.

The MPCBB secure configuration bit of a given SRAM block can be modified only with a secure privileged transaction if the same SRAM block is configured as privileged. Otherwise, a secure transaction (unprivileged) is sufficient.

The TZIC gathers illegal events generated within the system when an illegal access is detected. TZIC can then generate a secure interrupt towards the CPU if needed.

Figure 14. GTZC block diagram

5.4.2 Illegal access definition

Three different types of illegal access (ILA) exist:

• • Illegal nonsecure access

Any nonsecure transaction trying to write a secure resource is considered as illegal: consequently, the addressed resource generates an illegal access interrupt for illegal write access and a bus error for illegal fetch access. Some exceptions exist on secure and privileged configuration registers: the latter ones authorize nonsecure read access

to secure registers (see GTZC1_TZSC_SECCFG _n and GTZC1_TZSC_PRIVCFG _n ).

• • Illegal secure access

Any secure transaction trying to access a nonsecure block in internal block-based SRAM or watermarked memory is considered as illegal.

Correct TZIC settings enable the capture of the associated event and then generate the GTZC1_TZIC interrupt to the NVIC. This applies to read, write, and execute accesses.

Concerning the MPCBB controller, there is an option to ignore secure data read/write access on nonsecure SRAM blocks, by setting the SRWILADIS bit in the GTZC1_MPCBB _x _CR register. Secure read and write data transactions are then allowed on nonsecure SRAM blocks, while secure execution access remains not allowed.

Any secure execute transaction trying to access a nonsecure peripheral register is considered as illegal and generates a bus error.

• • Illegal unprivileged access

Any unprivileged transaction trying to access a privileged resource is considered as illegal. There is no illegal access event generated for illegal read and write access. The addressed resource follows a silent-fail behavior, returning all zero data for read and ignoring any write. No bus error is generated. A bus error is generated when any unprivileged execute transaction tries to access a privileged memory.

5.4.3 TrustZone security controller (TZSC)

The TZSC is composed of a configurable set of registers, providing the following features:

• • The control of secure and privileged state for all peripherals is done through:
  • – GTZC1_TZSC_SECCFG _n registers to control AHB/APB firewall stubs for the securable peripherals
  • – GTZC1_TZSC_PRIVCFG _n registers to control AHB/APB firewall stubs for the privileged peripherals
• • For watermark memory protection controller (external memories and backup SRAM), two independent regions can be defined and the following fields are used to program:
  • – The start of the first protected subregion on external memory/backup SRAM: SUBA_START[10:0]
  • – The length of the first protected subregion on external memory/backup SRAM: SUBA_LENGTH[11:0]
  • – The start of the second protected subregion on external memory/backup SRAM: SUBB_START[10:0]
  • – The length of the second protected subregion on external memory/backup SRAM: SUBB_LENGTH[11:0]

A control register for each subregion can be used to enable/disable the watermark memory protection controller as well as defining the right attributes of each subregion.

Figure 15. Watermark memory protection controller (region x/sub-regions A and B)

In the figure above, region x represents the external memory region (such as XSPI1 bank). Secure and privileged attributes of subregions A and B are independently configurable. When no subregions are defined or enabled on the region x, then the default attribute of the region x is set as “secure-privileged”.

The tables below describe the secure/privileged properties of the common area of subregion A and B when an overlap exists.

Table 29. Secure properties of sub-regions A and B

Table 30. Privileged properties of sub-regions A and B

5.4.4 Memory protection controller - block based (MPCBB)

The MPCBB is composed of a configurable set of registers allowing security and privileged policy to be defined for internal SRAM memories. The security and privileged policy can be individually configured per each 512-byte block of SRAM.

Figure 16. MPCBB block diagram

In order to set up the MPCBB, the following actions are needed (for example at boot time):

• • Secure firmware must define which memory blocks are secure by setting the correct bits in GTZC1_MPCBBx_SECCFGRn.
• • Privileged firmware must define which memory blocks are privileged by setting the correct bits in GTZC1_MPCBBx_PRIVCFGRn.

An MPCBB superblock is made of 32 consecutive blocks. For each superblock, a secure application can lock all related secure/privileged bits using the correct bits in GTZC1_MPCBBx_CFGLOCK. This lock remains active until the next system reset.

Note: The block size is 512 bytes. The superblock size is 512 x 32 = 16 Kbytes.

5.4.5 TrustZone illegal access controller (TZIC)

The TZIC concentrates all illegal access source events. It is used only when the system is TrustZone enabled (TZEN = 1).

TZIC allows the trace (flag) of which event triggered the secure illegal access interrupt. Register masks (GTZC1_TZIC_IERx) are available to filter unwanted events. On an unmasked illegal event, TZIC generates the GTZC1_IRQn interrupt to the NVIC.

For each illegal event source, a status flag and a clear bit exist (respectively within GTZC1_TZIC_SRx and GTZC1_TZIC_FCRx). The reset value of mask registers (GTZC1_TZIC_IERx) is such that all events are masked.

5.4.6 Power-on/reset state

The power-on and reset state of the TZSC clear to 0 all bits of GTZC1_TZSC_SECCFGRn and GTZC1_TZSC_PRIVCFGRn, meaning that all securable peripherals are respectively set to nonsecure and unprivileged.

For internal SRAMs, all GTZC1_MPCBBx_SECCFGRn and GTZC1_MPCBBx_PRIVCFGRn are set:

• • When TrustZone security is enabled at system level (TZEN = 1), to 0xFFFF FFFF, making these internal memories block secure and privileged by default
• • When TrustZone security is disabled at system level (TZEN = 0), to 0x0000 0000, making these internal memories block nonsecure and unprivileged by default

For external memories MPCWMx:

• • All GTZC1_TZSC_MPCWMxyR registers are set to 0x0000 0000, making these memories secure and privileged by default when TrustZone security is enabled at system level (TZEN = 1)
• • When TrustZone security is disabled at system level (TZEN = 0), GTZC1_TZSC_PMCWMxyR registers are not accessible and these memories are nonsecure and unprivileged.

Secure boot code can then program the security settings, making components secure or not as needed.

5.5 GTZC interrupts

TZIC is a secure peripheral, which systematically generates an illegal access event when accessed by a nonsecure access. The MPCBB and TZSC are TrustZone-aware peripherals, meaning that secure and nonsecure registers coexist within the peripheral.

Table 31. GTZC interrupt request

5.6 GTZC1 TZSC registers

All registers can only be accessed in words (32-bit).

5.6.1 GTZC1 TZSC control register (GTZC1_TZSC_CR)

Address offset: 0x000

Reset value: 0x0000 0000

Secure privileged access only.

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 LCK : Lock the configuration of GTZC1_TZSC_SECCFGRn and GTZC1_TZSC_PRIVCFGRn registers until next reset

This bit is cleared by default and once set, it can not be reset until system reset.

0: Configuration of all GTZC1_TZSC_SECCFGRn and GTZC1_TZSC_PRIVCFGRn registers not locked

1: Configuration of all GTZC1_TZSC_SECCFGRn and GTZC1_TZSC_PRIVCFGRn registers locked

5.6.2 GTZC1 TZSC secure configuration register 1 (GTZC1_TZSC_SECCFGR1)

Address offset: 0x010

Reset value: 0x0000 0000

Write-secure access only.

This register can be written only by secure privileged transaction when the corresponding GTZC1_TZSC_PRIVCFGR1 register bit is set to 1. If a given PRIV bit is not set, the equivalent SEC bit can be written by secure unprivileged transaction.

Read accesses are authorized for any type of transactions, secure or not, privileged or not.

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 LPTIM2SEC : Secure access mode for LPTIM2

0: Nonsecure

1: Secure

Bits 16:14 Reserved, must be kept at reset value.

Bit 13 I2C1SEC : Secure access mode for I2C1

0: Nonsecure

1: Secure

Bits 12:8 Reserved, must be kept at reset value.

Bit 7 IWDGSEC : Secure access mode for IWDG

0: Nonsecure

1: Secure

Bits 6:1 Reserved, must be kept at reset value.

Bit 0 TIM2SEC : Secure access mode for TIM2

0: Nonsecure

1: Secure

5.6.3 GTZC1 TZSC secure configuration register 2 (GTZC1_TZSC_SECCFGR2)

Address offset: 0x014

Reset value: 0x0000 0000

Write-secure access only.

This register can be written only by a secure privileged transaction when the corresponding GTZC1_TZSC_PRIVCFGR2 register bit is set to 1. If a given PRIV is not set, the equivalent SEC bit can be written by a secure unprivileged transaction.

Read accesses are authorized for any type of transactions, secure or not, privileged or not.

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 ADC4SEC : Secure access mode for ADC4

0: Nonsecure

1: Secure

Bits 23:20 Reserved, must be kept at reset value.

Bit 19 LPTIM1SEC : Secure access mode for LPTIM1

0: Nonsecure

1: Secure

Bit 18 I2C3SEC : Secure access mode for I2C3

0: Nonsecure

1: Secure

Bit 17 LPUART1SEC : Secure access mode for LPUART1

0: Nonsecure

1: Secure

Bit 16 SPI3SEC : Secure access mode for SPI3

0: Nonsecure

1: Secure

Bit 15 USB1SEC : Secure access mode for USB1

0: Nonsecure

1: Secure

Note: This bit is reserved on STM32WBA23xx devices

Bits 14:8 Reserved, must be kept at reset value.

Bit 7 SAI1SEC : Secure access mode for SAI1

0: Nonsecure

1: Secure

Bit 6 TIM17SEC : Secure access mode for TIM17

0: Nonsecure

1: Secure

Bit 5 TIM16SEC : Secure access mode for TIM16

0: Nonsecure

1: Secure

Bit 4 Reserved, must be kept at reset value.

Bit 3 USART1SEC : Secure access mode for USART1

0: Nonsecure

1: Secure

Bits 2:0 Reserved, must be kept at reset value.

5.6.4 GTZC1 TZSC secure configuration register 3 (GTZC1_TZSC_SECCFGR3)

Address offset: 0x018

Reset value: 0x0000 0000

Write-secure access only.

This register can be written only by a secure privileged transaction when the corresponding GTZC1_TZSC_PRIVCFGR3 register bit is set to 1. If a given PRIV is not set, the equivalent SEC bit can be written by a secure unprivileged transaction.

Read accesses are authorized for any type of transactions, secure or not, privileged or not.

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 PTACONVSEC : Secure access mode for PTACONV

0: Nonsecure

1: Secure

Bit 23 RADIOSEC : Secure access mode for 2.4 GHz RADIO

0: Nonsecure

1: Secure

Bit 22 RAMCFGSEC : Secure access mode for RAMCFG

0: Nonsecure

1: Secure

Bit 21 Reserved, must be kept at reset value.

Bit 20 XSPI1SEC : Secure access mode for XSPI1 and DLYBXS1

0: Nonsecure

1: Secure

Bits 19:17 Reserved, must be kept at reset value.

Bit 16 PKASEC : Secure access mode for PKA

0: Nonsecure

1: Secure

Bits 15:14 Reserved, must be kept at reset value.

Bit 13 RNGSEC : Secure access mode for RNG

0: Nonsecure

1: Secure

Bit 12 HASHSEC : Secure access mode for HASH

0: Nonsecure

1: Secure

Bit 11 AESSEC : Secure access mode for AES

0: Nonsecure

1: Secure

Bits 10:7 Reserved, must be kept at reset value.

Bit 6 ICACHE_REGSEC : Secure access mode for ICACHE registers

0: Nonsecure

1: Secure

Bits 5:4 Reserved, must be kept at reset value.

Bit 3 CRCSEC : Secure access mode for CRC

0: Nonsecure

1: Secure

Bits 2:0 Reserved, must be kept at reset value.

5.6.5 GTZC1 TZSC privilege configuration register 1 (GTZC1_TZSC_PRIVCFGR1)

Address offset: 0x020

Reset value: 0x0000 0000

Write-privileged access only.

This register can be written only by a secure privileged transaction when the corresponding GTZC1_TZSC_SECCFGR1 register bit is set to 1. If a given SEC bit is not set, the equivalent PRIV bit can be written by a nonsecure privileged transaction.

Read accesses are authorized for any type of transactions, secure or not, privileged or not.

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 LPTIM2PRIV : Privileged access mode for LPTIM2

0: Unprivileged

1: Privileged

Bits 16:14 Reserved, must be kept at reset value.

Bit 13 I2C1PRIV : Privileged access mode for I2C1

0: Unprivileged

1: Privileged

Bits 12:8 Reserved, must be kept at reset value.

Bit 7 IWDGPRIV : Privileged access mode for IWDG

0: Unprivileged

1: Privileged

Bits 6:1 Reserved, must be kept at reset value.

Bit 0 TIM2PRIV : Privileged access mode for TIM2

0: Unprivileged

1: Privileged

5.6.6 GTZC1 TZSC privilege configuration register 2 (GTZC1_TZSC_PRIVCFGR2)

Address offset: 0x024

Reset value: 0x0000 0000

Write-privileged access only.

This register can be written only by a secure privileged transaction when the corresponding GTZC1_TZSC_SECCFGR2 register bit is set to 1. If a given SEC bit is not set, the equivalent PRIV bit can be written by a nonsecure privileged transaction.

Read accesses are authorized for any type of transactions, secure or not, privileged or not.

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 ADC4PRIV : Privileged access mode for ADC4

0: Unprivileged

1: Privileged

Bits 23:20 Reserved, must be kept at reset value.

Bit 19 LPTIM1PRIV : Privileged access mode for LPTIM1

0: Unprivileged

1: Privileged

Bit 18 I2C3PRIV : Privileged access mode for I2C3

0: Unprivileged

1: Privileged

Bit 17 LPUART1PRIV : Privileged access mode for LPUART1

0: Unprivileged

1: Privileged

Bit 16 SPI3PRIV : Privileged access mode for SPI3

0: Unprivileged

1: Privileged

Bit 15 USBPRIV : Privileged access mode for USB

0: Unprivileged

1: Privileged

Note: This bit is reserved on STM32WBA23xx devices

Bits 14:8 Reserved, must be kept at reset value.

Bit 7 SAI1PRIV : Privileged access mode for SAI1

0: Unprivileged

1: Privileged

Bit 6 TIM17PRIV : Privileged access mode for TIM17

0: Unprivileged

1: Privileged

Bit 5 TIM16PRIV : Privileged access mode for TIM16

0: Unprivileged

1: Privileged

Bit 4 Reserved, must be kept at reset value.

Bit 3 USART1PRIV : Privileged access mode for USART1

0: Unprivileged

1: Privileged

Bits 2:0 Reserved, must be kept at reset value.

5.6.7 GTZC1 TZSC privilege configuration register 3 (GTZC1_TZSC_PRIVCFGR3)

Address offset: 0x028

Reset value: 0x0000 0000

Write-privileged access only.

This register can be written only by a secure privileged transaction when the corresponding GTZC1_TZSC_SECCFGR3 register bit is set to 1. If a given SEC bit is not set, the equivalent PRIV bit can be written by a nonsecure privileged transaction.

Read accesses are authorized for any type of transactions, secure or not, privileged or not.

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 PTACONVPRIV : Privileged access mode for PTACONV

0: Unprivileged

1: Privileged

Bit 23 RADIOPRIV : Privileged access mode for 2.4 GHz RADIO

0: Unprivileged

1: Privileged

Bit 22 RAMCFGPRIV : Privileged access mode for RAMCFG

0: Unprivileged

1: Privileged

Bit 21 Reserved, must be kept at reset value.

Bit 20 XSPI1PRIV : Privileged access mode for XSPI1 and DLYBXS1

0: Unprivileged

1: Privileged

Bits 19:17 Reserved, must be kept at reset value.

Bit 16 PKAPRIV : Privileged access mode for PKA

0: Unprivileged

1: Privileged

Bits 15:14 Reserved, must be kept at reset value.

Bit 13 RNGPRIV : Privileged access mode for RNG

0: Unprivileged

1: Privileged

Bit 12 HASHPRIV : Privileged access mode for HASH

0: Unprivileged

1: Privileged

Bit 11 AESPRIV : Privileged access mode for AES

0: Unprivileged

1: Privileged

Bits 10:7 Reserved, must be kept at reset value.

Bit 6 ICACHE_REGPRIV : Privileged access mode for ICACHE registers

0: Unprivileged

1: Privileged

Bits 5:4 Reserved, must be kept at reset value.

Bit 3 CRCPRIV : Privileged access mode for CRC

0: Unprivileged

1: Privileged

Bits 2:0 Reserved, must be kept at reset value.

5.6.8 GTZC1 TZSC memory 1 subregion z watermark configuration register (GTZC1_TZSC_MPCWM1zCFGR) (z = A to B)

Address offset: Block A: 0x040

Address offset: Block B: 0x048

Reset value: 0x0000 0000

Secure privilege access only.

Note: Some registers are only available on some devices in the STM32WBA2. Refer to the device datasheet for availability of its associated memory region.

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 PRIV : Privileged sub-region z

This bit is taken into account only if SREN is set.

0: Privileged and unprivileged accesses are granted in sub-region z.

1: Only privileged accesses are granted in sub-region z.

Bit 8 SEC : Secure sub-region z

This bit is taken into account only if SREN is set.

0: Only nonsecure data accesses are granted to sub-region z.

1: Only secure data accesses are granted to sub-region z.

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 SRLOCK : Sub-region z lock

This bit, once set, can be cleared only by a system reset.

0: GTZC1_TZSC_MPCWM1zCFGR, GTZC1_TZSC_MPCWM1zR can be written.

1: Writes to GTZC1_TZSC_MPCWM1zCFGR, GTZC1_TZSC_MPCWM1zR are ignored.

Bit 0 SREN : Sub-region z enable

0: Sub-region z is disabled. Access control applies to any access between this sub-region start- and end-addresses.

1: Sub-region z is enabled. Access control defined in GTZC1_TZSC_MPCWM1zCFGR applies to any access between this sub-region start- and end-addresses, defined in GTZC1_TZSC_MPCWM1zR.

5.6.9 GTZC1 TZSC memory 1 subregion A watermark register (GTZC1_TZSC_MPCWM1AR)

Address offset: 0x044

Reset value: 0x0000 0000

Secure privilege access only.

When SUBA_START + SUBA_LENGTH is higher than the maximum size allowed for the memory, a saturation of SUBA_LENGTH is applied automatically.

When an overlap of subregion A and B exists, secure/privileged attributes of both sub-regions apply on the common section (see Section 5.4.3 ).

Note: Some registers are only available on some devices in the STM32WBA2 series. Refer to the device datasheet for availability of its associated memory region.

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 SUBA_LENGTH[11:0] : Length of sub-region A

This field defines the length of the sub-region A, to be multiplied by the granularity defined in Table 27 .

When SUBA_START + SUBA_LENGTH is higher than the maximum size allowed for the memory, a saturation of SUBA_LENGTH is applied automatically.

If SUBA_LENGTH = 0, the sub-region A is disabled. (SREN bit in GTZC1_TZSC_MPCMW1ACFGR is cleared).

Bits 15:11 Reserved, must be kept at reset value.

Bits 10:0 SUBA_START[10:0] : Start of sub-region A

This field defines the address offset of the sub-region A, to be multiplied by the granularity defined in Table 27 , versus the start of memory bank base address.

5.6.10 GTZC1 TZSC memory 1 subregion B watermark register (GTZC1_TZSC_MPCWM1BR)

Address offset: 0x04C

Reset value: 0x0000 0000

Secure privilege access only.

When SUBB_START + SUBB_LENGTH is higher than the maximum size allowed for the memory, a saturation of SUBB_LENGTH is applied automatically.

When an overlap of subregion A and B exists, secure/privileged attributes of both subregions apply on the common section (see Section 5.4.3 ).

Note: Some registers are only available on some devices in the STM32WBA2. Refer to the device datasheet for availability of its associated memory region.

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 SUBB_LENGTH[11:0] : Length of sub-region B

This field defines the length of the sub-region B, to be multiplied by the granularity defined in Table 27 .

When SUBB_START + SUBB_LENGTH is higher than the maximum size allowed for the memory, a saturation of SUBB_LENGTH is applied automatically.

If SUBB_LENGTH = 0, the sub-region B is disabled. (SREN bit in GTZC1_TZSC_MPCMW1BCFGR is cleared).

Bits 15:11 Reserved, must be kept at reset value.

Bits 10:0 SUBB_START[10:0] : Start of sub-region B

This field defines the address offset of the sub-region B, to be multiplied by the granularity defined in Table 27 , versus the start of the of memory bank base address.

5.6.11 GTZC1 TZSC register map

Table 32. GTZC1 TZSC register map and reset values

Table 32. GTZC1 TZSC register map and reset values (continued)

Refer to Table 26: GTZC sub-blocks address offset .

5.7 GTZC1 TZIC registers

All registers can only be accessed in words (32 bits).

5.7.1 GTZC1 TZIC interrupt enable register 1 (GTZC1_TZIC_IER1)

Address offset: 0x000

Reset value: 0x0000 0000

Secure privileged access only.

This register is used to enable interrupt of illegal access.

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 LPTIM2IE : Illegal access interrupt enable for LPTIM2

0: Interrupt disabled

1: Interrupt enabled

Bits 16:14 Reserved, must be kept at reset value.

Bit 13 I2C1IE : Illegal access interrupt enable for I2C1

0: Interrupt disabled

1: Interrupt enabled

Bits 12:8 Reserved, must be kept at reset value.

Bit 7 IWDGIE : Illegal access interrupt enable for IWDG

0: Interrupt disabled

1: Interrupt enabled

Bits 6:1 Reserved, must be kept at reset value.

Bit 0 TIM2IE : Illegal access interrupt enable for TIM2

0: Interrupt disabled

1: Interrupt enabled

5.7.2 GTZC1 TZIC interrupt enable register 2 (GTZC1_TZIC_IER2)

Address offset: 0x004

Reset value: 0x0000 0000

Secure privileged access only.

This register is used to enable interrupt of illegal access.

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 ADC4IE : Illegal access interrupt enable for ADC4

0: Interrupt disabled

1: Interrupt enabled

Bits 23:20 Reserved, must be kept at reset value.

Bit 19 LPTIM1IE : Illegal access interrupt enable for LPTIM1

0: Interrupt disabled

1: Interrupt enabled

Bit 18 I2C3IE : Illegal access interrupt enable for I2C3

0: Interrupt disabled

1: Interrupt enabled

Bit 17 LPUART1IE : Illegal access interrupt enable for LPUART1

0: Interrupt disabled

1: Interrupt enabled

Bit 16 SPI3IE : Illegal access interrupt enable for SPI3

0: Interrupt disabled

1: Interrupt enabled

Bit 15 USBIE : Illegal access interrupt enable for USB

0: Interrupt disabled

1: Interrupt enabled

Note: This bit is reserved on STM32WBA23xx devices

Bits 14:8 Reserved, must be kept at reset value.

Bit 7 SAI1IE : Illegal access interrupt enable for SAI1

0: Interrupt disabled

1: Interrupt enabled

Bit 6 TIM17IE : Illegal access interrupt enable for TIM17

0: Interrupt disabled

1: Interrupt enabled

Bit 5 TIM16IE : Illegal access interrupt enable for TIM16

0: Interrupt disabled

1: Interrupt enabled

Bit 4 Reserved, must be kept at reset value.

Bit 3 USART1IE : Illegal access interrupt enable for USART1

0: Interrupt disabled

1: Interrupt enabled

Bits 2:0 Reserved, must be kept at reset value.

5.7.3 GTZC1 TZIC interrupt enable register 3 (GTZC1_TZIC_IER3)

Address offset: 0x008

Reset value: 0x0000 0000

Secure privileged access only.

This register is used to enable interrupt of illegal access.

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 PTACONVIE : Illegal access interrupt enable for PTACONV

0: Interrupt disabled

1: Interrupt enabled

Bit 23 RADIOIE : Illegal access interrupt enable for 2.4 GHz RADIO

0: Interrupt disabled

1: Interrupt enabled

Bit 22 RAMCFGIE : Illegal access interrupt enable for RAMCFG

0: Interrupt disabled

1: Interrupt enabled

Bit 21 Reserved, must be kept at reset value.

Bit 20 XSPI1IE : Illegal access interrupt enable for XSPI1 and DLYBXS1

0: Interrupt disabled

1: Interrupt enabled

Bits 19:17 Reserved, must be kept at reset value.

Bit 16 PKAIE : Illegal access interrupt enable for PKA

0: Interrupt disabled

1: Interrupt enabled

Bits 15:14 Reserved, must be kept at reset value.

Bit 13 RNGIE : Illegal access interrupt enable for RNG

0: Interrupt disabled

1: Interrupt enabled

Bit 12 HASHIE : Illegal access interrupt enable for HASH

0: Interrupt disabled

1: Interrupt enabled

Bit 11 AESIE : Illegal access interrupt enable for AES

0: Interrupt disabled

1: Interrupt enabled

Bits 10:7 Reserved, must be kept at reset value.

Bit 6 ICACHE_REGIE : Illegal access interrupt enable for ICACHE registers

0: Interrupt disabled

1: Interrupt enabled

Bits 5:4 Reserved, must be kept at reset value.

Bit 3 CRCIE : Illegal access interrupt enable for CRC

0: Interrupt disabled

1: Interrupt enabled

Bits 2:0 Reserved, must be kept at reset value.

5.7.4 GTZC1 TZIC interrupt enable register 4 (GTZC1_TZIC_IER4)

Address offset: 0x00C

Reset value: 0x0000 0000

Secure privileged access only.

This register is used to enable interrupt of illegal access.

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 MPCBB2IE : Illegal access interrupt enable for MPCBB2

0: Interrupt disabled

1: Interrupt enabled

Bit 24 SRAM2IE : Illegal access interrupt enable for SRAM2

0: Interrupt disabled

1: Interrupt enabled

1. Bit 23 MPCBB1IE : Illegal access interrupt enable for MPCBB1
   0: Interrupt disabled
   1: Interrupt enabled
2. Bit 22 SRAM1IE : Illegal access interrupt enable for SRAM1
   0: Interrupt disabled
   1: Interrupt enabled
3. Bit 21 Reserved, must be kept at reset value.
4. Bit 20 MPCWM1MEM1IE : Illegal access interrupt enable for MPCWM1 protected external memory on XSPI1
   0: Interrupt disabled
   1: Interrupt enabled
5. Bits 19:16 Reserved, must be kept at reset value.
6. Bit 15 TZICIE : Illegal access interrupt enable for GTZC1 TZIC
   0: Interrupt disabled
   1: Interrupt enabled
7. Bit 14 TZSCIE : Illegal access interrupt enable for GTZC1 TZSC
   0: Interrupt disabled
   1: Interrupt enabled
8. Bit 13 EXTIIE : Illegal access interrupt enable for EXTI
   0: Interrupt disabled
   1: Interrupt enabled
9. Bit 12 Reserved, must be kept at reset value.
10. Bit 11 RCCIE : Illegal access interrupt enable for RCC
    0: Interrupt disabled
    1: Interrupt enabled
11. Bit 10 PWRIE : Illegal access interrupt enable for PWR
    0: Interrupt disabled
    1: Interrupt enabled
12. Bit 9 TAMPIE : Illegal access interrupt enable for TAMP
    0: Interrupt disabled
    1: Interrupt enabled
13. Bit 8 RTCIE : Illegal access interrupt enable for RTC
    0: Interrupt disabled
    1: Interrupt enabled
14. Bit 7 SYSCFGIE : Illegal access interrupt enable for SYSCFG
    0: Interrupt disabled
    1: Interrupt enabled
15. Bits 6:4 Reserved, must be kept at reset value.
16. Bit 3 OTFDEC1IE : Illegal access interrupt enable for OTFDEC1
    0: Interrupt disabled
    1: Interrupt enabled
17. Bit 2 FLASH_REGIE : Illegal access interrupt enable for FLASH interface
    0: Interrupt disabled
    1: Interrupt enabled

Bit 1 FLASHIE : Illegal access interrupt enable for FLASH memory

0: Interrupt disabled

1: Interrupt enabled

Bit 0 LPDMA1IE : Illegal access interrupt enable for LPDMA1

0: Interrupt disabled

1: Interrupt enabled

5.7.5 GTZC1 TZIC status register 1 (GTZC1_TZIC_SR1)

Address offset: 0x010

Reset value: 0x0000 0000

Secure privileged access only.

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 LPTIM2F : Illegal access flag for LPTIM2

0: No illegal access event

1: Illegal access event

Bits 16:14 Reserved, must be kept at reset value.

Bit 13 I2C1F : Illegal access flag for I2C1

0: No illegal access event

1: Illegal access event

Bits 12:8 Reserved, must be kept at reset value.

Bit 7 IWDGF : Illegal access flag for IWDG

0: No illegal access event

1: Illegal access event

Bits 6:1 Reserved, must be kept at reset value.

Bit 0 TIM2F : Illegal access flag for TIM2

0: No illegal access event

1: Illegal access event

5.7.6 GTZC1 TZIC status register 2 (GTZC1_TZIC_SR2)

Address offset: 0x014

Reset value: 0x0000 0000

Secure privileged access only.

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 ADC4F : Illegal access flag for ADC4

0: No illegal access event

1: Illegal access event

Bits 23:20 Reserved, must be kept at reset value.

Bit 19 LPTIM1F : Illegal access flag for LPTIM1

0: No illegal access event

1: Illegal access event

Bit 18 I2C3F : Illegal access flag for I2C3

0: No illegal access event

1: Illegal access event

Bit 17 LPUART1F : Illegal access flag for LPUART1

0: No illegal access event

1: Illegal access event

Bit 16 SPI3F : Illegal access flag for SPI3

0: No illegal access event

1: Illegal access event

Bit 15 USB1F : Illegal access flag for USB1

0: No illegal access event

1: Illegal access event

Note: This bit is reserved on STM32WBA23xx devices

Bits 14:8 Reserved, must be kept at reset value.

Bit 7 SAI1F : Illegal access flag for SAI1

0: No illegal access event

1: Illegal access event

Bit 6 TIM17F : Illegal access flag for TIM17

0: No illegal access event

1: Illegal access event

Bit 5 TIM16F : Illegal access flag for TIM16

0: No illegal access event

1: Illegal access event

Bit 4 Reserved, must be kept at reset value.

Bit 3 USART1F : Illegal access flag for USART1

0: No illegal access event

1: Illegal access event

Bits 2:0 Reserved, must be kept at reset value.

5.7.7 GTZC1 TZIC status register 3 (GTZC1_TZIC_SR3)

Address offset: 0x018

Reset value: 0x0000 0000

Secure privileged access only.

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 PTACONVF : Illegal access flag for PTACONV

0: No illegal access event

1: Illegal access event

Bit 23 RADIOF : Illegal access flag for 2.4 GHz RADIO

0: No illegal access event

1: Illegal access event

Bit 22 RAMCFGF : Illegal access flag for RAMCFG

0: No illegal access event

1: Illegal access event

Bit 21 Reserved, must be kept at reset value.

Bit 20 XSPI1F : Illegal access flag for XSPI1 and DLYBXS1

0: No illegal access event

1: Illegal access event

Bits 19:17 Reserved, must be kept at reset value.

Bit 16 PKAF : Illegal access flag for PKA

0: No illegal access event

1: Illegal access event

Bits 15:14 Reserved, must be kept at reset value.

Bit 13 RNGF : Illegal access flag for RNG

0: No illegal access event

1: Illegal access event

Bit 12 HASHF : Illegal access flag for HASH

0: No illegal access event

1: Illegal access event

Bit 11 AESF : Illegal access flag for AES

0: No illegal access event

1: Illegal access event

Bits 10:7 Reserved, must be kept at reset value.

Bit 6 ICACHE_REGF : Illegal access flag for ICACHE registers

0: No illegal access event

1: Illegal access event

Bits 5:4 Reserved, must be kept at reset value.

Bit 3 CRCF : Illegal access flag for CRC

0: No illegal access event

1: Illegal access event

Bits 2:0 Reserved, must be kept at reset value.

5.7.8 GTZC1 TZIC status register 4 (GTZC1_TZIC_SR4)

Address offset: 0x01C

Reset value: 0x0000 0000

Secure privileged access only.

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 MPCBB2F : Illegal access flag for MPCBB2

0: No illegal access event

1: Illegal access event

Bit 24 SRAM2F : Illegal access flag for SRAM2

0: No illegal access event

1: Illegal access event

Bit 23 MPCBB1F : Illegal access flag for MPCBB1

0: No illegal access event

1: Illegal access event

Bit 22 SRAM1F : Illegal access flag for SRAM1

0: No illegal access event

1: Illegal access event

Bit 21 Reserved, must be kept at reset value.

Bit 20 MPCWM1MEMF : Illegal access flag for MPCWM1 protected external memory

0: No illegal access event

1: Illegal access event

Bits 19:16 Reserved, must be kept at reset value.

Bit 15 TZICF : Illegal access flag for GTZC1 TZIC

0: No illegal access event

1: Illegal access event

Bit 14 TZSCF : Illegal access flag for GTZC1 TZSC

0: No illegal access event

1: Illegal access event

Bit 13 EXTIF : Illegal access flag for EXTI

0: No illegal access event

1: Illegal access event

Bit 12 Reserved, must be kept at reset value.

Bit 11 RCCF : Illegal access flag for RCC

0: No illegal access event

1: Illegal access event

Bit 10 PWRF : Illegal access flag for PWR

0: No illegal access event

1: Illegal access event

Bit 9 TAMPF : Illegal access flag for TAMP

0: No illegal access event

1: Illegal access event

Bit 8 RTCF : Illegal access flag for RTC

0: No illegal access event

1: Illegal access event

Bit 7 SYSCFGF : Illegal access flag for SYSCFG

0: No illegal access event

1: Illegal access event

Bits 6:4 Reserved, must be kept at reset value.

Bit 3 OTFDEC1F : Illegal access flag for OTFDEC1

0: No illegal access event

1: Illegal access event

Bit 2 FLASH_REGF : Illegal access flag for FLASH interface

0: No illegal access event

1: Illegal access event

Bit 1 FLASHF : Illegal access flag for FLASH memory

0: No illegal access event

1: Illegal access event

Bit 0 LPDMA1F : Illegal access flag for LPDMA1

0: No illegal access event

1: Illegal access event

5.7.9 GTZC1 TZIC flag clear register 1 (GTZC1_TZIC_FCR1)

Address offset: 0x020

Reset value: 0x0000 0000

Secure privileged access only.

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 CLPTIM2F : Clear the illegal access flag for LPTIM2

0: No action

1: Status flag cleared

Bits 16:14 Reserved, must be kept at reset value.

Bit 13 CI2C1F : Clear the illegal access flag for I2C1

0: No action

1: Status flag cleared

Bits 12:8 Reserved, must be kept at reset value.

Bit 7 CIWDGF : Clear the illegal access flag for IWDG

0: No action

1: Status flag cleared

Bits 6:1 Reserved, must be kept at reset value.

Bit 0 CTIM2F : Clear the illegal access flag for TIM2

0: No action

1: Status flag cleared

5.7.10 GTZC1 TZIC flag clear register 2 (GTZC1_TZIC_FCR2)

Address offset: 0x024

Reset value: 0x0000 0000

Secure privileged access only.

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 CADC4F : Clear the illegal access flag for ADC4

0: No action

1: Status flag cleared

Bits 23:20 Reserved, must be kept at reset value.

Bit 19 CLPTIM1F : Clear the illegal access flag for LPTIM1

0: No action

1: Status flag cleared

Bit 18 CI2C3F : Clear the illegal access flag for I2C3

0: No action

1: Status flag cleared

Bit 17 CLPUART1F : Clear the illegal access flag for LPUART1

0: No action

1: Status flag cleared

Bit 16 CSPI3F : Clear the illegal access flag for SPI3

0: No action

1: Status flag cleared

Bit 15 CUSBF : Clear the illegal access flag for USB

0: No action

1: Status flag cleared

Note: This bit is reserved on STM32WBA23xx devices

Bits 14:8 Reserved, must be kept at reset value.

Bit 7 CSA1F : Clear the illegal access flag for SAI1

0: No action

1: Status flag cleared

Bit 6 CTIM17F : Clear the illegal access flag for TIM17

0: No action

1: Status flag cleared

Bit 5 CTIM16F : Clear the illegal access flag for TIM16

0: No action

1: Status flag cleared

Bit 4 Reserved, must be kept at reset value.

Bit 3 CUSART1F : Clear the illegal access flag for USART1

0: No action

1: Status flag cleared

Bits 2:0 Reserved, must be kept at reset value.

5.7.11 GTZC1 TZIC flag clear register 3 (GTZC1_TZIC_FCR3)

Address offset: 0x028

Reset value: 0x0000 0000

Secure privileged access only.

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 CPTACONVF : Clear the illegal access flag for PTACONV

0: No action

1: Status flag cleared

Bit 23 CRADIOF : Clear the illegal access flag for 2.4 GHz RADIO

0: No action

1: Status flag cleared

Bit 22 CRAMCFGF : Clear the illegal access flag for RAMCFG

0: No action

1: Status flag cleared

Bit 21 Reserved, must be kept at reset value.

Bit 20 CXSPI1F : Clear the illegal access flag for XSPI1 and DLYBXS1

0: No action

1: Status flag cleared

Bits 19:17 Reserved, must be kept at reset value.

Bit 16 CPKAF : Clear the illegal access flag for PKA

0: No action

1: Status flag cleared

Bits 15:14 Reserved, must be kept at reset value.

Bit 13 CRNGF : Clear the illegal access flag for RNG

0: No action

1: Status flag cleared

Bit 12 CHASHF : Clear the illegal access flag for HASH

0: No action

1: Status flag cleared

Bit 11 CAESF : Clear the illegal access flag for AES

0: No action

1: Status flag cleared

Bits 10:7 Reserved, must be kept at reset value.

Bit 6 CICACHE_REGF : Clear the illegal access flag for ICACHE registers

0: No action

1: Status flag cleared

Bits 5:4 Reserved, must be kept at reset value.

Bit 3 CCRCF : Clear the illegal access flag for CRC

0: No action

1: Status flag cleared

Bits 2:0 Reserved, must be kept at reset value.

5.7.12 GTZC1 TZIC flag clear register 4 (GTZC1_TZIC_FCR4)

Address offset: 0x02C

Reset value: 0x0000 0000

Secure privileged access only.

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 CMPCBB2F : Clear the illegal access flag for MPCBB2

0: No action

1: Status flag cleared

Bit 24 CSRAM2F : Clear the illegal access flag for SRAM2

0: No action

1: Status flag cleared

Bit 23 CMPCBB1F : Clear the illegal access flag for MPCBB1

0: No action

1: Status flag cleared

Bit 22 CSRAM1F : Clear the illegal access flag for SRAM1

0: No action

1: Status flag cleared

Bit 21 Reserved, must be kept at reset value.

Bit 20 CMPCWM1MEM1F : Clear the illegal access flag for MPCWM1 protected external memory

0: No action

1: Status flag cleared

Bits 19:16 Reserved, must be kept at reset value.

1. Bit 15 CTZICF : Clear the illegal access flag for GTZC1 TZIC
   0: No action
   1: Status flag cleared
2. Bit 14 CTZSCF : Clear the illegal access flag for GTZC1 TZSC
   0: No action
   1: Status flag cleared
3. Bit 13 CEXTIF : Clear the illegal access flag for EXTI
   0: No action
   1: Status flag cleared
4. Bit 12 Reserved, must be kept at reset value.
5. Bit 11 CRCCF : Clear the illegal access flag for RCC
   0: No action
   1: Status flag cleared
6. Bit 10 CPWRF : Clear the illegal access flag for PWR
   0: No action
   1: Status flag cleared
7. Bit 9 CTAMPF : Clear the illegal access flag for TAMP
   0: No action
   1: Status flag cleared
8. Bit 8 CRTCF : Clear the illegal access flag for RTC
   0: No action
   1: Status flag cleared
9. Bit 7 CSYSCFGF : Clear the illegal access flag for SYSCFG
   0: No action
   1: Status flag cleared
10. Bits 6:4 Reserved, must be kept at reset value.
11. Bit 3 COTFDEC1F : Clear the illegal access flag for OTFDEC1
    0: No action
    1: Status flag cleared
12. Bit 2 CFLASH_REGF : Clear the illegal access flag for FLASH interface
    0: No action
    1: Status flag cleared
13. Bit 1 CFLASHF : Clear the illegal access flag for FLASH memory
    0: No action
    1: Status flag cleared
14. Bit 0 CLPDMA1F : Clear the illegal access flag for LPDMA1
    0: No action
    1: Status flag cleared

5.7.13 GTZC1 TZIC register map

Table 33. GTZC1 TZIC register map and reset values

Table 33. GTZC1 TZIC register map and reset values (continued)

Refer to Table 26: GTZC sub-blocks address offset .

5.8 GTZC1 MPCBB registers

All registers can only be accessed in words (32 bits).

5.8.1 GTZC1 MPCBB control register (GTZC1_MPCBBx_CR) (x = 1 to 2)

Address offset: 0x000

Reset value: 0x0000 0000

Secure privileged access only.

Bit 31 SRWILADIS : secure read/write illegal access disable

This bit disables the detection of an illegal access when a secure read/write transaction access a nonsecure blocks of the block-based SRAMx (secure fetch on nonsecure block is always considered illegal).

0: enabled, secure read/write access not allowed on nonsecure SRAMx block

1: disabled, secure read/write access allowed on nonsecure SRAMx block

Bit 30 INVSECSTATE : SRAM clocks security state

This bit is used to define the internal SRAM clocks control in RCC as secure or not.

0: SRAM clock is secured if a secure area exists in the MPCBBx. It is nonsecure if there is no secure area.

1: SRAM clock is nonsecure even if a secure area exists in the MPCBBx, and secure even if no secure block is set in the MPCBBx.

Bits 29:1 Reserved, must be kept at reset value.

Bit 0 GLOCK : Lock the control register of the MPCBBx until next reset

This bit is cleared by default and once set, it can not be reset until system reset.

0: Control register not locked

1: Control register locked

5.8.2 GTZC1 MPCBB1 configuration lock register
(GTZC1_MPCBB1_CFGLOCK)

Address offset: 0x010

Reset value: 0x0000 0000

Secure privileged access only.

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 SPLCK[3:0] : Security/privilege configuration lock super-block (n = 0 to 3)

This bit is set by software and can be cleared only by system reset.

0: GTZC1_MPCBB1_SECCFGGRn and GTZC1_MPCBB1_PRIVCFGGRn can be written.

1: Writes to GTZC1_MPCBB1_SECCFGGRn and GTZC1_MPCBB1_PRIVCFGGRn are ignored

5.8.3 GTZC1 MPCBB2 configuration lock register
(GTZC1_MPCBB2_CFGLOCK)

Address offset: 0x010

Reset value: 0x0000 0000

Secure privileged access only.

Bits 31:2 Reserved, must be kept at reset value.

Bits 1:0 SPLCK[1:0] : Security/privilege configuration lock super-block (n = 0 to 1)

This bit is set by software and can be cleared only by system reset.

0: GTZC1_MPCBB2_SECCFGn and GTZC1_MPCBB2_PRIVCFGn can be written.

1: Writes to GTZC1_MPCBB2_SECCFGn and GTZC1_MPCBB2_PRIVCFGn are ignored

5.8.4 GTZC1 MPCBB security configuration for superblock n register (GTZC1_MPCBBx_SECCFGn) (x = 1 to 2)

Address offset: 0x100 + 0x04 * n, (n = 0 to 1)

Reset value: 0xFFFF FFFF

The given reset value is valid when TZEN = 1. The reset value is 0x0000 0000 when TZEN = 0.

Write access to this register is secure only. Any read is allowed.

Bits 31:0 SEC[31:0] : Security configuration for block y (y = 0 to 31) in super block n

0: Nonsecure access only to block y, belonging to super-block n. Secure access is also allowed if the SRWILADIS bit is set in GTZC1_MPCBBx_CR.
1: Secure access only to block y, belonging to super-block n.

Unprivileged write to this bit is ignored if PRIVy bit is set in GTZC1_MPCBBx_PRIVCFGn.

Writes are ignored if SPLCKn bit is set in GTZC1_MPCBBx_CFGLOCK.

5.8.5 GTZC1 MPCBB1 security configuration for superblock n register (GTZC1_MPCBB1_SECCFGn)

Address offset: 0x100 + 0x04 * n, (n = 2 to 3)

Reset value: 0xFFFF FFFF

The given reset value is valid when TZEN = 1. The reset value is 0x0000 0000 when TZEN = 0.

Write access to this register is secure only. Any read is allowed.

Bits 31:0 SEC[31:0] : Security configuration for block y (y = 0 to 31) in super block n

0: Nonsecure access only to block y, belonging to super-block n. Secure access is also allowed if the SRWILADIS bit is set in GTZC1_MPCBB1_CR.

1: Secure access only to block y, belonging to super-block n.

Unprivileged write to this bit is ignored if PRIVy bit is set in GTZC1_MPCBB1_PRIVCFGRn.

Writes are ignored if SPLCKn bit is set in GTZC1_MPCBB1_CFGLOCK.

5.8.6 GTZC1 MPCBB privileged configuration for superblock n register (GTZC1_MPCBBx_PRIVCFGRn) (x = 1 to 2)

Address offset: 0x200 + 0x04 * n, (n = 0 to 1)

Reset value: 0xFFFF FFFF

The given reset value is valid when TZEN = 1. The reset value is 0x0000 0000 when TZEN = 0.

Write access to this register is privileged only. Any read is allowed.

Bits 31:0 PRIV[31:0] : Privileged configuration for block y (y = 0 to 31), belonging to super-block n.

0: Privileged and unprivileged access to block y, belonging to super-block n

1: Only privileged access to block y, belonging to super-block n

Nonsecure write to this bit is ignored if SECy bit is set in GTZC1_MPCBBx_SECCFGRn.

Writes are ignored if SPLCKn bit is set in GTZC1_MPCBBx_CFGLOCK.

5.8.7 GTZC1 MPCBB1 privileged configuration for superblock n register (GTZC1_MPCBB1_PRIVCFGRn)

Address offset: 0x200 + 0x04 * n, (n = 2 to 3)

Reset value: 0xFFFF FFFF

The given reset value is valid when TZEN = 1. The reset value is 0x0000 0000 when TZEN = 0.

Write access to this register is privileged only. Any read is allowed.

Bits 31:0 PRIV[31:0] : Privileged configuration for block y (y = 0 to 31), belonging to super-block n.

0: Privileged and unprivileged access to block y, belonging to super-block n

1: Only privileged access to block y, belonging to super-block n

Nonsecure write to this bit is ignored if SECy bit is set in GTZC1_MPCBB1_SECCFGFn.

Writes are ignored if SPLCKn bit is set in GTZC1_MPCBB1_CFGLOCK.

5.8.8 GTZC1 MPCBB1 register map

Table 34. GTZC1 MPCBB1 register map and reset values

Refer to Table 26: GTZC sub-blocks address offset .

Table 35. GTZC1 MPCBB2 register map and reset values

Refer to Section 2.3: Memory organization for the register boundary addresses.