RM0521-STM32WBA2

This reference manual targets application developers. It provides complete information on how to use the STM32WBA2 microprocessor memory and peripherals.

The STM32WBA2 is a family of microprocessors with different packages and peripherals.

Refer to the corresponding datasheets for ordering information, mechanical and electrical device characteristics.

For information on the Arm ® , Cortex ® -M33 core, refer to the corresponding Technical Reference Manuals available on http://infocenter.arm.com .

The STM32WBA2 microprocessors include ST state-of-the-art patented technology.

Contents

4.4.2Armv8-M security extension of Cortex-M33 . . . . .88
4.4.3Memory and peripheral allocation using IDAU/SAU . . . . .88
4.4.4Memory and peripheral allocation using GTZC . . . . .90
4.4.5Managing security in TrustZone-aware peripherals . . . . .94
4.4.6Activating TrustZone security . . . . .100
4.4.7Deactivating TrustZone security . . . . .101
4.5Other resource isolations . . . . .101
4.5.1Temporal isolation using secure hide protection (HDP) . . . . .101
4.5.2RSSLIB functions . . . . .102
4.5.3Resource isolation using Cortex privileged mode . . . . .103
4.6Secure execution . . . . .107
4.6.1Memory protection unit (MPU) . . . . .107
4.6.2Embedded flash memory write protection . . . . .108
4.6.3Tamper detection and response . . . . .108
4.7Secure storage . . . . .110
4.7.1Unique ID . . . . .110
4.8Crypto engines . . . . .110
4.8.1Crypto engines features . . . . .111
4.8.2On-the-fly decryption engine (OTFDEC) . . . . .111
4.9Product life cycle . . . . .112
4.9.1Life cycle management with readout protection (RDP) . . . . .113
4.9.2Recommended option byte settings . . . . .116
4.10Access controlled debug . . . . .116
4.10.1Debug protection with readout protection (RDP) . . . . .116
4.11Software intellectual property protection and collaborative development . . . . .117
4.11.1Software intellectual property protection with RDP . . . . .118
4.11.2Software intellectual property protection with OTFDEC . . . . .118
4.11.3Other software intellectual property protections . . . . .119
5Global TrustZone® controller (GTZC) . . . . .120
5.1Introduction . . . . .120
5.2GTZC main features . . . . .120
5.3GTZC implementation . . . . .122
5.4GTZC functional description . . . . .123
5.4.1GTZC block diagram . . . . .123
5.4.2Illegal access definition . . . . .124
5.7.13GTZC1 TZIC register map .....157
5.8GTZC1 MPCBB registers .....158
5.8.1GTZC1 MPCBB control register (GTZC1_MPCBBx_CR) (x = 1 to 2) .....158
5.8.2GTZC1 MPCBB1 configuration lock register
(GTZC1_MPCBB1_CFGLOCK) .....		159
5.8.3GTZC1 MPCBB2 configuration lock register
(GTZC1_MPCBB2_CFGLOCK) .....		159
5.8.4GTZC1 MPCBB security configuration for superblock n register
(GTZC1_MPCBBx_SECCFGn) (x = 1 to 2) .....		160
5.8.5GTZC1 MPCBB1 security configuration for superblock n register
(GTZC1_MPCBB1_SECCFGn) .....		160
5.8.6GTZC1 MPCBB privileged configuration for superblock n
register (GTZC1_MPCBBx_PRIVCFGn) (x = 1 to 2) .....		161
5.8.7GTZC1 MPCBB1 privileged configuration for superblock n
register (GTZC1_MPCBB1_PRIVCFGn) .....		161
5.8.8GTZC1 MPCBB1 register map .....162
6RAMs configuration controller (RAMCFG) .....164
6.1Introduction .....164
6.2RAMCFG main features .....164
6.3RAMCFG functional description .....164
6.3.1Internal SRAM features .....164
6.3.2Internal SRAM parity .....165
6.3.3Internal SRAM write protection .....166
6.3.4Internal SRAM read access latency .....166
6.3.5Internal SRAM erase .....167
6.4RAMCFG low-power modes .....167
6.5RAMCFG interrupts .....167
6.6RAMCFG registers .....168
6.6.1RAMCFG SRAM1 control register (RAMCFG_M1CR) .....168
6.6.2RAMCFG SRAM1 interrupt status register (RAMCFG_M1ISR) .....169
6.6.3RAMCFG SRAM erase key register (RAMCFG_MxERKEYR) .....169
6.6.4RAMCFG SRAM2 control register (RAMCFG_M2CR) .....170
6.6.5RAMCFG SRAM2 interrupt enable register (RAMCFG_M2IER) .....171
6.6.6RAMCFG SRAM2 interrupt status register (RAMCFG_M2ISR) .....171
6.6.7RAMCFG SRAM2 parity error address register (RAMCFG_M2PEAR) .....172
6.6.8RAMCFG SRAM2 interrupt clear register (RAMCFG_M2ICR) .....173
6.6.9RAMCFG SRAM2 write protection register 1 .. (RAMCFG_M2WPR1) .....173
7.9FLASH registers . . . . .217
7.9.1FLASH access control register (FLASH_ACR) . . . . .217
7.9.2FLASH key register (FLASH_NSKEYR) . . . . .218
7.9.3FLASH secure key register (FLASH_SECKEYR) . . . . .219
7.9.4FLASH option key register (FLASH_OPTKEYR) . . . . .219
7.9.5FLASH power-down key register (FLASH_PDKEYR) . . . . .220
7.9.6FLASH status register (FLASH_NSSR) . . . . .220
7.9.7FLASH secure status register (FLASH_SECSR) . . . . .222
7.9.8FLASH control register (FLASH_NSCR1) . . . . .224
7.9.9FLASH secure control register (FLASH_SECCR1) . . . . .226
7.9.10FLASH ECC register (FLASH_ECCR) . . . . .227
7.9.11FLASH operation status register (FLASH_OPSR) . . . . .228
7.9.12FLASH control 2 register (FLASH_NSCR2) . . . . .229
7.9.13FLASH secure control 2 register (FLASH_SECCR2) . . . . .230
7.9.14FLASH option register (FLASH_OPTR) . . . . .230
7.9.15FLASH boot address 0 register (FLASH_NSBOOTADD0R) . . . . .232
7.9.16FLASH boot address 1 register (FLASH_NSBOOTADD1R) . . . . .233
7.9.17FLASH secure boot address 0 register (FLASH_SECBOOTADD0R) . . . . .233
7.9.18FLASH secure watermark register 1 (FLASH_SECWMR1) . . . . .234
7.9.19FLASH secure watermark register 2 (FLASH_SECWMR2) . . . . .235
7.9.20FLASH WRP area A address register (FLASH_WRPAR) . . . . .235
7.9.21FLASH WRP area B address register (FLASH_WRPBR) . . . . .236
7.9.22FLASH secure block based register x (FLASH_SECBBRx) . . . . .237
7.9.23FLASH secure HDP control register (FLASH_SECHDPCR) . . . . .237
7.9.24FLASH privilege configuration register (FLASH_PRIFCFGR) . . . . .238
7.9.25FLASH secure HDP extension register (FLASH_SECHDPEXTR) . . . . .239
7.9.26FLASH privilege block based register x (FLASH_PRIVBBRx) . . . . .239
7.9.27FLASH OEM1 key register 1 (FLASH_OEM1KEYR1) . . . . .240
7.9.28FLASH OEM1 key register 2 (FLASH_OEM1KEYR2) . . . . .240
7.9.29FLASH OEM1 key register 3 (FLASH_OEM1KEYR3) . . . . .241
7.9.30FLASH OEM1 key register 4 (FLASH_OEM1KEYR4) . . . . .241
7.9.31FLASH OEM2 key register 1 (FLASH_OEM2KEYR1) . . . . .242
7.9.32FLASH OEM2 key register 2 (FLASH_OEM2KEYR2) . . . . .242
7.9.33FLASH OEM2 key register 3 (FLASH_OEM2KEYR3) . . . . .243
7.9.34FLASH OEM2 key register 4 (FLASH_OEM2KEYR4) . . . . .243
7.9.35FLASH OEM key status register (FLASH_OEMKEYSR) . . . . .244
7.9.36FLASH register map . . . . .245
8Instruction cache (ICACHE) . . . . .249
8.1ICACHE introduction . . . . .249
8.2ICACHE main features . . . . .249
8.3ICACHE implementation . . . . .250
8.4ICACHE functional description . . . . .250
8.4.1ICACHE block diagram . . . . .251
8.4.2ICACHE reset and clocks . . . . .251
8.4.3ICACHE TAG memory . . . . .252
8.4.4Direct-mapped ICACHE (1-way cache) . . . . .253
8.4.5ICACHE enable . . . . .254
8.4.6Cacheable and noncacheable traffic . . . . .254
8.4.7Address remapping . . . . .255
8.4.8Cacheable accesses . . . . .257
8.4.9Dual-master cache . . . . .258
8.4.10ICACHE security . . . . .258
8.4.11ICACHE maintenance . . . . .258
8.4.12ICACHE performance monitoring . . . . .259
8.4.13ICACHE boot . . . . .259
8.5ICACHE low-power modes . . . . .259
8.6ICACHE error management and interrupts . . . . .260
8.7ICACHE registers . . . . .260
8.7.1ICACHE control register (ICACHE_CR) . . . . .260
8.7.2ICACHE status register (ICACHE_SR) . . . . .261
8.7.3ICACHE interrupt enable register (ICACHE_IER) . . . . .262
8.7.4ICACHE flag clear register (ICACHE_FCR) . . . . .262
8.7.5ICACHE hit monitor register (ICACHE_HMONR) . . . . .263
8.7.6ICACHE miss monitor register (ICACHE_MMONR) . . . . .263
8.7.7ICACHE region x configuration register (ICACHE_CRRx) . . . . .263
8.7.8ICACHE register map . . . . .264
9Radio system . . . . .266
9.1Introduction . . . . .266
9.2Main features . . . . .266
9.32.4 GHz RADIO implementation . . . . .267
9.4Functional description . . . . .267
9.4.1Block diagram . . . . .267
9.4.2Pins and internal signals .....267
9.4.3Transmit output power .....268
9.4.4Bluetooth AoA/AoD and channel sounding antenna selection .....269
9.4.5RXTX data SRAM access .....269
9.5Low-power modes .....270
10PTA converter (PTACONV) .....271
10.1PTACONV introduction .....271
10.2PTACONV main features .....271
10.3PTACONV functional description .....271
10.3.1PTACONV block diagram .....272
10.3.2PTACONV pins and internal signals .....272
10.3.3PTACONV protocols .....273
10.3.4PTACONV interface with the 2.4 GHz RADIO .....276
10.4PTACONV low-power modes .....276
10.5PTACONV registers .....278
10.5.1PTACONV active control register (PTACONV_ACTCR) .....278
10.5.2PTACONV priority control register (PTACONV_PRICR) .....279
10.5.3PTACONV control register (PTACONV_CR) .....279
10.5.4PTACONV register map .....281
11Power control (PWR) .....282
11.1Introduction .....282
11.2PWR main features .....282
11.3PWR pins and internal signals .....283
11.4PWR power supplies and supply domains .....285
11.4.1External power supplies .....286
11.4.2Application power supply schemes .....287
11.4.3Power-up and power-down power sequences .....288
11.4.4Independent analog peripherals supply .....288
11.4.5Independent USB transceiver supply .....288
11.4.6Independent RADIO peripheral supply .....288
11.4.7Backup domain .....288
11.4.8Internal regulators .....289
11.5PWR system supply voltage regulation .....289
11.5.1SMPS and LDO embedded regulators .....289
11.10.13PWR supply voltage monitoring status register (PWR_SVMSR) . . . . .336
11.10.14PWR wake-up status register (PWR_WUSR) . . . . .337
11.10.15PWR wake-up status clear register (PWR_WUSCR) . . . . .338
11.10.16PWR port A Standby I/O retention enable register
(PWR_IORETENRA) . . . . .		339
11.10.17PWR port A Standby I/O retention status register
(PWR_IORETRA) . . . . .		340
11.10.18PWR port B Standby I/O retention enable register
(PWR_IORETENRB) . . . . .		340
11.10.19PWR port B Standby I/O retention status register
(PWR_IORETRB) . . . . .		341
11.10.20PWR port C Standby I/O retention enable register
(PWR_IORETENRC) . . . . .		342
11.10.21PWR port C Standby I/O retention status register
(PWR_IORETRC) . . . . .		342
11.10.22PWR port H Standby I/O retention enable register
(PWR_IORETENRH) . . . . .		343
11.10.23PWR port H Standby I/O retention status register
(PWR_IORETRH) . . . . .		344
11.10.24PWR 2.4 GHz RADIO status and control register
(PWR_RADIOSCR) . . . . .		344
11.10.25PWR Stop 2 peripheral IOs retention register (PWR_S2RETR) . . . . .346
11.10.26PWR register map . . . . .347
12Reset and clock control (RCC) . . . . .350
12.1Introduction . . . . .350
12.2RCC pins and internal signals . . . . .350
12.3RCC reset functional description . . . . .350
12.3.1Power reset . . . . .350
12.3.2System reset . . . . .351
12.3.3Backup domain reset . . . . .352
12.3.4Individual peripheral reset . . . . .352
12.3.5CPU reset . . . . .352
12.4RCC clocks functional description . . . . .352
12.4.1HSE32 clock with trimming . . . . .354
12.4.2HSI16 clock . . . . .356
12.4.3PLL1 . . . . .357
12.4.4LSE clock . . . . .359
12.4.5LSI clock . . . . .360
12.4.6System clock (SYSCLK) selection . . . . .362
12.4.7Clock source frequency versus voltage scaling . . . . .365
12.4.8HSE32 clock security system (HSECSS) . . . . .365
12.4.9LSE clock security system on (LSECSS) . . . . .365
12.4.10ADC kernel clock . . . . .366
12.4.11RTC and TAMP kernel clock . . . . .366
12.4.122.4 GHz RADIO bus clocks . . . . .367
12.4.132.4 GHz RADIO kernel clocks . . . . .368
12.4.14Timer kernel clock . . . . .368
12.4.15Independent watchdog kernel clock . . . . .369
12.4.16USB kernel clock . . . . .369
12.4.17XSPI feedback clock delay . . . . .369
12.4.18SysTick calibration value register . . . . .369
12.4.19Clock-out capability . . . . .370
12.4.20Internal/external clock measurement . . . . .370
12.4.21Audio synchronization . . . . .371
12.4.22Peripheral clock gating and autonomous mode . . . . .373
12.5RCC security and privilege functional description . . . . .376
12.5.1RCC TrustZone ® security protection modes . . . . .376
12.5.2RCC privilege protection modes . . . . .378
12.6RCC low-power modes . . . . .379
12.7RCC interrupts . . . . .380
12.8RCC registers . . . . .381
12.8.1RCC clock control register (RCC_CR) . . . . .381
12.8.2RCC internal clock sources calibration register 3 (RCC_ICSCR3) . . . . .383
12.8.3RCC clock configuration register 1 (RCC_CFGR1) . . . . .384
12.8.4RCC clock configuration register 2 (RCC_CFGR2) . . . . .385
12.8.5RCC clock configuration register 3 (RCC_CFGR3) . . . . .386
12.8.6RCC PLL1 configuration register (RCC_PLL1CFGR) . . . . .387
12.8.7RCC PLL1 dividers register (RCC_PLL1DIVR) . . . . .389
12.8.8RCC PLL1 fractional divider register (RCC_PLL1FRACR) . . . . .390
12.8.9RCC clock interrupt enable register (RCC_CIER) . . . . .391
12.8.10RCC clock interrupt flag register (RCC_CIFR) . . . . .393
12.8.11RCC clock interrupt clear register (RCC_CICR) . . . . .395
12.8.12RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . .396
12.8.13RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . .397
12.8.14RCC AHB4 peripheral reset register (RCC_AHB4RSTR) . . . . .399
12.8.15RCC AHB5 peripheral reset register (RCC_AHB5RSTR) . . . . .400
12.8.16RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . .400
12.8.17RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . .401
12.8.18RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .402
12.8.19RCC APB7 peripheral reset register (RCC_APB7RSTR) . . . . .403
12.8.20RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . .405
12.8.21RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . .406
12.8.22RCC AHB4 peripheral clock enable register (RCC_AHB4ENR) . . . . .409
12.8.23RCC AHB5 peripheral clock enable register (RCC_AHB5ENR) . . . . .410
12.8.24RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . . .411
12.8.25RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . . .412
12.8.26RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .412
12.8.27RCC APB7 peripheral clock enable register (RCC_APB7ENR) . . . . .414
12.8.28RCC AHB1 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB1SMENR) . . . . .		415
12.8.29RCC AHB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB2SMENR) . . . . .		417
12.8.30RCC AHB4 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB4SMENR) . . . . .		420
12.8.31RCC AHB5 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB5SMENR) . . . . .		421
12.8.32RCC APB1 peripheral clocks enable in Sleep and Stop modes
register 1 (RCC_APB1SMENR1) . . . . .		422
12.8.33RCC APB1 peripheral clocks enable in Sleep and Stop modes
register 2 (RCC_APB1SMENR2) . . . . .		423
12.8.34RCC APB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_APB2SMENR) . . . . .		423
12.8.35RCC APB7 peripheral clock enable in Sleep and Stop modes register
(RCC_APB7SMENR) . . . . .		425
12.8.36RCC peripherals independent clock configuration register 1
(RCC_CCIPR1) . . . . .		427
12.8.37RCC peripherals independent clock configuration register 2
(RCC_CCIPR2) . . . . .		429
12.8.38RCC peripherals independent clock configuration register 3
(RCC_CCIPR3) . . . . .		430
12.8.39RCC backup domain control register (RCC_BDCR1) . . . . .431
12.8.40RCC Backup domain control register (RCC_BDCR2) . . . . .437
12.8.41RCC control/status register (RCC_CSR) . . . . .438
12.8.42RCC secure configuration register (RCC_SECCFGR) . . . . .439
12.8.43RCC privilege configuration register (RCC_PRIVCFGR) . . . . .441
12.8.44RCC audio synchronization control register (RCC_ASCR) . . . . .441
12.8.45RCC audio synchronization interrupt enable register (RCC_ASIER) . . .442
12.8.46RCC audio synchronization status register (RCC_ASSR) . . . . .443
12.8.47RCC audio synchronization counter register (RCC_ASCNTR) . . . . .444
12.8.48RCC audio synchronization auto-reautoreload register
(RCC_ASARR) . . . . .		445
12.8.49RCC audio synchronization capture register (RCC_ASCAR) . . . . .445
12.8.50RCC audio synchronization compare register (RCC_ASCOR) . . . . .446
12.8.51RCC clock configuration register 2 (RCC_CFGR4) . . . . .446
12.8.52RCC RADIO peripheral clock enable register (RCC_RADIOENR) . . . . .447
12.8.53RCC external clock sources calibration register 1(RCC_ECSCR1) . . . . .448
12.8.54RCC LSI key register (RCC_LSIKEYR) . . . . .449
12.8.55RCC register map . . . . .451
13General-purpose I/Os (GPIO) . . . . .458
13.1GPIO introduction . . . . .458
13.2GPIO main features . . . . .458
13.3GPIO implementation . . . . .458
13.4GPIO functional description . . . . .459
13.4.1GPIO general-purpose I/O . . . . .461
13.4.2GPIO pin alternate function multiplexer and mapping . . . . .461
13.4.3GPIO port control registers . . . . .462
13.4.4GPIO port data registers . . . . .462
13.4.5GPIO data bitwise handling . . . . .462
13.4.6GPIO locking mechanism . . . . .463
13.4.7GPIO alternate function input/output . . . . .463
13.4.8GPIO external interrupt/wake-up lines . . . . .463
13.4.9GPIO input configuration . . . . .464
13.4.10GPIO output configuration . . . . .464
13.4.11GPIO alternate function configuration . . . . .465
13.4.12GPIO analog configuration . . . . .466
13.4.13GPIO compensation cell . . . . .466
13.4.14GPIO Standby retention . . . . .466
13.4.15GPIO using the LSE oscillator pins as GPIOs . . . . .466
13.4.16GPIO using GPIO pins with RTC . . . . .466
13.4.17GPIO using PH3 as GPIO . . . . .467
13.4.18GPIO TrustZone® security . . . . .467
13.4.19GPIO privileged and unprivileged modes . . . . .468
13.5GPIO port A registers . . . . .469
13.5.1GPIO port A mode register (GPIOA_MODER) . . . . .469
13.5.2GPIO port A output type register (GPIOA_OTYPER) . . . . .470
13.5.3GPIO port A output speed register (GPIOA_OSPEEDR) . . . . .470
13.5.4GPIO port A pull-up/pull-down register (GPIOA_PUPDR) . . . . .471
13.5.5GPIO port A input data register (GPIOA_IDR) . . . . .472
13.5.6GPIO port A output data register (GPIOA_ODR) . . . . .472
13.5.7GPIO port A bit set/reset register (GPIOA_BSRR) . . . . .473
13.5.8GPIO port A configuration lock register (GPIOA_LCKR) . . . . .473
13.5.9GPIO port A alternate function low register (GPIOA_AFRL) . . . . .474
13.5.10GPIO port A alternate function high register (GPIOA_AFRH) . . . . .475
13.5.11GPIO port A bit reset register (GPIOA_BRR) . . . . .476
13.5.12GPIO port A secure configuration register (GPIOA_SECCFGR) . . . . .477
13.6GPIO port B registers . . . . .477
13.6.1GPIO port B mode register (GPIOB_MODER) . . . . .477
13.6.2GPIO port B output type register (GPIOB_OTYPER) . . . . .478
13.6.3GPIO port B output speed register (GPIOB_OSPEEDR) . . . . .479
13.6.4GPIO port B pull-up/pull-down register (GPIOB_PUPDR) . . . . .480
13.6.5GPIO port B input data register (GPIOB_IDR) . . . . .480
13.6.6GPIO port B output data register (GPIOB_ODR) . . . . .481
13.6.7GPIO port B bit set/reset register (GPIOB_BSRR) . . . . .482
13.6.8GPIO port B configuration lock register (GPIOB_LCKR) . . . . .482
13.6.9GPIO port B alternate function low register (GPIOB_AFRL) . . . . .484
13.6.10GPIO port B alternate function high register (GPIOB_AFRH) . . . . .485
13.6.11GPIO port B bit reset register (GPIOB_BRR) . . . . .485
13.6.12GPIO port B secure configuration register (GPIOB_SECCFGR) . . . . .486
13.7GPIO port C registers . . . . .487
13.7.1GPIO port C mode register (GPIOC_MODER) . . . . .487
13.7.2GPIO port C output type register (GPIOC_OTYPER) . . . . .488
13.7.3GPIO port C output speed register (GPIOC_OSPEEDR) . . . . .488
13.7.4GPIO port C pull-up/pull-down register (GPIOC_PUPDR) . . . . .489
13.7.5GPIO port C input data register (GPIOC_IDR) . . . . .489
13.7.6GPIO port C output data register (GPIOC_ODR) . . . . .490
13.7.7GPIO port C bit set/reset register (GPIOC_BSRR) . . . . .490
13.7.8GPIO port C configuration lock register (GPIOC_LCKR) . . . . .491
13.7.9GPIO port C alternate function high register (GPIOC_AFRH) . . . . .492
13.7.10GPIO port C bit reset register (GPIOC_BRR) .....492
13.7.11GPIO port C secure configuration register (GPIOC_SECCFGR) .....493
13.8GPIO port H registers .....493
13.8.1GPIO port H mode register (GPIOH_MODER) .....493
13.8.2GPIO port H output type register (GPIOH_OTYPER) .....494
13.8.3GPIO port H output speed register (GPIOH_OSPEEDR) .....494
13.8.4GPIO port H pull-up/pull-down register (GPIOH_PUPDR) .....495
13.8.5GPIO port H input data register (GPIOH_IDR) .....495
13.8.6GPIO port H output data register (GPIOH_ODR) .....496
13.8.7GPIO port H bit set/reset register (GPIOH_BSRR) .....496
13.8.8GPIO port H configuration lock register (GPIOH_LCKR) .....497
13.8.9GPIO port H alternate function low register (GPIOH_AFRL) .....498
13.8.10GPIO port H bit reset register (GPIOH_BRR) .....499
13.8.11GPIO port H secure configuration register (GPIOH_SECCFGR) .....499
13.8.12GPIOA register map .....500
13.8.13GPIOB register map .....501
13.8.14GPIOC register map .....502
13.8.15GPIOH register map .....503
14System configuration controller (SYSCFG) .....504
14.1SYSCFG main features .....504
14.2SYSCFG functional description .....504
14.2.1I/O compensation cell management .....504
14.2.2SYSCFG TrustZone ® security and privilege .....505
14.3SYSCFG registers .....507
14.3.1SYSCFG secure configuration register (SYSCFG_SECCFGR) .....507
14.3.2SYSCFG configuration register 1 (SYSCFG_CFGR1) .....507
14.3.3SYSCFG FPU interrupt mask register (SYSCFG_FPUIMR) .....510
14.3.4SYSCFG CPU nonsecure lock register (SYSCFG_CNSLCKR) .....510
14.3.5SYSCFG CPU secure lock register (SYSCFG_CSLOCKR) .....511
14.3.6SYSCFG configuration register 2 (SYSCFG_CFGR2) .....512
14.3.7SYSCFG memory erase status register (SYSCFG_MESR) .....513
14.3.8SYSCFG compensation cell control/status register
(SYSCFG_CCCSR) .....		514
14.3.9SYSCFG compensation cell value register (SYSCFG_CCVR) .....515
14.3.10SYSCFG compensation cell code register (SYSCFG_CCCR) .....516
14.3.11SYSCFG flash abort interrupt enable register ..(SYSCFG_FAIER)516
14.3.12SYSCFG register map .....520
15Peripherals interconnect matrix .....521
15.1Introduction .....521
15.2Connection summary .....521
15.3Interconnection details .....522
15.3.1Master to slave interconnection for timers .....522
15.3.2Triggers to ADC4 .....522
15.3.3ADC4 analog watchdog as trigger to timer .....523
15.3.4Clock source to timer .....523
15.3.5Triggers to low-power timer .....524
15.3.6Internal analog signals to analog peripheral .....525
15.3.7System errors as break signals to timers .....525
15.3.8Triggers to LPDMA1 .....525
15.3.9Internal tamper sources .....526
15.3.10Triggers to communication peripherals .....526
15.3.11Output from tamper .....527
15.3.12Timers generating IRTIM signal .....527
16Low-power direct memory access controller (LPDMA) .....528
16.1LPDMA introduction .....528
16.2LPDMA main features .....528
16.3LPDMA implementation .....529
16.3.1LPDMA channels .....529
16.3.2LPDMA autonomous mode in low-power modes .....529
16.3.3LPDMA requests .....530
16.3.4LPDMA block requests .....531
16.3.5LPDMA triggers .....531
16.4LPDMA functional description .....533
16.4.1LPDMA block diagram .....533
16.4.2LPDMA channel state and direct programming without
any linked-list .....		533
16.4.3LPDMA channel suspend and resume .....534
16.4.4LPDMA channel abort and restart .....535
16.4.5LPDMA linked-list data structure .....536
16.4.6Linked-list item transfer execution .....538
17.2Interrupt and exception vectors . . . . .586
18Extended interrupts and event controller (EXTI) . . . . .590
18.1EXTI main features . . . . .590
18.2EXTI block diagram . . . . .590
18.2.1EXTI connections between peripherals and CPU . . . . .592
18.2.2EXTI interrupt/event mapping . . . . .592
18.3EXTI functional description . . . . .592
18.3.1EXTI configurable event input wake-up . . . . .593
18.3.2EXTI mux selection . . . . .593
18.4EXTI functional behavior . . . . .594
18.5EXTI event protection . . . . .595
18.5.1EXTI security protection . . . . .595
18.5.2EXTI privilege protection . . . . .596
18.6EXTI registers . . . . .597
18.6.1EXTI rising trigger selection register (EXTI_RTSR1) . . . . .597
18.6.2EXTI falling trigger selection register (EXTI_FTSR1) . . . . .598
18.6.3EXTI software interrupt event register (EXTI_SWIER1) . . . . .598
18.6.4EXTI rising edge pending register (EXTI_RPR1) . . . . .599
18.6.5EXTI falling edge pending register (EXTI_FPR1) . . . . .600
18.6.6EXTI security configuration register (EXTI_SECCFGR1) . . . . .600
18.6.7EXTI privilege configuration register (EXTI_PRIVCFGR1) . . . . .601
18.6.8EXTI external interrupt selection register (EXTI_EXTICR1) . . . . .601
18.6.9EXTI external interrupt selection register (EXTI_EXTICR2) . . . . .603
18.6.10EXTI external interrupt selection register (EXTI_EXTICR3) . . . . .604
18.6.11EXTI external interrupt selection register (EXTI_EXTICR4) . . . . .605
18.6.12EXTI lock register (EXTI_LOCKR) . . . . .607
18.6.13EXTI CPU wake-up with interrupt mask register (EXTI_IMR1) . . . . .607
18.6.14EXTI CPU wake-up with event mask register (EXTI_EMR1) . . . . .608
18.6.15EXTI register map . . . . .609
19Cyclic redundancy check calculation unit (CRC) . . . . .611
19.1CRC introduction . . . . .611
19.2CRC main features . . . . .611
19.3CRC functional description . . . . .612
19.3.1CRC block diagram . . . . .612
20.7.2XSPI device configuration register 1 (XSPI_DCR1) . . . . .641
20.7.3XSPI device configuration register 2 (XSPI_DCR2) . . . . .643
20.7.4XSPI status register (XSPI_SR) . . . . .644
20.7.5XSPI flag clear register (XSPI_FCR) . . . . .645
20.7.6XSPI data length register (XSPI_DLR) . . . . .645
20.7.7XSPI address register (XSPI_AR) . . . . .646
20.7.8XSPI data register (XSPI_DR) . . . . .646
20.7.9XSPI communication configuration register (XSPI_CCR) . . . . .647
20.7.10XSPI timing configuration register (XSPI_TCR) . . . . .649
20.7.11XSPI instruction register (XSPI_IR) . . . . .650
20.7.12XSPI alternate bytes register (XSPI_ABR) . . . . .650
20.7.13XSPI low-power timeout register (XSPI_LPTR) . . . . .650
20.7.14XSPI register map . . . . .651
21Delay block (DLYB) . . . . .653
21.1DLYB introduction . . . . .653
21.2DLYB main features . . . . .653
21.3DLYB implementation . . . . .653
21.4DLYB functional description . . . . .653
21.4.1DLYB diagram . . . . .653
21.4.2DLYB pins and internal signals . . . . .654
21.4.3General description . . . . .654
21.4.4Delay line length configuration procedure . . . . .655
21.4.5Output clock phase configuration procedure . . . . .656
21.5DLYB registers . . . . .657
21.5.1DLYB control register (DLYB_CR) . . . . .657
21.5.2DLYB configuration register (DLYB_CFGR) . . . . .657
21.5.3DLYB register map . . . . .658
22Analog-to-digital converter (ADC4) . . . . .659
22.1ADC introduction . . . . .659
22.2ADC main features . . . . .659
22.3ADC implementation . . . . .660
22.4ADC functional description . . . . .662
22.4.1ADC block diagram . . . . .662
22.4.2ADC pins and internal signals . . . . .662
22.4.3ADC voltage regulator (ADVREGEN) . . . . .663
22.4.4Calibration (ADCAL) . . . . .664
22.4.5ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .666
22.4.6ADC clock (PRESC[3:0]) . . . . .668
22.4.7ADC connectivity . . . . .669
22.4.8Configuring the ADC . . . . .670
22.4.9Channel selection (CHSEL, SCANDIR, CHSELRMOD) . . . . .670
22.4.10Programmable sampling time (SMPx[2:0]) . . . . .671
22.4.11Single conversion mode (CONT = 0) . . . . .672
22.4.12Continuous conversion mode (CONT = 1) . . . . .672
22.4.13Starting conversions (ADSTART) . . . . .673
22.4.14Timings . . . . .674
22.4.15Stopping an ongoing conversion (ADSTP) . . . . .675
22.4.16Conversion on external trigger and trigger polarity
(EXTSEL, EXTEN) . . . . .		675
22.4.17Discontinuous mode (DISCEN) . . . . .676
22.4.18Programmable resolution (RES) - fast conversion mode . . . . .676
22.4.19End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . .677
22.4.20End of conversion sequence (EOS flag) . . . . .678
22.4.21Example timing diagrams (single/continuous modes
hardware/software triggers) . . . . .		678
22.4.22Low-frequency trigger mode . . . . .680
22.4.23Data management . . . . .680
22.4.24Low-power features . . . . .684
22.4.25Analog window watchdog . . . . .688
22.4.26Oversampler . . . . .692
22.4.27Temperature sensor and internal reference voltage . . . . .695
22.5ADC in low-power modes . . . . .698
22.6ADC interrupts . . . . .698
22.7ADC registers . . . . .700
22.7.1ADC interrupt and status register (ADC_ISR) . . . . .700
22.7.2ADC interrupt enable register (ADC_IER) . . . . .701
22.7.3ADC control register (ADC_CR) . . . . .704
22.7.4ADC configuration register 1 (ADC_CFGR1) . . . . .706
22.7.5ADC configuration register 2 (ADC_CFGR2) . . . . .709
22.7.6ADC sampling time register (ADC_SMPR) . . . . .710
22.7.7ADC watchdog threshold register (ADC_AWD1TR) . . . . .711
22.7.8ADC watchdog threshold register (ADC_AWD2TR) . . . . .712
22.7.9ADC channel selection register [alternate] (ADC_CHSELR) . . . . .713
22.7.10ADC channel selection register [alternate] (ADC_CHSELR) . . . . .713
22.7.11ADC watchdog threshold register (ADC_AWD3TR) . . . . .715
22.7.12ADC data register (ADC_DR) . . . . .716
22.7.13ADC power register (ADC_PWR) . . . . .716
22.7.14ADC Analog Watchdog 2 Configuration register (ADC_AWD2CR) . . . . .717
22.7.15ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR) . . . . .717
22.7.16ADC Calibration factor (ADC_CALFACT) . . . . .718
22.7.17ADC common configuration register (ADC_CCR) . . . . .718
22.7.18ADC register map . . . . .719
23True random number generator (RNG) . . . . .722
23.1RNG introduction . . . . .722
23.2RNG main features . . . . .722
23.3RNG functional description . . . . .723
23.3.1RNG block diagram . . . . .723
23.3.2RNG internal signals . . . . .723
23.3.3Random number generation . . . . .724
23.3.4RNG initialization . . . . .726
23.3.5RNG operation . . . . .727
23.3.6RNG clocking . . . . .729
23.3.7Error management . . . . .729
23.3.8RNG low-power use . . . . .731
23.4RNG interrupts . . . . .731
23.5RNG processing time . . . . .732
23.6RNG entropy source validation . . . . .732
23.6.1Introduction . . . . .732
23.6.2Validation conditions . . . . .732
23.7RNG registers . . . . .734
23.7.1RNG control register (RNG_CR) . . . . .734
23.7.2RNG status register (RNG_SR) . . . . .736
23.7.3RNG data register (RNG_DR) . . . . .737
23.7.4RNG noise source control register (RNG_NSCR) . . . . .738
23.7.5RNG health test control register x (RNG_HTCRx) . . . . .738
23.7.6RNG health test status register 0 (RNG_HTSR0) . . . . .739
24.9.5AES key register 0 (AES_KEYR0) . . . . .776
24.9.6AES key register 1 (AES_KEYR1) . . . . .776
24.9.7AES key register 2 (AES_KEYR2) . . . . .777
24.9.8AES key register 3 (AES_KEYR3) . . . . .777
24.9.9AES initialization vector register 0 (AES_IVR0) . . . . .777
24.9.10AES initialization vector register 1 (AES_IVR1) . . . . .778
24.9.11AES initialization vector register 2 (AES_IVR2) . . . . .778
24.9.12AES initialization vector register 3 (AES_IVR3) . . . . .778
24.9.13AES key register 4 (AES_KEYR4) . . . . .779
24.9.14AES key register 5 (AES_KEYR5) . . . . .779
24.9.15AES key register 6 (AES_KEYR6) . . . . .779
24.9.16AES key register 7 (AES_KEYR7) . . . . .780
24.9.17AES suspend registers (AES_SUSPRx) . . . . .780
24.9.18AES interrupt enable register (AES_IER) . . . . .780
24.9.19AES interrupt status register (AES_ISR) . . . . .781
24.9.20AES interrupt clear register (AES_ICR) . . . . .782
24.9.21AES register map . . . . .783
25Hash processor (HASH) . . . . .785
25.1HASH introduction . . . . .785
25.2HASH main features . . . . .785
25.3HASH implementation . . . . .786
25.4HASH functional description . . . . .786
25.4.1HASH block diagram . . . . .786
25.4.2HASH internal signals . . . . .786
25.4.3About secure hash algorithms . . . . .787
25.4.4Message data feeding . . . . .787
25.4.5Message digest computing . . . . .788
25.4.6Message padding . . . . .790
25.4.7HMAC operation . . . . .791
25.4.8HASH suspend/resume operations . . . . .793
25.4.9HASH DMA interface . . . . .795
25.4.10HASH error management . . . . .795
25.4.11HASH processing time . . . . .795
25.5HASH interrupts . . . . .796
25.6HASH registers . . . . .796
25.6.1HASH control register (HASH_CR) . . . . .796
25.6.2HASH data input register (HASH_DIN) . . . . .798
25.6.3HASH start register (HASH_STR) . . . . .799
25.6.4HASH digest registers . . . . .800
25.6.5HASH interrupt enable register (HASH_IMR) . . . . .802
25.6.6HASH status register (HASH_SR) . . . . .802
25.6.7HASH context swap registers . . . . .803
25.6.8HASH register map . . . . .804
26On-the-fly decryption engine (OTFDEC) . . . . .806
26.1OTFDEC introduction . . . . .806
26.2OTFDEC main features . . . . .806
26.3OTFDEC functional description . . . . .807
26.3.1OTFDEC block diagram . . . . .807
26.3.2OTFDEC internal signals . . . . .807
26.3.3OTFDEC on-the-fly decryption . . . . .808
26.3.4OTFDEC usage of AES in counter mode decryption . . . . .809
26.3.5Flow control management . . . . .810
26.3.6OTFDEC error management . . . . .810
26.4OTFDEC interrupts . . . . .811
26.5OTFDEC application information . . . . .811
26.5.1OTFDEC initialization process . . . . .811
26.5.2OTFDEC and power management . . . . .813
26.5.3Encrypting for OTFDEC . . . . .813
26.5.4OTFDEC key CRC source code . . . . .814
26.6OTFDEC registers . . . . .815
26.6.1OTFDEC control register (OTFDEC_CR) . . . . .815
26.6.2OTFDEC privileged access control configuration register
(OTFDEC_PRIVCFGR) . . . . .		816
26.6.3OTFDEC region x configuration register (OTFDEC_RxCFGR) . . . . .816
26.6.4OTFDEC region x start address register
(OTFDEC_RxSTARTADDR) . . . . .		818
26.6.5OTFDEC region x end address register (OTFDEC_RxENDADDR) . . . . .818
26.6.6OTFDEC region x nonce register 0 (OTFDEC_RxNONCER0) . . . . .819
26.6.7OTFDEC region x nonce register 1 (OTFDEC_RxNONCER1) . . . . .820
26.6.8OTFDEC region x key register 0 (OTFDEC_RxKEYR0) . . . . .820
26.6.9OTFDEC region x key register 1 (OTFDEC_RxKEYR1) . . . . .821
26.6.10OTFDEC region x key register 2 (OTFDEC_RxKEYR2) .....821
26.6.11OTFDEC region x key register 3 (OTFDEC_RxKEYR3) .....822
26.6.12OTFDEC interrupt status register (OTFDEC_ISR) .....822
26.6.13OTFDEC interrupt clear register (OTFDEC_ICR) .....823
26.6.14OTFDEC interrupt enable register (OTFDEC_IER) .....824
26.6.15OTFDEC register map .....825
27Public key accelerator (PKA) .....829
27.1PKA introduction .....829
27.2PKA main features .....829
27.3PKA functional description .....830
27.3.1PKA block diagram .....830
27.3.2PKA internal signals .....830
27.3.3PKA reset and clocks .....830
27.3.4PKA public key acceleration .....831
27.3.5Typical applications for PKA .....833
27.3.6PKA procedure to perform an operation .....835
27.3.7PKA error management .....836
27.4PKA operating modes .....837
27.4.1Introduction .....837
27.4.2Montgomery parameter computation .....838
27.4.3Modular addition .....838
27.4.4Modular subtraction .....839
27.4.5Modular and Montgomery multiplication .....839
27.4.6Modular exponentiation .....840
27.4.7Modular inversion .....842
27.4.8Modular reduction .....842
27.4.9Arithmetic addition .....843
27.4.10Arithmetic subtraction .....843
27.4.11Arithmetic multiplication .....844
27.4.12Arithmetic comparison .....844
27.4.13RSA CRT exponentiation .....844
27.4.14Point on elliptic curve Fp check .....845
27.4.15ECC Fp scalar multiplication .....846
27.4.16ECDSA sign .....847
27.4.17ECDSA verification .....849
27.4.18ECC complete addition .....850
28.4.18Encoder interface mode . . . . .907
28.4.19Direction bit output . . . . .925
28.4.20UIF bit remapping . . . . .926
28.4.21Timer input XOR function . . . . .926
28.4.22Timers and external trigger synchronization . . . . .926
28.4.23Timer synchronization . . . . .930
28.4.24ADC triggers . . . . .935
28.4.25ADC synchronization . . . . .936
28.4.26DMA burst mode . . . . .937
28.4.27TIM2 DMA requests . . . . .938
28.4.28Debug mode . . . . .938
28.4.29TIM2 low-power modes . . . . .938
28.4.30TIM2 interrupts . . . . .939
28.5TIM2 registers . . . . .940
28.5.1TIM2 control register 1 (TIM2_CR1) . . . . .940
28.5.2TIM2 control register 2 (TIM2_CR2) . . . . .941
28.5.3TIM2 slave mode control register (TIM2_SMCR) . . . . .943
28.5.4TIM2 DMA/Interrupt enable register (TIM2_DIER) . . . . .947
28.5.5TIM2 status register (TIM2_SR) . . . . .948
28.5.6TIM2 event generation register (TIM2_EGR) . . . . .950
28.5.7TIM2 capture/compare mode register 1 (TIM2_CCMR1) . . . . .951
28.5.8TIM2 capture/compare mode register 1 [alternate]
(TIM2_CCMR1) . . . . .		953
28.5.9TIM2 capture/compare mode register 2 (TIM2_CCMR2) . . . . .955
28.5.10TIM2 capture/compare mode register 2 [alternate]
(TIM2_CCMR2) . . . . .		956
28.5.11TIM2 capture/compare enable register (TIM2_CCER) . . . . .959
28.5.12TIM2 counter (TIM2_CNT) . . . . .961
28.5.13TIM2 prescaler (TIM2_PSC) . . . . .961
28.5.14TIM2 autoreload register (TIM2_ARR) . . . . .962
28.5.15TIM2 capture/compare register 1 (TIM2_CCR1) . . . . .962
28.5.16TIM2 capture/compare register 2 (TIM2_CCR2) . . . . .963
28.5.17TIM2 capture/compare register 3 (TIM2_CCR3) . . . . .964
28.5.18TIM2 capture/compare register 4 (TIM2_CCR4) . . . . .965
28.5.19TIM2 timer encoder control register (TIM2_ECR) . . . . .966
28.5.20TIM2 timer input selection register (TIM2_TISEL) . . . . .967
28.5.21TIM2 alternate function register 1 (TIM2_AF1) . . . . .968
28.5.22TIM2 alternate function register 2 (TIM2_AF2) .....969
28.5.23TIM2 DMA control register (TIM2_DCR) .....970
28.5.24TIM2 DMA address for full transfer (TIM2_DMAR) .....971
28.5.25TIM2 register map .....972
29General purpose timers (TIM16/TIM17) .....975
29.1TIM16/TIM17 introduction .....975
29.2TIM16/TIM17 main features .....975
29.3Implementation .....975
29.4TIM16/TIM17 functional description .....976
29.4.1Block diagram .....976
29.4.2TIM16/TIM17 pins and internal signals .....976
29.4.3Time-base unit .....979
29.4.4Counter modes .....981
29.4.5Repetition counter .....985
29.4.6Clock selection .....986
29.4.7Capture/compare channels .....988
29.4.8Input capture mode .....990
29.4.9Forced output mode .....991
29.4.10Output compare mode .....991
29.4.11PWM mode .....993
29.4.12Complementary outputs and dead-time insertion .....998
29.4.13Using the break function .....1000
29.4.14Bidirectional break input .....1005
29.4.15Clearing the tim_ocxref signal on an external event .....1006
29.4.166-step PWM generation .....1007
29.4.17One-pulse mode .....1009
29.4.18UIF bit remapping .....1010
29.4.19Using timer output as trigger for other timers (TIM16/TIM17 only) ..1010
29.4.20DMA burst mode .....1011
29.4.21TIM16/TIM17 DMA requests .....1012
29.4.22Debug mode .....1012
29.5TIM16/TIM17 low-power modes .....1012
29.6TIM16/TIM17 interrupts .....1012
29.7TIM16/TIM17 registers .....1014
29.7.1TIMx control register 1 (TIMx_CR1)(x = 16 to 17) .....1014
29.7.2TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . .1015
29.7.3TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . .1016
29.7.4TIMx status register (TIMx_SR)(x = 16 to 17) . . . . .1017
29.7.5TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . .1018
29.7.6TIMx capture/compare mode register 1 (TIMx_CCMR1)
(x = 16 to 17) . . . . .		1019
29.7.7TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . .		1020
29.7.8TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . . . .1022
29.7.9TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . .1025
29.7.10TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . .1025
29.7.11TIMx auto-reautoreload register (TIMx_ARR)(x = 16 to 17) . . . . .1026
29.7.12TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . .1026
29.7.13TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . .1027
29.7.14TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . .1028
29.7.15TIMx timer deadtime register 2 (TIMx_DTR2)(x = 16 to 17) . . . . .1031
29.7.16TIMx input selection register (TIMx_TISEL)(x = 16 to 17) . . . . .1032
29.7.17TIMx alternate function register 1 (TIMx_AF1)(x = 16 to 17) . . . . .1032
29.7.18TIMx alternate function register 2 (TIMx_AF2)(x = 16 to 17) . . . . .1035
29.7.19TIMx option register 1 (TIMx_OR1)(x = 16 to 17) . . . . .1035
29.7.20TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . .1036
29.7.21TIM16/TIM17 DMA address for full transfer
(TIMx_DMAR)(x = 16 to 17) . . . . .		1037
29.7.22TIM16/TIM17 register map . . . . .1038
30Low-power timer (LPTIM) . . . . .1040
30.1LPTIM introduction . . . . .1040
30.2LPTIM main features . . . . .1040
30.3LPTIM implementation . . . . .1040
30.4LPTIM functional description . . . . .1042
30.4.1LPTIM block diagram . . . . .1042
30.4.2LPTIM pins and internal signals . . . . .1042
30.4.3LPTIM input and trigger mapping . . . . .1044
30.4.4LPTIM reset and clocks . . . . .1045
30.4.5Glitch filter . . . . .1045
30.4.6Prescaler . . . . .1046
30.4.7Trigger multiplexer . . . . .1046
30.4.8Operating mode . . . . .1047
30.4.9Timeout function . . . . .1049
30.4.10Waveform generation . . . . .1049
30.4.11Register update . . . . .1050
30.4.12Counter mode . . . . .1051
30.4.13Timer enable . . . . .1051
30.4.14Timer counter reset . . . . .1052
30.4.15Encoder mode . . . . .1052
30.4.16Repetition counter . . . . .1054
30.4.17Capture/compare channels . . . . .1055
30.4.18Input capture mode . . . . .1056
30.4.19PWM mode . . . . .1058
30.4.20Autonomous mode . . . . .1060
30.4.21DMA requests . . . . .1061
30.4.22Debug mode . . . . .1062
30.5LPTIM low-power modes . . . . .1062
30.6LPTIM interrupts . . . . .1062
30.7LPTIM registers . . . . .1063
30.7.1LPTIMx interrupt and status register [alternate] (LPTIMx_ISR)
(x = 1, 2) . . . . .		1064
30.7.2LPTIMx interrupt and status register [alternate] (LPTIMx_ISR)
(x = 1, 2) . . . . .		1066
30.7.3LPTIMx interrupt clear register [alternate] (LPTIMx_ICR)
(x = 1, 2) . . . . .		1068
30.7.4LPTIMx interrupt clear register [alternate] (LPTIMx_ICR)
(x = 1, 2) . . . . .		1069
30.7.5LPTIMx interrupt enable register [alternate] (LPTIMx_DIER)
(x = 1, 2) . . . . .		1071
30.7.6LPTIMx interrupt enable register [alternate] (LPTIMx_DIER)
(x = 1, 2) . . . . .		1072
30.7.7LPTIM configuration register (LPTIM_CFGR) . . . . .1074
30.7.8LPTIM control register (LPTIM_CR) . . . . .1077
30.7.9LPTIM compare register 1 (LPTIM_CCR1) . . . . .1078
30.7.10LPTIM autoreload register (LPTIM_ARR) . . . . .1078
30.7.11LPTIM counter register (LPTIM_CNT) . . . . .1079
30.7.12LPTIM configuration register 2 (LPTIM_CFGR2) . . . . .1079
30.7.13LPTIM repetition register (LPTIM_RCR) . . . . .1080
30.7.14LPTIM capture/compare mode register 1 (LPTIM_CCMR1) . . . . .1081
30.7.15LPTIM compare register 2 (LPTIM_CCR2) . . . . .1083
30.7.16LPTIM register map .....1084
31Infrared interface (IRTIM) .....1086
32Independent watchdog (IWDG) .....1087
32.1IWDG introduction .....1087
32.2IWDG main features .....1087
32.3IWDG implementation .....1087
32.4IWDG functional description .....1088
32.4.1IWDG block diagram .....1088
32.4.2IWDG internal signals .....1089
32.4.3Software and hardware watchdog modes .....1089
32.4.4Window option .....1090
32.4.5Debug .....1093
32.4.6Register access protection .....1093
32.5IWDG low power modes .....1093
32.6IWDG interrupts .....1094
32.7IWDG registers .....1095
32.7.1IWDG key register (IWDG_KR) .....1095
32.7.2IWDG prescaler register (IWDG_PR) .....1096
32.7.3IWDG reload register (IWDG_RLR) .....1097
32.7.4IWDG status register (IWDG_SR) .....1097
32.7.5IWDG window register (IWDG_WINR) .....1098
32.7.6IWDG early wake-up interrupt register (IWDG_EWCR) .....1099
32.7.7IWDG register map .....1101
33Real-time clock (RTC) .....1102
33.1RTC introduction .....1102
33.2RTC main features .....1102
33.3RTC functional description .....1102
33.3.1RTC block diagram .....1102
33.3.2RTC pins and internal signals .....1104
33.3.3GPIOs controlled by the RTC and TAMP .....1105
33.3.4RTC secure protection modes .....1107
33.3.5RTC privilege protection modes .....1109
33.3.6Clock and prescalers .....1110
33.6.22RTC secure masked interrupt status register (RTC_SMISR) . . . . .1150
33.6.23RTC status clear register (RTC_SCR) . . . . .1151
33.6.24RTC alarm A binary mode register (RTC_ALRABINR) . . . . .1152
33.6.25RTC alarm B binary mode register (RTC_ALRBBINR) . . . . .1153
33.6.26RTC register map . . . . .1154
34Tamper and backup registers (TAMP) . . . . .1156
34.1TAMP introduction . . . . .1156
34.2TAMP main features . . . . .1156
34.3TAMP functional description . . . . .1157
34.3.1TAMP block diagram . . . . .1157
34.3.2TAMP pins and internal signals . . . . .1158
34.3.3GPIOs controlled by the RTC and TAMP . . . . .1160
34.3.4TAMP register write protection . . . . .1161
34.3.5TAMP secure protection modes . . . . .1161
34.3.6Backup registers protection zones . . . . .1162
34.3.7TAMP privilege protection modes . . . . .1162
34.3.8Tamper detection . . . . .1163
34.3.9TAMP backup registers and other device secrets erase . . . . .1163
34.3.10Tamper detection configuration and initialization . . . . .1165
34.4TAMP low-power modes . . . . .1171
34.5TAMP interrupts . . . . .1172
34.6TAMP registers . . . . .1172
34.6.1TAMP control register 1 (TAMP_CR1) . . . . .1172
34.6.2TAMP control register 2 (TAMP_CR2) . . . . .1174
34.6.3TAMP control register 3 (TAMP_CR3) . . . . .1176
34.6.4TAMP filter control register (TAMP_FLTCR) . . . . .1177
34.6.5TAMP active tamper control register 1 (TAMP_ATCR1) . . . . .1178
34.6.6TAMP active tamper seed register (TAMP_ATSEEDR) . . . . .1181
34.6.7TAMP active tamper output register (TAMP_ATOR) . . . . .1181
34.6.8TAMP active tamper control register 2 (TAMP_ATCR2) . . . . .1182
34.6.9TAMP secure configuration register (TAMP_SECCFGGR) . . . . .1184
34.6.10TAMP privilege configuration register (TAMP_PRIVCFGGR) . . . . .1186
34.6.11TAMP interrupt enable register (TAMP_IER) . . . . .1187
34.6.12TAMP status register (TAMP_SR) . . . . .1189
34.6.13TAMP nonsecure masked interrupt status register (TAMP_MISR) . . . . .1191

35.9I2C registers . . . . .1251
35.9.1I2C control register 1 (I2C_CR1) . . . . .1251
35.9.2I2C control register 2 (I2C_CR2) . . . . .1254
35.9.3I2C own address 1 register (I2C_OAR1) . . . . .1256
35.9.4I2C own address 2 register (I2C_OAR2) . . . . .1256
35.9.5I2C timing register (I2C_TIMINGR) . . . . .1257
35.9.6I2C timeout register (I2C_TIMEOUTR) . . . . .1258
35.9.7I2C interrupt and status register (I2C_ISR) . . . . .1259
35.9.8I2C interrupt clear register (I2C_ICR) . . . . .1262
35.9.9I2C PEC register (I2C_PECR) . . . . .1263
35.9.10I2C receive data register (I2C_RXDR) . . . . .1263
35.9.11I2C transmit data register (I2C_TXDR) . . . . .1264
35.9.12I2C autonomous mode control register (I2C_AUTOOCR) . . . . .1264
35.9.13I2C register map . . . . .1266
36Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . .1268
36.1USART introduction . . . . .1268
36.2USART main features . . . . .1268
36.3USART extended features . . . . .1269
36.4USART implementation . . . . .1269
36.5USART functional description . . . . .1271
36.5.1USART block diagram . . . . .1271
36.5.2USART pins and internal signals . . . . .1271
36.5.3USART clocks . . . . .1274
36.5.4USART character description . . . . .1274
36.5.5USART FIFOs and thresholds . . . . .1276
36.5.6USART transmitter . . . . .1276
36.5.7USART receiver . . . . .1279
36.5.8USART baud rate generation . . . . .1286
36.5.9Tolerance of the USART receiver to clock deviation . . . . .1288
36.5.10USART auto baud rate detection . . . . .1289
36.5.11USART multiprocessor communication . . . . .1291
36.5.12USART Modbus communication . . . . .1293
36.5.13USART parity control . . . . .1294
36.5.14USART LIN (local interconnection network) mode . . . . .1295
36.5.15USART synchronous mode . . . . .1297
36.5.16USART single-wire half-duplex communication . . . . .1301
36.5.17USART receiver timeout . . . . .1301
36.5.18USART smartcard mode . . . . .1302
36.5.19USART IrDA SIR ENDEC block . . . . .1306
36.5.20Continuous communication using USART and DMA . . . . .1309
36.5.21RS232 hardware flow control and RS485 driver enable . . . . .1311
36.5.22USART autonomous mode . . . . .1313
36.6USART in low-power modes . . . . .1315
36.7USART interrupts . . . . .1316
36.8USART registers . . . . .1318
36.8.1USART control register 1 (USART_CR1) . . . . .1318
36.8.2USART control register 1 [alternate] (USART_CR1) . . . . .1322
36.8.3USART control register 2 (USART_CR2) . . . . .1325
36.8.4USART control register 3 (USART_CR3) . . . . .1329
36.8.5USART control register 3 [alternate] (USART_CR3) . . . . .1333
36.8.6USART baud rate register (USART_BRR) . . . . .1336
36.8.7USART guard time and prescaler register (USART_GTPR) . . . . .1337
36.8.8USART receiver timeout register (USART_RTOR) . . . . .1338
36.8.9USART request register (USART_RQR) . . . . .1339
36.8.10USART interrupt and status register (USART_ISR) . . . . .1340
36.8.11USART interrupt and status register [alternate] (USART_ISR) . . . . .1346
36.8.12USART interrupt flag clear register (USART_ICR) . . . . .1351
36.8.13USART receive data register (USART_RDR) . . . . .1352
36.8.14USART transmit data register (USART_TDR) . . . . .1353
36.8.15USART prescaler register (USART_PRESC) . . . . .1353
36.8.16USART autonomous mode control register (USART_AUTOOCR) . . . . .1354
36.8.17USART register map . . . . .1355
37Low-power universal asynchronous receiver transmitter (LPUART) . . . . .1357
37.1LPUART introduction . . . . .1357
37.2LPUART main features . . . . .1357
37.3LPUART implementation . . . . .1358
37.4LPUART functional description . . . . .1359
37.4.1LPUART block diagram . . . . .1359
37.4.2LPUART pins and internal signals . . . . .1360
37.4.3LPUART clocks . . . . .1362
37.4.4LPUART character description . . . . .1362
37.4.5LPUART FIFOs and thresholds . . . . .1364
37.4.6LPUART transmitter . . . . .1364
37.4.7LPUART receiver . . . . .1368
37.4.8LPUART baud rate generation . . . . .1372
37.4.9Tolerance of the LPUART receiver to clock deviation . . . . .1373
37.4.10LPUART multiprocessor communication . . . . .1374
37.4.11LPUART parity control . . . . .1376
37.4.12LPUART single-wire half-duplex communication . . . . .1377
37.4.13Continuous communication using DMA and LPUART . . . . .1377
37.4.14RS232 hardware flow control and RS485 driver enable . . . . .1380
37.4.15LPUART autonomous mode . . . . .1382
37.5LPUART in low-power modes . . . . .1384
37.6LPUART interrupts . . . . .1385
37.7LPUART registers . . . . .1386
37.7.1LPUART control register 1 (LPUART_CR1) . . . . .1386
37.7.2LPUART control register 1 [alternate] (LPUART_CR1) . . . . .1389
37.7.3LPUART control register 2 (LPUART_CR2) . . . . .1392
37.7.4LPUART control register 3 (LPUART_CR3) . . . . .1394
37.7.5LPUART control register 3 [alternate] (LPUART_CR3) . . . . .1396
37.7.6LPUART baud rate register (LPUART_BRR) . . . . .1398
37.7.7LPUART request register (LPUART_RQR) . . . . .1398
37.7.8LPUART interrupt and status register (LPUART_ISR) . . . . .1399
37.7.9LPUART interrupt and status register [alternate] (LPUART_ISR) . . . . .1404
37.7.10LPUART interrupt flag clear register (LPUART_ICR) . . . . .1407
37.7.11LPUART receive data register (LPUART_RDR) . . . . .1408
37.7.12LPUART transmit data register (LPUART_TDR) . . . . .1408
37.7.13LPUART prescaler register (LPUART_PRESC) . . . . .1409
37.7.14LPUART autonomous mode control register (LPUART_AUTOCR) . . . . .1410
37.7.15LPUART register map . . . . .1410
38Serial peripheral interface (SPI) . . . . .1413
38.1SPI introduction . . . . .1413
38.2SPI main features . . . . .1413
38.3SPI implementation . . . . .1414
38.4SPI functional description . . . . .1415
38.4.1SPI block diagram . . . . .1415
38.4.2SPI pins and internal signals . . . . .1416
38.4.3SPI communication general aspects . . . . .1418
38.4.4Communications between one master and one slave . . . . .1418
38.4.5Standard multislave communication . . . . .1420
38.4.6Multimaster communication . . . . .1423
38.4.7Slave select (NSS pin) management . . . . .1424
38.4.8Ready pin (RDY) management . . . . .1428
38.4.9Communication formats . . . . .1428
38.4.10Configuring the SPI . . . . .1430
38.4.11Enabling the SPI . . . . .1431
38.4.12SPI data transmission and reception procedures . . . . .1432
38.4.13Disabling the SPI . . . . .1436
38.4.14Communication using DMA (direct memory addressing) . . . . .1437
38.4.15Autonomous mode . . . . .1438
38.5SPI specific modes and control . . . . .1440
38.5.1TI mode . . . . .1440
38.5.2SPI error flags . . . . .1440
38.5.3CRC computation . . . . .1444
38.6SPI in low-power modes . . . . .1445
38.7SPI interrupts . . . . .1445
38.8SPI registers . . . . .1447
38.8.1SPI control register 1 (SPI_CR1) . . . . .1447
38.8.2SPI control register 2 (SPI_CR2) . . . . .1449
38.8.3SPI configuration register 1 (SPI_CFG1) . . . . .1449
38.8.4SPI configuration register 2 (SPI_CFG2) . . . . .1451
38.8.5SPI interrupt enable register (SPI_IER) . . . . .1453
38.8.6SPI status register (SPI_SR) . . . . .1454
38.8.7SPI interrupt/status flags clear register (SPI_IFCR) . . . . .1457
38.8.8SPI autonomous mode control register (SPI_AUTOCR) . . . . .1457
38.8.9SPI transmit data register (SPI_TXDR) . . . . .1458
38.8.10SPI receive data register (SPI_RXDR) . . . . .1459
38.8.11SPI polynomial register (SPI_CRCPOLY) . . . . .1459
38.8.12SPI transmitter CRC register (SPI_TXCRC) . . . . .1460
38.8.13SPI receiver CRC register (SPI_RXCRC) . . . . .1460
38.8.14SPI underrun data register (SPI_UDRDR) . . . . .1461
38.8.15SPI register map . . . . .1462
39Serial audio interface (SAI) . . . . .1463
39.1SAI introduction . . . . .1463
39.2SAI main features . . . . .1463
39.3SAI implementation . . . . .1464
39.4SAI functional description . . . . .1465
39.4.1SAI block diagram . . . . .1465
39.4.2SAI pins and internal signals . . . . .1466
39.4.3Main SAI modes . . . . .1466
39.4.4SAI synchronization mode . . . . .1467
39.4.5Audio data size . . . . .1468
39.4.6Frame synchronization . . . . .1468
39.4.7Slot configuration . . . . .1471
39.4.8SAI clock generator . . . . .1473
39.4.9Internal FIFOs . . . . .1476
39.4.10PDM interface . . . . .1478
39.4.11AC'97 link controller . . . . .1486
39.4.12SPDIF output . . . . .1487
39.4.13Specific features . . . . .1490
39.4.14Error flags . . . . .1494
39.4.15Disabling the SAI . . . . .1497
39.4.16SAI DMA interface . . . . .1497
39.5SAI interrupts . . . . .1498
39.6SAI registers . . . . .1500
39.6.1SAI configuration register 1 (SAI_ACR1) . . . . .1500
39.6.2SAI configuration register 2 (SAI_ACR2) . . . . .1502
39.6.3SAI frame configuration register (SAI_AFRCR) . . . . .1504
39.6.4SAI slot register (SAI_ASLOTR) . . . . .1505
39.6.5SAI interrupt mask register (SAI_AIM) . . . . .1506
39.6.6SAI status register (SAI_ASR) . . . . .1508
39.6.7SAI clear flag register (SAI_ACLRFR) . . . . .1510
39.6.8SAI data register (SAI_ADR) . . . . .1511
39.6.9SAI configuration register 1 (SAI_BCR1) . . . . .1511
39.6.10SAI configuration register 2 (SAI_BCR2) . . . . .1514
39.6.11SAI frame configuration register (SAI_BFRFCR) . . . . .1516
39.6.12SAI slot register (SAI_BSLOTR) . . . . .1517
39.6.13SAI interrupt mask register (SAI_BIM) . . . . .1518
39.6.14SAI status register (SAI_BSR) . . . . .1519
39.6.15SAI clear flag register (SAI_BCLRFR) . . . . .1521
39.6.16SAI data register (SAI_BDR) . . . . .1522
39.6.17SAI PDM control register (SAI_PDMCR) . . . . .1523
39.6.18SAI PDM delay register (SAI_PDMPLY) . . . . .1524
39.6.19SAI register map . . . . .1526
40Universal serial bus full-speed host/device interface (USB) . . . . .1528
40.1USB introduction . . . . .1528
40.2USB main features . . . . .1528
40.3USB implementation . . . . .1528
40.4USB functional description . . . . .1529
40.4.1USB block diagram . . . . .1529
40.4.2USB pins and internal signals . . . . .1530
40.4.3USB reset and clocks . . . . .1530
40.4.4General description and Device mode functionality . . . . .1530
40.4.5Description of USB blocks used in both Device and Host modes . . . . .1531
40.4.6Description of host frame scheduler (HFS) specific to Host mode . . . . .1532
40.5Programming considerations for Device and Host modes . . . . .1533
40.5.1Generic USB Device programming . . . . .1533
40.5.2System and power-on reset . . . . .1534
40.5.3Double-buffered endpoints and usage in Device mode . . . . .1541
40.5.4Double buffered channels: usage in Host mode . . . . .1543
40.5.5Isochronous transfers in Device mode . . . . .1544
40.5.6Isochronous transfers in Host mode . . . . .1545
40.5.7Suspend/resume events . . . . .1546
40.6USB registers . . . . .1549
40.6.1USB control register (USB_CNTR) . . . . .1550
40.6.2USB interrupt status register (USB_ISTR) . . . . .1553
40.6.3USB frame number register (USB_FNR) . . . . .1557
40.6.4USB Device address (USB_DADDR) . . . . .1557
40.6.5USB LPM control and status register (USB_LPMCSR) . . . . .1558
40.6.6USB battery charging detector (USB_BCDR) . . . . .1559
40.6.7USB endpoint/channel n register (USB_CHEPnR) .....1560
40.7USBSRAM registers .....1569
40.7.1Channel/endpoint transmit buffer descriptor n
(USBSRAM_CHEP_TXRXBD_n) .....		1570
40.7.2Channel/endpoint receive buffer descriptor n [alternate]
(USBSRAM_CHEP_TXRXBD_n) .....		1570
40.7.3Channel/endpoint receive buffer descriptor n
(USBSRAM_CHEP_RXTXBD_n) .....		1572
40.7.4Channel/endpoint transmit buffer descriptor n [alternate]
(USBSRAM_CHEP_RXTXBD_n) .....		1573
40.7.5USBSRAM register map .....1574
41Debug support (DBG) .....1575
41.1DBG introduction and main features .....1575
41.2DBG functional description .....1576
41.2.1DBG block diagram .....1576
41.2.2DBG pins and internal signals .....1576
41.2.3DBG reset and clocks .....1577
41.2.4DBG power domains .....1577
41.2.5DBG low-power modes .....1577
41.2.6Security .....1578
41.2.7Serial-wire and JTAG debug port .....1579
41.2.8JTAG debug port .....1580
41.2.9Serial-wire debug port .....1582
41.3Debug port registers .....1583
41.3.1DP identification register [alternate] (DP_PIDR) .....1584
41.3.2DP abort register [alternate] (DP_ABORTR) .....1585
41.3.3DP control and status register (DP_CTRLSTATR) .....1585
41.3.4DP data link control register (DP_DLCR) .....1587
41.3.5DP target identification register (DP_TARGETIDR) .....1587
41.3.6DP data link protocol identification register (DP_DLPIDR) .....1588
41.3.7DP resend register (DP_EVENSTATR) .....1588
41.3.8DP resend register (DP_RESENR) .....1589
41.3.9DP access port select register (DP_SELECTR) .....1589
41.3.10DP read buffer register (DP_BUFFR) .....1590
41.3.11DP register map and reset values .....1590
41.4Access port .....1592
41.4.1Access port registers .....1592
41.4.2AP control/status word register (APx_CSWR) (x = 0 to 1) . . . . .1593
41.4.3AP transfer address register (APx_TAR) (x = 0 to 1) . . . . .1594
41.4.4AP data read/write register (APx_DRWR) (x = 0 to 1) . . . . .1594
41.4.5AP banked data registers y (APx_BDyR) (x = 0 to 1) . . . . .1594
41.4.6AP configuration register (APx_CFGR) (x = 0 to 1) . . . . .1595
41.4.7AP base address register (APx_BASER) (x = 0 to 1) . . . . .1595
41.4.8AP identification register (APx_IDR) (x = 0 to 1) . . . . .1596
41.4.9Access port register map and reset values . . . . .1597
41.5System debug AP0 features . . . . .1598
41.5.1System debug ROM table . . . . .1598
41.5.2System debug memory type register (SYSROM_MEMTYPER) . . . . .1599
41.5.3Sytem debug CoreSight peripheral identity register 4
(SYSROM_PIDR4) . . . . .		1599
41.5.4System debug CoreSight peripheral identity register 0
(SYSROM_PIDR0) . . . . .		1600
41.5.5System debug CoreSight peripheral identity register 1
(SYSROM_PIDR1) . . . . .		1600
41.5.6System debug CoreSight peripheral identity register 2
(SYSROM_PIDR2) . . . . .		1601
41.5.7System debug CoreSight peripheral identity register 3
(SYSROM_PIDR3) . . . . .		1601
41.5.8System debug CoreSight component identity register 0
(SYSROM_CIDR0) . . . . .		1602
41.5.9System debug CoreSight peripheral identity register 1
(SYSROM_CIDR1) . . . . .		1602
41.5.10System debug CoreSight component identity register 2
(SYSROM_CIDR2) . . . . .		1603
41.5.11System debug CoreSight component identity register 3
(SYSROM_CIDR3) . . . . .		1603
41.5.12System debug ROM table register map and reset values . . . . .1604
41.6Cortex-M33 AP1 features . . . . .1605
41.6.1CPU ROM tables . . . . .1605
41.6.2MCU and processor ROM memory type register
(ROM_MEMTYPER) . . . . .		1608
41.6.3MCU and processor ROM CoreSight peripheral identity register 4
(ROM_PIDR4) . . . . .		1608
41.6.4MCU and processor ROM CoreSight peripheral identity register 0
(ROM_PIDR0) . . . . .		1609
41.6.5MCU and processor ROM CoreSight peripheral identity register 1
(ROM_PIDR1) . . . . .		1609
41.6.6MCU and processor ROM CoreSight peripheral identity register 2 (ROM_PIDR2) . . . . .1610
41.6.7MCU and processor ROM CoreSight peripheral identity register 3 (ROM_PIDR3) . . . . .1610
41.6.8MCU and processor ROM CoreSight component identity register 0 (ROM_CIDR0) . . . . .1611
41.6.9MCU and processor ROM CoreSight peripheral identity register 1 (ROM_CIDR1) . . . . .1611
41.6.10MCU and processor ROM CoreSight component identity register 2 (ROM_CIDR2) . . . . .1612
41.6.11MCU and processor ROM CoreSight component identity register 3 (ROM_CIDR3) . . . . .1612
41.6.12MCU and processor ROM tables register map and reset values . . . . .1613
41.7Data watchpoint and trace unit (DWT) . . . . .1614
41.7.1DWT control register (DWT_CTRLR) . . . . .1615
41.7.2DWT cycle count register (DWT_CYCCNTR) . . . . .1616
41.7.3DWT CPI count register (DWT_CPICNTR) . . . . .1617
41.7.4DWT exception count register (DWT_EXCCNTR) . . . . .1617
41.7.5DWT sleep count register (DWT_SLP CNTR) . . . . .1617
41.7.6DWT LSU count register (DWT_LSUCNTR) . . . . .1618
41.7.7DWT fold count register (DWT_FOLDCNTR) . . . . .1618
41.7.8DWT program counter sample register (DWT_PCSR) . . . . .1619
41.7.9DWT comparator register x (DWT_COMPxR) . . . . .1619
41.7.10DWT function register 0(DWT_FUNCTR0) . . . . .1619
41.7.11DWT device type architecture register (DWT_DEVARCHR) . . . . .1623
41.7.12DWT device type register 4 (DWT_DEVTYPE) . . . . .1624
41.7.13DWT CoreSight peripheral identity register 4 (DWT_PIDR4) . . . . .1624
41.7.14DWT CoreSight peripheral identity register 0 (DWT_PIDR0) . . . . .1625
41.7.15DWT CoreSight peripheral identity register 1 (DWT_PIDR1) . . . . .1625
41.7.16DWT CoreSight peripheral identity register 2 (DWT_PIDR2) . . . . .1626
41.7.17DWT CoreSight peripheral identity register 3 (DWT_PIDR3) . . . . .1626
41.7.18DWT CoreSight component identity register 0 (DWT_CIDR0) . . . . .1627
41.7.19DWT CoreSight peripheral identity register 1 (DWT_CIDR1) . . . . .1627
41.7.20DWT CoreSight component identity register 2 (DWT_CIDR2) . . . . .1627
41.7.21DWT CoreSight component identity register 3 (DWT_CIDR3) . . . . .1628
41.7.22DWT register map and reset values . . . . .1629
41.8Instrumentation trace macrocell (ITM) . . . . .1632
41.8.1ITM registers . . . . .1632
41.8.2ITM stimulus register x (ITM_STIMRx) . . . . .1632
41.8.3ITM trace enable register (ITM_TER) . . . . .1633
41.8.4ITM trace privilege register (ITM_TPR) . . . . .1633
41.8.5ITM trace control register (ITM_TCR) . . . . .1634
41.8.6ITM device type architecture register (ITM_DEVARCHR) . . . . .1635
41.8.7ITM device type register 4 (ITM_DEVTYPE) . . . . .1635
41.8.8ITM CoreSight peripheral identity register 4 (ITM_PIDR4) . . . . .1636
41.8.9ITM CoreSight peripheral identity register 0 (ITM_PIDR0) . . . . .1636
41.8.10ITM CoreSight peripheral identity register 1 (ITM_PIDR1) . . . . .1636
41.8.11ITM CoreSight peripheral identity register 2 (ITM_PIDR2) . . . . .1637
41.8.12ITM CoreSight peripheral identity register 3 (ITM_PIDR3) . . . . .1637
41.8.13ITM CoreSight component identity register 0 (ITM_CIDR0) . . . . .1638
41.8.14ITM CoreSight peripheral identity register 1 (ITM_CIDR1) . . . . .1638
41.8.15ITM CoreSight component identity register 2 (ITM_CIDR2) . . . . .1638
41.8.16ITM CoreSight component identity register 3 (ITM_CIDR3) . . . . .1639
41.8.17ITM register map and reset values . . . . .1640
41.9Breakpoint unit (BPU) . . . . .1642
41.9.1BPU control register (BPU_CTRLR) . . . . .1642
41.9.2BPU comparator x register (BPU_COMPxR) . . . . .1642
41.9.3BPU device type architecture register (BPU_DEVARCHR) . . . . .1643
41.9.4BPU device type register 4 (BPU_DEVTYPE) . . . . .1643
41.9.5BPU CoreSight peripheral identity register 4 (BPU_PIDR4) . . . . .1644
41.9.6BPU CoreSight peripheral identity register 0 (BPU_PIDR0) . . . . .1644
41.9.7BPU CoreSight peripheral identity register 1 (BPU_PIDR1) . . . . .1644
41.9.8BPU CoreSight peripheral identity register 2 (BPU_PIDR2) . . . . .1645
41.9.9BPU CoreSight peripheral identity register 3 (BPU_PIDR3) . . . . .1645
41.9.10BPU CoreSight component identity register 0 (BPU_CIDR0) . . . . .1646
41.9.11BPU CoreSight peripheral identity register 1 (BPU_CIDR1) . . . . .1646
41.9.12BPU CoreSight component identity register 2 (BPU_CIDR2) . . . . .1646
41.9.13BPU CoreSight component identity register 3 (BPU_CIDR3) . . . . .1647
41.9.14BPU register map and reset values . . . . .1648
41.10Embedded trace macrocell (ETM) . . . . .1649
41.10.1ETM registers . . . . .1649
41.10.2ETM register map and reset values . . . . .1672
41.11Trace port interface unit (TPIU) . . . . .1675
41.11.1TPIU registers . . . . .1676
41.11.2TPIU supported port size register (TPIU_SSPSR) . . . . .1676
41.11.3TPIU current port size register (TPIU_CSPSR) . . . . .1677
41.11.4TPIU asynchronous clock prescaler register (TPIU_ACPR) . . . . .1677
41.11.5TPIU selected pin protocol register (TPIU_SPPR) . . . . .1677
41.11.6TPIU formatter and flush status register (TPIU_FFSR) . . . . .1678
41.11.7TPIU formatter and flush control register (TPIU_FFCR) . . . . .1678
41.11.8TPIU formatter synchronization counter register (TPIU_FSCR) . . . . .1679
41.11.9TPIU claim tag set register (TPIU_CLAIMSETR) . . . . .1680
41.11.10TPIU claim tag clear register (TPIU_CLAIMCLR) . . . . .1680
41.11.11TPIU device configuration register (TPIU_DEVIDR) . . . . .1681
41.11.12TPIU device type identifier register (TPIU_DEVTYPE) . . . . .1681
41.11.13TPIU CoreSight peripheral identity register 4 (TPIU_PIDR4) . . . . .1682
41.11.14TPIU CoreSight peripheral identity register 0 (TPIU_PIDR0) . . . . .1682
41.11.15TPIU CoreSight peripheral identity register 1 (TPIU_PIDR1) . . . . .1682
41.11.16TPIU CoreSight peripheral identity register 2 (TPIU_PIDR2) . . . . .1683
41.11.17TPIU CoreSight peripheral identity register 3 (TPIU_PIDR3) . . . . .1683
41.11.18TPIU CoreSight component identity register 0 (TPIU_CIDR0) . . . . .1684
41.11.19TPIU CoreSight peripheral identity register 1 (TPIU_CIDR1) . . . . .1684
41.11.20TPIU CoreSight component identity register 2 (TPIU_CIDR2) . . . . .1684
41.11.21TPIU CoreSight component identity register 3 (TPIU_CIDR3) . . . . .1685
41.11.22TPIU register map and reset values . . . . .1686
41.12Cross trigger interface (CTI) . . . . .1688
41.12.1CTI registers . . . . .1689
41.13Microcontroller debug unit (DBGMCU) . . . . .1702
41.13.1DBGMCU access . . . . .1702
41.13.2Device ID . . . . .1702
41.13.3Part number codification . . . . .1702
41.13.4Low-power mode emulation . . . . .1702
41.13.5Low-power mode status . . . . .1704
41.13.6Peripheral clock freeze . . . . .1704
41.13.7DBGMCU registers . . . . .1705
41.13.8DBGMCU register map and reset values . . . . .1717
41.14References . . . . .1719
42Device electronic signature (DESIG) . . . . .1720
42.1Device electronic signature registers . . . . .1720
42.1.1DESIG package data register (DESIG_PKGR) . . . . .1720
42.1.2DESIG 96-bit unique device ID register 1 (DESIG_UIDR1) . . . . .1720
42.1.3DESIG 96-bit unique device ID register 2 (DESIG_UIDR2) . . . . .1721

42.1.4 DESIG 96-bit unique device ID register 3 (DESIG_UIDR3) . . . . . 1721

42.1.5 DESIG temperature calibration 1 register (DESIG_TSCAL1R) . . . . . 1722

42.1.6 DESIG temperature calibration 2 register (DESIG_TSCAL2R) . . . . . 1722

42.1.7 DESIG flash size data register (DESIG_FLASHSIZER) . . . . . 1722

42.1.8 DESIG internal voltage reference calibration register
(DESIG_VREFINTCALR) . . . . . 1723

42.1.9 DESIG IEEE 64-bit unique device ID register 1 (DESIG_UID64R1) . 1723

42.1.10 DESIG IEEE 64-bit unique device ID register 2 (DESIG_UID64R2) . 1723

42.1.11 DESIG register map . . . . . 1724

43        Revision history . . . . . 1725

List of tables

Table 1.Bus matrix acces arbitration . . . . .70
Table 2.Memory map security attribution example vs. SAU configuration regions . . . . .71
Table 3.Securable peripherals by TZSC . . . . .72
Table 4.TrustZone ® -aware peripherals . . . . .73
Table 5.Memory map and peripheral register boundary addresses . . . . .77
Table 6.Boot modes when TrustZone ® is disabled (TZEN = 0) . . . . .83
Table 7.Boot modes when TrustZone ® is enabled (TZEN = 1). . . . .83
Table 8.Boot space versus RDP protection . . . . .84
Table 9.Configuring security attributes with IDAU and SAU . . . . .90
Table 10.MPCWM resources. . . . .92
Table 11.MPCBB resources . . . . .92
Table 12.DMA channel use (security) . . . . .95
Table 13.Secure alternate function between peripherals and allocated I/Os . . . . .98
Table 14.Nonsecure peripheral functions not connected to secure I/Os . . . . .98
Table 15.Nonsecure peripheral functions that can be connected to secure I/Os . . . . .99
Table 16.TrustZone-aware DBGMCU accesses management . . . . .100
Table 17.DMA channel use (privilege). . . . .105
Table 18.Internal tampers in TAMP . . . . .108
Table 19.Accelerated cryptographic operations . . . . .111
Table 20.Main product life-cycle transitions. . . . .113
Table 21.Typical product life-cycle phases . . . . .113
Table 22.OEM key RDP unlocking methods . . . . .115
Table 23.Debug protection with RDP . . . . .117
Table 24.Software intellectual property protection with RDP. . . . .118
Table 25.GTZC features . . . . .122
Table 26.GTZC sub-blocks address offset . . . . .123
Table 27.MPCWM resource assignment . . . . .123
Table 28.MPCBB resource assignment. . . . .123
Table 29.Secure properties of sub-regions A and B . . . . .126
Table 30.Privileged properties of sub-regions A and B . . . . .126
Table 31.GTZC interrupt request. . . . .128
Table 32.GTZC1 TZSC register map and reset values . . . . .140
Table 33.GTZC1 TZIC register map and reset values. . . . .157
Table 34.GTZC1 MPCBB1 register map and reset values . . . . .162
Table 35.GTZC1 MPCBB2 register map and reset values . . . . .163
Table 36.Internal SRAMs features. . . . .165
Table 37.SRAM access parity errors . . . . .166
Table 38.SRAM parity error bus master ID. . . . .166
Table 39.Number of wait states versus hclk frequency and voltage range scaling . . . . .166
Table 40.Effect of low-power modes on RAMCFG . . . . .167
Table 41.RAMCFG interrupt requests . . . . .167
Table 42.RAMCFG register map and reset values . . . . .174
Table 43.Flash module 1-Mbyte single bank organization . . . . .176
Table 44.Number of wait states according to CPU clock (hclk1) frequency (LPM = 0). . . . .177
Table 45.Number of wait states according to CPU clock (hclk1) frequency (LPM = 1). . . . .178
Table 46.Program and erase suspend control. . . . .187
Table 47.Flash operation interrupted by a system reset . . . . .190
Table 48.User option byte organization mapping . . . . .191
Table 49.Default secure option bytes after TZEN activation . . . . .194
Table 50.Secure watermark-based area . . . . .195
Table 51.Secure hide protection . . . . .196
Table 52.Write access to HDP_PEXT and HDPEXT_ACCDIS . . . . .197
Table 53.Secure hide protection extension . . . . .198
Table 54.Flash security state . . . . .199
Table 55.WRP protection . . . . .201
Table 56.Flash memory readout protection status (TZEN=0) . . . . .202
Table 57.Access status versus protection level and execution modes when TZEN = 0 . . . . .203
Table 58.Flash memory readout protection status (TZEN = 1) . . . . .204
Table 59.Access status versus protection level and execution modes when TZEN = 1 . . . . .205
Table 60.Flash memory access versus RDP level when TrustZone is active (TZEN = 1) . . . . .211
Table 61.Flash memory secure access versus HDP and HDP extension (TZEN = 1) . . . . .212
Table 62.Flash memory access versus RDP level when TrustZone is disabled (TZEN = 0) . . . . .212
Table 63.Flash memory mass erase versus RDP level when TrustZone is active (TZEN = 1) . . . . .213
Table 64.Flash system memory, OTP and RSS accesses . . . . .213
Table 65.Flash page access versus privilege mode . . . . .214
Table 66.Flash mass erase versus privilege mode . . . . .214
Table 67.Flash registers access . . . . .214
Table 68.SECBBRx registers access when TrustZone is active (TZEN = 1) . . . . .214
Table 69.PRIVBBRx registers access when TrustZone is active (TZEN = 1) . . . . .215
Table 70.PRIVBBRx registers access when TrustZone is disabled (TZEN = 0) . . . . .215
Table 71.Flash interrupt requests . . . . .215
Table 72.FLASH register map and reset values . . . . .245
Table 73.ICACHE features . . . . .250
Table 74.TAG memory dimensioning parameters
for n-way set associative operating mode (default) . . . . .		252
Table 75.TAG memory dimensioning parameters for direct-mapped cache mode . . . . .253
Table 76.ICACHE cacheability for AHB transaction . . . . .255
Table 77.Memory configurations . . . . .255
Table 78.ICACHE remap region size, base address, and remap address . . . . .256
Table 79.ICACHE interrupts . . . . .260
Table 80.ICACHE register map and reset values . . . . .264
Table 81.Radio features . . . . .267
Table 82.Input/output pins . . . . .267
Table 83.PA output power table format . . . . .268
Table 84.2.4 GHz RADIO supply configuration . . . . .269
Table 85.Effect of low-power modes on the 2.4 GHz RADIO . . . . .270
Table 86.2.4 PTACONV input/output pins . . . . .272
Table 87.PTACONV internal input/output signals . . . . .272
Table 88.2.4 PTACONV timing parameters . . . . .276
Table 89.Effect of low-power modes on the PTACONV . . . . .277
Table 90.PTACONV register map and reset values . . . . .281
Table 91.PWR input/output pins . . . . .283
Table 92.PWR internal input/output signals . . . . .283
Table 93.PWR wake-up source selection . . . . .284
Table 94.Low-power mode summary . . . . .298
Table 95.Functionalities depending on the working mode . . . . .299
Table 96.Sleep mode . . . . .306
Table 97.Stop 0 mode . . . . .309
Table 98.Stop 1 mode . . . . .311
Table 99.Stop 2 mode . . . . .313
Table 100.Stop 3 mode . . . . .315
Table 101.GPIO retention pin with pull-up and pull-down . . . . .317
Table 102.Standby mode. . . . .319
Table 103.Power modes output states versus MCU power modes. . . . .320
Table 104.PWR Security configuration summary . . . . .321
Table 105.PWR interrupt requests . . . . .322
Table 106.PWR register map and reset values . . . . .347
Table 107.RCC input/output signals connected to package pins or balls . . . . .350
Table 108.LSI clock selection . . . . .361
Table 109.SYSCLK and bus maximum frequency . . . . .362
Table 110.PLL1RCLKPRERDY delay versus pll1rclock frequency. . . . .363
Table 111.PLL1RCLKPRERDY and SYSCLK behavior . . . . .363
Table 112.Clock source maximum frequency . . . . .365
Table 113.2.4 GHz RADIO bus clock control . . . . .367
Table 114.Autonomous peripherals. . . . .375
Table 115.RCC security configuration summary . . . . .377
Table 116.Interrupt sources and control . . . . .380
Table 117.RCC register map and reset values . . . . .451
Table 118.GPIO implementation . . . . .458
Table 119.Port bit configuration. . . . .460
Table 120.GPIO secured bits . . . . .468
Table 121.GPIOA register map and reset values . . . . .500
Table 122.GPIOB register map and reset values . . . . .501
Table 123.GPIOC register map and reset values . . . . .502
Table 124.GPIOH register map and reset values . . . . .503
Table 125.Effect of low-power modes on I/O compensation . . . . .505
Table 126.TrustZone security and privilege register access . . . . .505
Table 127.BOOSTEN and ANASWVDD set/cleared. . . . .509
Table 128.SYSCFG register map and reset values. . . . .520
Table 129.Peripherals interconnect matrix . . . . .521
Table 130.LPDMA1 channels implementation. . . . .529
Table 131.LPDMA1 autonomous mode and wake-up in low-power modes . . . . .529
Table 132.Programmed LPDMA1 request. . . . .530
Table 133.Programmed LPDMA1 request as a block request . . . . .531
Table 134.Programmed LPDMA1 trigger . . . . .532
Table 135.Programmed LPDMA source/destination single. . . . .551
Table 136.Programmed data handling . . . . .552
Table 137.Effect of low-power modes on LPDMA. . . . .564
Table 138.LPDMA interrupt requests . . . . .565
Table 139.LPDMA register map and reset values . . . . .584
Table 140.Vector table. . . . .586
Table 141.EXTI pin overview. . . . .591
Table 142.EVG pin overview . . . . .591
Table 143.EXTI line connections. . . . .592
Table 144.Masking functionality . . . . .594
Table 145.Register protection overview . . . . .595
Table 146.EXTI register map sections. . . . .597
Table 147.EXTI register map and reset values . . . . .609
Table 148.CRC internal input/output signals . . . . .612
Table 149.CRC register map and reset values . . . . .617
Table 150.XSPI implementation . . . . .618
Table 151.XSPI input/output pins . . . . .620
Table 152.XSPI internal signals . . . . .620
Table 153.OctaRAM command address bit assignment
(based on 64 Mb OctaRAM) . . . . .		633
Table 154.Address alignment cases . . . . .637
Table 155.XSPI interrupt requests . . . . .638
Table 156.XSPI register map and reset values . . . . .651
Table 157.STM32WBA2 features . . . . .653
Table 158.DLYB internal input/output signals . . . . .654
Table 159.DLYB interconnection . . . . .654
Table 160.Delay block control . . . . .655
Table 161.DLYB register map and reset values . . . . .658
Table 162.ADC features . . . . .660
Table 163.Memory location of the temperature sensor calibration values . . . . .661
Table 164.Memory location of the internal reference voltage sensor
calibration value . . . . .		661
Table 165.ADC input/output pins . . . . .662
Table 166.ADC internal input/output signals . . . . .663
Table 167.ADC interconnection . . . . .663
Table 168.Latency between trigger and start of conversion . . . . .668
Table 169.Configuring the trigger polarity . . . . .675
Table 170.t SAR timings depending on resolution . . . . .677
Table 171.Analog watchdog comparison . . . . .689
Table 172.Analog watchdog 1 channel selection . . . . .689
Table 173.Maximum output results vs N and M. Grayed values indicates truncation . . . . .693
Table 174.Effect of low-power modes on the ADC . . . . .698
Table 175.ADC wake-up and interrupt requests . . . . .699
Table 176.ADC register map and reset values . . . . .719
Table 177.RNG internal input/output signals . . . . .723
Table 178.RNG interrupt requests . . . . .732
Table 179.RNG configurations . . . . .733
Table 180.Additional health test configurations . . . . .733
Table 181.Configuration selection . . . . .733
Table 182.RNG register map and reset map . . . . .741
Table 183.AES features . . . . .743
Table 184.AES internal input/output signals . . . . .743
Table 185.AES approved symmetric key functions . . . . .744
Table 186.Counter mode initialization vector definition . . . . .753
Table 187.Initialization of IV registers in GCM mode . . . . .756
Table 188.GCM last block definition . . . . .756
Table 189.Initialization of IV registers in CCM mode . . . . .763
Table 190.AES data swapping example . . . . .765
Table 191.Key endianness in AES_KEYRx registers (128/256-bit keys) . . . . .768
Table 192.IVI bitfield spread over AES_IVRx registers . . . . .768
Table 193.Effect of low-power modes on AES . . . . .769
Table 194.AES interrupt requests . . . . .770
Table 195.Processing latency for ECB, CBC and CTR . . . . .771
Table 196.Processing latency for GCM and CCM (in clock cycles) . . . . .771
Table 197.AES register map and reset values . . . . .783
Table 198.HASH internal input/output signals . . . . .786
Table 199.Information on supported hash algorithms . . . . .787
Table 200.Hash processor outputs . . . . .790
Table 201.Processing time (in clock cycle) . . . . .795
Table 202.HASH interrupt requests . . . . .796
Table 203.HASH1 register map and reset values . . . . .804
Table 204.OTFDEC internal input/output signals . . . . .807
Table 205.OTFDEC interrupt requests . . . . .811
Table 206.OTFDEC register map and reset values . . . . .825
Table 207.Internal input/output signals . . . . .830
Table 208.PKA integer arithmetic functions list . . . . .831
Table 209.PKA prime field (Fp) elliptic curve functions list . . . . .832
Table 210.Example of 'a' curve coefficient for ECC Fp scalar . . . . .838
Table 211.Montgomery parameter computation . . . . .838
Table 212.Modular addition . . . . .839
Table 213.Modular subtraction . . . . .839
Table 214.Montgomery multiplication . . . . .840
Table 215.Modular exponentiation (normal mode) . . . . .841
Table 216.Modular exponentiation (fast mode) . . . . .841
Table 217.Modular exponentiation (protected mode) . . . . .842
Table 218.Modular inversion . . . . .842
Table 219.Modular reduction . . . . .843
Table 220.Arithmetic addition . . . . .843
Table 221.Arithmetic subtraction . . . . .843
Table 222.Arithmetic multiplication . . . . .844
Table 223.Arithmetic comparison . . . . .844
Table 224.CRT exponentiation . . . . .845
Table 225.Point on elliptic curve Fp check . . . . .846
Table 226.ECC Fp scalar multiplication . . . . .846
Table 227.ECDSA sign - Inputs . . . . .848
Table 228.ECDSA sign - Outputs . . . . .848
Table 229.Extended ECDSA sign - additional outputs . . . . .849
Table 230.ECDSA verification - inputs . . . . .849
Table 231.ECDSA verification - outputs . . . . .850
Table 232.ECC complete addition . . . . .850
Table 233.ECC double base ladder . . . . .851
Table 234.ECC projective to affine . . . . .852
Table 235.Family of supported curves for ECC operations . . . . .853
Table 236.Modular exponentiation . . . . .854
Table 237.ECC scalar multiplication . . . . .854
Table 238.ECDSA signature average computation time . . . . .855
Table 239.ECDSA verification average computation times . . . . .855
Table 240.ECC double base ladder average computation times . . . . .855
Table 241.ECC projective to affine average computation times . . . . .855
Table 242.ECC complete addition average computation times . . . . .855
Table 243.Point on elliptic curve Fp check average computation times . . . . .855
Table 244.Montgomery parameters average computation times . . . . .856
Table 245.Effect of low-power modes on PKA . . . . .856
Table 246.PKA interrupt requests . . . . .856
Table 247.PKA register map and reset values . . . . .861
Table 248.General purpose timers . . . . .863
Table 249.TIM input/output pins . . . . .865
Table 250.TIM internal input/output signals . . . . .865
Table 251.Interconnect to the tim_ti1 input multiplexer . . . . .866
Table 252.Interconnect to the tim_ti2 input multiplexer . . . . .866
Table 253.Interconnect to the tim_ti3 input multiplexer . . . . .866
Table 254.Interconnect to the tim_ti4 input multiplexer . . . . .866
Table 255.TIMx internal trigger connection . . . . .867
Table 256.Interconnect to the tim_etr input multiplexer . . . . .867
Table 257.Interconnect to the tim_ocref_clr input multiplexer . . . . .867
Table 258.CCR and ARR register change dithering pattern . . . . .898
Table 259.CCR register change dithering pattern in center-aligned PWM mode . . . . .899
Table 260.Counting direction versus encoder signals(CC1P = CC2P = 0) . . . . .908
Table 261.Counting direction versus encoder signals and polarity settings . . . . .913
Table 262.DMA request . . . . .938
Table 263.Effect of low-power modes on TIM2 . . . . .938
Table 264.Interrupt requests . . . . .939
Table 265.Output control bit for standard tim_ocx channels . . . . .960
Table 266.TIM2 register map and reset values . . . . .972
Table 267.TIM16/TIM17 . . . . .975
Table 268.TIM input/output pins . . . . .976
Table 269.TIM internal input/output signals . . . . .977
Table 270.Interconnect to the tim_ti1 input multiplexer . . . . .978
Table 271.Timer break interconnect . . . . .978
Table 272.System break interconnect . . . . .978
Table 273.Interconnect to the ocref_clr input multiplexer . . . . .978
Table 274.CCR and ARR register change dithering pattern . . . . .997
Table 275.Break protection disarming conditions . . . . .1005
Table 276.DMA request . . . . .1012
Table 277.Effect of low-power modes on TIM16/TIM17 . . . . .1012
Table 278.Interrupt requests . . . . .1013
Table 279.Output control bits for complementary tim_oc1 and tim_oc1n channels with break feature (TIM16/TIM17) . . . . .1024
Table 280.TIM16/TIM17 register map and reset values . . . . .1038
Table 281.LPTIM device implementation . . . . .1041
Table 282.LPTIM features . . . . .1041
Table 283.LPTIM1/2 input/output pins . . . . .1042
Table 284.LPTIM1/2 internal signals . . . . .1043
Table 285.LPTIM1/2 external trigger connections . . . . .1044
Table 286.LPTIM1/2 input 1 connections . . . . .1044
Table 287.LPTIM1/2 input 2 connections . . . . .1044
Table 288.LPTIM1/2 input capture 1 connections . . . . .1044
Table 289.LPTIM1/2 input capture 2 connections . . . . .1044
Table 290.Prescaler division ratios . . . . .1046
Table 291.Encoder counting scenarios . . . . .1053
Table 292.Input capture Glitch filter latency (in counter step unit). . . . .1057
Table 293.Effect of low-power modes on the LPTIM . . . . .1062
Table 294.Interrupt events . . . . .1063
Table 295.LPTIM register map and reset values . . . . .1084
Table 296.IWDG features . . . . .1087
Table 297.IWDG delays versus actions . . . . .1088
Table 298.IWDG internal input/output signals . . . . .1089
Table 299.Effect of low power modes on IWDG . . . . .1093
Table 300.IWDG interrupt request . . . . .1095
Table 301.IWDG register map and reset values . . . . .1101
Table 302.RTC input/output pins . . . . .1104
Table 303.RTC internal input/output signals . . . . .1104
Table 304.RTC interconnection . . . . .1105
Table 305.RTC pin PC13 configuration . . . . .1105
Table 306.RTC_OUT mapping . . . . .1107
Table 307.Effect of low-power modes on RTC . . . . .1123
Table 308.RTC pins functionality over modes . . . . .1123
Table 309.Nonsecure interrupt requests . . . . .1124
Table 310.Secure interrupt requests . . . . .1124
Table 311.RTC register map and reset values . . . . .1154
Table 312.TAMP input/output pins . . . . .1158
Table 313.TAMP internal input/output signals . . . . .1158
Table 314.TAMP interconnection . . . . .1159
Table 315.Device resource x tamper protection . . . . .1164
Table 316.Active tamper output change period . . . . .1168
Table 317.Minimum ATPER value . . . . .1169
Table 318.Active tamper filtered pulse duration . . . . .1170
Table 319.Effect of low-power modes on TAMP . . . . .1171
Table 320.TAMP pins functionality over modes . . . . .1171
Table 321.Interrupt requests . . . . .1172
Table 322.TAMP register map and reset values . . . . .1198
Table 323.I2C implementation . . . . .1201
Table 324.I2C input/output pins . . . . .1202
Table 325.I2C internal input/output signals . . . . .1203
Table 326.I2C1 interconnection . . . . .1203
Table 327.I2C3 interconnection . . . . .1203
Table 328.Comparison of analog and digital filters . . . . .1206
Table 329.I 2 C-bus and SMBus specification data setup and hold times . . . . .1208
Table 330.I2C configuration . . . . .1212
Table 331.I 2 C-bus and SMBus specification clock timings . . . . .1223
Table 332.Timing settings for f I2CCLK of 8 MHz . . . . .1233
Table 333.Timing settings for f I2CCLK of 16 MHz . . . . .1233
Table 334.SMBus timeout specifications . . . . .1235
Table 335.SMBus with PEC configuration . . . . .1237
Table 336.TIMEOUTA[11:0] for maximum t TIMEOUT of 25 ms . . . . .1238
Table 337.TIMEOUTB[11:0] for maximum t LOW:SEXT and t LOW:MEXT of 8 ms . . . . .1238
Table 338.TIMEOUTA[11:0] for maximum t IDLE of 50 µs . . . . .1238
Table 339.Effect of low-power modes to I2C . . . . .1248
Table 340.I2C interrupt requests . . . . .1249
Table 341.I2C register map and reset values . . . . .1266
Table 342.Instance implementation on STM32WBA2 . . . . .1269
Table 343.USART/LPUART features . . . . .1269
Table 344.USART/UART input/output pins . . . . .1272
Table 345.USART internal input/output signals . . . . .1273
Table 346.USART interconnection (USART1) . . . . .1273
Table 347.Noise detection from sampled data . . . . .1285
Table 348.Tolerance of the USART receiver when BRR [3:0] = 0000 . . . . .1289
Table 349.Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . .1289
Table 350.USART frame formats . . . . .1294
Table 351.Effect of low-power modes on the USART . . . . .1315
Table 352.USART interrupt requests . . . . .1316
Table 353.USART register map and reset values . . . . .1355
Table 354.Instance implementation on STM32WBA2 . . . . .1358
Table 355.USART/LPUART features . . . . .1358
Table 356.LPUART input/output pins . . . . .1360
Table 357.LPUART internal input/output signals . . . . .1360
Table 358.LPUART interconnections (LPUART1) . . . . .1361
Table 359.Error calculation for programmed baud rates at lpuart_ker_ck_pres= 32.768 kHz . . . . .1372
Table 360.Tolerance of the LPUART receiver. . . . .1373
Table 362.Effect of low-power modes on the LPUART . . . . .1384
Table 363.LPUART interrupt requests. . . . .1385
Table 364.LPUART register map and reset values . . . . .1410
Table 365.SPI features . . . . .1414
Table 366.SPI input/output pins. . . . .1416
Table 367.SPI internal input/output signals . . . . .1417
Table 368.SPI interconnection (SPI3) . . . . .1417
Table 369.Effect of low-power modes on the SPI . . . . .1445
Table 370.SPI wake-up and interrupt requests . . . . .1446
Table 371.SPI register map and reset values . . . . .1462
Table 372.SAI features . . . . .1464
Table 373.SAI internal input/output signals . . . . .1466
Table 374.SAI input/output pins. . . . .1466
Table 375.MCLK_x activation conditions. . . . .1473
Table 376.Clock generator programming examples . . . . .1476
Table 377.SAI_A configuration for TDM mode . . . . .1483
Table 378.TDM frame configuration examples . . . . .1485
Table 379.SOPD pattern . . . . .1488
Table 380.Parity bit calculation . . . . .1488
Table 381.Audio sampling frequency versus symbol rates . . . . .1489
Table 382.SAI interrupt sources . . . . .1498
Table 383.SAI register map and reset values . . . . .1526
Table 384.STM32WBA2 USB implementation . . . . .1528
Table 385.USB input/output pins . . . . .1530
Table 386.Double-buffering buffer flag definition. . . . .1542
Table 387.Bulk double-buffering memory buffers usage (Device mode). . . . .1542
Table 388.Bulk double-buffering memory buffers usage (Host mode) . . . . .1544
Table 389.Isochronous memory buffers usage . . . . .1545
Table 390.Isochronous memory buffers usage . . . . .1546
Table 391.Resume event detection . . . . .1548
Table 392.Resume event detection for host . . . . .1549
Table 393.Reception status encoding . . . . .1567
Table 394.Endpoint/channel type encoding. . . . .1567
Table 395.Endpoint/channel kind meaning . . . . .1567
Table 396.Transmission status encoding . . . . .1567
Table 397.USB register map and reset values . . . . .1568
Table 398.Definition of allocated buffer memory . . . . .1571
Table 399.USB SRAM register map and reset values . . . . .1574
Table 400.JTAG/serial-wire debug port pins . . . . .1576
Table 401.Single-wire trace port pins . . . . .1576
Table 402.Embedded trace port pins. . . . .1577
Table 403.Authentication signal states . . . . .1579
Table 404.JTAG-DP data registers . . . . .1581
Table 405.Packet request . . . . .1583
Table 406.ACK response. . . . .1583
Table 407.Data transfer. . . . .1583
Table 408.DP register map and reset values . . . . .1590
Table 409.AP register map and reset values. . . . .1597
Table 410.System debug ROM table . . . . .1598
Table 411.MCU ROM table . . . . .1605
Table 412.Processor ROM table . . . . .1606
Table 413.ROM table register map and reset values . . . . .1613
Table 414.DWT register map and reset values . . . . .1629
Table 415.ITM register map and reset values . . . . .1640
Table 416.BPU register map and reset values . . . . .1648
Table 417.ETM register map and reset values . . . . .1672
Table 418.TPIU register map and reset values . . . . .1686
Table 419.CTI inputs . . . . .1688
Table 420.CTI outputs . . . . .1688
Table 421.CTI register map and reset values . . . . .1700
Table 422.Low power debug overview . . . . .1703
Table 423.Low-power mode status flags . . . . .1704
Table 424.Peripheral clock freeze control . . . . .1704
Table 425.Peripheral behavior in debug mode . . . . .1705
Table 426.Debugger access to freeze register bits . . . . .1705
Table 427.DBGMCU register map and reset values . . . . .1717
Table 428.DESIG register map and reset values . . . . .1724
Table 429.Document revision history . . . . .1725

List of figures

Figure 1.System architecture . . . . .69
Figure 2.Memory map . . . . .76
Figure 3.Secure/nonsecure partitioning using TrustZone technology . . . . .87
Figure 4.Sharing memory map between CPU in secure and nonsecure state . . . . .89
Figure 5.Secure world transition and memory partitioning . . . . .90
Figure 6.Global TrustZone framework and TrustZone awareness . . . . .91
Figure 7.Flash memory TrustZone protections . . . . .94
Figure 8.Flash memory secure HDP area . . . . .102
Figure 9.Key management principle . . . . .110
Figure 10.Device life-cycle security . . . . .112
Figure 11.RDP level transition scheme . . . . .114
Figure 12.Collaborative development principle . . . . .117
Figure 13.GTZC in Armv8-M subsystem block diagram . . . . .122
Figure 14.GTZC block diagram . . . . .124
Figure 15.Watermark memory protection controller (region x/sub-regions A and B) . . . . .126
Figure 16.MPCBB block diagram . . . . .127
Figure 17.Example secure, HDP, HDP extension areas . . . . .198
Figure 18.RDP level transition scheme when TrustZone is disabled (TZEN = 0) . . . . .207
Figure 19.RDP level transition scheme when TrustZone is enabled (TZEN = 1) . . . . .208
Figure 20.ICACHE block diagram . . . . .251
Figure 21.ICACHE TAG and data memories functional view . . . . .253
Figure 22.ICACHE remapping address mechanism . . . . .256
Figure 23.Radio system block diagram . . . . .267
Figure 24.Transmit path and output power control . . . . .268
Figure 25.Bluetooth AoA/AoD antennas control . . . . .269
Figure 26.PTACONV block diagram . . . . .272
Figure 27.4-wire PTA grant protocol . . . . .273
Figure 28.4-wire PTA deny protocol . . . . .274
Figure 29.3-wire time-multiplexed PTA_STATUS . . . . .275
Figure 30.Power supply overview . . . . .285
Figure 31.Application power supply schemes . . . . .287
Figure 32.Brownout reset waveform . . . . .292
Figure 33.PVD thresholds . . . . .293
Figure 34.Operating modes . . . . .297
Figure 35.Simplified diagram of the reset circuit . . . . .351
Figure 36.Clock tree . . . . .354
Figure 37.HSE32 hardware configurations . . . . .356
Figure 38.LSE 32 clock sources . . . . .360
Figure 39.Radio control . . . . .368
Figure 40.Audio synchronization counter block diagram . . . . .372
Figure 41.Audio synchronization timing example . . . . .373
Figure 42.Structure of 3 or 5 V-tolerant GPIO (TT or FT) . . . . .459
Figure 43.Input floating / pull-up / pull-down configurations . . . . .464
Figure 44.Output configuration . . . . .465
Figure 45.Alternate function configuration . . . . .465
Figure 46.High-impedance analog configuration . . . . .466
Figure 47.I/O compensation cell block diagram . . . . .504
Figure 48.LPDMA block diagram . . . . .533
Figure 49.LPDMA channel direct programming without linked-list (LPDMA_CxLLR = 0) . . . . .534
Figure 50.LPDMA channel suspend and resume sequence . . . . .535
Figure 51.LPDMA channel abort and restart sequence . . . . .536
Figure 52.Static linked-list data structure (all Uxx = 1) of channel x . . . . .537
Figure 53.LPDMA dynamic linked-list data structure of an addressing channel x . . . . .538
Figure 54.LPDMA channel execution and linked-list programming
in run-to-completion mode (LPDMA_CxCR.LSM = 0) . . . . .		540
Figure 55.Inserting a LLn with an auxiliary LPDMA channel y . . . . .542
Figure 56.LPDMA channel execution and linked-list programming
in link step mode (LPDMA_CxCR.LSM = 1) . . . . .		544
Figure 57.Building LLn+1: LPDMA dynamic linked-lists in link step mode . . . . .545
Figure 58.Replace with a new LLn' in register file in link step mode . . . . .546
Figure 59.Replace with a new LLn' and LLn+1' in memory in link step mode (option 1) . . . . .547
Figure 60.Replace with a new LLn' and LLn+1' in memory in link step mode (option 2) . . . . .548
Figure 61.LPDMA channel execution and linked-list programming . . . . .550
Figure 62.LPDMA arbitration policy . . . . .554
Figure 63.Trigger hit, memorization and overrun waveform . . . . .558
Figure 64.LPDMA circular buffer programming: update of the memory start address . . . . .559
Figure 65.Shared LPDMA channel with circular buffering:
update of the memory start address . . . . .		560
Figure 66.EXTI block diagram . . . . .591
Figure 67.Configurable event trigger logic CPU wake-up . . . . .593
Figure 68.EXTI mux GPIO selection . . . . .594
Figure 69.CRC calculation unit block diagram . . . . .612
Figure 70.XSPI block diagram for quad configuration . . . . .620
Figure 71.SDR read command in octal configuration . . . . .621
Figure 72.DTR read in octal-SPI mode with DQS (Macronix mode) example . . . . .624
Figure 73.SDR write command in octal-SPI mode example . . . . .626
Figure 74.DTR write in octal-SPI mode (Macronix mode) example . . . . .627
Figure 75.D0/D1 data ordering in octal-SPI DTR mode (Micron) - Read access . . . . .632
Figure 76.OctaRAM read operation with reverse data ordering D1/D0 . . . . .632
Figure 77.NCS when CKMODE = 0 (T = CLK period) . . . . .636
Figure 78.Example of software control of two external memories (octal mode) . . . . .637
Figure 79.DLYB block diagram . . . . .654
Figure 80.ADC block diagram . . . . .662
Figure 81.ADC calibration . . . . .665
Figure 82.Calibration factor forcing . . . . .666
Figure 83.Enabling/disabling the ADC . . . . .667
Figure 84.ADC clock scheme . . . . .668
Figure 85.ADC4 connectivity . . . . .669
Figure 86.Analog-to-digital conversion time . . . . .674
Figure 87.ADC conversion timings . . . . .674
Figure 88.Stopping an ongoing conversion . . . . .675
Figure 89.Single conversions of a sequence, software trigger . . . . .678
Figure 90.Continuous conversion of a sequence, software trigger . . . . .679
Figure 91.Single conversions of a sequence, hardware trigger . . . . .679
Figure 92.Continuous conversions of a sequence, hardware trigger . . . . .680
Figure 93.Data alignment and resolution (oversampling disabled: OVSE = 0) . . . . .681
Figure 94.Example of overrun (OVR) . . . . .682
Figure 95.Wait conversion mode (continuous mode, software trigger) . . . . .684
Figure 96.Auto-off mode state diagram . . . . .686
Figure 97.ADC behavior with WAIT = 0 and AUTOFF = 1 . . . . .686
Figure 98.ADC behavior with WAIT = 1 and AUTOFF = 1 . . . . .687
Figure 99.Autonomous mode state diagram . . . . .688
Figure 100.Analog watchdog guarded area . . . . .689
Figure 101.ADC_AWDx_OUT signal generation . . . . .690
Figure 102.ADC_AWDx_OUT signal generation (AWDx flag not cleared by software) . . . . .691
Figure 103.ADC_AWDx_OUT signal generation (on a single channel) . . . . .691
Figure 104.Analog watchdog threshold update . . . . .692
Figure 105.20-bit to 16-bit result truncation . . . . .692
Figure 106.Numerical example with 5-bits shift and rounding . . . . .693
Figure 107.Triggered oversampling mode (TOVS bit = 1) . . . . .695
Figure 108.Temperature sensor and VREFINT channel block diagram . . . . .696
Figure 109.RNG block diagram . . . . .723
Figure 110.NIST SP800-90B entropy source model . . . . .724
Figure 111.RNG initialization overview . . . . .727
Figure 112.AES block diagram . . . . .743
Figure 113.Encryption/ decryption typical usage . . . . .745
Figure 114.Typical operation with authentication . . . . .747
Figure 115.Example of suspend mode management . . . . .748
Figure 116.ECB encryption . . . . .749
Figure 117.ECB decryption . . . . .749
Figure 118.CBC encryption . . . . .750
Figure 119.CBC decryption . . . . .750
Figure 120.Message construction in CTR mode . . . . .752
Figure 121.CTR encryption . . . . .753
Figure 122.Message construction in GCM . . . . .754
Figure 123.GCM authenticated encryption . . . . .756
Figure 124.Message construction in GMAC mode . . . . .759
Figure 125.GMAC authentication mode . . . . .760
Figure 126.Message construction in CCM mode . . . . .761
Figure 127.CCM mode authenticated encryption . . . . .762
Figure 128.128-bit block construction according to the data type . . . . .767
Figure 129.HASH block diagram . . . . .786
Figure 130.Message data swapping feature . . . . .788
Figure 131.HASH suspend/resume mechanism . . . . .793
Figure 132.OTFDEC block diagram . . . . .807
Figure 133.Typical OTFDEC use in a SoC . . . . .808
Figure 134.AES CTR decryption flow . . . . .809
Figure 135.OTFDEC flow control overview (dual burst read request) . . . . .810
Figure 136.PKA block diagram . . . . .830
Figure 137.General-purpose timer block diagram . . . . .864
Figure 138.Counter timing diagram with prescaler division change from 1 to 2 . . . . .869
Figure 139.Counter timing diagram with prescaler division change from 1 to 4 . . . . .869
Figure 140.Counter timing diagram, internal clock divided by 1 . . . . .870
Figure 141.Counter timing diagram, internal clock divided by 2 . . . . .871
Figure 142.Counter timing diagram, internal clock divided by 4 . . . . .871
Figure 143.Counter timing diagram, internal clock divided by N . . . . .872
Figure 144.Counter timing diagram, Update event when ARPE = 0 (TIMx_ARR not preloaded) . . . . .872
Figure 145.Counter timing diagram, Update event when ARPE = 1 (TIMx_ARR preloaded) . . . . .873
Figure 146.Counter timing diagram, internal clock divided by 1 . . . . .874
Figure 147.Counter timing diagram, internal clock divided by 2 . . . . .875
Figure 148.Counter timing diagram, internal clock divided by 4 . . . . .875
Figure 149.Counter timing diagram, internal clock divided by N . . . . .876
Figure 150. Counter timing diagram, Update event . . . . .876
Figure 151. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .878
Figure 152. Counter timing diagram, internal clock divided by 2 . . . . .878
Figure 153. Counter timing diagram, internal clock divided by 4, TIMx_ARR = 0x36 . . . . .879
Figure 154. Counter timing diagram, internal clock divided by N . . . . .879
Figure 155. Counter timing diagram, Update event with ARPE = 1 (counter underflow) . . . . .880
Figure 156. Counter timing diagram, Update event with ARPE = 1 (counter overflow) . . . . .881
Figure 157. Control circuit in normal mode, internal clock divided by 1 . . . . .882
Figure 158. tim_ti2 external clock connection example . . . . .882
Figure 159. Control circuit in external clock mode 1 . . . . .883
Figure 160. External trigger input block . . . . .884
Figure 161. Control circuit in external clock mode 2 . . . . .885
Figure 162. Capture/compare channel (example: channel 1 input stage) . . . . .885
Figure 163. Capture/compare channel 1 main circuit . . . . .886
Figure 164. Output stage of capture/compare channel (channel 1, idem ch.2, 3 and 4) . . . . .886
Figure 165. PWM input mode timing . . . . .889
Figure 166. Output compare mode, toggle on tim_oc1 . . . . .891
Figure 167. Edge-aligned PWM waveforms (ARR = 8) . . . . .892
Figure 168. Center-aligned PWM waveforms (ARR = 8) . . . . .893
Figure 169. Dithering principle . . . . .894
Figure 170. Data format and register coding in dithering mode . . . . .895
Figure 171. PWM resolution vs frequency (16-bit mode) . . . . .896
Figure 172. PWM resolution vs frequency (32-bit mode) . . . . .896
Figure 173. PWM dithering pattern . . . . .897
Figure 174. Dithering effect on duty cycle in center-aligned PWM mode . . . . .898
Figure 175. Generation of two phase-shifted PWM signals with 50% duty cycle . . . . .900
Figure 176. Combined PWM mode on channels 1 and 3 . . . . .901
Figure 177. OCREF_CLR input selection multiplexer . . . . .902
Figure 178. Clearing TIMx tim_ocxref . . . . .902
Figure 179. Example of One-pulse mode . . . . .903
Figure 180. Retriggerable one-pulse mode . . . . .905
Figure 181. Pulse generator circuitry . . . . .906
Figure 182. Pulse generation on compare event, for edge-aligned and encoder modes . . . . .906
Figure 183. Extended pulse width in case of concurrent triggers . . . . .907
Figure 184. Example of counter operation in encoder interface mode . . . . .909
Figure 185. Example of encoder interface mode with tim_ti1fp1 polarity inverted . . . . .909
Figure 186. Quadrature encoder counting modes . . . . .910
Figure 187. Direction plus clock encoder mode . . . . .911
Figure 188. Directional clock encoder mode (CC1P = CC2P = 0) . . . . .912
Figure 189. Directional clock encoder mode (CC1P = CC2P = 1) . . . . .912
Figure 190. Index gating options . . . . .914
Figure 191. Jittered Index signals . . . . .914
Figure 192. Index generation for IPOS[1:0] = 11 . . . . .915
Figure 193. Counter reading with index gated on channel A (IPOS[1:0] = 11) . . . . .915
Figure 194. Counter reading with index ungated (IPOS[1:0] = 00) . . . . .916
Figure 195. Counter reading with index gated on channel A and B . . . . .916
Figure 196. Encoder mode behavior in case of narrow index pulse (IPOS[1:0] = 11) . . . . .917
Figure 197. Counter reset Narrow index pulse (closer view, ARR = 0x07) . . . . .918
Figure 198. Index behavior in x1 and x2 mode (IPOS[1:0] = 01) . . . . .919
Figure 199. Directional index sensitivity . . . . .919
Figure 200. Counter reset as function of FIDX bit setting . . . . .920
Figure 201. Index blanking . . . . .920
Figure 202. Index behavior in clock + direction mode, IPOS[0] = 1 . . . . .921
Figure 203. Index behavior in directional clock mode, IPOS[0] = 1 . . . . .921
Figure 204. State diagram for quadrature encoded signals . . . . .922
Figure 205. Up-counting encoder error detection . . . . .923
Figure 206. Down-counting encode error detection . . . . .924
Figure 207. Encoder mode change with preload transferred on update (SMSPS = 0) . . . . .925
Figure 208. Control circuit in reset mode . . . . .927
Figure 209. Control circuit in gated mode . . . . .928
Figure 210. Control circuit in trigger mode . . . . .928
Figure 211. Control circuit in external clock mode 2 + trigger mode . . . . .930
Figure 212. Master/Slave timer example . . . . .930
Figure 213. Master/slave connection example with 1 channel only timers . . . . .931
Figure 214. Gating TIM_slv with tim_oc1ref of TIM_mstr . . . . .932
Figure 215. Gating TIM_slv with Enable of TIM_mstr . . . . .933
Figure 216. Triggering TIM_slv with update of TIM_mstr. . . . .934
Figure 217. Triggering TIM_slv with Enable of TIM_mstr . . . . .934
Figure 218. Triggering TIM_mstr and TIM_slv with TIM_mstr tim_ti1 input. . . . .935
Figure 219. TIM16/TIM17 block diagram . . . . .976
Figure 220. Counter timing diagram with prescaler division change from 1 to 2 . . . . .980
Figure 221. Counter timing diagram with prescaler division change from 1 to 4 . . . . .980
Figure 222. Counter timing diagram, internal clock divided by 1 . . . . .982
Figure 223. Counter timing diagram, internal clock divided by 2 . . . . .982
Figure 224. Counter timing diagram, internal clock divided by 4 . . . . .983
Figure 225. Counter timing diagram, internal clock divided by N . . . . .983
Figure 226. Counter timing diagram, update event when ARPE = 0
(TIMx_ARR not preloaded). . . . .		984
Figure 227. Counter timing diagram, update event when ARPE = 1
(TIMx_ARR preloaded). . . . .		985
Figure 228. Update rate examples depending on mode and TIMx_RCR register settings . . . . .986
Figure 229. Control circuit in normal mode, internal clock divided by 1 . . . . .987
Figure 230. tim_ti2 external clock connection example . . . . .987
Figure 231. Control circuit in external clock mode 1 . . . . .988
Figure 232. Capture/compare channel (example: channel 1 input stage) . . . . .989
Figure 233. Capture/compare channel 1 main circuit . . . . .989
Figure 234. Output stage of capture/compare channel (channel 1). . . . .990
Figure 235. Output compare mode, toggle on tim_oc1 . . . . .993
Figure 236. Edge-aligned PWM waveforms (ARR = 8) . . . . .994
Figure 237. Dithering principle . . . . .995
Figure 238. Data format and register coding in dithering mode . . . . .995
Figure 239. PWM resolution vs frequency . . . . .996
Figure 240. PWM dithering pattern . . . . .997
Figure 241. Complementary output with symmetrical dead-time insertion. . . . .999
Figure 242. Asymmetrical deadtime . . . . .999
Figure 243. Dead-time waveforms with delay greater than the negative pulse. . . . .1000
Figure 244. Dead-time waveforms with delay greater than the positive pulse. . . . .1000
Figure 245. Break circuitry overview . . . . .1002
Figure 246. Output behavior in response to a break event on tim_brk . . . . .1004
Figure 247. Output redirection . . . . .1006
Figure 248. tim_ocref_clr input selection multiplexer. . . . .1007
Figure 249. 6-step generation, COM example (OSSR = 1) . . . . .1008
Figure 250. Example of one pulse mode. . . . .1009
Figure 251. LPTIM block diagram (1) . . . . .1042
Figure 252. Glitch filter timing diagram . . . . .1046
Figure 253. LPTIM output waveform, single-counting mode configuration when repetition register content is different than zero (with PRELOAD = 1) . . . . .1047
Figure 254. LPTIM output waveform, single-counting mode configuration and Set-once mode activated (WAVE bit is set) . . . . .1048
Figure 255. LPTIM output waveform, Continuous counting mode configuration . . . . .1048
Figure 256. Waveform generation . . . . .1050
Figure 257. Encoder mode counting sequence . . . . .1054
Figure 258. Continuous counting mode when repetition register LPTIM_RCR different from zero (with PRELOAD = 1). . . . .1055
Figure 259. Capture/compare input stage (channel 1) . . . . .1056
Figure 260. Capture/compare output stage (channel 1) . . . . .1056
Figure 261. Edge-aligned PWM mode (PRELOAD = 1) . . . . .1058
Figure 262. Edge-aligned PWM waveforms (ARR=8 and CCxP = 0) . . . . .1059
Figure 263. PWM mode with immediate update versus preloaded update . . . . .1060
Figure 264. IRTIM internal hardware connections with TIM16 and TIM17 . . . . .1086
Figure 265. Independent watchdog block diagram . . . . .1088
Figure 266. Reset timing due to timeout . . . . .1090
Figure 267. Reset timing due to refresh in the not allowed area . . . . .1091
Figure 268. Changing PR, RL, and performing a refresh (1) . . . . .1092
Figure 269. Independent watchdog interrupt timing diagram . . . . .1094
Figure 270. RTC block diagram . . . . .1103
Figure 271. TAMP block diagram . . . . .1157
Figure 272. Backup registers protection zones . . . . .1162
Figure 273. Tamper sampling with precharge pulse . . . . .1166
Figure 274. Low level detection with precharge and filtering . . . . .1167
Figure 275. Active tamper filtering . . . . .1169
Figure 276. Block diagram . . . . .1202
Figure 277. I 2 C-bus protocol . . . . .1205
Figure 278. Setup and hold timings . . . . .1207
Figure 279. I2C initialization flow . . . . .1209
Figure 280. Data reception . . . . .1210
Figure 281. Data transmission . . . . .1211
Figure 282. Target initialization flow . . . . .1214
Figure 283. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . .1216
Figure 284. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . .1217
Figure 285. Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . .1218
Figure 286. Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . .1219
Figure 287. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . .1220
Figure 288. Transfer bus diagrams for I2C target receiver (mandatory events only) . . . . .1220
Figure 289. Controller clock generation . . . . .1222
Figure 290. Controller initialization flow . . . . .1224
Figure 291. 10-bit address read access with HEAD10R = 0 . . . . .1224
Figure 292. 10-bit address read access with HEAD10R = 1 . . . . .1225
Figure 293. Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes. . . . .1226
Figure 294. Transfer sequence flow for I2C controller transmitter, N > 255 bytes. . . . .1227
Figure 295. Transfer bus diagrams for I2C controller transmitter (mandatory events only) . . . . .1228
Figure 296. Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes . . . . .1230
Figure 297. Transfer sequence flow for I2C controller receiver, N > 255 bytes. . . . .1231
Figure 298. Transfer bus diagrams for I2C controller receiver . . . . .
(mandatory events only) . . . . .1232
Figure 299. Timeout intervals for \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \) . . . . .1236
Figure 300. Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . .1239
Figure 301. Transfer bus diagram for SMBus target transmitter (SBC = 1). . . . .1240
Figure 302. Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . .1241
Figure 303. Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . .1242
Figure 304. Bus transfer diagrams for SMBus controller transmitter . . . . .1243
Figure 305. Bus transfer diagrams for SMBus controller receiver . . . . .1245
Figure 306. USART block diagram . . . . .1271
Figure 307. Word length programming . . . . .1275
Figure 308. Configurable stop bits . . . . .1277
Figure 309. TC/TXE behavior when transmitting . . . . .1279
Figure 310. Start bit detection when oversampling by 16 or 8. . . . .1280
Figure 311. usart_ker_ck clock divider block diagram . . . . .1283
Figure 312. Data sampling when oversampling by 16 . . . . .1284
Figure 313. Data sampling when oversampling by 8 . . . . .1285
Figure 314. Mute mode using Idle line detection . . . . .1292
Figure 315. Mute mode using address mark detection . . . . .1293
Figure 316. Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . .1296
Figure 317. Break detection in LIN mode vs. Framing error detection. . . . .1297
Figure 318. USART example of synchronous master transmission. . . . .1298
Figure 319. USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . .		1298
Figure 320. USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . .		1299
Figure 321. USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . .		1300
Figure 322. ISO 7816-3 asynchronous protocol . . . . .1302
Figure 323. Parity error detection using the 1.5 stop bits . . . . .1304
Figure 324. IrDA SIR ENDEC block diagram. . . . .1308
Figure 325. IrDA data modulation (3/16) - normal mode . . . . .1308
Figure 326. Transmission using DMA . . . . .1310
Figure 327. Reception using DMA . . . . .1311
Figure 328. Hardware flow control between two USARTs. . . . .1311
Figure 329. RS232 RTS flow control . . . . .1312
Figure 330. RS232 CTS flow control . . . . .1313
Figure 331. LPUART block diagram . . . . .1359
Figure 332. LPUART word length programming . . . . .1363
Figure 333. Configurable stop bits . . . . .1365
Figure 334. TC/TXE behavior when transmitting . . . . .1367
Figure 335. lpuart_ker_ck clock divider block diagram . . . . .1371
Figure 336. Mute mode using Idle line detection . . . . .1375
Figure 337. Mute mode using address mark detection . . . . .1376
Figure 338. Transmission using DMA . . . . .1378
Figure 339. Reception using DMA . . . . .1379
Figure 340. Hardware flow control between two LPUARTs. . . . .1380
Figure 341. RS232 RTS flow control . . . . .1380
Figure 342. RS232 CTS flow control . . . . .1381
Figure 343. SPI block diagram . . . . .1415
Figure 344. Full-duplex single master/ single slave application. . . . .1418
Figure 345. Half-duplex single master/ single slave application . . . . .1419
Figure 346. Simplex single master / single slave application . . . . .1419
(master in transmit-only / slave in receive-only mode) . . . . .1420
Figure 347. Master and three independent slaves connected in star topology . . . . .1421
Figure 348. Master and three slaves connected in circular (daisy chain) topology . . . . .1423
Figure 349. Multimaster application . . . . .1424
Figure 350. Scheme of NSS control logic . . . . .1426
Figure 351. Data flow timing control (SSOE = 1, SSOM = 0, SSM = 0) . . . . .1426
Figure 352. NSS interleaving pulses between data (SSOE = 1, SSOM = 1, SSM = 0) . . . . .1427
Figure 353. Data clock timing diagram . . . . .1429
Figure 354. TI mode transfer . . . . .1440
Figure 355. Optional configurations of the slave behavior when an underrun condition is detected . . . . .1442
Figure 356. SAI functional block diagram . . . . .1465
Figure 357. Audio frame . . . . .1468
Figure 358. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .1470
Figure 359. FS role is start of frame (FSDEF = 0) . . . . .1471
Figure 360. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .1472
Figure 361. First bit offset . . . . .1472
Figure 362. Audio block clock generator overview . . . . .1474
Figure 363. PDM typical connection and timing . . . . .1478
Figure 364. Detailed PDM interface block diagram . . . . .1479
Figure 365. Start-up sequence . . . . .1480
Figure 366. SAI_ADR format in TDM mode, 32-bit slot width . . . . .1481
Figure 367. SAI_ADR format in TDM mode, 16-bit slot width . . . . .1482
Figure 368. SAI_ADR format in TDM mode, 8-bit slot width . . . . .1483
Figure 369. AC'97 audio frame . . . . .1486
Figure 370. SPDIF format . . . . .1487
Figure 371. SAI_xDR register ordering . . . . .1488
Figure 372. Data companding hardware in an audio block in the SAI . . . . .1491
Figure 373. Tristate strategy on SD output line on an inactive slot . . . . .1493
Figure 374. Tristate on output data line in a protocol like I2S . . . . .1494
Figure 375. Overrun detection error . . . . .1495
Figure 376. FIFO underrun event . . . . .1495
Figure 377. USB peripheral block diagram . . . . .1529
Figure 378. Packet buffer areas with examples of buffer description table locations . . . . .1536
Figure 379. Block diagram of debug support infrastructure . . . . .1576
Figure 380. JTAG TAP state machine . . . . .1580
Figure 381. AP0: CoreSight topology . . . . .1598
Figure 382. CPU CoreSight topology . . . . .1607
Figure 383. TPIU architecture . . . . .1676
Figure 384. Embedded cross trigger . . . . .1688

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