19. Extended interrupts and event controller (EXTI)

The extended interrupts and event controller (EXTI) manages the individual CPU and system wake-up through configurable event inputs. It provides wake-up requests to the power control, and generates an interrupt request to the CPU NVIC and events to the CPU event input. For the CPU, an additional event generation block (EVG) is needed to generate the CPU event signal.

The EXTI wake-up requests allow the system to be woken up from Stop modes.

The interrupt request and event request generation can be used also in Run modes.

The EXTI also includes the EXTI mux for interconnect IO port selection.

19.1 EXTI main features

• 21 input events supported
• All event inputs allow the possibility to wake up the system.
• Events that do not have an associated wake-up flag in the peripheral, have a flag in the EXTI and generate an interrupt to the CPU from the EXTI.
• Events can be used to generate a CPU wake-up event.

The configurable events have the following features:

• Selectable active trigger edge
• Interrupt pending status register bits independent for the rising and falling edge
• Individual interrupt and event generation mask, used for conditioning the CPU wake-up, interrupt, and event generation
• Software trigger possibility
• Secure events: The access to control and configuration bits of secure input events can be made secure and/or privileged.
• Interconnect exti selection from IO port.

19.2 EXTI block diagram

The EXTI consists of a register block accessed via an AHB interface, the event input trigger block, the masking block, and EXTI mux, as shown in Figure 69 :

• The register block contains all the EXTI registers
• The event input trigger block provides event input edge trigger logic
• The masking block provides the event input distribution to the different wake-up, interrupt and event outputs, and their masking
• The EXTI mux provides the exti interconnect IO port selection

Figure 69. EXTI block diagram

Figure 69. EXTI block diagram. The diagram shows the internal architecture of the EXTI block. On the left, 'GPIO' and 'Peripherals' blocks are connected to the 'EXTI' block. 'GPIO' connects via 'IOPort' to an 'EXTI mux'. 'Peripherals' connect via 'Wake-up' and 'Configurable event(y)' signals to an 'Event trigger'. The 'EXTI' block contains 'Registers', 'EXTI mux', 'Event trigger', and 'Masking' components. The 'Registers' are connected to an 'AHB interface' (with 'hclk' input) and output 'exti_ilac' and 'exti[15:0]' signals. 'exti[15:0]' goes 'To interconnect'. The 'Event trigger' outputs 'events' to the 'Masking' block. The 'Masking' block outputs 'sys_wake-up', 'c_wake-up', 'it_exti_per(y)', 'c_evt_exti', and 'c_evt_rst' signals. 'sys_wake-up' and 'c_wake-up' go to a 'PWR' block. 'it_exti_per(y)', 'c_evt_exti', and 'c_evt_rst' go to an 'EVG' block. The 'EVG' block contains a 'Pulse' component and outputs 'c_event' and 'c_fclk' signals. 'c_event' goes to 'rxev' and 'nvic(x)' blocks, which are part of the 'CPU'. 'c_fclk' goes to the 'CPU'.

Table 139. EXTI pin overview

Pin name	I/O	Description
AHB interface	I/O	EXTI register bus interface. When one event is configured to enable security, the AHB interface supports secure accesses.
hclk	I	AHB bus clock and EXTI system clock
Configurable event(y)	I	Asynchronous wake-up events from peripherals that do not have an associated interrupt and flag in the peripheral
exti_ilac	O	Illegal access event
IOPort(n)	I	GPIOs block IO ports[15:0]
exti[15:0]	O	Interconnect to other peripherals exti signal selection from GPIO port
it_exti_per(y)	O	Interrupts to the CPU associated with configurable event (y)
c_evt_exti	O	High-level sensitive event output for CPU, synchronous to hclk
c_evt_rst	I	Asynchronous reset input to clear c_evt_exti
sys_wakeup	O	Asynchronous system wake-up request to PWR for ck_sys and hclk
c_wakeup	O	Wake-up request to PWR for CPU, synchronous to hclk

Table 140. EVG pin overview

Pin name	I/O	Description
c_fclk	I	CPU free running clock
c_evt_in	I	High-level sensitive events input from EXTI, asynchronous to CPU clock
c_event	O	Event pulse, synchronous to CPU clock
c_evt_rst	O	Event reset signal, synchronous to CPU clock

19.2.1 EXTI connections between peripherals and CPU

Some peripherals able to generate wake-up or interrupt events when the system is in Stop mode are connected to the EXTI.

• Peripheral wake-up signals that generate a pulse or do not have an interrupt status bit in the peripheral are connected to an EXTI configurable event input. For these events, the EXTI provides a status pending bit that must be cleared. It is the EXTI interrupt, associated with the status bit that interrupts the CPU.
• All GPIO ports input to the EXTI multiplexer make possible the selection of a port pin to wake-up the system via a configurable event.

The EXTI configurable event interrupts are connected to the NVIC.

The dedicated EXTI/EVG CPU event is connected to the CPU rxeiv input.

The EXTI CPU wake-up signals are connected to the PWR and are used to wake up the system and the CPU subsystem bus clocks.

19.2.2 EXTI interrupt/event mapping

The EXTI lines are connected as shown in Table 141 .

Table 141. EXTI line connections

EXTI line	Line source	Line type
0-15	GPIO	Configurable
16	PVD output	Configurable
17	COMP1_out	Configurable
18	COMP2_out ⁽¹⁾	Configurable
19	2.4 GHz RADIO_io[6]	Configurable
20	2.4 GHz RADIO_io[7]	Configurable

1. Not available on STM32WBA64xx devices.

19.3 EXTI functional description

The events features are controlled from register bits as follows:

Active trigger edge enable
- by rising edge selection in the EXTI rising trigger selection register (EXTI_RTSR1)
- by falling edge selection in the EXTI falling trigger selection register (EXTI_FTSR1)
Software trigger in the EXTI software interrupt event register (EXTI_SWIER1)
Interrupt pending flag in the
- EXTI rising edge pending register (EXTI_RPR1)
- EXTI falling edge pending register (EXTI_FPR1)
CPU wake-up and interrupt enable in the
- EXTI CPU wake-up with interrupt mask register (EXTI_IMR1)
CPU wake-up and event enable in the
- EXTI CPU wake-up with event mask register (EXTI_EMR1)

19.3.1 EXTI configurable event input wake-up

Figure 70 is a detailed representation of the logic associated with configurable event inputs that wake up the CPU subsystem bus clocks and generate an EXTI pending flag and interrupt to the CPU, and/or a CPU wake-up event.

Figure 70. Configurable event trigger logic CPU wake-up

Figure 70: Configurable event trigger logic CPU wake-up. This block diagram shows the internal logic of the EXTI peripheral. On the left, an 'AHB interface' and 'hclk' are connected to a 'Peripheral interface' block. This block contains several registers: 'Falling trigger selection register', 'Rising trigger selection register', 'Software interrupt event register', 'CPU event mask register', 'CPU interrupt mask register', and 'Pending request register'. A 'Configurable event input(y)' enters from the left and is processed by an 'Asynchronous edge detection circuit' which outputs 'rst'. This 'rst' signal is also fed into a 'Rising edge detect pulse generator' which outputs 'hclk'. The 'Asynchronous edge detection circuit' also outputs a signal to a 'Rising edge detect pulse generator'. The 'Rising edge detect pulse generator' outputs a signal to a 'CPU event(y)' OR gate. This OR gate also receives inputs from 'Other CPU events(x,y)' and 'CPU wake-up(y)'. The output of this OR gate is connected to a 'Rising edge detect' block which outputs 'c_evt_rst' and 'c_evt_exti'. These signals are fed into an 'EVG' (Event Vector Generator) block which outputs 'ck_fqik_c' and 'c_event'. The 'Rising edge detect' block also outputs a signal to a 'CPU wake-up(y)' OR gate. This OR gate also receives inputs from 'Other CPU wake-ups' and 'Other wake-ups wake-up(y)'. The output of this OR gate is connected to a 'sync' block which outputs 'c_wake-up' and 'sys_wake-up'. The 'sync' block also receives inputs from 'hclk' and 'rst'. The 'Pending request register' is connected to the 'Rising edge detect pulse generator' and the 'CPU event(y)' OR gate. The 'CPU event mask register' and 'CPU interrupt mask register' are connected to the 'CPU event(y)' OR gate. The 'Software interrupt event register' is connected to the 'Asynchronous edge detection circuit'.

Only for the input events that support the CPU rxeu generation c_event .

The software interrupt event register allows configurable events to be triggered by software, writing the corresponding register bit, whatever the edge selection setting.

The configurable event active trigger edge (or both edges) is selected and enabled in the rising/falling edge selection registers.

The CPU has its dedicated wake-up (interrupt) mask register and dedicated event mask registers. When the event is enabled, it is generated to the CPU. All events for the CPU are ordered together into a single CPU event signal. The event pending registers (EXTI_RPR and EXTI_FPR) are not set for an unmasked CPU event.

The configurable events have unique interrupt pending request registers. The pending register is only set for an unmasked interrupt. Each configurable event provides a common interrupt to the CPU. The configurable event interrupts must be acknowledged by software in the EXTI_RPR and/or EXTI_FPR registers.

When a CPU wake-up (interrupt) or CPU event is enabled, the asynchronous edge detection circuit is reset by the clocked delay and rising edge detect pulse generator. This guarantees that the EXTI hclk clock is woken up before the asynchronous edge detection circuit is reset.

Note: A detected configurable event interrupt pending request can be cleared by the CPU with the correct access permission. The system is unable to enter into low-power modes as long as an interrupt pending request is active.

19.3.2 EXTI mux selection

The EXTI mux allows the selection of GPIOs as interrupts and wake-up and interconnect exti signal. GPIOs are connected via 16 EXTI mux lines to the first 16 EXTI inputs as configurable event. The selection of GPIO port as EXTI mux output is controlled in the EXTI external interrupt selection register (EXTI_EXTICR1) .

Figure 71. EXTI mux GPIO selection

Diagram of EXTI mux GPIO selection showing three multiplexers for EXTI0, EXTI1, and EXTI15. Each multiplexer selects from a group of GPIO pins (PA, PB, PC, and Px) based on configuration in the EXTI_EXTICR1 register. The outputs are labeled EXTI0, EXTI1, and EXTI15. A dotted line indicates that the pattern repeats for other EXTI lines. The diagram is labeled MS44726V1.

The EXTI mux outputs are available as output signals from the EXTI as exti signal to other peripherals, independent from the masking in EXTI_IMR and EXTI_EMR registers. The interconnect exti signals are not altered by edge trigger selection. The interconnect exti signal has the same polarity as the GPIO port input signal.

The interconnect exti signal is not controlled by EXTI software interrupt (SWI).

19.4 EXTI functional behavior

Table 142. Masking functionality

CPU interrupt enable (in EXTI_IMR.IMFn)	CPU event enable (in EXTI_EMR.EMFn)	Configurable event inputs (in EXTI_RPR.RPIFn and EXTI_FPR.FPIFn)	EXTI(n) interrupt	CPU event	CPU wake-up
0	0	No	Masked	Masked	Masked
0	1	No	Masked	Yes	Yes
1	0	Status latched	Yes	Masked	Yes
1	1	Status latched	Yes	Yes	Yes

For configurable event inputs, when the enabled edges occur on the event input, an event request is generated. When the associated CPU interrupt is unmasked, the corresponding pending bits EXTI_RPR.RPIFn and/or EXTI_FPR.FPIFn is/are set: the CPU subsystem is woken up and the CPU interrupt signal is activated. The EXTI_RPR.RPIFn and/or EXTI_FPR.FPIFn pending bits must be cleared by software writing it to 1. This action clears the CPU interrupt.

For the configurable event inputs, an event request can be generated by software when writing a 1 in the software interrupt/event register EXTI_SWIER, allowing the generation of a rising edge on the event. When the event is unmasked in EXTI_IMR or EXTI_EMR the rising edge event pending bit is set in EXTI_RPR, whatever the setting in EXTI_RTSR.

19.5 EXTI event protection

The EXTI is able to protect event register bits from being modified by nonsecure and unprivileged accesses. The protection is individually activated per input event via the register bits in EXTI_SECCFGR and EXTI_PRIVCFGR. At EXTI level, the protection consists in preventing the following unauthorized write access:

• Change the settings of the secure and/or privileged configurable events.
• Change the masking of the secure and/or privileged input events.
• Clear pending status of the secure and/or privileged input events.

Table 143. Register protection overview

Register name	Access type	Protection ⁽¹⁾⁽²⁾
EXTI_RTSR	RW	Security and privilege can be bit-wise enabled in EXTI_SECCFGR and EXTI_PRIVCFGR.
EXTI_FTSR	RW
EXTI_SWIER	RW
EXTI_RPR	RW
EXTI_FPR	RW
EXTI_SECCFGR	RW	Always secure. Privilege can be bit-wise enabled in EXTI_PRIVCFGR.
EXTI_PRIVCFGR	RW	Always privileged. Security can be bit-wise enabled in EXTI_SECCFGR.

Table 143. Register protection overview (continued)

Register name	Access type	Protection ⁽¹⁾⁽²⁾
EXTI_EXTICRn	RW	Security and privilege can be bit-wise enabled in EXTI_SECCFGR and EXTI_PRIVCFGR.
EXTI_LOCKR	RW	Always secure
EXTI_IM	RW	Security and privilege can be bit-wise enabled in EXTI_SECCFGR and EXTI_PRIVCFGR.
EXTI_EMR	RW
EXTI_HWCFGR	R	Non-secure unprivileged
EXTI_VER	R
EXTI_ID	R
EXTI_SID	R

1. Security is enabled with the individual input event (EXTI_SECCFGR register).

2. Privilege is enabled with the individual Input event (EXTI_PRIVCFGR register).

19.5.1 EXTI security protection

When security is enabled for an input event, the associated input event configuration and control bits can only be modified and read by a secure access. A nonsecure write access is discarded and a read returns 0.

When input events are nonsecure, the security is disabled. The associated input event configuration and control bits can be modified and read by a secure access and nonsecure access.

The security configuration in the registers EXTI_SECCFGR can be globally locked after reset by EXTI_LOCKR.LOCK.

19.5.2 EXTI privilege protection

When privilege is enabled for an input event, the associated input event configuration and control bits can only be modified and read by a privileged access. An unprivileged write access is discarded and a read returns 0.

When input events are unprivileged, the privilege is disabled. The associated input event configuration and control bits can be modified and read by a privileged access and unprivileged access.

The privileged configuration in the registers EXTI_PRIVCFGR can be globally locked after reset by EXTI_LOCKR.LOCK.

19.6 EXTI registers

The EXTI register map is divided in sections, as indicated in Table 144 .

Table 144. EXTI register map sections

Address offset	Description
0x000 - 0x01C	General configurable event [20:0] configuration
0x060 - 0x06C	EXTI IO port mux selection
0x070	EXTI protection lock configuration
0x080 - 0x0BC	CPU input event configuration

All the registers can be accessed with word (32-bit), half-word (16-bit) and byte (8-bit) access.

19.6.1 EXTI rising trigger selection register (EXTI_RTSR1)

Address offset: 0x000

Reset value: 0x0000 0000

Contains only register bits for configurable events.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	RT20	RT19	RT18	RT17	RT16
											rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RT15	RT14	RT13	RT12	RT11	RT10	RT9	RT8	RT7	RT6	RT5	RT4	RT3	RT2	RT1	RT0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:0 RT[20:0] : Rising trigger event configuration bit of configurable event input x ⁽¹⁾(x = 0 to 20)

When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure accesses.

When EXTI_SECCFGR.SECx is enabled, RTx can be accessed only with secure access.

Non-secure write to this bit x is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, RTx can be accessed only with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0.

0: Rising trigger disabled (for event and interrupt) for input line

1: Rising trigger enabled (for event and interrupt) for input line

1. The configurable event inputs are edge triggered, no glitch must be generated on these inputs. If a rising edge on the configurable event input occurs during writing of the register, the associated pending bit is not set. Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

19.6.2 EXTI falling trigger selection register (EXTI_FTSR1)

Address offset: 0x004

Reset value: 0x0000 0000

Contains only register bits for configurable events.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	FT20	FT19	FT18	FT17	FT16
											rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FT15	FT14	FT13	FT12	FT11	FT10	FT9	FT8	FT7	FT6	FT5	FT4	FT3	FT2	FT1	FT0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:0 FT[20:0] : Falling trigger event configuration bit of configurable event input x ⁽¹⁾(x = 0 to 20)

When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure accesses.

When EXTI_SECCFGR.SECx is enabled, FTx can be accessed only with secure access.

Non-secure write to this FTx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, FTx can be accessed only with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0.

0: Falling trigger disabled (for event and Interrupt) for input line

1: Falling trigger enabled (for event and Interrupt) for input line.

1. The configurable event inputs are edge triggered. No glitch must be generated on these inputs. If a falling edge on the configurable event input occurs during writing of the register, the associated pending bit is not set. Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a trigger.

19.6.3 EXTI software interrupt event register (EXTI_SWIER1)

Address offset: 0x008

Reset value: 0x0000 0000

Contains only register bits for configurable events.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	SWI20	SWI19	SWI18	SWI17	SWI16
											rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWI15	SWI14	SWI13	SWI12	SWI11	SWI10	SWI9	SWI8	SWI7	SWI6	SWI5	SWI4	SWI3	SWI2	SWI1	SWI0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:0 SWI[20:0] : Software interrupt on event x (x = 0 to 20)

When EXTI_SECFGR.SECx is disabled, SWIx can be accessed with non-secure and secure accesses.

When EXTI_SECCFGR.SECx is enabled, SWIx can be accessed only with secure access.

Non-secure write to this SWI x is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can be accessed only with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0.

When unmasked in EXTI_IMR or EXTI_EMR, a software interrupt is generated and EXTI_PR is set, independently from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read.

0: Writing 0 has no effect.

1: Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware.

19.6.4 EXTI rising edge pending register (EXTI_RPR1)

Address offset: 0x00C

Reset value: 0x0000 0000

Contains only register bits for configurable events.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	RPIF20	RPIF19	RPIF18	RPIF17	RPIF16
											rc_w1	rc_w1	rc_w1	rc_w1	rc_w1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RPIF15	RPIF14	RPIF13	RPIF12	RPIF11	RPIF10	RPIF9	RPIF8	RPIF7	RPIF6	RPIF5	RPIF4	RPIF3	RPIF2	RPIF1	RPIF0
rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:0 RPIF[20:0] : configurable event inputs x rising edge pending bit (x = 0 to 20)

When EXTI_SECFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure accesses.

When EXTI_SECCFGR.SECx is enabled, RPIFx can be accessed only with secure access.

Non-secure write to this RPIFx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can be accessed only with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0.

0: No rising edge trigger request occurred

1: Rising edge trigger request occurred

This bit is set when the rising edge event or when unmasked in EXTI_IMR or EXTI_EMR and an EXTI_SWIER software trigger arrives on the configurable event line, and cleared by writing 1 to it.

19.6.5 EXTI falling edge pending register (EXTI_FPR1)

Address offset: 0x010

Reset value: 0x0000 0000

Contains only register bits for configurable events.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	FPIF20	FPIF19	FPIF18	FPIF17	FPIF16
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FPIF15	FPIF14	FPIF13	FPIF12	FPIF11	FPIF10	FPIF9	FPIF8	FPIF7	FPIF6	FPIF5	FPIF4	FPIF3	FPIF2	FPIF1	FPIF0
rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1	rc_w1

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:0 FPIF[20:0] : configurable event inputs x falling edge pending bit (x =0 to 20)

When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure accesses.

When EXTI_SECCFGR.SECx is enabled, FPIFx can be accessed only with secure access.

Non-secure write to this FPIFx is discarded, non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access.

When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can be accessed only with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0.

0: No falling edge trigger request occurred

1: Falling edge trigger request occurred

This bit is set when the falling edge event arrives on the configurable event line, and cleared by writing 1 to it.

19.6.6 EXTI security configuration register (EXTI_SECCFGR1)

Address offset: 0x014

Reset value: 0x0000 0000

This register provides write access security, a nonsecure write access is ignored and causes the generation of an illegal access event. A nonsecure read returns the register data.

Contains only register bits for security capable input events.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	SEC20	SEC19	SEC18	SEC17	SEC16
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:0 SEC[20:0] : Security enable on event input x (x = 0 to 20)
When EXTI_PRIVCFG.PRIVx is disabled, SECx can be accessed with privileged and unprivileged accesses.
When EXTI_PRIVCFG.PRIVx is enabled, SECx can only be written with privileged access.
Unprivileged write to this SECx is discarded.
0: Event security disabled (non-secure)
1: Event security enabled (secure)

19.6.7 EXTI privilege configuration register (EXTI_PRIVCFG1)

Address offset: 0x018

Reset value: 0x0000 0000

This register provides privileged write access protection. An unprivileged read returns the register data.

Contains only register bits for security capable input events.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16
											rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:0 PRIV[20:0] : Security enable on event input x (x = 0 to 20)
When EXTI_SECCFG.SECx is disabled, PRIVx can be accessed with secure and non-secure access.
When EXTI_SECCFG.SECx is enabled, PRIVx can only be written with secure access.
Non-secure write to this PRIVx is discarded.
0: Event privilege disabled (unprivileged)
1: Event privilege enabled (privileged)

19.6.8 EXTI external interrupt selection register (EXTI_EXTICR1)

Address offset: 0x060

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EXTI3[7:0]								EXTI2[7:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTI1[7:0]								EXTI0[7:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:24 EXTI3[7:0] : EXTI3 GPIO port selection on interconnect exti3

These bits are written by software to select the source input for EXTI3 external interrupt.

When EXTI_SECCFGR.SEC3 is disabled, EXTI3 can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SEC3 is enabled, EXTI3 can be accessed only with secure access.

Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR.PRIV3 is disabled, EXTI3 can be accessed with privileged and unprivileged accesses.

When EXTI_PRIVCFGR.PRIV3 is enabled, EXTI3 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA3 pin

0x01: PB3 pin

0x02: PC3 pin

0x03: PD3 pin

0x04: PE3 pin

0x06: PG3 pin

0x07: PH3 pin

Others: reserved

Bits 23:16 EXTI2[7:0] : EXTI2 GPIO port selection on interconnect exti2

These bits are written by software to select the source input for EXTI2 external interrupt.

When EXTI_SECCFGR.SEC2 is disabled, EXTI2 can be accessed with non-secure and secure access.

When EXTI_SECCFGR.SEC2 is enabled, EXTI2 can be accessed only with secure access.

Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR.PRIV2 is disabled, EXTI2 can be accessed with privileged and unprivileged accesses.

When EXTI_PRIVCFGR.PRIV2 is enabled, EXTI2 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA2 pin

0x01: PB2 pin

0x02: PC2 pin

0x03: PD2 pin

0x04: PE2 pin

0x06: PG2 pin

Others: reserved

Bits 15:8 EXTI1[7:0] : EXTI1 GPIO port selection on interconnect exti1

These bits are written by software to select the source input for EXTI1 external interrupt.

When EXTI_SECCFGR.SEC1 is disabled, EXTI1 can be accessed with non-secure and secure accesses.

When EXTI_SECCFGR.SEC1 is enabled, EXTI1 can be accessed only with secure access.

Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR.PRIV1 is disabled, EXTI1 can be accessed with privileged and unprivileged accesses.

When EXTI_PRIVCFGR.PRIV1 is enabled, EXTI1 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA1 pin

0x01: PB1 pin

0x02: PC1 pin

0x03: PD1 pin

0x04: PE1 pin

Others: reserved

Bits 7:0 EXTI0[7:0] : EXTI0 GPIO port selection on interconnect exti0

These bits are written by software to select the source input for EXTI0 external interrupt.

When EXTI_SECCFGR.SEC0 is disabled, EXTI0 can be accessed with non-secure and secure accesses.

When EXTI_SECCFGR.SEC0 is enabled, EXTI0 can be accessed only with secure access.

Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR.PRIV0 is disabled, EXTI0 can be accessed with privileged and unprivileged accesses.

When EXTI_PRIVCFGR.PRIV0 is enabled, EXTI0 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA0 pin

0x01: PB0 pin

0x02: PC0 pin

0x03: PD0 pin

0x04: PE0 pin

Others: reserved

19.6.9 EXTI external interrupt selection register (EXTI_EXTICR2)

Address offset: 0x064

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EXTI7[7:0]								EXTI6[7:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTI5[7:0]								EXTI4[7:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:24 EXTI7[7:0] : EXTI7 GPIO port selection on interconnect exti7

These bits are written by software to select the source input for EXTI7 external interrupt.

When EXTI_SECCFGR.SEC7 is disabled, EXTI7 can be accessed with non-secure and secure accesses.

When EXTI_SECCFGR.SEC7 is enabled, EXTI7 can be accessed only with secure access.

Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR.PRIV7 is disabled, EXTI7 can be accessed with privileged and unprivileged accesses.

When EXTI_PRIVCFGR.PRIV7 is enabled, EXTI7 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA7 pin

0x01: PB7 pin

0x02: PC7 pin

0x03: PD7 pin

0x06: PG7 pin

Others: reserved

Bits 23:16 EXTI6[7:0] : EXTI6 GPIO port selection on interconnect exti6

These bits are written by software to select the source input for EXTI6 external interrupt.

When EXTI_SECCFGR.SEC6 is disabled, EXTI6 can be accessed with non-secure and secure accesses.

When EXTI_SECCFGR.SEC6 is enabled, EXTI6 can be accessed only with secure access.

Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR.PRIV6 is disabled, EXTI6 can be accessed with privileged and unprivileged accesses.

When EXTI_PRIVCFGR.PRIV6 is enabled, EXTI6 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA6 pin

0x01: PB6 pin

0x02: PC6 pin

0x03: PD6 pin

0x04: PE6 pin

0x06: PG6 pin

Others: reserved

Bits 15:8 EXTI5[7:0] : EXTI5 GPIO port selection on interconnect exti5

These bits are written by software to select the source input for EXTI5 external interrupt.

When EXTI_SECCFGR.SEC5 is disabled, EXTI5 can be accessed with non-secure and secure accesses.

When EXTI_SECCFGR.SEC5 is enabled, EXTI5 can be accessed only with secure access.

Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR.PRIV5 is disabled, EXTI5 can be accessed with privileged and unprivileged accesses.

When EXTI_PRIVCFGR.PRIV5 is enabled, EXTI5 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA5 pin

0x01: PB5 pin

0x02: PC5 pin

0x03: PD5 pin

0x04: PE5 pin

0x06: PG5 pin

Others: reserved

Bits 7:0 EXTI4[7:0] : EXTI4 GPIO port selection on interconnect exti4

These bits are written by software to select the source input for EXTI4 external interrupt.

When EXTI_SECCFGR.SEC4 is disabled, EXTI4 can be accessed with non-secure and secure accesses.

When EXTI_SECCFGR.SEC4 is enabled, EXTI4 can be accessed only with secure access.

Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR.PRIV4 is disabled, EXTI4 can be accessed with privileged and unprivileged accesses.

When EXTI_PRIVCFGR.PRIV4 is enabled, EXTI4 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA4 pin

0x01: PB4 pin

0x02: PC4 pin

0x03: PD4 pin

0x04: PE4 pin

0x06: PG4 pin

Others: reserved

19.6.10 EXTI external interrupt selection register (EXTI_EXTICR3)

Address offset: 0x068

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EXTI11[7:0]								EXTI10[7:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTI9[7:0]								EXTI8[7:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:24 EXTI11[7:0] : EXTI11 GPIO port selection on interconnect exti11

These bits are written by software to select the source input for EXTI11 external interrupt. When EXTI_SECCFGR.SEC11 is disabled, EXTI11 can be accessed with non-secure and secure accesses.

When EXTI_SECCFGR.SEC11 is enabled, EXTI11 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR.PRIV11 is disabled, EXTI11 can be accessed with privileged and unprivileged accesses.

When EXTI_PRIVCFGR.PRIV11 is enabled, EXTI11 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA11 pin

0x01: PB11 pin

0x02: PC11 pin

0x03: PD11 pin

0x06: PG11 pin

Others: reserved

Bits 23:16 EXTI10[7:0] : EXTI10 GPIO port selection on interconnect exti10

These bits are written by software to select the source input for EXTI10 external interrupt.

When EXTI_SECCFGR.SEC10 is disabled, EXTI10 can be accessed with non-secure and secure accesses.

When EXTI_SECCFGR.SEC10 is enabled, EXTI10 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR.PRIV10 is disabled, EXTI10 can be accessed with privileged and unprivileged accesses.

When EXTI_PRIVCFGR.PRIV10 is enabled, EXTI10 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA10 pin

0x01: PB10 pin

0x02: PC10 pin

0x03: PD10 pin

0x06: PG10 pin

Others: reserved

Bits 15:8 EXTI9[7:0] : EXTI9 GPIO port selection on interconnect exti9

These bits are written by software to select the source input for EXTI9 external interrupt.
When EXTI_SECCFGR.SEC9 is disabled, EXTI9 can be accessed with non-secure and secure accesses.
When EXTI_SECCFGR.SEC9 is enabled, EXTI9 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.
When EXTI_PRIVCFGR.PRIV9 is disabled, EXTI9 can be accessed with privileged and unprivileged accesses.
When EXTI_PRIVCFGR.PRIV9 is enabled, EXTI9 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA9 pin
0x01: PB9 pin
0x02: PC9 pin
0x03: PD9 pin
0x06: PG9 pin
Others: reserved

Bits 7:0 EXTI8[7:0] : EXTI8 GPIO port selection on interconnect exti8

These bits are written by software to select the source input for EXTI8 external interrupt.
When EXTI_SECCFGR.SEC8 is disabled, EXTI8 can be accessed with non-secure and secure accesses.
When EXTI_SECCFGR.SEC8 is enabled, EXTI8 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.
When EXTI_PRIVCFGR.PRIV8 is disabled, EXTI8 can be accessed with privileged and unprivileged accesses.
When EXTI_PRIVCFGR.PRIV8 is enabled, EXTI8 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA8 pin
0x01: PB8 pin
0x02: PC8 pin
0x03: PD8 pin
0x06: PG8 pin
Others: reserved

19.6.11 EXTI external interrupt selection register (EXTI_EXTICR4)

Address offset: 0x06C

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EXTI15[7:0]								EXTI14[7:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTI13[7:0]								EXTI12[7:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:24 EXTI15[7:0] : EXTI15 GPIO port selection on interconnect exti15

These bits are written by software to select the source input for EXTI15 external interrupt. When EXTI_SECCFGR.SEC15 is disabled, EXTI15 can be accessed with non-secure and secure accesses.

When EXTI_SECCFGR.SEC15 is enabled, EXTI15 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR.PRIV15 is disabled, EXTI15 can be accessed with privileged and unprivileged accesses.

When EXTI_PRIVCFGR.PRIV15 is enabled, EXTI15 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA15 pin

0x01: PB15 pin

0x02: PC15 pin

0x03: PD15 pin

0x06: PG15 pin

Others: reserved

Bits 23:16 EXTI14[7:0] : EXTI14 GPIO port selection on interconnect exti14

These bits are written by software to select the source input for EXTI14 external interrupt.

When EXTI_SECCFGR.SEC14 is disabled, EXTI14 can be accessed with non-secure and secure accesses.

When EXTI_SECCFGR.SEC14 is enabled, EXTI14 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR.PRIV14 is disabled, EXTI14 can be accessed with privileged and unprivileged accesses.

When EXTI_PRIVCFGR.PRIV14 is enabled, EXTI14 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA14 pin

0x01: PB14 pin

0x02: PC14 pin

0x03: PD14 pin

0x06: PG14 pin

Others: reserved

Bits 15:8 EXTI13[7:0] : EXTI13 GPIO port selection on interconnect exti13

These bits are written by software to select the source input for EXTI13 external interrupt.

When EXTI_SECCFGR.SEC13 is disabled, EXTI13 can be accessed with non-secure and secure accesses.

When EXTI_SECCFGR.SEC13 is enabled, EXTI13 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR.PRIV13 is disabled, EXTI13 can be accessed with privileged and unprivileged accesses.

When EXTI_PRIVCFGR.PRIV13 is enabled, EXTI13 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA13 pin

0x01: PB13 pin

0x02: PC13 pin

0x03: PD13 pin

0x06: PG13 pin

Others: reserved

Bits 7:0 EXTI12[7:0] : EXTI0 GPIO port selection on interconnect exti12

These bits are written by software to select the source input for EXTI12 external interrupt.

When EXTI_SECCFGR.SEC12 is disabled, EXTI12 can be accessed with non-secure and secure accesses.

When EXTI_SECCFGR.SEC12 is enabled, EXTI12 can be accessed only with secure access. Non-secure write is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged accesses.

When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0x00: PA12 pin

0x01: PB12 pin

0x02: PC12 pin

0x03: PD12 pin

0x06: PG12 pin

Others: reserved

19.6.12 EXTI lock register (EXTI_LOCKR)

Address offset: 0x070

Reset value: 0x0000 0000

This register provides write access security: a nonsecure write access is ignored and a read access returns 0, and both generates an illegal access event.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	LOCK
															rs

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 LOCK : Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock

This bit is written once after reset.

0: Security and privilege configuration open, can be modified.

1: Security and privilege configuration locked, can no longer be modified.

19.6.13 EXTI CPU wake-up with interrupt mask register (EXTI_IMR1)

Address offset: 0x080

Reset value: 0x0000 0000

Contains register bits for configurable events.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	IM20	IM19	IM18	IM17	IM16
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IM15	IM14	IM13	IM12	IM11	IM10	IM9	IM8	IM7	IM6	IM5	IM4	IM3	IM2	IM1	IM0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:0 IM[20:0] : CPU wake-up with interrupt mask on event input x ⁽¹⁾(x = 0 to 20)

When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure accesses.

When EXTI_SECCFGR.SECx is enabled, IMx can be accessed only with secure access.

Non-secure write to this bit is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged accesses.

When EXTI_PRIVCFGR.PRIVx is enabled, IMx can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0: Wake-up with interrupt request from input event x is masked.

1: Wake-up with interrupt request from input event x is unmasked.

1. The reset value for configurable event inputs is set to 0, to disable the interrupt by default.

19.6.14 EXTI CPU wake-up with event mask register (EXTI_EMR1)

Address offset: 0x084

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	EM20	EM19	EM18	EM17	EM16
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EM15	EM14	EM13	EM12	EM11	EM10	EM9	EM8	EM7	EM6	EM5	EM4	EM3	EM2	EM1	EM0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:0 EM[20:0] : CPU wake-up with event generation mask on event input x (x = 0 to 20)

When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure accesses.

When EXTI_SECCFGR.SECx is enabled, EMx can be accessed only with secure access.

Non-secure write to this bit x is discarded and non-secure read returns 0.

When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged accesses.

When EXTI_PRIVCFGR.PRIVx is enabled, EMx can be accessed only with privileged access. Unprivileged write to this bit is discarded.

0: Wake-up with event generation from Line x is masked.

1: Wake-up with event generation from Line x is unmasked.

19.6.15 EXTI register map

Table 145. EXTI register map and reset values

Offset	Register name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x000	EXTI_RTSR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	RT20	RT19	RT18	RT17	RT16	RT15	RT14	RT13	RT12	RT11	RT10	RT9	RT8	RT7	RT6	RT5	RT4	RT3	RT2	RT1	RT0
0x000	Reset value												0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x004	EXTI_FTSR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	FT20	FT19	FT18	FT17	FT16	FT15	FT14	FT13	FT12	FT11	FT10	FT9	FT8	FT7	FT6	FT5	FT4	FT3	FT2	FT1	FT0
0x004	Reset value												0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x008	EXTI_SWIER1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	SWI20	SWI19	SWI18	SWI17	SWI16	SWI15	SWI14	SWI13	SWI12	SWI11	SWI10	SWI9	SWI8	SWI7	SWI6	SWI5	SWI4	SWI3	SWI2	SWI1	SWI0
0x008	Reset value												0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x00C	EXTI_RPR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	RPIF20	RPIF19	RPIF18	RPIF17	RPIF16	RPIF15	RPIF14	RPIF13	RPIF12	RPIF11	RPIF10	RPIF9	RPIF8	RPIF7	RPIF6	RPIF5	RPIF4	RPIF3	RPIF2	RPIF1	RPIF0
0x00C	Reset value												0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x010	EXTI_FPR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	FPIF20	FPIF19	FPIF18	FPIF17	FPIF16	FPIF15	FPIF14	FPIF13	FPIF12	FPIF11	FPIF10	FPIF9	FPIF8	FPIF7	FPIF6	FPIF5	FPIF4	FPIF3	FPIF2	FPIF1	FPIF0
0x010	Reset value												0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x014	EXTI_SECCFG1R	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	SEC20	SEC19	SEC18	SEC17	SEC16	SEC15	SEC14	SEC13	SEC12	SEC11	SEC10	SEC9	SEC8	SEC7	SEC6	SEC5	SEC4	SEC3	SEC2	SEC1	SEC0
0x014	Reset value												0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x018	EXTI_PRIVCFG1R	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	PRIV20	PRIV19	PRIV18	PRIV17	PRIV16	PRIV15	PRIV14	PRIV13	PRIV12	PRIV11	PRIV10	PRIV9	PRIV8	PRIV7	PRIV6	PRIV5	PRIV4	PRIV3	PRIV2	PRIV1	PRIV0
0x018	Reset value												0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x020 to 0x05C	Reserved	Reserved
0x060	EXTI_EXTICR1	EXTI3[7:0]								EXTI2[7:0]								EXTI1[7:0]								EXTI0[7:0]
0x060	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x064	EXTI_EXTICR2	EXTI7[7:0]								EXTI6[7:0]								EXTI5[7:0]								EXTI4[7:0]
0x064	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x068	EXTI_EXTICR3	EXTI11[7:0]								EXTI10[7:0]								EXTI9[7:0]								EXTI8[7:0]
0x068	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x06C	EXTI_EXTICR4	EXTI15[7:0]								EXTI14[7:0]								EXTI13[7:0]								EXTI12[7:0]
0x06C	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x070	EXTI_LOCKR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	LOCK
0x070	Reset value																																0
0x074 to 0x07C	Reserved	Reserved
0x080	EXTI_IMR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	IM20	IM19	IM18	IM17	IM16	IM15	IM14	IM13	IM12	IM11	IM10	IM9	IM8	IM7	IM6	IM5	IM4	IM3	IM2	IM1	IM0
0x080	Reset value												0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Table 145. EXTI register map and reset values (continued)

Offset	Register name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x084	EXTI_EMR1	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	EM20	EM19	EM18	EM17	EM16	EM15	EM14	EM13	EM12	EM11	EM10	EM9	EM8	EM7	EM6	EM5	EM4	EM3	EM2	EM1	EM0
0x084	Reset value												0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x088 to 0x3FC	Reserved	Reserved

Refer to Section 2.3: Memory organization for the register boundary addresses.