14. General-purpose I/Os (GPIO)

14.1 GPIO introduction

Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR), a 16-bit reset register (GPIOx_BRR), and a 32-bit set/reset register (GPIOx_BSRR).

In addition, all GPIOs have a 32-bit locking register (GPIOx_LCKR), two 32-bit alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL), a high-speed low-voltage enable register (GPIOx_HSLVR), and a secure configuration register (GPIOx_SECCFGR).

14.2 GPIO main features

• • Output states: push-pull or open drain + pull-up/down.
• • Output data from output data register (GPIOx_ODR) or peripheral (alternate function output).
• • Speed selection for each I/O.
• • Input states: floating, pull-up/down, analog.
• • Input data to input data register (GPIOx_IDR) or peripheral (alternate function input).
• • Bit set and reset register (GPIOx_BSRR) for bitwise write access to GPIOx_ODR.
• • Lock mechanism (GPIOx_LCKR) provided to freeze the I/O port configurations.
• • Analog function.
• • Alternate function selection registers.
• • Fast toggle capable of changing every two clock cycles.
• • Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several peripheral functions.
• • High-speed at low IO voltage operation.
• • TrustZone® security support.

14.3 GPIO implementation

Table 114. GPIO implementation

1. 1. PD[7:6] can be used only for USB OTG-HS_DM and OTG-HS_DP. When USB OTG_HS is not used, keep it in GPIO analog mode.

14.4 GPIO functional description

Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the GPIO ports can be individually configured by software in several modes:

• • Input floating
• • Input pull-up
• • Input pull-down
• • Analog
• • Analog pull-down
• • Output open-drain with pull-up or pull-down capability
• • Output push-pull with pull-up or pull-down capability
• • Alternate function push-pull with pull-up or pull-down capability
• • Alternate function open-drain with pull-up or pull-down capability

Each I/O port bit is freely programmable. The I/O port registers must be accessed as 32-bit words, half-words, or bytes. The GPIOx_BSRR and GPIOx_BRR registers allow atomic read/modify access to any of the GPIOx_ODR registers. In this way, there is no risk of an IRQ occurring between the read and the modify access.

GPIO configuration is available only in Run and Stop modes, it keeps the I/O port in its defined state. In Standby modes, the GPIO configuration is lost. To keep the I/O port input definition and output levels, a GPIO standby retention can be enabled (see Section 11.7.9: PWR Standby mode ).

Figure 45 shows the basic structure of a 3- or 5 V-tolerant GPIO (TT or FT). Table 115 gives the possible port bit configurations.

Figure 45. Structure of 3 V- or 5 V-tolerant GPIO (TT or FT)

1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate function.

14.4.1 GPIO general-purpose I/O

During and just after reset, the alternate functions are not active and most of the I/O ports are configured in analog mode.

The debug pins are in AF pull-up/pull-down after reset:

• • PA15: JTDI in pull-up
• • PA14: JTCK/SWCLK in pull-down
• • PA13: JTMS/SWDIO in pull-up
• • PB4: NJTRST in pull-up
• • PB3: JTDO/TRACEWO in floating state no pull-up/pull-down

PH3/BOOT0 is in input mode during the reset until at least the end of the option byte loading phase (see Section 14.4.19 ).

When the pin is configured as output, the value written to the output data register (GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull mode or open-drain mode (only the low level is driven, the high level is high-Z).

The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB clock cycle.

All GPIO pins have weak internal pull-up and pull-down resistors that can be activated or not depending on the value in the GPIOx_PUPDR register.

14.4.2 GPIO pin alternate function multiplexer and mapping

The device I/O pins are connected to on-board peripherals/modules through a multiplexer that allows only one peripheral alternate function (AF) connected to an I/O pin at a time. In this way, there is no conflict between peripherals available on the same I/O pin.

Each I/O pin has a multiplexer with up to 16 alternate function inputs (AF0 to AF15) that can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15) registers:

• • After reset, the multiplexer selection is alternate function 0 (AF0). The I/Os are configured in alternate function mode through the GPIOx_MODER register.
• • The specific alternate function assignments for each pin are detailed in the device datasheet.

In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped onto different I/O pins to optimize the number of peripherals available in smaller packages.

For secure peripherals the GPIO pin must be secure to use the secure peripheral alternate function.

To use an I/O in a given configuration, the user must proceed as follows:

• • Debug function: after each device reset these pins are assigned as alternate function pins immediately usable by the debugger host.
• • GPIO: configure the desired I/O as output, input, or analog in the GPIOx_MODER register.
• • Peripheral alternate function:
  • – Connect the I/O to the desired alternate function in one of the GPIOx_AFRL or GPIOx_AFRH register.
  • – Select the type, pull-up/down, and output speed via the GPIOx_OTYPER, GPIOx_PUPDR and GPIOx_OSPEEDER registers respectively.
  • – Configure the desired I/O as an alternate function in the GPIOx_MODER register.
• • Additional functions:
  • – For the ADC, COMP and PVD_IN, configure the desired I/O in analog mode in the GPIOx_MODER register and configure the required function in the ADC, COMP, and PVD registers.

Refer to the “Alternate function mapping” table in the device datasheet for the detailed mapping of the alternate function I/O pins.

14.4.3 GPIO port additional function multiplexer

For the additional functions like RTC, TAMPx, WKUPx and LSE oscillator, configure the required I/O function in the related RTC, TAMP, PWR, and RCC registers. These functions have priority over the configuration in the standard GPIO registers.

14.4.4 GPIO port control registers

Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The GPIOx_MODER register is used to select the I/O mode (input, output, AF, analog). The GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (push-pull or open-drain) and speed. The GPIOx_PUPDR register is used to select the pull-up/pull-down whatever the I/O direction.

14.4.5 GPIO port data registers

Each GPIO has two 16-bit memory-mapped data registers: input and output data registers.

GPIOx_ODR stores the data to be output, it is read/write accessible. The data input through the I/Os is stored into the input data register (GPIOx_IDR), a read-only register.

When changing MODER to select input or ODR level, up to three HCLK cycles are needed to reflect the GPIO pin level in the IDR register.

14.4.6 GPIO data bitwise handling

The bit set reset register (GPIOx_BSRR) is a 32-bit register that allows the application to set and reset each individual bit in the output data register (GPIOx_ODR). This register has twice the size of GPIOx_ODR.

Two control bits in GPIOx_BSRR, namely BS(i) and BR(i) correspond to each bit in GPIOx_ODR. When written to 1, BS(i) sets the corresponding ODR(i) bit. When written to 1, BR(i) resets the ODR(i) corresponding bit.

Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in GPIOx_ODR. If there is an attempt to set and reset a bit in GPIOx_BSRR, the set action takes priority.

Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a “one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always be accessed directly. The GPIOx_BSRR register provides a way of performing atomic bitwise handling.

There is no need for the software to disable interrupts when programming the GPIOx_ODR at bit level: one or more bits can be modified in a single atomic AHB write access.

Individual bits in GPIOx_ODR can also be reset in a single atomic AHB write to GPIOx_BRR.

14.4.7 GPIO locking mechanism

The GPIO control registers can be frozen by applying a specific write sequence to the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL, GPIOx_AFRH and GPIOx_HSLVR.

To write the GPIOx_LCKR register, a specific write/read sequence must be applied. When the right LOCK sequence is applied to bit 16, the value of LCKR[15:0] is used to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must be the same). When the LOCK sequence is applied to a port bit, the value of the port bit can no longer be modified until the next MCU reset or peripheral reset. Each GPIOx_LCKR bit freezes the corresponding bit in the control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH).

The LOCK sequence can only be performed using a word (32-bit long) access to the GPIOx_LCKR register because GPIOx_LCKR bit 16 must be set at the same time as the [15:0] bits.

14.4.8 GPIO alternate function input/output

Two registers are provided to select one of the alternate function inputs/outputs available for each I/O. With these registers, the user can connect an alternate function to some other pin as required by the application.

This means that a number of possible peripheral functions are multiplexed on each GPIO using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can thus select any one of the possible functions for each I/O. The AF selection signal being common to the alternate function input and alternate function output, a single channel is selected for the alternate function input/output of a given I/O.

To know which functions are multiplexed on each GPIO pin, refer to the device datasheet.

14.4.9 GPIO external interrupt/wake-up lines

All ports have external interrupt capability. To use external interrupt lines, the port can be configured in input, output, or alternate function mode (the port must not be configured in analog mode). Refer to Section 19: Extended interrupts and event controller (EXTI) .

14.4.10 GPIO input configuration

When the I/O port is programmed as input:

• • The output buffer is disabled
• • The Schmitt trigger input is activated
• • The pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register
• • The data present on the I/O pin are sampled into the input data register every AHB clock cycle
• • A read access to the input data register provides the I/O state

Figure 46 shows the input configuration of the I/O port bit.

Figure 46. Input floating / pull-up / pull-down configurations

14.4.11 GPIO output configuration

When the I/O port is programmed as output:

• • The output buffer is enabled:
  • – Open-drain mode: a 0 in the output register activates the N-MOS whereas a 1 in the output register leaves the port in high-Z (the P-MOS is never activated)
  • – Push-pull mode: a 0 in the output register activates the N-MOS whereas a 1 in the output register activates the P-MOS
• • The Schmitt trigger input is activated
• • The pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register
• • The data present on the I/O pin are sampled into the input data register every AHB clock cycle
• • A read access to the input data register gets the I/O state
• • A read access to the output data register gets the last written value

Figure 47 shows the output configuration of the I/O port bit.

14.4.12 GPIO alternate function configuration

When the I/O port is programmed as an alternate function:

• • The output buffer can be configured in open-drain or push-pull mode
• • The output buffer is driven by the signals coming from the peripheral (transmitter enable and data)
• • The Schmitt trigger input is activated
• • The weak pull-up and pull-down resistors are activated or not depending on the value in the GPIOx_PUPDR register
• • The data present on the I/O pin are sampled into the input data register every AHB clock cycle
• • A read access to the input data register gets the I/O state

Figure 48 shows the alternate function configuration of the I/O port bit.

Figure 48. Alternate function configuration

14.4.13 GPIO analog configuration

When the I/O port is programmed in analog configuration:

• • The output buffer is disabled
• • The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).
• • The weak pull-down resistor is activated depending on the value in the GPIOx_PUPDR register. The weak pull-up resistor is disabled by hardware.
• • Read access to the input data register gets the value 0.

Figure 49 shows the high-Z, analog-input configuration of the I/O port bits.

Figure 49. High-impedance analog configuration

14.4.14 High-speed low-voltage mode (HSLV)

Some I/Os have the capability to increase their maximum speed at low voltage by configuring them in HSLV mode. The I/O HSLV bit controls whether the I/O output speed is

optimized to operate up to maximum I/O supply level, refer to datasheet (default setting HSLV = 0) or below, refer to datasheet (HSLV = 1).

Caution: The I/O HSLV configuration bit must not be set if the I/O supply ( \( V_{DD} \) or \( V_{DDIO2} \) ) is above 2.7 V. Setting it while the voltage is higher than the absolute maximum ratings can damage the device. The I/O HSLV bit can be set only when the corresponding user option bit is activated (IO_VDD_HSLV or IO_VDDIO2_HSLV depending on the I/O supply, refer to Section 7.4: FLASH option bytes ). There is no hardware protection associated with this feature, so it is recommended to use it only as a static configuration for fixed I/O supply.

14.4.15 GPIO compensation cell

The I/O commutation slew rate ( \( t_{fall}/t_{rise} \) ) can be adapted by software depending on process, voltage and temperature conditions, to reduce the I/O noise on the power supply. Refer to Section 15: System configuration controller (SYSCFG) for more details.

14.4.16 GPIO standby retention

The I/O state can be retained in Standby mode. This is configured in PWR.

14.4.17 GPIO using the LSE oscillator pins as GPIOs

When the LSE oscillator is switched off (default state after reset), the related oscillator pins can be used as normal GPIOs.

When the LSE oscillator is switched on (by setting the LSEON bit in the RCC_BDCR1 register), the oscillator takes control of its associated pins and the GPIO configuration of these pins has no effect.

When the oscillator is configured in a user external clock mode, only the pin is reserved for clock input, and the OSC32_OUT pin can still be used as a normal GPIO.

14.4.18 GPIO using GPIO pins with RTC

The PC13/PC14/PC15 GPIO functionality is lost when the Core domain is powered off (when the device enters Standby modes). In this case, if their GPIO configuration is not bypassed by the RTC configuration, these pins are set in an analog input mode.

For details about I/O control by the RTC, refer to Section 37.3: RTC functional description .

14.4.19 GPIO using PH3 as GPIO

PH3 may be used as a boot pin (BOOT0) or as a GPIO. Depending on the nSWBOOT0 user option bit in the FLASH_OPTR, PH3 switches from the input mode to the analog input mode:

• • After the option byte loading phase if nSWBOOT0 = 1.
• • After reset if nSWBOOT0 = 0.

14.4.20 GPIO using PD6 and PD7

PD6 and PD7 provide USB OTG_HS functions, but they cannot be used for any other function, including GPIO. When USB OTG_HS is not used, PD6 and PD7 must be kept in analog mode.

14.4.21 GPIO TrustZone® security

The TrustZone® security is activated by the TZEN user option bit in the FLASH_OPTR. When the TrustZone® is active (TZEN = 1), each I/O pin of the GPIO port can be individually configured as secure through the GPIOx_SECCFGR register.

When the selected I/O pin is configured as secure, its corresponding configuration bits for alternate function, mode selection, I/O data are secure against a nonsecure access. In case of nonsecure access, these bits are RAZ/WI.

The I/Os with peripheral functions are also conditioned by the peripheral security configuration (see Section 5: Global TrustZone controller (GTZC) for more details):

• • Peripherals for which the I/O pin selection is done through alternate functions registers: if the peripheral is configured as secure, it cannot be connected to a nonsecure I/O pin. If this is not respected, the input data to the secure peripheral is forced to 0 (the I/O input pin value is ignored) and the output pin value is forced to 0, thus avoiding any secure information leaks through nonsecure I/Os.
• • I/Os with analog switches, directly controlled by peripherals (such as ADC): if the I/O is secure, the I/O analog switch cannot be controlled by a nonsecure peripheral. If this is not respected, the switch remains open. This prevents the redirection of secure data to a nonsecure peripheral or I/O through the analog path. Refer to Section 3: System security for more details.
• • Some of the paths between I/Os “additional functions” and peripherals are not blocked if the I/O is secure and the peripheral is nonsecure. Therefore, it is recommended that those peripherals be configured as secure even when not used by the application. Refer to Section 3: System security for the list of concerned peripherals. When the path has a security control, it follows the same rule as I/O selection through alternate functions.

Refer to the device pins definition table in the datasheet for more information about peripheral alternate functions and additional functions mapping.

After reset, all GPIO ports are secure.

Table 116 gives a summary of the I/O port secured bits following the security configuration bit in the GPIO_SECCFGR register. When the I/O bit port is configured as secure:

• • Secured bits: read and write operations are allowed only by a secure access. Nonsecure read or write accesses on secured bits are RAZ/WI. There is no illegal access event generated.
• • Nonsecure bits: no restriction. Read and write operations are allowed by both secure and nonsecure accesses.

When the TrustZone® security is disabled (TZEN = 0), all register bits are nonsecure. The GPIOx_SECCFGR register is RAZ/WI.

Table 116. GPIO secured bits

1. x = port index, y = port pin index, for values see Table 114: GPIO implementation .

As soon as at least one function is configured as secure, the GPIO reset and clock control bits in the RCC are also secured.

14.4.22 GPIO privileged and unprivileged modes

All GPIO registers can be read and written by privileged and unprivileged accesses, whatever the security state (secure or nonsecure).

14.5 GPIO port A to B registers

14.5.1 GPIO port x mode register (GPIOx_MODER) (x = A to B)

Address offset: 0x000

Reset value: 0xABFF FFFF (for port A)

Reset value: 0xFFFF FEBF (for port B)

Bits 31:30 MODE15[1:0] : Port configuration I/O pin 15

These bits are written by software to configure the I/O mode. Access can be protected by GPIOx SEC15.

00: Input mode

01: General purpose output mode

10: Alternate function mode

11: Analog mode (reset state)

Bits 29:28 MODE14[1:0] : Port configuration I/O pin 14

Bits 27:26 MODE13[1:0] : Port configuration I/O pin 13

Bits 25:24 MODE12[1:0] : Port configuration I/O pin 12

Bits 23:22 MODE11[1:0] : Port configuration I/O pin 11

Bits 21:20 MODE10[1:0] : Port configuration I/O pin 10

Bits 19:18 MODE9[1:0] : Port configuration I/O pin 9

Bits 17:16 MODE8[1:0] : Port configuration I/O pin 8

Bits 15:14 MODE7[1:0] : Port configuration I/O pin 7

Bits 13:12 MODE6[1:0] : Port configuration I/O pin 6

Bits 11:10 MODE5[1:0] : Port configuration I/O pin 5

Bits 9:8 MODE4[1:0] : Port configuration I/O pin 4

Bits 7:6 MODE3[1:0] : Port configuration I/O pin 3

Bits 5:4 MODE2[1:0] : Port configuration I/O pin 2

Bits 3:2 MODE1[1:0] : Port configuration I/O pin 1

Bits 1:0 MODE0[1:0] : Port configuration I/O pin 0

14.5.2 GPIO port x output type register (GPIOx_OTYPER) (x = A to B)

Address offset: 0x004

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OT[15:0] : Port configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O output type. Access can be protected by GPIOx SECy.

0: Output push-pull (reset state)

1: Output open-drain

14.5.3 GPIO port x output speed register (GPIOx_OSPEEDR) (x = A to B)

Address offset: 0x008

Reset value: 0x0800 0000 (for port A)

Reset value: 0x0000 0080 (for port B)

Bits 31:30 OSPEED15[1:0] : Port configuration I/O pin 15

These bits are written by software to configure the I/O output speed. Access can be protected by GPIOx SEC15.

00: Low speed

01: Medium speed

10: High speed

11: Reserved

Note: Refer to the device datasheet for the frequency specifications, the power supply, and the load conditions for each speed.

Bits 29:28 OSPEED14[1:0] : Port configuration I/O pin 14

Bits 27:26 OSPEED13[1:0] : Port configuration I/O pin 13

Bits 25:24 OSPEED12[1:0] : Port configuration I/O pin 12

Bits 23:22 OSPEED11[1:0] : Port configuration I/O pin 11

Bits 21:20 OSPEED10[1:0] : Port configuration I/O pin 10

Bits 19:18 OSPEED9[1:0] : Port configuration I/O pin 9

Bits 17:16 OSPEED8[1:0] : Port configuration I/O pin 8

Bits 15:14 OSPEED7[1:0] : Port configuration I/O pin 7

Bits 13:12 OSPEED6[1:0] : Port configuration I/O pin 6

Bits 11:10 OSPEED5[1:0] : Port configuration I/O pin 5

Bits 9:8 OSPEED4[1:0] : Port configuration I/O pin 4

Bits 7:6 OSPEED3[1:0] : Port configuration I/O pin 3

Bits 5:4 OSPEED2[1:0] : Port configuration I/O pin 2

Bits 3:2 OSPEED1[1:0] : Port configuration I/O pin 1

Bits 1:0 OSPEED0[1:0] : Port configuration I/O pin 0

14.5.4 GPIO port x pull-up/pull-down register (GPIOx_PUPDR) (x = A to B)

Address offset: 0x00C

Reset value: 0x6400 0000 (for port A)

Reset value: 0x0000 0100 (for port B)

Bits 31:30 PUPD15[1:0] : Port configuration I/O pin 15

These bits are written by software to configure the I/O pull-up or pull-down. Access can be protected by GPIOx SEC15.

00: No pull-up, pull-down

01: Pull-up

10: Pull-down

11: Reserved

Bits 29:28 PUPD14[1:0] : Port configuration I/O pin 14

Bits 27:26 PUPD13[1:0] : Port configuration I/O pin 13

Bits 25:24 PUPD12[1:0] : Port configuration I/O pin 12

Bits 23:22 PUPD11[1:0] : Port configuration I/O pin 11

Bits 21:20 PUPD10[1:0] : Port configuration I/O pin 10

Bits 19:18 PUPD9[1:0] : Port configuration I/O pin 9

Bits 17:16 PUPD8[1:0] : Port configuration I/O pin 8

Bits 15:14 PUPD7[1:0] : Port configuration I/O pin 7

Bits 13:12 PUPD6[1:0] : Port configuration I/O pin 6

Bits 11:10 PUPD5[1:0] : Port configuration I/O pin 5

Bits 9:8 PUPD4[1:0] : Port configuration I/O pin 4

Bits 7:6 PUPD3[1:0] : Port configuration I/O pin 3

Bits 5:4 PUPD2[1:0] : Port configuration I/O pin 2

Bits 3:2 PUPD1[1:0] : Port configuration I/O pin 1

Bits 1:0 PUPD0[1:0] : Port configuration I/O pin 0

14.5.5 GPIO port x input data register (GPIOx_IDR) (x = A to B)

Address offset: 0x010

Reset value: 0x0000 XXXX

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 ID[15:0] : Port input data I/O pin y (y = 15 to 0)

These bits are read-only. They contain the input value of the corresponding I/O port.
Access can be protected by GPIOx SECy.

14.5.6 GPIO port x output data register (GPIOx_ODR) (x = A to B)

Address offset: 0x014

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OD[15:0] : Port output data I/O pin y (y = 15 to 0)

These bits can be read and written by software. Access can be protected by GPIOx SECy.

Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers.

14.5.7 GPIO port x bit set/reset register (GPIOx_BSRR) (x = A to B)

Address offset: 0x018

Reset value: 0x0000 0000

Bits 31:16 BR[15:0] : Port reset I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns 0.

Access can be protected by GPIOx SECy.

0: No action on the corresponding ODy bit

1: Resets the corresponding ODy bit

Note: If both BSy and BRy are set, BSy has priority.

Bits 15:0 BS[15:0] : Port set I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns 0.

Access can be protected by GPIOx SECy.

0: No action on the corresponding ODy bit

1: Sets the corresponding ODy bit

14.5.8 GPIO port x configuration lock register (GPIOx_LCKR) (x = A to B)

Address offset: 0x01C

Reset value: 0x0000 0000

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.

Note: A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.

Each lock bit freezes a specific configuration register (control and alternate function registers).

Bits 31:17 Reserved, must be kept at reset value.

This bit can be read any time. It can be modified only using the lock key write sequence.
Access can be protected by any GPIOx SECy.
0: Port configuration lock key not active
1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset.

- LOCK key write sequence:

WR LCKR[16] = 1 + LCKR[15:0]

WR LCKR[16] = 0 + LCKR[15:0]

WR LCKR[16] = 1 + LCKR[15:0]

- LOCK key read:

RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active)

Note: During the LOCK key write sequence, the value of LCKR[15:0] must not change.

Any error in the lock sequence aborts the LOCK.

After the first LOCK sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset.

These bits are read/write but can be written only when the LCKK bit is 0
Access can be protected by GPIOx SECy.
0: Port configuration not locked
1: Port configuration locked

14.5.9 GPIO port x alternate function low register (GPIOx_AFRL)
(x = A to B)

Address offset: 0x020

Reset value: 0x0000 0000

Bits 31:28 AFSEL7[3:0] : Alternate function selection for port I/O pin 7

These bits are written by software to configure alternate function I/Os. Access can be protected by GPIOx SEC7.

0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15

Bits 27:24 AFSEL6[3:0] : Alternate function selection for port I/O pin 6

Bits 23:20 AFSEL5[3:0] : Alternate function selection for port I/O pin 5

Bits 19:16 AFSEL4[3:0] : Alternate function selection for port I/O pin 4

Bits 15:12 AFSEL3[3:0] : Alternate function selection for port I/O pin 3

Bits 11:8 AFSEL2[3:0] : Alternate function selection for port I/O pin 2

Bits 7:4 AFSEL1[3:0] : Alternate function selection for port I/O pin 1

Bits 3:0 AFSEL0[3:0] : Alternate function selection for port I/O pin 0

14.5.10 GPIO port x alternate function high register (GPIOx_AFRH)
(x = A to B)

Address offset: 0x024

Reset value: 0x0000 0000

Bits 31:28 AFSEL15[3:0] : Alternate function selection for port I/O pin 15

These bits are written by software to configure alternate function I/Os. Access can be protected by GPIOx SEC15.

0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15

Bits 27:24 AFSEL14[3:0] : Alternate function selection for port I/O pin 14

Bits 23:20 AFSEL13[3:0] : Alternate function selection for port I/O pin 13

Bits 19:16 AFSEL12[3:0] : Alternate function selection for port I/O pin 12

Bits 15:12 AFSEL11[3:0] : Alternate function selection for port I/O pin 11

Bits 11:8 AFSEL10[3:0] : Alternate function selection for port I/O pin 10

Bits 7:4 AFSEL9[3:0] : Alternate function selection for port I/O pin 9

Bits 3:0 AFSEL8[3:0] : Alternate function selection for port I/O pin 8

14.5.11 GPIO port x bit reset register (GPIOx_BRR) (x = A to B)

Address offset: 0x028

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 BR[15:0] : Port reset I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns 0.

Access can be protected by GPIOx SECy.

0: No action on the corresponding ODy bit

1: Reset the corresponding ODy bit

14.5.12 GPIO port x secure configuration register (GPIOx_SECCFGR)
(x = A to B)

Address offset: 0x030

Reset value: 0x0000 FFFF

When the system is secure (TZEN = 1), this register provides write access security and can be written only by a secure access. It is used to configure a selected I/O as secure. A nonsecure write access to this register is discarded.

When the system is not secure (TZEN = 0), this register is RAZ/WI.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 SEC[15:0] : I/O pin of port secure bit enable y (y = 15 to 0)

These bits are written by software to enable the security I/O port pin.

0: The I/O pin is nonsecure

1: The I/O pin is secure. Refer to Table 116 for all corresponding secured bits.

14.5.13 GPIOA to B register map

Table 117. GPIOA to B register map and reset values

Refer to Section 2.3.2: Memory map and register boundary addresses for the register boundary addresses.

14.6 GPIO port C registers

14.6.1 GPIO port C mode register (GPIOC_MODER)

Address offset: 0x000

Reset value: 0xFFFF FFFF

Bits 31:30 MODE15[1:0] : Port configuration I/O pin 15

These bits are written by software to configure the I/O mode. Access can be protected by GPIOC SEC15.

00: Input mode

01: General purpose output mode

10: Alternate function mode

11: Analog mode (reset state)

Bits 29:28 MODE14[1:0] : Port configuration I/O pin 14

Bits 27:26 MODE13[1:0] : Port configuration I/O pin 13

Bits 25:24 MODE12[1:0] : Port configuration I/O pin 12

Bits 23:22 MODE11[1:0] : Port configuration I/O pin 11

Bits 21:20 MODE10[1:0] : Port configuration I/O pin 10

Bits 19:18 MODE9[1:0] : Port configuration I/O pin 9

Bits 17:16 MODE8[1:0] : Port configuration I/O pin 8

Bits 15:14 MODE7[1:0] : Port configuration I/O pin 7

Bits 13:12 MODE6[1:0] : Port configuration I/O pin 6

Bits 11:10 MODE5[1:0] : Port configuration I/O pin 5

Bits 9:8 MODE4[1:0] : Port configuration I/O pin 4

Bits 7:6 MODE3[1:0] : Port configuration I/O pin 3

Bits 5:4 MODE2[1:0] : Port configuration I/O pin 2

Bits 3:2 MODE1[1:0] : Port configuration I/O pin 1

Bits 1:0 MODE0[1:0] : Port configuration I/O pin 0

14.6.2 GPIO port C output type register (GPIOC_OTYPER)

Address offset: 0x004

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OT[15:0] : Port configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O output type. Access can be protected by GPIOC SECy.

0: Output push-pull (reset state)

1: Output open-drain

14.6.3 GPIO port C output speed register (GPIOC_OSPEEDR)

Address offset: 0x008

Reset value: 0x0000 0000

Bits 31:30 OSPEED15[1:0] : Port configuration I/O pin 15

These bits are written by software to configure the I/O output speed. Access can be protected by GPIOC SEC15.

00: Low speed

01: Medium speed

10: High speed

11: Reserved

Note: Refer to the device datasheet for the frequency specifications, the power supply, and the load conditions for each speed.

Bits 29:28 OSPEED14[1:0] : Port configuration I/O pin 14

Bits 27:26 OSPEED13[1:0] : Port configuration I/O pin 13

Bits 25:24 OSPEED12[1:0] : Port configuration I/O pin 12

Bits 23:22 OSPEED11[1:0] : Port configuration I/O pin 11

Bits 21:20 OSPEED10[1:0] : Port configuration I/O pin 10

Bits 19:18 OSPEED9[1:0] : Port configuration I/O pin 9

Bits 17:16 OSPEED8[1:0] : Port configuration I/O pin 8

Bits 15:14 OSPEED7[1:0] : Port configuration I/O pin 7

Bits 13:12 OSPEED6[1:0] : Port configuration I/O pin 6

Bits 11:10 OSPEED5[1:0] : Port configuration I/O pin 5

Bits 9:8 OSPEED4[1:0] : Port configuration I/O pin 4

Bits 7:6 OSPEED3[1:0] : Port configuration I/O pin 3

Bits 5:4 OSPEED2[1:0] : Port configuration I/O pin 2

Bits 3:2 OSPEED1[1:0] : Port configuration I/O pin 1

Bits 1:0 OSPEED0[1:0] : Port configuration I/O pin 0

14.6.4 GPIO port C pull-up/pull-down register (GPIOC_PUPDR)

Address offset: 0x00C

Reset value: 0x0000 0000

Bits 31:30 PUPD15[1:0] : Port configuration I/O pin 15

These bits are written by software to configure the I/O pull-up or pull-down. Access can be protected by GPIOC SEC15.

00: No pull-up, pull-down

01: Pull-up

10: Pull-down

11: Reserved

Bits 29:28 PUPD14[1:0] : Port configuration I/O pin 14

Bits 27:26 PUPD13[1:0] : Port configuration I/O pin 13

Bits 25:24 PUPD12[1:0] : Port configuration I/O pin 12

Bits 23:22 PUPD11[1:0] : Port configuration I/O pin 11

Bits 21:20 PUPD10[1:0] : Port configuration I/O pin 10

Bits 19:18 PUPD9[1:0] : Port configuration I/O pin 9

Bits 17:16 PUPD8[1:0] : Port configuration I/O pin 8

Bits 15:14 PUPD7[1:0] : Port configuration I/O pin 7

Bits 13:12 PUPD6[1:0] : Port configuration I/O pin 6

Bits 11:10 PUPD5[1:0] : Port configuration I/O pin 5

Bits 9:8 PUPD4[1:0] : Port configuration I/O pin 4

Bits 7:6 PUPD3[1:0] : Port configuration I/O pin 3

Bits 5:4 PUPD2[1:0] : Port configuration I/O pin 2

Bits 3:2 PUPD1[1:0] : Port configuration I/O pin 1

Bits 1:0 PUPD0[1:0] : Port configuration I/O pin 0

14.6.5 GPIO port C input data register (GPIOC_IDR)

Address offset: 0x010

Reset value: 0x0000 XXXX

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 ID[15:0] : Port input data I/O pin y (y = 15 to 0)

These bits are read-only. They contain the input value of the corresponding I/O port.
Access can be protected by GPIOC SECy.

14.6.6 GPIO port C output data register (GPIOC_ODR)

Address offset: 0x014

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OD[15:0] : Port output data I/O pin y (y = 15 to 0)

These bits can be read and written by software. Access can be protected by GPIOC SECy.

Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOC_BSRR or GPIOC_BRR registers.

14.6.7 GPIO port C bit set/reset register (GPIOC_BSRR)

Address offset: 0x018

Reset value: 0x0000 0000

Bits 31:16 BR[15:0] : Port reset I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns 0.

Access can be protected by GPIOC SECy.

0: No action on the corresponding ODy bit

1: Resets the corresponding ODy bit

Note: If both BSy and BRy are set, BSy has priority.

Bits 15:0 BS[15:0] : Port set I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns 0.

Access can be protected by GPIOC SECy.

0: No action on the corresponding ODy bit

1: Sets the corresponding ODy bit

14.6.8 GPIO port C configuration lock register (GPIOC_LCKR)

Address offset: 0x01C

Reset value: 0x0000 0000

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.

Note: A specific write sequence is used to write to the GPIOC_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.

Each lock bit freezes a specific configuration register (control and alternate function registers).

Bits 31:17 Reserved, must be kept at reset value.

This bit can be read any time. It can be modified only using the lock key write sequence.

Access can be protected by any GPIOC SECy.

0: Port configuration lock key not active

1: Port configuration lock key active. The GPIOC_LCKR register is locked until the next MCU reset or peripheral reset.

- LOCK key write sequence:

WR LCKR[16] = 1 + LCKR[15:0]

WR LCKR[16] = 0 + LCKR[15:0]

WR LCKR[16] = 1 + LCKR[15:0]

- LOCK key read:

RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active)

Note: During the LOCK key write sequence, the value of LCKR[15:0] must not change.

Any error in the lock sequence aborts the LOCK.

After the first LOCK sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset.

These bits are read/write but can be written only when the LCKK bit is 0

Access can be protected by GPIOC SECy.

0: Port configuration not locked

1: Port configuration locked

14.6.9 GPIO port C alternate function low register (GPIOC_AFRL)

Address offset: 0x020

Reset value: 0x0000 0000

Bits 31:28 AFSEL7[3:0] : Alternate function selection for port I/O pin 7

These bits are written by software to configure alternate function I/Os. Access can be protected by GPIOC SEC7.
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15

Bits 27:24 AFSEL6[3:0] : Alternate function selection for port I/O pin 6

Bits 23:20 AFSEL5[3:0] : Alternate function selection for port I/O pin 5

Bits 19:16 AFSEL4[3:0] : Alternate function selection for port I/O pin 4

Bits 15:12 AFSEL3[3:0] : Alternate function selection for port I/O pin 3

Bits 11:8 AFSEL2[3:0] : Alternate function selection for port I/O pin 2

Bits 7:4 AFSEL1[3:0] : Alternate function selection for port I/O pin 1

Bits 3:0 AFSEL0[3:0] : Alternate function selection for port I/O pin 0

14.6.10 GPIO port C alternate function high register (GPIOC_AFRH)

Address offset: 0x024

Reset value: 0x0000 0000

Bits 31:28 AFSEL15[3:0] : Alternate function selection for port I/O pin 15

These bits are written by software to configure alternate function I/Os. Access can be protected by GPIOC SEC15.

0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15

Bits 27:24 AFSEL14[3:0] : Alternate function selection for port I/O pin 14

Bits 23:20 AFSEL13[3:0] : Alternate function selection for port I/O pin 13

Bits 19:16 AFSEL12[3:0] : Alternate function selection for port I/O pin 12

Bits 15:12 AFSEL11[3:0] : Alternate function selection for port I/O pin 11

Bits 11:8 AFSEL10[3:0] : Alternate function selection for port I/O pin 10

Bits 7:4 AFSEL9[3:0] : Alternate function selection for port I/O pin 9

Bits 3:0 AFSEL8[3:0] : Alternate function selection for port I/O pin 8

14.6.11 GPIO port C bit reset register (GPIOC_BRR)

Address offset: 0x028

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 BR[15:0] : Port reset I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns 0.

Access can be protected by GPIOC SECy.

0: No action on the corresponding ODy bit

1: Reset the corresponding ODy bit

14.6.12 GPIO port C secure configuration register (GPIOC_SECCFGR)

Address offset: 0x030

Reset value: 0x0000 FFFF

When the system is secure (TZEN = 1), this register provides write access security and can be written only by a secure access. It is used to configure a selected I/O as secure. A nonsecure write access to this register is discarded.

When the system is not secure (TZEN = 0), this register is RAZ/WI.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 SEC[15:0] : I/O pin of port secure bit enable y (y = 15 to 0)

These bits are written by software to enable the security I/O port pin.

0: The I/O pin is nonsecure

1: The I/O pin is secure. Refer to Table 116 for all corresponding secured bits.

14.6.13 GPIOC register map

Table 118. GPIOC register map and reset values

Refer to Section 2.3.2: Memory map and register boundary addresses for the register boundary addresses.

14.7 GPIO port D registers

14.7.1 GPIO port D mode register (GPIO_D_MODER)

Address offset: 0x000

Reset value: 0xFFFF FFFF

Bits 31:30 MODE15[1:0] : Port configuration I/O pin 15

These bits are written by software to configure the I/O mode. Access can be protected by GPIO_D SEC15.

00: Input mode

01: General purpose output mode

10: Alternate function mode

11: Analog mode (reset state)

Bits 29:28 MODE14[1:0] : Port configuration I/O pin 14

Bits 27:26 MODE13[1:0] : Port configuration I/O pin 13

Bits 25:24 MODE12[1:0] : Port configuration I/O pin 12

Bits 23:22 MODE11[1:0] : Port configuration I/O pin 11

Bits 21:20 MODE10[1:0] : Port configuration I/O pin 10

Bits 19:18 MODE9[1:0] : Port configuration I/O pin 9

Bits 17:16 MODE8[1:0] : Port configuration I/O pin 8

Bits 15:14 MODE7[1:0] : Port configuration I/O pin 7

Bits 13:12 MODE6[1:0] : Port configuration I/O pin 6

Bits 11:10 MODE5[1:0] : Port configuration I/O pin 5

Bits 9:8 MODE4[1:0] : Port configuration I/O pin 4

Bits 7:6 MODE3[1:0] : Port configuration I/O pin 3

Bits 5:4 MODE2[1:0] : Port configuration I/O pin 2

Bits 3:2 MODE1[1:0] : Port configuration I/O pin 1

Bits 1:0 MODE0[1:0] : Port configuration I/O pin 0

14.7.2 GPIO port D output type register (GPIO_D_OTYPER)

Address offset: 0x004

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OT[15:0] : Port configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O output type. Access can be protected by GPID SECy.

0: Output push-pull (reset state)

1: Output open-drain

14.7.3 GPIO port D output speed register (GPIO_D_OSPEEDR)

Address offset: 0x008

Reset value: 0x0000 0000

Bits 31:30 OSPEED15[1:0] : Port configuration I/O pin 15

These bits are written by software to configure the I/O output speed. Access can be protected by GPIOD SEC15.

00: Low speed

01: Medium speed

10: High speed

11: Reserved

Note: Refer to the device datasheet for the frequency specifications, the power supply, and the load conditions for each speed.

Bits 29:28 OSPEED14[1:0] : Port configuration I/O pin 14

Bits 27:26 OSPEED13[1:0] : Port configuration I/O pin 13

Bits 25:24 OSPEED12[1:0] : Port configuration I/O pin 12

Bits 23:22 OSPEED11[1:0] : Port configuration I/O pin 11

Bits 21:20 OSPEED10[1:0] : Port configuration I/O pin 10

Bits 19:18 OSPEED9[1:0] : Port configuration I/O pin 9

Bits 17:16 OSPEED8[1:0] : Port configuration I/O pin 8

Bits 15:14 OSPEED7[1:0] : Port configuration I/O pin 7

Bits 13:12 OSPEED6[1:0] : Port configuration I/O pin 6

Bits 11:10 OSPEED5[1:0] : Port configuration I/O pin 5

Bits 9:8 OSPEED4[1:0] : Port configuration I/O pin 4

Bits 7:6 OSPEED3[1:0] : Port configuration I/O pin 3

Bits 5:4 OSPEED2[1:0] : Port configuration I/O pin 2

Bits 3:2 OSPEED1[1:0] : Port configuration I/O pin 1

Bits 1:0 OSPEED0[1:0] : Port configuration I/O pin 0

14.7.4 GPIO port D pull-up/pull-down register (GPIO_D_PUPDR)

Address offset: 0x00C

Reset value: 0x0000 0000

Bits 31:30 PUPD15[1:0] : Port configuration I/O pin 15

These bits are written by software to configure the I/O pull-up or pull-down. Access can be protected by GPIO_D SEC15.

00: No pull-up, pull-down

01: Pull-up

10: Pull-down

11: Reserved

Bits 29:28 PUPD14[1:0] : Port configuration I/O pin 14

Bits 27:26 PUPD13[1:0] : Port configuration I/O pin 13

Bits 25:24 PUPD12[1:0] : Port configuration I/O pin 12

Bits 23:22 PUPD11[1:0] : Port configuration I/O pin 11

Bits 21:20 PUPD10[1:0] : Port configuration I/O pin 10

Bits 19:18 PUPD9[1:0] : Port configuration I/O pin 9

Bits 17:16 PUPD8[1:0] : Port configuration I/O pin 8

Bits 15:14 PUPD7[1:0] : Port configuration I/O pin 7

Bits 13:12 PUPD6[1:0] : Port configuration I/O pin 6

Bits 11:10 PUPD5[1:0] : Port configuration I/O pin 5

Bits 9:8 PUPD4[1:0] : Port configuration I/O pin 4

Bits 7:6 PUPD3[1:0] : Port configuration I/O pin 3

Bits 5:4 PUPD2[1:0] : Port configuration I/O pin 2

Bits 3:2 PUPD1[1:0] : Port configuration I/O pin 1

Bits 1:0 PUPD0[1:0] : Port configuration I/O pin 0

14.7.5 GPIO port D input data register (GPIOD_IDR)

Address offset: 0x010

Reset value: 0x0000 XXXX

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 ID[15:0] : Port input data I/O pin y (y = 15 to 0)

These bits are read-only. They contain the input value of the corresponding I/O port.

Access can be protected by GPIOD SECy.

14.7.6 GPIO port D output data register (GPIOD_ODR)

Address offset: 0x014

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OD[15:0] : Port output data I/O pin y (y = 15 to 0)

These bits can be read and written by software. Access can be protected by GPIOD SECy.

Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOD_BSRR or GPIOD_BRR registers.

14.7.7 GPIO port D bit set/reset register (GPIOD_BSRR)

Address offset: 0x018

Reset value: 0x0000 0000

Bits 31:16 BR[15:0] : Port reset I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns 0.

Access can be protected by GPIOD SECy.

0: No action on the corresponding ODy bit

1: Resets the corresponding ODy bit

Note: If both BSy and BRy are set, BSy has priority.

Bits 15:0 BS[15:0] : Port set I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns 0.

Access can be protected by GPIOD SECy.

0: No action on the corresponding ODy bit

1: Sets the corresponding ODy bit

14.7.8 GPIO port D configuration lock register (GPIOD_LCKR)

Address offset: 0x01C

Reset value: 0x0000 0000

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.

Note: A specific write sequence is used to write to the GPIOD_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.

Each lock bit freezes a specific configuration register (control and alternate function registers).

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 LCKK : Lock key

This bit can be read any time. It can be modified only using the lock key write sequence.

Access can be protected by any GPIOD SECy.

0: Port configuration lock key not active

1: Port configuration lock key active. The GPIOD_LCKR register is locked until the next MCU reset or peripheral reset.

- LOCK key write sequence:

WR LCKR[16] = 1 + LCKR[15:0]

WR LCKR[16] = 0 + LCKR[15:0]

WR LCKR[16] = 1 + LCKR[15:0]

- LOCK key read:

RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active)

Note: During the LOCK key write sequence, the value of LCKR[15:0] must not change.

Any error in the lock sequence aborts the LOCK.

After the first LOCK sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset.

Bits 15:0 LCK[15:0] : Port lock I/O pin y (y = 15 to 0)

These bits are read/write but can be written only when the LCKK bit is 0

Access can be protected by GPIOD SECy.

0: Port configuration not locked

1: Port configuration locked

14.7.9 GPIO port D alternate function low register (GPIOD_AFRL)

Address offset: 0x020

Reset value: 0x0000 0000

Bits 31:28 AFSEL7[3:0] : Alternate function selection for port I/O pin 7

These bits are written by software to configure alternate function I/Os. Access can be protected by GPIOD SEC7.

0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15

Bits 27:24 AFSEL6[3:0] : Alternate function selection for port I/O pin 6

Bits 23:20 AFSEL5[3:0] : Alternate function selection for port I/O pin 5

Bits 19:16 AFSEL4[3:0] : Alternate function selection for port I/O pin 4

Bits 15:12 AFSEL3[3:0] : Alternate function selection for port I/O pin 3

Bits 11:8 AFSEL2[3:0] : Alternate function selection for port I/O pin 2

Bits 7:4 AFSEL1[3:0] : Alternate function selection for port I/O pin 1

Bits 3:0 AFSEL0[3:0] : Alternate function selection for port I/O pin 0

14.7.10 GPIO port D alternate function high register (GPIOD_AFRH)

Address offset: 0x024

Reset value: 0x0000 0000

Bits 31:28 AFSEL15[3:0] : Alternate function selection for port I/O pin 15

These bits are written by software to configure alternate function I/Os. Access can be protected by GPIOA SEC15.

0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15

Bits 27:24 AFSEL14[3:0] : Alternate function selection for port I/O pin 14

Bits 23:20 AFSEL13[3:0] : Alternate function selection for port I/O pin 13

Bits 19:16 AFSEL12[3:0] : Alternate function selection for port I/O pin 12

Bits 15:12 AFSEL11[3:0] : Alternate function selection for port I/O pin 11

Bits 11:8 AFSEL10[3:0] : Alternate function selection for port I/O pin 10

Bits 7:4 AFSEL9[3:0] : Alternate function selection for port I/O pin 9

Bits 3:0 AFSEL8[3:0] : Alternate function selection for port I/O pin 8

14.7.11 GPIO port D bit reset register (GPIOA_BRR)

Address offset: 0x028

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 BR[15:0] : Port reset I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns 0.

Access can be protected by GPIOA SECy.

0: No action on the corresponding ODy bit

1: Reset the corresponding ODy bit

14.7.12 GPIO port D high-speed low-voltage register (GPIOD_HSLVR)

Address offset: 0x02C

Reset value: 0x0000 0000

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 HSLV14 : Port D high-speed low-voltage configuration

This bit is written by software to optimize the I/O speed when the I/O supply is low.

The bit is active only if the IO_VDD_HSLV user option bit is set. It must be used only if the I/O supply voltage \( V_{DD} \) is below 2.7 V.

Setting this bit when the I/O supply \( V_{DD} \) is higher than 2.7 V can be destructive.

Access can be protected by GPIOD SECy.

0: I/O speed optimization disabled

1: I/O speed optimization enabled

Note: Not all I/Os support the HSLV mode. Refer to the pin description in the corresponding datasheet for the list of I/Os supporting this feature.

Bits 13:0 Reserved, must be kept at reset value.

14.7.13 GPIO port D secure configuration register (GPIOD_SECCFGR)

Address offset: 0x030

Reset value: 0x0000 FFFF

When the system is secure (TZEN = 1), this register provides write access security and can be written only by a secure access. It is used to configure a selected I/O as secure. A nonsecure write access to this register is discarded.

When the system is not secure (TZEN = 0), this register is RAZ/WI.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 SEC[15:0] : I/O pin of port secure bit enable y (y = 15 to 0)

These bits are written by software to enable the security I/O port pin.

0: The I/O pin is non-secure

1: The I/O pin is secure. Refer to Table 116 for all corresponding secured bits.

14.7.14 GPIOD register map

Table 119. GPIOD register map and reset values

Refer to Section 2.3.2: Memory map and register boundary addresses for the register boundary addresses.

14.8 GPIO port E registers

14.8.1 GPIO port E mode register (GPIOE_MODER)

Address offset: 0x000

Reset value: 0x0000 3FFF

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:12 MODE6[1:0] : Port configuration I/O pin 6

These bits are written by software to configure the I/O mode. Access can be protected by GPIOE SEC6.

00: Input mode

01: General purpose output mode

10: Alternate function mode

11: Analog mode (reset state)

Bits 11:10 MODE5[1:0] : Port configuration I/O pin 5

Bits 9:8 MODE4[1:0] : Port configuration I/O pin 4

Bits 7:6 MODE3[1:0] : Port configuration I/O pin 3

Bits 5:4 MODE2[1:0] : Port configuration I/O pin 2

Bits 3:2 MODE1[1:0] : Port configuration I/O pin 1

Bits 1:0 MODE0[1:0] : Port configuration I/O pin 0

14.8.2 GPIO port E output type register (GPIOE_OTYPER)

Address offset: 0x004

Reset value: 0x0000 0000

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:0 OT[6:0] : Port configuration I/O pin y (y = 6 to 0)

These bits are written by software to configure the I/O output type. Access can be protected by GPIOE SECy.
0: Output push-pull (reset state)
1: Output open-drain

14.8.3 GPIO port E output speed register (GPIOE_OSPEEDR)

Address offset: 0x008

Reset value: 0x0000 0000

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:12 OSPEED6[1:0] : Port configuration I/O pin 6

These bits are written by software to configure the I/O output speed. Access can be protected by GPIOE SEC6.

00: Low speed
01: Medium speed
10: High speed
11: Reserved

Note: Refer to the device datasheet for the frequency specifications, the power supply, and the load conditions for each speed.

Bits 11:10 OSPEED5[1:0] : Port configuration I/O pin 5

Bits 9:8 OSPEED4[1:0] : Port configuration I/O pin 4

Bits 7:6 OSPEED3[1:0] : Port configuration I/O pin 3

Bits 5:4 OSPEED2[1:0] : Port configuration I/O pin 2

Bits 3:2 OSPEED1[1:0] : Port configuration I/O pin 1

Bits 1:0 OSPEED0[1:0] : Port configuration I/O pin 0

14.8.4 GPIO port E pull-up/pull-down register (GPIOE_PUPDR)

Address offset: 0x00C

Reset value: 0x0000 0000

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:12 PUPD6[1:0] : Port configuration I/O pin 6

These bits are written by software to configure the I/O pull-up or pull-down. Access can be protected by GPIOE SEC6.

00: No pull-up, pull-down

01: Pull-up

10: Pull-down

11: Reserved

Bits 11:10 PUPD5[1:0] : Port configuration I/O pin 5

Bits 9:8 PUPD4[1:0] : Port configuration I/O pin 4

Bits 7:6 PUPD3[1:0] : Port configuration I/O pin 3

Bits 5:4 PUPD2[1:0] : Port configuration I/O pin 2

Bits 3:2 PUPD1[1:0] : Port configuration I/O pin 1

Bits 1:0 PUPD0[1:0] : Port configuration I/O pin 0

14.8.5 GPIO port E input data register (GPIOE_IDR)

Address offset: 0x010

Reset value: 0x0000 XXXX