11. Power control (PWR)

11.1 Introduction

The power controller manages the device power supplies and power modes transitions.

11.2 PWR main features

The power controller (PWR) main features are:

• • Power supplies and supply domains
  • – Core domain ( \( V_{CORE} \) )
  • – \( V_{DD} \) domain
  • – Analog domain ( \( V_{DDA} \) )
  • – Supply for the SMPS power stage (available only on STM32WBA63/65xx devices)
  • – Supply for the 2.4 GHz RADIO
  • – \( V_{DDIO2} \) domain on GPIO port PG[15:2] (available only on STM32WBA62/65xx devices)
  • – \( V_{DDUSB} \) domain for USB OTG transceiver (available only on STM32WBA62/64/65xx devices)
• • System supply voltage regulation
  • – SMPS step-down converter
  • – Linear voltage regulator (LDO)
• • Power supply supervision
  • – BOR monitor (including Power-on reset)
  • – PVD monitor
• • Power management
  • – Operating modes
  • – Voltage scaling control
  • – Low-power modes
• • GPIO retention in Standby
• • TrustZone® security and privileged protection

11.3 PWR pins and internal signals

Table 86. PWR input/output pins

1. 1. Available only on STM32WBA62/64/65xx devices.
2. 2. Available only on STM32WBA62/65xx devices.
3. 3. Available only on STM32WBA63/65xx devices.
4. 4. Available only on STM32WBA62/64xx devices.

Table 87. PWR internal input/output signals

Each of the wake-up event WKUPx can be generated from device pins or internal events, selected by WUSELx[1:0] in the PWR_WUCR3 register (x = 1 to 8). A WKUP interrupt is generated only when WKUPx is generated from a device pin. WKUPx generated from internal events are associated with an internal event interrupt.

Table 88. PWR wake-up source selection

1. As enabled in the RTC interrupt and according the RTC interrupt security setting.

2. As enabled in the TAMP mask.

11.4 PWR power supplies and supply domains

Figure 30. Power supply overview

Warning: When SMPS devices are used in a LDO application, without inductor between VLXSMPS and VDD11, the pins VDDSMPS and VLXSMPS must be connected to ground.

11.4.1 External power supplies

The devices require a 1.71 to 3.6 V \( V_{DD} \) operating voltage supply. Several independent supplies can be provided for specific peripherals. Those supplies must be provided with a valid operating supply on the VDD pin:

• • \( V_{DD} = 1.71 \text{ V to } 3.6 \text{ V} \)
  \( V_{DD} \) is the external power supply for the I/Os, the internal regulator, and the system analog such as reset, power management, and internal clocks. It is provided externally through the VDD pins.
• • \( V_{DDIO2} = 1.08 \text{ V to } 3.6 \text{ V} \) (available only on STM32WBA62/65xx devices)
  \( V_{DDIO2} \) is the independent external power supply for GPIO port PG. This voltage level is independent from \( V_{DD} \) , and must preferably be connected to VDD when GPIO port PG is not used.
• • \( V_{DDUSB} = 3.0 \text{ V to } 3.6 \text{ V} \)
  \( V_{DDUSB} \) is the independent external power supply for the USB OTG transceiver. When no independent supply is used, connect it to VDD.
• • \( V_{DDA} = 1.62/1.8 \text{ V (VREFBUF) to } 3.6 \text{ V} \)
  \( V_{DDA} \) is the external analog power supply for ADC and comparators. The \( V_{DDA} \) voltage level is independent from the \( V_{DD} \) voltage and must preferably be connected to VDD when these peripherals are not used.
• • \( V_{REF+} = 1.0 \text{ V to } V_{DDA} \)
  \( V_{REF+} \) is the input reference voltage for ADC, and the output of the internal voltage reference buffer when enabled. \( V_{REF+} \) can be grounded when the ADC is not used. This pin is not available on all packages, in this case it is bonded to \( V_{DDA} \) .
• • \( V_{DDSMPS} = 1.71 \text{ V to } 3.6 \text{ V} \) (available only on STM32WBA63/65xx devices)
  \( V_{DDSMPS} \) is the external power supply for the SMPS step-down converter. It is provided externally through \( V_{DDSMPS} \) supply pin, and must be connected to the same supply as VDD pin.
• • \( V_{LXSMPS} \) is the switched SMPS step-down converter output. (available only on STM32WBA63/65xx devices)

Note: The SMPS power supply pins are available only on specific package with SMPS step-down converter option.

• • \( V_{DD11}/V_{CAP} = 0.9 \text{ V to } 1.2 \text{ V} \)
  \( V_{CORE} \) is the internal power supply for the digital logic.
• • \( V_{DDRFPA} = 0 \text{ V to } 3.6 \text{ V} \) (must be above 1.2 V for 2.4 GHz RADIO operation).
  \( V_{DDRFPA} \) must be equal to or lower than \( V_{DDRF} \) .
  \( V_{DDRFPA} \) is the external power supply for the 2.4 GHz RADIO front-end part and PA.
  • – \( V_{DDRFPA} \) when connected to \( V_{DD11} \) supports a transmit maximum low output power
  • – \( V_{DDRFPA} \) when connected to VDD supports a transmit maximum high output power
• • \( V_{DDANA} = 0 \text{ V to } 3.6 \text{ V} \) (must be above 1.2 V for 2.4 GHz RADIO operation), available only on STM32WBA63/65xx devices).
  \( V_{DDANA} \) must be equal to or lower than \( V_{DDRF} \) .
  \( V_{DDANA} \) is the external power supply for the 2.4 GHz RADIO part, can be connected to \( V_{DD11} \) .

Note: The VDDANA supply pin is available only on specific packages with SMPS step-down converter option. In packages with only LDO support, VDDANA is double bonded with VDDRF.

• • \( V_{DDRF} = 1.71 \text{ V to } 3.6 \text{ V} \)
  \( V_{DDRF} \) is the external power supply for the 2.4 GHz RADIO IF part. VDDRF must always be connected to the supply used for VDD.
• • \( V_{DDHPA} = 0.9 \text{ V to } 2.3 \text{ V} \)
  \( V_{DDHPA} \) is the internal power supply for the 2.4 GHz RADIO power amplifier.

11.4.2 Application power supply schemes

The device supports different supply schemes, as shown in Figure 31 . The maximum achievable transmit output power from the 2.4 GHz RADIO internal PA is linked to the supply scheme.

• • In packages supporting an SMPS, a maximum transmit low output power can be reached with lowest power consumption. In this power scheme \( V_{DDRFPA} \) is connected to V _DD11 , and REGVDDHPA is connected to V11 internal selected by REGPASEL register bit.
• • In all other power schemes \( V_{DDRFPA} \) is connected to V _DD , allowing maximum transmit high output power.

Figure 31. Application power supply schemes

11.4.3 Power-up and power-down power sequences

During power-up and power-down phases, respect the following requirements:

• • When \( V_{DD} \) is below 1 V, other power supplies ( \( V_{DDUSB} \) , \( V_{DDIO2} \) , \( V_{DDA} \) , \( V_{DDRF} \) ) must remain below \( V_{DD} + 300 \) mV.
• • When \( V_{DD} \) is above 1 V, all power supplies are independent.

During the power-down phase, \( V_{DD} \) can temporarily become lower than other supplies only if the energy provided to the MCU remains below 1 mJ; this allows external decoupling capacitors discharge with different time constants during the power-down transient phase.

11.4.4 Independent analog peripherals supply

To improve A/D conversion accuracy and 2.4 GHz RADIO performance, and to extend the supply flexibility, the analog and 2.4 GHz RADIO peripherals have independent power supplies that can be separately filtered and shielded from noise on the PCB:

• • the analog peripherals voltage supply input is available on a separate V _DDA pin
• • the 2.4 GHz RADIO peripheral voltage supply input is available on separate V _DDRF , V _DDANA , and V _DDRFP pins.

The V _DDA supply voltage can be different from V _DD . The V _DDA must be present before enabling any of the analog peripherals supplied by V _DDA (ADC4 and COMP).

When a single supply is used, V _DDA can be externally connected to V _DD through the external filtering circuit to ensure a noise-free V _DDA voltage.

ADC reference voltage

To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to V _REF+ pin a separate reference voltage lower than V _DDA . V _REF+ is the highest voltage, represented by the full-scale value, for an analog input (ADC) signal.

V _REF+ can be provided either by an external reference or by an internal buffered voltage reference (VREFBUF). The internal voltage reference can output various voltage levels. This voltage reference can also be provided to external components through V _REF+ pin. Refer to the device datasheet and to Section 22: Voltage reference buffer (VREFBUF) for further information.

11.4.5 Independent GPIOG[15:2] I/O supply

The GPIOG[15:2] port pins are supplied through an independent V _DDIO2 supply pin.

After reset, the I/Os supplied by V _DDIO2 are logically and electrically isolated and therefore are not available. The isolation must be removed before using any of the GPIOG[15:2] port pins, by setting the IO2SV bit in the PWR_SVMCR register, once the V _DDIO2 supply is present.

The following sequence must be done before using any I/O from PG[15:2]:

1. 1. make sure V _DDIO2 is supply present
2. 2. Set IO2SV in PWR_SVMCR to remove the V _DDIO2 power isolation.

There is no dedicated V _DDIO2 supply monitor. Application software shall ensure that V _DDIO2 is supplied at the right level before removing the logically and electrically isolation. Ensuring that V _DDIO2 is supplied can be done by a software time delay, or measuring V _DDIO2 using an ADC channel.

11.4.6 Independent USB transceiver supply

The USB OTG transceiver is supplied through an independent V _DDUSB supply pin. For its operation the V _DDUSB range is from 3.0 to 3.6 V, independent from V _DD and other supplies.

After reset, the USB OTG transceiver and I/Os supplied by V _DDUSB are logically and electrically isolated and therefore not available. The isolation must be removed before using the USB OTG, by setting the USV bit in the PWR_SVMCR register, once the V _DDUSB supply is present.

There is no dedicated VDDUSB supply monitor. The application must ensure that VDDUSB is supplied at the right level before removing the logical and electrical isolation. Ensuring that VDDUSB is supplied can be done by a software time delay, or by measuring it using an ADC channel.

The following sequence must be done before using the USB OTG:

1. 1. Make sure that VDDUSB supply is present.
2. 2. Set USV in PWR_SVMCR to remove the V _DDUSB power isolation.

Using PD[7:6] and GPIO

When PD[7:6] are used as OTG_HSDM and OTG_HSDP alternate function, the GPIOs must be configured in analog mode (default setting) in the GPIO peripheral.

When the USB OTG is not used PD[7:6] cannot be used, keep it in analog mode (default setting) in the GPIO peripheral.

11.4.7 USB OTG power management

The USB OTG transceiver is functional only in voltage scaling range 1. The USB OTG (embedded power distribution) booster must be enabled and ready before using the USB OTG: VDD11USBDIS bit must be cleared to 0, USBPWREN and USBBOOSTEN bits must be set to 1.

The following sequence must be done before using the USB OTG:

1. 1. make sure that VDDUSB supply is present
2. 2. remove the V _DDUSB power isolation by setting USV to 1
3. 3. make sure that voltage scaling is range 1 in ACTVOS = 1
4. 4. enable VDD11USB supply by clearing VDD11USBDIS to 0
5. 5. enable USB OTG internal power by setting USBPWREN to 1
6. 6. wait for VDD11USB supply to be ready in VDD11USBRDY = 1
7. 7. enable USB OTG booster by setting USBBOOSTEN to 1
8. 8. wait for USB OTG booster to be ready in USBBOOSTRDY = 1

In Stop 0 voltage scaling range 1, it is possible to keep the USB OTG configuration. This allows the USB OTG to wake up the MCU from Stop mode. To reduce power consumption, shut off the USB OTG before entering Stop and Standby modes.

In Run and Stop 0 voltage scaling range 2, Stop 1, Stop 2, and Standby modes, it is not possible to keep the USB OTG configuration. The USB OTG must be shut off before entering these modes.

The following steps are needed to shut off the USB OTG:

1. 1. disable USB OTG booster by clearing USBBOOSTEN to 0
2. 2. disable USB OTG internal power by clearing USBPWREN to 0.
3. 3. disable VDD11USB by setting VDD11USBDIS to 1.
4. 4. wait for VDD11USB supply to be ready in VDD11USBRDY = 1.

11.4.8 Radio peripherals supply

The 2.4 GHz RADIO V _DDRF , V _DDANA , and V _DDRPA supply voltages can be different from V _DD . The supplies must be present before enabling the 2.4 GHz RADIO.

When a single supply is used, VDDRF, VDDANA, and VDDRFP A supplies can be externally connected to VDD through external filtering circuitry to ensure noise-free supply voltage.

In devices with SMPS, VDDANA can be externally connected to VDD11 through external filtering circuitry to ensure noise-free supply voltage.

In devices with SMPS, for low transmit output power applications VDDRFP A can be externally connected to VDD11 through external filtering circuitry to ensure noise-free supply voltage.

11.4.9 Backup domain

The backup domain contains the RTC, TAMP, backup registers, LSE oscillator, and is directly supplied from VDD pin.

Backup domain access

After a system reset, the Backup domain (RCC Backup domain control register RCC_BDCR1, RTC registers, TAMP registers, backup registers) is protected against possible unwanted write accesses. To enable access to the Backup domain, proceed as follows:

1. 1. Enable the power interface clock by setting the PWREN bits in the Section 12.8.22: RCC AHB4 peripheral clock enable register (RCC_AHB4ENR) .
2. 2. Set the DBP bit in the PWR disable Backup domain register (PWR_DBPR) to enable access to the Backup domain.

11.4.10 Internal regulators

The devices embed two regulators: one LDO and one SMPS in parallel to provide the V _CORE (for digital peripherals, SRAM and embedded flash memory). Both regulators generate this voltage on VDD11/VCAP pins. The SMPS is available only on some devices.

Both regulators can provide two different voltage ranges (voltage scaling) and can operate in Run and Stop modes.

It is possible to switch from SMPS to LDO and from LDO to SMPS and change range on the fly (when the 2.4 GHz RADIO and USB OTG are not active).

Other internal supplies for the 2.4 GHz RADIO are generated for the dedicated regulator.

11.5 PWR system supply voltage regulation

11.5.1 SMPS and LDO embedded regulators

All devices embed an internal linear voltage regulator (LDO). Some devices embed also an internal SMPS step-down converter, which can be selected when the application runs, depending upon application requirements.

The SMPS allows the power consumption to be reduced. Some peripherals can be perturbed by the noise generated by the SMPS, requiring the application to switch to LDO when running this peripheral, to reach the best performances.

The LDO and the SMPS regulators have two modes, namely Main regulator mode (used when performance is needed), and Low-power regulator mode. LDO or SMPS can be used in all voltage scaling ranges, and in all Stop modes and Standby with retention mode.

11.5.2 LDO and SMPS versus reset, voltage scaling, and low-power modes

After BOR0 power-on reset and system reset, the LDO regulator is enabled, in range 2. Switching to the SMPS regulator provides lower consumption in particular for high \( V_{DD} \) voltages. It is possible to switch from LDO to SMPS, or from SMPS to LDO in any range, by configuring the REGSEL register bit.

It is recommended to switch to SMPS before changing the voltage range.

When exiting from Stop or Standby retention modes, the regulator is the same used to enter the low-power mode. When exiting from Standby modes, the LDO regulator is always used to startup. When Standby has been entered from the SMPS regulator, after exiting Standby with the LDO, the regulator is switched automatically to SMPS regulator.

When exiting from Stop 0 modes the voltage range is the same as on entering Stop 0 mode. When exiting from Stop 1, Stop 2, and Standby modes the voltage range 2 is used.

When the 2.4 GHz RADIO is active, the regulator and range cannot be changed. Any requested regulator or range change while the 2.4 GHz RADIO is active is suspended and takes effect only after the 2.4 GHz RADIO and PHY have entered Sleep or deep sleep mode.

11.5.3 LDO and SMPS step-down converter fast startup

After BOR0 power-on reset, the LDO regulator starts in high-power mode and in slow-startup mode. The slow-startup feature is selected to limit the inrush current after power-on reset. This increases the wake-up time also when exiting Standby modes.

It is possible to configure fast-startup on the fly and it is applied for next startup either after a system reset or wake-up from Standby mode. The fast-startup is selected by setting the FSTEN bit in the PWR_CR3 register. Fast-startup selection applies to both LDO and SMPS regulators.

11.5.4 Dynamic voltage scaling management

The dynamic voltage scaling is a power management technique that consists in increasing or decreasing the voltage used for the digital peripherals ( \( V_{CORE} \) ), according to the application performance and power consumption needs.

Dynamic voltage scaling to increase \( V_{CORE} \) is known as overvolting. This is used to improve device performance.

Dynamic voltage scaling to decrease \( V_{CORE} \) is known as undervolting. It is performed to save power, particularly in devices where the energy comes from a battery and is thus limited.

The regulator operates in the following ranges:

• • Range 1: high performance

It allows a system clock frequency up to 100 MHz, and is required for any 2.4 GHz RADIO transmit and receive operation.

When the 2.4 GHz RADIO is active the range cannot be changed. Any requested range change while the 2.4 GHz RADIO is active is suspended and only takes effect after the 2.4 GHz RADIO and PHY have entered Sleep or deep sleep mode.

• • Range 2: low-power range

The system clock frequency can be up to 16 MHz. The 2.4 GHz RADIO cannot transmit nor receive.

Voltage scaling is selected through the VOS bit in the PWR_VOSR register.

The sequence to switch the voltage scaling from range 2 to range 1 is the following:

1. 1. Program the VOS to range 1 in the PWR_VOSR
2. 2. Wait until the VOSRDY flag is set in the PWR_VOSR
3. 3. If target SYSCLK > 50 MHz
   1. a) Switch on the PLL1 oscillator source
   2. b) Select the PLL1 clock source in PLL1SRC in the RCC_PLL1CFGGR
4. 4. Adjust number of wait states according to the new target SYSCLK frequency. Flash LATENCY in the FLASH_ACR, and SRAM WSC in the RAMCFG_MxCR.
5. 5. Configure and enable the PLL1 is needed
6. 6. Switch to the new SYSCLK frequency.

The sequence to switch the voltage scaling from range 1 to range 2 is the following:

1. 1. Switch to the SYSCLK frequency \( \leq 16 \) MHz
2. 2. Adjust number of wait states according to the new target SYSCLK frequency. Flash LATENCY in the FLASH_ACR, and SRAM WSC in the RAMCFG_MxCR.
3. 3. Disable the PLL1
4. 4. Program the VOS to range 2 in the PWR_VOSR
5. 5. Optionally wait until the ACTVOS in the PWR_SVMSR = VOS in the PWR_VOSR and ACTVOSRDY flag is set in PWR_SVMSR

Note: When switching the voltage scaling, the sequence must be completed (VOS = ACTVOS and ACTVOSRDY = 1) before entering Stop or Standby modes. When the 2.4 GHz RADIO is active (PWR_RADIOSCR.MODE = active) the system does not enter low-power mode and the CPU can enter deep sleep mode independently from VOS, ACTVOS and ACTVOSRDY.

11.5.5 Deep sleep 2.4 GHz RADIO PA regulator

The PA regulator REG VDDHPA is used to supply the 2.4 GHz RADIO internal PA with the correct voltage level \( V_{DDHPA} \) for a given transmit output power. This regulator output voltage \( V_{DDHPA} \) is controlled from the 2.4 GHz RADIO link layer software. \( V_{DDHPA} \) maximum supply level and associated maximum transmit output power is depended on the application supply scheme. See Section 11.4.2: Application power supply schemes .

The application software can control the REG VDDHPA regulator input voltage.

• • Force the input voltage selection of the REG VDDHPA regulator to be from VDDRFPA pin by setting the REGPASEL register bit.
  • – When the REG VDDHPA regulator input voltage is forced to VDDRFPA, power consumption at low transmit output power is higher.
• • Allow the 1.2 V \( V_{DDHPA} \) voltage level to be generated directly from the VDD11 supply via the REGPABYPEN register bit. This can be selected only when VDD11 is supplied

from the device SMPS. This is available only when the input voltage of the REG VDDHPA regulator is not forced to VDDRFP.

• – When the SMPS is used, allowing the 1.2 V \( V_{DDHPA} \) voltage level to be generated directly from the VDD11 lowers power consumption at the transmit output levels using this supply level.

The required REG VDDHPA regulator supply source configuration in REGPASEL and REGPABYPEN must be set before using the regulator. When the REG VDDHPA regulator is used, REGPASEL and REGPABYPEN must not be changed.

The REG VDDHPA is forced off, discharging the external capacitor, in Stop 2 and all Standby modes.

For more information on the 2.4 GHz RADIO transmit output power and REG VDDHPA regulator control see Section 9.4.3: Transmit output power .

11.6 PWR power supply supervision

11.6.1 Brownout reset (BOR)

The device has an integrated BOR (brownout reset) circuitry. The BOR is active in all power modes, and cannot be disabled. The BOR reset also generates a system reset on pin NRST.

Five BOR thresholds can be selected through option bytes. A power-on reset is always generated at the \( V_{BOR0} \) thresholds.

The Backup domain is supplied by \( V_{DD} \) and is reset by the \( V_{BOR0} \) thresholds.

The other \( V_{BORx} \) ( \( x = 1 \) to 4) thresholds keep most of the device under system reset until the supply voltage \( V_{DD} \) reaches the specified threshold. When \( V_{DD} \) drops below the selected threshold, a system reset on pin NRST is generated. When \( V_{DD} \) is above the \( V_{BORx} \) upper limit, the system reset on pin NRST is released and the system can start.

For more details on the brownout reset thresholds, refer to the electrical characteristics section in the datasheet.

During Stop 1 Stop 2, and Standby modes, it is possible to set the BOR0 in Ultra-low power (discontinuous) mode to further reduce the current consumption by setting the ULPMEN bit in PWR control register 1 (PWR_CR1) .

Warning: In Ultra-low power mode, the supply monitoring is discontinuous and may not detect fast drops in supply, hence it must not be used together with autonomous peripherals using HSI16 as kernel clock.

Figure 32. Brownout reset waveform

1. 1. The reset temporization \( t_{RSTTEMPO} \) is present only for the BOR0 lowest threshold ( \( V_{BOR0} \) ).
2. 2. The rising edge of the system reset NRST can be driven from the \( V_{BOR0} \) power-on reset or \( V_{BORx} \) (x = 1 to 4) rising threshold depend on the \( V_{DD} \) rising slope.

11.6.2 Programmable voltage detector (PVD)

The PVD can be used to monitor the \( V_{DD} \) power supply by comparing it to a threshold selected by the PVDLS[2:0] bits in the PWR supply voltage monitoring control register (PWR_SVMCR) . Also the PVD can be used to monitor an analog signal on the PVD_IN I/O by comparing it to the \( V_{REFINT} \) threshold. The PVD is enabled by setting the PVDE bit.

A PVDO flag is available in the PWR supply voltage monitoring status register (PWR_SVMSR) to indicate if \( V_{DD} \) is higher or lower than the PVD threshold. This event is internally connected to the EXTI and can generate an interrupt if enabled through the EXTI registers (refer to Table 99 ).

The rising/falling edge sensitivity of the EXTI line must be configured according to PVD output behavior. For example, if the EXTI line is configured to rising edge sensitivity, the interrupt is generated when \( V_{DD} \) drops below the PVD threshold. As an example the service routine can perform emergency shutdown tasks.

The PVD can remain active in Stop 0, Stop 1, and Stop 2 modes, and the PVD interrupt can wake up the system from the Stop modes. The PVD is not functional in Standby mode.

Figure 33. PVD thresholds

11.7 PWR power management

11.7.1 PWR power modes

By default, the microcontroller is in Run mode range 2 and the 2.4 GHz RADIO in deep sleep after a system or a power reset. Several low-power modes are available to save power when the CPU or peripherals do not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode that gives the best compromise between low-power consumption, short startup time and available wake-up sources.

The device features these low-power modes:

• • Run mode:
  The CPU is running. The power consumption can be reduced by slowing down the system clocks and configuring voltage scaling to lower-power range, and/or gating the clocks to the APB and AHB peripherals when they are not used.
• • Sleep mode:
  CPU clock off, all peripherals including Cortex-M33 core such as NVIC and SysTick can run and wake up the CPU when an interrupt or an event occurs. Refer to Section 11.7.5 .
• • Stop 0, Stop 1 modes:
  Stop modes achieve the lowest power consumption while retaining the registers content. The SRAM content can be selected to be retained or not. All clocks (except some autonomous peripherals bus and kernel clocks) in the Core domain are stopped. The PLL and HSE32 crystal oscillator are disabled. The HSI16 RC oscillator is disabled when not activated as autonomous peripheral bus or kernel clock. The LSE or LSI can still run.

Some peripherals are autonomous and can operate in Stop modes by requesting their kernel clock, and in Stop 0 mode also when requesting their bus clock when needed. When a peripheral requests its (APB or AHB) bus clock, for example to transfer data with GPDMA1, the device transitions from Stop 1 to Stop 0 mode.

The I2C, USART, LPUART, SPI, LPTIM, ADC, RTC can remain active in Stop modes when kernel clock is LSE, LSI, or HSI16. The 2.4 GHz RADIO can remain active in Stop 0 mode on its kernel clock HSE32. In Stop 0 mode the autonomous peripherals bus clock can remain active using HSI16.

The brownout reset (BOR) remains always active, and the PVD can be kept active in Stop modes. In Stop 1 mode the BOR0 can be configured in ultra-low power mode to further reduce power consumption.

Warning: Ultra-low power mode must not be used together with autonomous peripherals using HSI16 as kernel clock.

In Stop 0 mode, the regulator remains in main regulator mode, allowing a very fast wake-up time but with higher consumption compared with Stop 1.

The system clock when exiting from Stop mode is HSI16 at 16 MHz.

Refer to Section 11.7.6 , and Section 11.7.7 .

• • Stop 2 mode:

This mode achieves the lowest power consumption while retaining some peripherals and the system configuration registers content. The SRAM content can be retained or not. All clocks (except some autonomous peripherals kernel clocks) in the Core domain are stopped. The PLL and HSE32 crystal oscillator are disabled. The HSI16 RC oscillator is disabled when not activated as autonomous peripheral kernel clock. The LSE or LSI can still run.

Some peripherals are autonomous and can operate by requesting their kernel clock when needed. The I2C3, LPUART1, SPI3, LPTIM1, RTC can remain active when kernel clock is LSE, LSI, or HSI16.

The brownout reset (BOR) remains always active, and the PVD can be kept active in Stop 2 mode. The BOR0 can be configured in ultra-low power mode to further reduce power consumption.

Warning: Ultra-low power mode must not be used together with autonomous peripherals using HSI16 as kernel clock.

The system clock when exiting from Stop mode is HSI16 at 16 MHz.

Refer to Section 11.7.9: PWR Standby mode .

• • Standby mode:

The Standby mode is used to achieve the lowest power consumption. The internal regulator is switched off so that the Core domain is powered off. The PLL, the HSI16 RC, and the HSE32 crystal oscillators are also switched off. The LSE or LSI can still run. The RTC and TAMPER can remain active in Standby modes when kernel clock is LSE or LSI.

The BOR always remains active in Standby mode. The BOR can be configured in ultra-low power mode to further reduce power consumption during standby mode.

The state of each I/O during Standby mode can be selected by software: I/O with internal pull-up, internal pull-down or floating.

When entering Standby mode register contents are lost except for registers in the Backup domain and Standby circuitry.

Optionally, the full SRAM1 and/or SRAM2 can be retained in Standby mode, supplied by the low-power regulator (Standby with retention mode).

Optionally, the 2.4 GHz RADIO sleep timer, RXTXRAM configuration, and sequence SRAM can be retained in Standby mode, supplied by the low-power regulator (Standby with retention mode).

The device exits Standby mode when an NRST pin external reset, an IWDG early interrupt or reset, WKUP pin event (configurable rising or falling edge), an RTC event occurs (alarm, periodic wake-up, timestamp), a TAMP tamper detection, or a 2.4 GHz RADIO sleep timer event (available only in Standby with retention mode). The tamper detection can be raised either due to external pins or due to an internal failure detection.

The system clock after wake-up is HSI16 16 MHz.

Refer to Section 11.7.9 .

The operating modes and transitions are shown in Figure 34 .

Figure 34. Operating modes

1. 1. When the 2.4 GHz RADIO is active the range and SMPS/LDO operating mode cannot be changed. Any request to change power operating mode is delayed and takes effect only after the 2.4 GHz RADIO has entered Sleep mode.
2. 2. The 2.4 GHz RADIO can only change states deep sleep, Sleep, and Active by software, when the device is in Run mode. When the device moves to a low-power mode, the 2.4 GHz RADIO remains in its same mode. 2.4 GHz RADIO deep sleep state is independent from the presence of power supply.
3. 3. BAM autonomous peripherals can operate on bus clock HSI16 and/or kernel clock LSE, LSI, or HSI16.
4. 4. Autonomous peripherals can operate on kernel clock LSE, LSI, or HSI16.
5. 5. Autonomous peripherals RTC, TAMP, 2.4 GHz RADIO sleep timer can operate on kernel clock LSE or LSI.
6. 6. Autonomous peripherals RTC, TAMP can operate on kernel clock LSE.

Image: ST Logo

RM0515 Rev 4

313/2115

1. 7. For Standby entered from SMPS modes, the wake-up is done to Run LDO-MR Range 2 mode and a subsequent move to Run SMPS-LP Range 2 mode is performed in hardware.
2. 8. Standby modes are entered regardless of autonomous peripherals kernel clock activity. It is up to software to select the correct low-power mode with autonomous peripherals kernel clock activity.

Table 89 shows the power modes overview.

Table 89. Low-power modes summary

1. Refer to Table 90 .

2. SMPS is available only on STM32WBA63/65xx devices.

Table 90. Functionalities depending on the working mode ⁽¹⁾ (continued)

1. 1. A = Active, Y = yes. O = optional (can be enabled/disabled by software). R = Retained, - = not available. Gray cells highlight the wake-up capability in each mode.
2. 2. The flash memory can be configured in power-down mode.
3. 3. PWR controller is partially retained.
4. 4. Some peripherals with autonomous mode and wake-up from Stop capability can request HS116 to be enabled. In this case, the oscillator is woken up by the peripheral, and is automatically put off when no peripheral needs it.
5. 5. For the autonomous 2.4 GHz RADIO the HSE32 can be kept running.
6. 6. GPIO pins from peripherals supporting autonomous mode are still operational.
7. 7. Only GPIOs with enabled wake-up functionality in the EXTI or WKUP are able to wake up the system.
8. 8. GPIO level retention from PTA interface in Stop 2 mode can be enabled.
9. 9. GPIO level retention in Standby modes can be enabled.
10. 10. Only GPIOs with WKUP functionality are able to wake up the system.
11. 11. BAM autonomous peripherals can wake up the GPDMA to perform data transfers.
12. 12. USB OTG booster must be enabled.
13. 13. USB OTG must be shut off by software before entering low-power modes.
14. 14. Functional through ADC4 in autonomous mode.
15. 15. DBGMCU remains accessible through AP0.
16. 16. DBGMCU remains accessible through AP0 when CDBGPWURUPREQ is set.

Debug mode

By default, the debug connection is lost if the application puts the MCU in Stop and Standby modes while the debug features are used. This is because the Cortex-M33 core is no longer clocked or powered.

However, by setting some configuration bits in the DBGMCU control registers, the software can be debugged even when using the low-power modes extensively. For more details, refer to Section 45.2.5: DBG low-power modes .

11.7.2 PWR background autonomous mode (BAM)

The devices support a background autonomous mode (BAM). This allows autonomous peripherals to be functional on its bus and kernel clock in Stop 0 mode and on its kernel clock in Stop 0 and Stop 1 modes and for a limited set of peripherals in Stop 2 mode (when the CPU is in deep sleep, not running any software). In Stop 1 mode, whenever an autonomous peripheral request its bus clock, Stop 0 mode is entered while the CPU remains in deep sleep.

Stop 0 and Stop 1 modes

In Stop 0 and Stop 1 modes, the autonomous peripherals are ADC, LPTIM, USART, LPUART, SPI, I2C:

• • Peripherals are autonomous only with LSE, LSI or HSI16 used as kernel clock, or HSI16 used as bus clock
• • When an autonomous peripheral request its bus clock Stop 0 mode is entered while keeping the CPU in deep sleep.

In Stop 0 mode the 2.4 GHz RADIO can operate autonomously on HSI16 used as bus clock and HSE32 used as kernel clock. The 2.4 GHz RADIO cannot be autonomous in Stop 1 mode.

When entering low-power modes Stop and Standby from Run and an autonomous peripheral bus clock request is active, Stop 0 mode is entered, regardless of the low-power mode selection in LPMS bits. Entering in the LPMS selected low-power mode (Stop 1 and Standby) is delayed until the autonomous peripheral bus clock request is released.

When in Stop 1 mode and an autonomous peripheral request its bus clock, Stop 0 mode is entered.

When in Stop 0 mode and all autonomous peripheral bus clock request are deactivated, the low-power mode selected in the LPMS bits is entered. Note that Stop 2 and Standby modes can be entered only when the 2.4 GHz RADIO is in deep sleep.

Note: As soon as the CPU enters deep sleep, the system enters Stop mode and the BAM operation autonomous peripheral bus clock and SYSCLK is switched to HSI16 at 16 MHz. If autonomous peripheral operation with higher bus clock frequencies is needed, the CPU must enter Sleep and keep the system in Run with the configured Run mode SYSCLK clock frequency.

Stop 2 mode

In Stop 2 mode, the autonomous peripherals are LPTIM1, LPUART1, SPI3, I2C3:

• • Peripherals are autonomous only with LSE, LSI or HSI16 used as kernel clock.

When in this mode, an autonomous peripheral must generate an interrupt to wake up the CPU. From Stop 2 mode autonomous peripheral BAM operation wake-up on bus clock and using the GPDMA1 is not supported.

BAM in Stop mode

BAM is supported by the autonomous peripherals with the following features:

• • Functionality in Stop mode thanks to the peripheral kernel clock request capability: the peripheral kernel clock is automatically switched on when requested by a peripheral, and automatically switched off when no peripheral requests it. For the peripheral kernel clock to be switched on, both the peripheralEN and peripheralSMEN bits in the RCC registers must be set.
• • DMA transfers supported in Stop 0 mode, thanks to the peripheral bus clock request capability: the system clock (HSI16) is automatically switched on when requested by a peripheral, and automatically switched off when no peripheral requests it. When the system clock is requested by an autonomous peripheral and both peripheralEN and peripheralSMEN bits in the RCC registers are set, the system clock is woken up and distributed to all peripherals for which the RCC peripheralEN and peripheralSMEN bits are set. This makes possible DMA transfers between peripherals and SRAMs. The

2.4 GHz RADIO bus clock is requested independently from the RADIOEN and RADIOSMEN.

• • Automatic start of the peripheral thanks to the hardware synchronous or asynchronous triggers (such as I/Os edge detection and low-power timer events)
• • Wake up the CPU from deep sleep mode through a peripheral interrupt.

The GPDMA1 is fully functional and the linked-list is updated in Stop 0 mode, allowing the different DMA transfers to be linked without any CPU intervention. This can be used to chain transfers between different peripherals, or to write peripheral registers, to change their configuration while in Stop 0 mode.

The DMA transfers from memory to memory can be started by hardware synchronous or asynchronous triggers, and the DMA transfers between peripherals and memories can also be gated by those triggers. In BAM in Stop mode only SRAM transfers are supported (flash memory transfers are not).

Here below some use-cases that can be done while remaining in Stop mode:

• • A/D conversion triggered by a low-power timer (or any other trigger)
  • – Wake-up from Stop mode on analog watchdog if the A/D conversion result is out of the programmed thresholds
  • – Wake-up from Stop mode on DMA buffer event
• • I ² C slave reception or transmission, SPI reception, UART/LPUART reception
  • – Wake-up at the end of peripheral transfer or on DMA buffer event
• • I ² C master transfer, SPI transmission, UART/LPUART transmission, triggered by a low-power timer (or any other trigger)
  • – Example: Sensor periodic read
  • – Wake-up at the end of peripheral transfer or on DMA buffer event
• • Bridges between peripherals
  • – Example: A/D converted data transferred by communication peripherals
• • Data transfer from/to GPIO to/from SRAM for:
  • – Controlling external components
  • – Implementing data transmission and reception protocols
• • Data transfer from one SRAM to another one.

Here below some 2.4 GHz RADIO use-cases that can be done while remaining in Stop 0 mode range 1:

• • Transmit and receive data packets.
  • – Wake-up at the end of the scheduled event.

11.7.3 PWR Run mode

Slowing down system clocks

In Run mode, the speed of the system clocks (SYSCLK, hclk, pclk) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down the peripherals before entering the Sleep mode.

For more details, refer to Section 12: Reset and clock control (RCC) .

In addition to slowing down the system clocks, the voltage range can be changed. When the system clocks frequency is low enough range 2 may be entered.

Peripheral clock gating

In Run mode, the hclk and pclk for individual peripherals and memories can be stopped at any time to reduce the power consumption. The peripheral clock gating is controlled by the RCC_AHBxENR and RCC_APBxENR registers.

In Sleep and Stop modes, the hclk and pclk for individual peripherals and memories can be stopped automatically. The Sleep and Stop mode peripheral clock gating is controlled by the RCC_AHBxSMENR and RCC_APBxSMENR registers. For autonomous peripherals to be able to request their clocks the peripheral bus clock in Sleep and Stop mode must be enabled. Except for the 2.4 GHz RADIO, which requests its bus clock independently from the setting in the RADIOEN and RADIOSMEN register bits.

For the 2.4 GHz RADIO the bus clock is running only in Sleep and Stop modes when the STRADIOCLKON is set, or when the 2.4 GHz RADIO is active and RADIOEN and RADIOSMEN are set.

11.7.4 PWR low-power modes

Entering into a low-power mode

The MCU enters in low-power modes by

• • The CPU executing the WFI (wait for interrupt), or WFE (wait for event) instructions, or when the SLEEPONEXIT bit in the Cortex-M33 system control register is set on Return from ISR .

Entering into a low-power mode through WFI or WFE is executed only if no interrupt is pending or no event is pending.

Software must enter Low-power Stop and Standby modes only when voltage scaling is ready (ACTVOSRDY = 1).

When an autonomous peripheral bus clock request is active only Stop 0 is entered, regardless of the low-power mode set in LPMS register bits.

Stop 1 mode is entered only when the 2.4 GHz RADIO is in Sleep or deep sleep mode.

Stop 2 and Standby modes are entered only when the 2.4 GHz RADIO is in deep sleep mode.

Standby modes are entered only when the 2.4 GHz RADIO is in deep sleep mode.

Exiting a low-power mode

The way the CPU exits the Sleep or Stop mode depends on the way the low-power mode was entered:

• • If the WFI instruction or Return from ISR was used to enter the low-power mode, any peripheral interrupt acknowledged by the NVIC can wake up the device.
• • If the WFE instruction is used to enter the low-power mode, the CPU exits the low-power mode as soon as an event occurs. The wake-up event can be generated by:
  • – an NVIC IRQ interrupt:
    When SEVONPEND = 0 in the Cortex-M33 system control register
    By enabling an interrupt in the peripheral control register and in the NVIC. When the CPU resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) must be cleared. Only NVIC interrupts with high enough priority wake up and

interrupt the CPU.

When SEVONPEND = 1 in the Cortex-M33 system control register

By enabling an interrupt in the peripheral control register and optionally in the NVIC. When the CPU resumes from WFE, the peripheral interrupt pending bit and when enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) must be cleared. All NVIC interrupts wake up the MCU, even the disabled ones. Only enabled NVIC interrupts with high enough priority wake up and interrupt the CPU.

– an event:

Configuring an EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bits corresponding to the event line is not set. It may be necessary to clear the interrupt flag in the peripheral.

The CPU exits Standby mode through a reset. After waking up from Standby mode, the program execution restarts in the same way as after a reset (boot pin sampling, option bytes loading, reset vector is fetched).

Caution: When the device is in Stop mode, a peripheral interrupt powers on an internal oscillator. The corresponding NVIC interrupt channel must be enabled to allow the interrupt to wake up the CPU from Stop mode. It is not allowed to disable a peripheral interrupt by disabling only the NVIC channel while keeping the peripheral interrupt enable, as the device could remain in Stop mode with clock ON.

The peripherals with autonomous mode feature are able to generate an AHB or APB clock request when the device is in Stop mode, depending on their internal events. The software must ensure that either DMA transfer or interrupt is served, by configuring properly and in a consistent way the RCC, the autonomous peripherals, the DMA channels, and NVIC. Note that when an autonomous peripheral requests the bus clock in Stop mode, the AHB, and APB clocks are distributed to all enabled peripherals on the same AHB or APB bus. Consequently, enabled peripherals, even without autonomous mode capability, are temporarily clocked and can also generate an interrupt during this time. These interrupts also wake up the device from Stop mode.

11.7.5 PWR Sleep mode

I/O states in Sleep mode

In Sleep mode, all I/O pins keep the same state as in Run mode. In addition I/O pins can be toggled through DMA or other active communication peripherals.

To further reduce the power consumption in Sleep mode, disabling the peripherals clocks in Sleep mode can be performed automatically by resetting the corresponding bit in the RCC_AHBxSMENR and RCC_APBxSMENR registers.

Entering the Sleep mode

The MCU enters the Sleep mode as described in Entering into a low-power mode , when the SLEEPDEEP bit in the Cortex-M33 system control register is clear (see the table below for details on how to enter the Sleep mode).

Exiting the Sleep mode

The MCU exits the Sleep mode as described in Exiting a low-power mode (see the table below for details on how to exit the Sleep mode).

11.7.6 PWR Stop 0 mode

The Stop mode is based on the CPU1 Cortex ^® -M33 deep sleep mode combined with peripheral clock gating. The voltage regulator configuration as used in Run mode remains the same in Stop 0 mode. In Stop mode, all clocks in the Core domain are stopped. The PLL, HSI16 and HSE32 oscillators are disabled.

Some peripherals with autonomous capability can switch on HSI16 or HSE32 for transferring data (see Section 11.7.2 for details). Autonomous capable peripherals using HSE32 require the use of Stop 0 mode range 1.

To reduce the power consumption in Stop mode, disabling the peripherals clocks can be performed automatically by resetting the corresponding bit in the RCC_AHBxSMENR and RCC_APBxSMENR registers. This bit must be set for the autonomous peripherals requesting clocks in Stop mode.

All register contents are preserved, SRAM1 and/or SRAM2 can totally or not be retained to further reduce consumption.

I/O states in Stop 0 mode

In the Stop 0 mode, all I/O pins keep the same state as in the Run mode. In addition, I/O pins can be toggled through DMA or other autonomous communication peripherals.

Entering the Stop 0 mode

The MCU enters the Stop 0 mode as described in Entering into a low-power mode , when the SLEEPDEEP bit in the Cortex-M33 system control register is set. The regulator is kept in the same regulation mode and voltage scaling range as used in Run mode. (see the table below for details on how to enter the Stop 0 mode).

If the flash memory programming is ongoing, the Stop 0 mode entry is delayed until the memory access is finished.

If an access to the APB domain is ongoing, the Stop 0 mode entry is delayed until the APB access is finished.

In Stop 0 mode, the following features can be selected by programming the individual control bits:

• • The independent watchdog (IWDG) is started by writing to its key register or by hardware option. Once started, it cannot be stopped except by a reset (see Section 35.4: IWDG functional description ).
• • The real-time clock (RTC) is configured by the RTCSEL bit in the RCC Backup domain control register (RCC_BDCR1) .
• • The internal RC oscillator LSI or LSI1 clock divided by 128, is configured by the LSION and LSI1PREDIV bits in the RCC_BDCR1 register.
• • The external 32.768 kHz oscillator (LSE) is configured by the LSEON bit in RCC_BDCR1.
• • The 2.4 GHz RADIO sleep timer configured through the link layer software.
• • SRAM1 retention configured by the SRAM1PDS1 bit in PWR control register 2 (PWR_CR2) .
• • SRAM2 retention configured by the SRAM2PDS1 bit in PWR control register 2 (PWR_CR2) .

Several peripherals can be autonomous in Stop 0 mode, increasing power consumption if enabled (see Section 11.7.2 for more details).

The COMPs and the PVD can be used in Stop mode. If not needed, they must be disabled by software to reduce power consumption.

The ADC4, VREFBUF, and the temperature sensor can consume power during the Stop 0 mode, unless they are disabled before entering the mode.

Entering Stop 1, Stop 2, and Standby modes from Stop 0

When entering low-power with Stop 1, Stop 2, or Standby selected in LPMS and an autonomous peripheral bus clock request is active, Stop 0 mode is entered instead. Only when all autonomous peripheral bus clock requests are de-asserted the LPMS selected low-power mode is subsequently entered. Stop 2 and standby modes are entered only when the 2.4 GHz RADIO is in deep sleep.

Exiting the Stop 0 mode

The MCU exits the Stop 0 mode as described in Exiting a low-power mode (see Table 92 ).

When exiting Stop 0 mode by issuing an interrupt or a wake-up event, HSI16 is selected as system clock.

Several peripherals are autonomous in Stop mode, and can generate interrupts with wake-up from Stop capability. All peripheral clocks must be enabled to allow a wake-up from Stop interrupt (see Peripheral clock gating ).

When exiting the Stop 0 mode, the MCU is in Run mode same range as before entering Stop 0 mode.

The MCU can enter another low-power mode, as selected in LPMS, from the Stop 0 mode when all autonomous peripheral bus clocks requests are de-asserted.

Table 92. Stop 0 mode

Table 92. Stop 0 mode (continued)

11.7.7 PWR Stop 1 mode

The Stop 1 mode is the same as Stop 0 mode except that the regulator is in low-power mode and voltage scaling is set to range 2. (see the table below for details on how to enter and exit Stop 1 mode).

The BOR is always available in Stop 1 mode. When not using autonomous peripherals operation with HSI16 as kernel clock, the BOR0 can be forced in ultra-low power mode by the ULPMEN bit in the PWR_CR1 to reach the lowest power consumption.

Entering the Stop 1 mode

The MCU enters the Stop 1 mode in the same way as entering Stop 0. Whenever an autonomous peripheral bus clock request is active, Stop 1 mode is not entered and Stop 0 mode is entered instead.

Entering the Stop 0 mode from Stop 1

When in low-power Stop 1 mode an autonomous peripheral bus clock request is activated, Stop 0 mode range 2 is entered, with HSI16 as system clock and HDIV5 is set to divide by 2 by hardware.

Exiting the Stop 1 mode

The MCU exits the Stop 1 mode as described in Exiting a low-power mode (see Table 93 ).

When exiting Stop 1 mode by issuing an interrupt or a wake-up event, Run range 2 with HSI16 selected as system clock and HDIV5 is set to divide by 2 by hardware. Before entering Stop 1 mode software must configure adequate FLASH wait states latency to at least 1 in FLASH_ACR register and SRAM1 and SRAM2 wait states to at least 1 in RAMCFG_MxCR.

Table 93. Stop 1 mode

Table 93. Stop 1 mode (continued)

11.7.8 PWR Stop 2 mode

This is the same as Stop 1 mode, except that some peripherals are powered down (see Table 94 for details on how to enter and exit the mode).

The BOR is always available in this mode. When not using autonomous peripherals operation with HSI16 as kernel clock, the BOR0 can be forced in ultra-low power mode by the ULPMEN bit in the PWR_CR1, to reach the lowest power consumption.

I/O states in Stop 2 mode

Before entering Stop 2 mode the not retained peripherals must be disabled and unselected from the GPIO alternate functions. Except for the PTACONV, where the GPIO state can be retained when enabled in the PTASREN register bit, the GPIO retains the output level. When entering Stop 2 mode, PTACONV signals enabled for Stop 2 mode retention keep their state during and after exiting from Stop 2 mode until the PTASR bit is cleared by software. When entering Stop 2 mode the PTASR bit is set by hardware when enabled in

PTASREN. The PTASR only controls output levels, it does not affect the GPIO pulls, analog, input and output states. When exiting from Stop 2 and before removing the PTACONV retention, the PTACONV peripheral must be re-initialized. Once the PTACONV peripheral configuration is reconfigured, disable the retention in PTASR.

Entering the Stop 2 mode

The MCU enters the Stop 2 mode in the same way as entering Stop 0. Whenever an autonomous peripheral bus clock request is active, Stop 2 mode is not entered and Stop 0 mode is entered instead.

Stop 2 mode is entered only when the 2.4 GHz RADIO is in deep sleep mode. Whenever the 2.4 GHz RADIO is in Active or Sleep mode, Stop 0 or Stop 1 modes are entered instead.

Note: Autonomous peripherals in Stop 2 mode must be configured by software to request a bus clock only when also generating a peripheral IRQ event to wake up the CPU.

Exiting the Stop 2 mode

The MCU exits the mode as described in Exiting a low-power mode (see Table 93 ). The STOP2F status flag in the PWR status register (PWR_SR) indicates that the MCU was in Stop 2 mode. The powered down peripherals registers are reset after wake-up from this mode.

When exiting Stop 2 mode by issuing an interrupt or a wake-up event, Run range 2 with HSI16 selected as system clock and HDIV5 is set to divide by 2 by hardware. Before entering Stop 2 mode software must configure adequate FLASH wait states latency to at least 1 in FLASH_ACR register and SRAM1 and SRAM2 wait states to at least 1 in RAMCFG_MxCR.

Table 94. Stop 2 mode

Table 94. Stop 2 mode (continued)

11.7.9 PWR Standby mode

It is based on the Cortex-M33 deep sleep mode, with the voltage regulators disabled (except when SRAM1, SRAM2, or 2.4 GHz RADIO RAMs and sleep timer are retained).

The PLL, HSI16 and HSE32 oscillators are also switched off.

The register contents are lost except for SRAMs and registers in the retention domain when enabled and the Backup domain and Standby circuitry (see Figure 30 ). SRAM1, SRAM2 content can fully be preserved depending on R1RSBx and R2RSB1 bit configuration in PWR_CR1. In this case, the low-power regulator is ON and provides the supply to SRAM1 and/or SRAM2. Also the 2.4 GHz RADIO SRAMs can be retained, and the sleep timer kept operational depending on RADIORSB bit configuration in PWR_CR1.

The BOR is always available in Standby mode. The ULPMEN bit in the PWR_CR1 register must be configured to 1 to reach the lowest power consumption by forcing the BOR0 in ultra-low power mode.

I/O states in Standby mode

In the Standby mode, the GPIOs are by default in floating state. If Standby GPIO retention is enabled in the PWR_IORETENRx register, the GPIO retains the pull or output level. When entering Standby mode, GPIOs that are enabled for Standby mode retention keep their pull or level during and after exiting from Standby mode until the PWR_IORETRx bit is cleared by software. When entering Standby mode the PWR_IORETRx bit is set by hardware for the GPIOs with Standby retention enabled. The PWR_IORETRx only controls the pulls, it does not affect the GPIO analog, input and output states. When exiting from Standby and before re-enabling a GPIO as output, the output level must be restored to the one retained. To do this, first enable the GPIO as input and copy the input data from GPIOx_IDR to the GPIOx_ODR, before setting the GPIO as output. Once the GPIO is reconfigured, disable the retained pulls in PWR_IORETRx.

The GPIO standby retention enable information in PWR_IORETENRx and PWR_IORETRx are retained in Standby mode.

Note: The Standby GPIO retention level cannot be guaranteed when the GPIO port pin is connected to a low impedance destination.

Table 95. GPIO retention pin with pull-up and pull-down

For GPIO port pins enabled to be functional in Standby modes, the Standby GPIO retention can also be controlled in the PWR_IORETENRx register. The following GPIO functions are available in Standby modes:

• • RTC outputs on PC13 and/or PB2 (standby GPIO retention must be disabled)
• • TAMP tamper pins
• • WKUPx_y wake-up pins
• • LSE pins on PC14 and/or PC15 (Standby GPIO retention must be disabled)
• • JTDO/TRACE SWO on PB3 when debugger is connected and CDBGPWRUPREQ is set (Standby GPIO retention must be disabled)

When waking up from Standby with a system reset (NRST) GPIO retention is removed before software can reconfigure the GPIO port pins in the GPIO peripheral.

Entering Standby mode

The MCU enters the Standby mode as described in Entering into a low-power mode , when the SLEEPDEEP bit in the Cortex-M33 System Control register is set (see Table 96 ).

Whenever an autonomous peripheral bus clock request is active, Standby mode is not entered and Stop 0 mode is entered instead.

Standby mode is entered only when the 2.4 GHz RADIO is in deep sleep mode. Whenever the 2.4 GHz RADIO is in Active or Sleep modes, Stop 0 or Stop 1 modes are entered instead.

In Standby mode, the following features can be selected by programming individual control bits:

• • The independent watchdog (IWDG) is started by writing to its Key register or by hardware option. Once started, it cannot be stopped, except by a reset (see Section 35.4: IWDG functional description ).
• • The real-time clock (RTC) is configured by the RTCSEL bit in RCC Backup domain control register (RCC_BDCR1) .
• • The internal RC oscillator LSI or LSI1 clock divided by 128 is configured by the LSION and LSI1PREDIV bits in RCC_BDCR1 .
• • The external 32.768 kHz oscillator (LSE) is configured by the LSEON bit in RCC_BDCR1 .
• • The 2.4 GHz RADIO SRAMs and sleep timer configured by the RADIORSB bit in PWR control register 1 (PWR_CR1) . Available in Standby retention mode.
• • SRAM1 retention configured by the R1RSBx bits in PWR control register 1 (PWR_CR1) . Available in Standby retention mode.
• • SRAM2 retention configured by the R2RSBx bits in PWR control register 1 (PWR_CR1) . Available in Standby retention mode.

Exiting Standby mode

The MCU exits the Standby mode as described in Exiting a low-power mode . The SBF status flag in the PWR status register (PWR_SR) indicates that the MCU was in Standby mode (see Table 96 for more details on how to exit Standby mode).

Table 96. Standby mode

Table 96. Standby mode

11.7.10 Power modes output pins

To help the debug, two signals are available as device pins alternate functions:

• • PWR_CSLEEP

When set, indicates that the CPU is in Sleep mode:

• – WFI or WFE has been executed, and CPU stops execution CPU hclk1 stopped

When cleared, indicates that the CPU is in Run mode.

• • PWR_CSTOP

When set, indicates that the device is in Stop mode, meaning that the following conditions are true:

• – WFI or WFE has been executed with CPU SLEEPDEEP = 1
• – No AHB/APB clock is running, except for BAM autonomous peripherals

When cleared, indicates that the device is in Run or Sleep mode with AHB/APB clocked.

Note: After WFI or WFE has been executed the SYSCLK clock is kept running in Stop 0 mode when an autonomous peripheral requests its bus clock. The peripherals bus clock request can prevent the device to enter the selected low-power mode, which enters Stop 0 mode instead. (refer to Section 11.7.2 and Section 11.7.4 ).

Table 97 explains the MCU power mode depending on these signals states.

Table 97. Power modes output states versus MCU power modes

1. 1. PWR_CSLEEP and PWR_CSTOP are generated in the Core domain, consequently they are not driven in Standby mode.

11.8 PWR security and privileged protection

11.8.1 PWR security protection

TrustZone security is activated by the TZEN user option bit in the FLASH_OPTR. Some PWR register fields can be secured against non-secure access.

The PWR TrustZone security allows the following features to be secured through the PWR_SECCFGR register:

• • Low-power mode
• • Wake-up (WKUP) pins
• • Voltage detection
• • Backup domain control

Other PWR configuration bits are secure when:

• • The system clock selection is secure in RCC: the voltage scaling (VOS) configuration is secure.
• • The I/O Standby mode retention configuration is secure when the corresponding GPIO is secure.

If SPRIV is set in the PWR privilege control register (PWR_PRIVCFGR) , the PWR_SECCFGR register can be written only by secure and privileged access. If SPRIV is cleared, PWR_SECCFGR can be written only by secure access, privileged, or unprivileged.

PWR_SECCFGR can be read by secure, non-secure, privileged, and unprivileged access.

A non-secure write access to PWR_SECCFGR is WI and generates an illegal access event and an interrupt if enabled in the GTZC.

When the TrustZone security is disabled (TZEN = 0), PWR_SECCFGR is RAZ/WI and all other registers are non-secure.

When a peripheral is configured as secure, its related PWR feature control bits, are also secure in the associated registers. PWR_PUCRx, PWR_PDCRx, PWR_RADIOSCR, and PWR_VOSR.

A peripheral is secure when:

• • For securable peripherals by GTZC-TZSC (TrustZone security controller), by the SEC security bit in the secure configuration registers corresponding to this peripheral.
• • For TrustZone-aware peripherals, a security feature of this peripheral is enabled through its dedicated bits.

Table 98 gives a summary of the PWR secured bits following the security configuration bit in PWR_SECCFGR.

A non-secure access to a secure-protected register bit is denied:

• • The secured bits are not written (WI) with a non-secure write access.
• • The secured bits are read as 0 (RAZ) with a non-secure read access.

Table 98. PWR security configuration summary

Table 98. PWR security configuration summary (continued)

1. PWR_SECCFGR is always secure.

2. PWR_PRIVCFGR.SPRIV is always secure.

11.8.2 PWR privileged protection

By default, after a reset, all PWR registers can be read or written with both privileged and unprivileged accesses, except PWR_PRIVCFGR that can be written with privileged access only. PWR_PRIVCFGR can be read by secure and non secure, privileged, and unprivileged accesses.

The SPRIV bit in PWR_PRIVCFGR can be written with secure privileged access only. This bit configures the privileged access of all PWR secure functions (defined by PWR_SECCFGR, GTZC, RCC, or GPIO as shown in Table 98 ).

When the SPRIV bit is set in PWR_PRIVCFGR:

• • The PWR secure bits can be written only with privileged access, including PWR_SECCFGR.
• • The PWR secure bits can be read only with privileged access except PWR_SECCFGR and PWR_PRIVCFGR that can be read by privileged or unprivileged access.
• • An unprivileged access to a privileged PWR bit or register is discarded: the bits are read as zero and the write to these bits is ignored (RAZ/WI).

The NSPRIV bit of PWR_PRIVCFGR can be written with privileged access only, secure or non-secure. This bit configures the privileged access of all PWR securable functions that are configured as non-secure (defined by PWR_SECCFGR, GTZC, RCC, or GPIO as

shown in Table 98 ).

When the NSPRIV bit is set in PWR_PRIVCFGGR:

• • The PWR securable bits that are configured as non-secure, can be written only with privileged access.
• • The PWR securable bits that are configured as non-secure, can be read only with privileged access except PWR_PRIVCFGGR that can be read by privileged or unprivileged accesses.
• • The VOSRDY bit in PWR_VOSR and the registers PWR_SR, PWR_SVMSR, PWR_BDSR and PWR_WUSR, can be read with privileged or unprivileged accesses.
• • An unprivileged access to a privileged PWR bit or register is discarded: the bits are read as zero and the write to these bits is ignored (RAZ/WI).

11.9 PWR interrupts

Table 99 gives a summary of the interrupt sources, and how to control them.

Table 99. PWR interrupt requests

1. The WKUP_S secure interrupt is used only when trustZone is enabled.

11.10 PWR registers

11.10.1 PWR control register 1 (PWR_CR1)

Address offset: 0x000

Reset value: 0x0000 0000 (reset value not affected by exit Standby mode)

Access: 14 AHB clock cycles added compared to a standard AHB access

Access to this register can be protected by bits LPMSEC and SPRIV or NSPRIV.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 R1RSB[4:1] : SRAM1 64 KB page x retention in Standby mode (x = 1 to 4)

Each bit is used to keep a SRAM1 64 KB page content in Standby retention mode.

0: SRAM1 64 KB, page x content not retained in Standby mode

1: SRAM1 64 KB, page x content retained in Standby mode

Bit 11 R1RSB567 : SRAM1 192 KB page 5 to 7 retention in Standby mode

Used to keep SRAM1 page 5 to 7 content in Standby retention mode.

0: SRAM1 192 KB, page 5 to 7 content not retained in Standby mode

1: SRAM1 192 KB, page 5 to 7 content retained in Standby mode

Bit 10 Reserved, must be kept at reset value.

Bit 9 RADIO RSB : 2.4 GHz RADIO SRAMs (RXTRAM and Sequence RAM) and Sleep clock retention in Standby mode.

This bit is used to keep the 2.4 GHz RADIO SRAMs content in Standby retention mode and the 2.4 GHz RADIO sleep timer operational.

0: 2.4 GHz RADIO SRAMs and sleep timer content not retained in Standby mode

1: 2.4 GHz RADIO SRAMs and sleep timer content retained in Standby mode

Bit 8 Reserved, must be kept at reset value.

Bit 7 ULPMEN : BOR0 ultra-low power mode.

This bit is used to reduce the consumption by configuring the BOR0 in discontinuous mode for Stop 1 and Standby modes. Discontinuous mode is available only when BOR levels 1 to 4 and PVD are disabled.

0: BOR0 operating in continuous (normal) mode in all operating modes

1: BOR0 operating in discontinuous (ultra-low power) mode in Stop 1 and Standby modes.

Note: This bit must be set to reach the lowest power consumption in the low-power modes, and not set together with autonomous peripherals using HSI16 as kernel clock.

Note: When BOR level 1 to 4 or PVD is enabled continuous mode applies independently from ULPMEN.

Bit 6 Reserved, must be kept at reset value.

Bit 5 R2RSB1 : SRAM2 retention in Standby mode

This bit is used to keep the SRAM2 content in Standby retention mode.

0: SRAM2 content not retained in Standby mode

1: SRAM2 content retained in Standby mode

Bits 4:3 Reserved, must be kept at reset value.

Bits 2:0 LPMS[2:0] : Low-power mode selection

These bits select the low-power mode entered when the CPU enters the deep sleep mode.

000: Stop 0 mode

001: Stop 1 mode

10x: Standby mode

Others: reserved

11.10.2 PWR control register 2 (PWR_CR2)

Address offset: 0x004

Reset value: 0x0000 0000

Access to this register can be protected by bits LPMSEC and SPRIV or NSPRIV.

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 FLASHFWU : Flash memory fast wake-up from Stop modes (Stop 0, 1)

This bit is used to obtain the best trade-off between low-power consumption and wake-up time when exiting the Stop 0 or Stop 1 modes.

When this bit is set, the flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption.

0: Flash memory enters low-power mode in Stop 0 and Stop 1 modes (lower power consumption).

1: Flash memory remains in normal mode in Stop 0 and Stop 1 modes (faster wake-up time).

Bit 13 Reserved, must be kept at reset value.

Bit 12 PKARAMPDS : PKA SRAM power-down in Stop modes

0: PKA SRAM content retained in Stop modes

1: PKA SRAM content lost in Stop modes

Note: In Stop 2 mode PKA SRAM is erased regardless of setting in PKARAMPDS..

Bit 11 PRAMPDS : OTG SRAM power-down in Stop modes

0: OTG SRAM content retained in Stop modes

1: OTG SRAM content lost in Stop modes

Note: This bit is reserved on STM32WBA63xx devices.

Bits 10:7 Reserved, must be kept at reset value.

Bit 6 SRAM1PDS567 : SRAM1 192 KB, page 5 to 7 power-down in Stop modes

0: SRAM1 192 KB, page 5 to 7 content retained in Stop modes

1: SRAM1 192 KB, page 5 to 7 content lost in Stop modes

Note: SRAM1 page retention in Standby mode is controlled by R1RSB567 bit in PWR_CR1.

Bit 5 Reserved, must be kept at reset value.

Bit 4 SRAM2PDS1 : SRAM2 power-down in Stop modes (Stop 0, 1)

0: SRAM2 content retained in Stop modes

1: SRAM2 content lost in Stop modes

Note: The SRAM2 retention in Standby mode is controlled by R2RSB1 bit in PWR_CR1.

Bits 3:0 SRAM1PDS[4:1] : SRAM1 page x power-down in Stop modes (x = 1 to 4)

0: SRAM1 64 KB page x content retained in Stop modes

1: SRAM1 64 KB page x content lost in Stop modes

Note: SRAM1 page retention in Standby mode is controlled by R1RSB[4:1] bits in PWR_CR1.

11.10.3 PWR control register 3 (PWR_CR3)

Address offset: 0x008

Power-on reset value: 0x0000 1540 (reset value not affected by exit Standby mode, not affected by system reset, except REGSEL)

Access: 14 AHB clock cycles added compared to a standard AHB access

Access to this register can be protected by bits VDMSEC and SPRIV or NSPRIV.

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:8 SELREP[5:0] : Low power mode regulator replica selection

xxxx00: Standby retention mode, 50% of replica

xxxx01: Standby retention mode, 100% of replica

xxxx10: Standby retention mode, 150% of replica

xxxx11: Standby retention mode, 200% of replica

xx00xx: Stop 2 mode, 50% of replica

xx01xx: Stop 2 mode, 100% of replica

xx10xx: Stop 2 mode, 150% of replica

xx11xx: Stop 2 mode, 200% of replica

00xxxx: Stop 1 mode, 50% of replica

01xxxx: Stop 1 mode, 100% of replica

10xxxx: Stop 1 mode, 150% of replica

11xxxx: Stop 1 mode, 200% of replica

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 DIVCLP[2:0] : Low power mode regulator clock division

000: Low power regulator clock not divided

Others: Low power regulator clock divided by \( 2^{\text{DIV\_CKCLP}} \)

Bit 3 Reserved, must be kept at reset value.

Bit 2 FSTEN : Fast soft start

0: LDO/SMPS fast startup disabled (limited inrush current after system reset and wake-up from Standby)

1: LDO/SMPS fast startup enabled

Bit 1 REGSEL : Regulator selection

0: LDO selected

1: SMPS selected

Note that this bit is reserved on STM32WBA62/64xx devices.

Bit 0 Reserved, must be kept at reset value.

11.10.4 PWR voltage scaling register (PWR_VOSR)

Address offset: 0x00C

Reset value: 0x4000 9000 (Hardware reset value: 0x0000 0000)

Bits 31:22 VDD11USBSWDLY[9:0] : USB OTG VDD11USB switch delay

Access can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

VDD11USBSWDLY cycles of clock PWR hclk.

Note: This bit is reserved on STM32WBA63xx devices.

Bit 21 VDD11USBDIS : USB OTG VDD11USB disable

Access can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

0: VDD11USB enabled

1: VDD11USB disabled

Note: This bit is reserved on STM32WBA63xx devices.

Access can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

This bit must be set in range 1 before enabling the OTG.

This bit is reset when going in all Stop modes.

0: USB OTG booster disabled

1: USB OTG booster enabled

Note: This bit is reserved on STM32WBA63xx devices.

USB OTG must be powered down before entering Run voltage scaling range 2, Stop 1, Stop 2 and Standby modes.

Access can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

0: USB OTG power disabled

1: USB OTG power enabled

Note: This bit is reserved on STM32WBA63xx devices.

Bits 18:17 Reserved, must be kept at reset value.

Set a and cleared by software.

Cleared by hardware when entering Stop 1 mode.

Access can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with bit SPRIV or when non-secure with bit NSPRIV.

0: Range 2 (lowest power)

1: Range 1 (highest frequency).

Set and cleared by hardware. When decreasing the voltage scaling range, VOSRDY must be one before increasing the SYSCLK frequency.

0: Not ready, voltage level < VOS selected level

1: Ready, voltage level ≥ VOS selected level

Note: Following a write to VOS, it takes one hclk clock cycle for VOSRDY to be updated.

Bit 14 Reserved, must be kept at reset value.

This bit is set by hardware when the power booster startup time is reached. The USB OTG clock can be provided only after this bit is set.

0: USB OTG power booster not ready

1: USB OTG power booster ready

Note: This bit is reserved on STM32WBA63xx devices.

This bit is set by hardware when the VDD11USB power startup time or deactivation time is reached.

0: USB OTG VDD11USB not ready.

1: USB OTG VDD11USB ready. At VDD11 level when VDD11USBDIS = 0, at ground level when VDD11USBDIS = 1.

Note: This bit is reserved on STM32WBA63xx devices.

Bits 11:0 Reserved, must be kept at reset value.

11.10.5 PWR supply voltage monitoring control register (PWR_SVMCR)

Address offset: 0x010

Reset value: 0x0000 0000

Access to this register can be protected by bits VDMSEC and SPRIV or NSPRIV.

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 IO2SV : VDDIO2 supply valid

This bit is used to validate the presence of a supply on VDDIO2 for electrical and logical isolation purpose. Setting this bit is mandatory to use the GPIOG[15:2].
0: VDDIO2 not supplied, electrical and logical isolation enabled.
1: VDDIO2 supply present, electrical and logical isolation disabled.

Note: This bit is reserved on STM32WBA63/64xx devices.

Bit 28 USV : VDDUSB supply valid

This bit is used to validate the presence of a supply on VDDUSB for electrical and logical isolation purpose. Setting this bit is mandatory to use the USB OTG_HS peripheral.
0: VDDUSB not supplied, electrical and logical isolation enabled.
1: VDDUSB supply present, electrical and logical isolation disabled.

Note: This bit is reserved on STM32WBA63xx devices.

Bits 27:8 Reserved, must be kept at reset value.

Bits 7:5 PVDLS[2:0] : Programmable voltage detector level selection

These bits select the threshold detected by the programmable voltage detector:

000: \( V_{PVD0} \sim 2.0 \text{ V} \)
001: \( V_{PVD1} \sim 2.2 \text{ V} \)
010: \( V_{PVD2} \sim 2.4 \text{ V} \)
011: \( V_{PVD3} \sim 2.5 \text{ V} \)
100: \( V_{PVD4} \sim 2.6 \text{ V} \)
101: \( V_{PVD5} \sim 2.8 \text{ V} \)
110: \( V_{PVD6} \sim 2.9 \text{ V} \)

111: External input analog voltage PVD_IN (compared internally to VREFINT). The I/O used as PVD_IN input must be configured in analog mode in the GPIO register.

Bit 4 PVDE : Programmable voltage detector enable

0: Programmable voltage detector disabled
1: Programmable voltage detector enabled

Bits 3:0 Reserved, must be kept at reset value.

11.10.6 PWR wake-up control register 1 (PWR_WUCR1)

Address offset: 0x014

Reset value: 0x0000 0000 (reset value not affected by exit Standby mode)

Access: 14 AHB clock cycles added compared to a standard AHB access

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 WUPEN8 : Wake-up and interrupt pin WKUP8 enable

Access can be secured by WUP8SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

0: Wake-up and interrupt pin WKUP8 disabled

1: Wake-up and interrupt pin WKUP8 enabled

Bit 6 WUPEN7 : Wake-up and interrupt pin WKUP7 enable

Access can be secured by WUP7SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

0: Wake-up and interrupt pin WKUP7 disabled

1: Wake-up and interrupt pin WKUP7 enabled

Bit 5 WUPEN6 : Wake-up and interrupt pin WKUP6 enable

Access can be secured by WUP6SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

0: Wake-up and interrupt pin WKUP6 disabled

1: Wake-up and interrupt pin WKUP6 enabled

Bit 4 WUPEN5 : Wake-up and interrupt pin WKUP5 enable

Access can be secured by WUP5SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

0: Wake-up and interrupt pin WKUP5 disabled

1: Wake-up and interrupt pin WKUP5 enabled

Bit 3 WUPEN4 : Wake-up and interrupt pin WKUP4 enable

Access can be secured by WUP4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

0: Wake-up and interrupt pin WKUP4 disabled

1: Wake-up and interrupt pin WKUP4 enabled

Bit 2 WUPEN3 : Wake-up and interrupt pin WKUP3 enable

Access can be secured by WUP3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.
0: Wake-up and interrupt pin WKUP3 disabled
1: Wake-up and interrupt pin WKUP3 enabled

Bit 1 WUPEN2 : Wake-up and interrupt pin WKUP2 enable

Access can be secured by WUP2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.
0: Wake-up and interrupt pin WKUP2 disabled
1: Wake-up and interrupt pin WKUP2 enabled

Bit 0 WUPEN1 : Wake-up and interrupt pin WKUP1 enable

Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.
0: Wake-up and interrupt pin WKUP1 disabled
1: Wake-up and interrupt pin WKUP1 enabled

11.10.7 PWR wake-up control register 2 (PWR_WUCR2)

Address offset: 0x018

Reset value: 0x0000 0000 (reset value not affected by exit Standby mode)

Access: 14 AHB clock cycles added compared to a standard AHB access

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 WUPP8 : Wake-up pin WKUP8 polarity

This bit must be configured when WUPEN8 = 0.
Access can be secured by WUP8SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)

Bit 6 WUPP7 : Wake-up pin WKUP7 polarity

This bit must be configured when WUPEN7 = 0.
Access can be secured by WUP7SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)

This bit must be configured when WUPEN6 = 0.

Access can be secured by WUP6SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

0: Detection on high level (rising edge)

1: Detection on low level (falling edge)

This bit must be configured when WUPEN5 = 0.

Access can be secured by WUP5SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

0: Detection on high level (rising edge)

1: Detection on low level (falling edge)

This bit must be configured when WUPEN4 = 0.

Access can be secured by WUP4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

0: Detection on high level (rising edge)

1: Detection on low level (falling edge)

This bit must be configured when WUPEN3 = 0.

Access can be secured by WUP3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

0: Detection on high level (rising edge)

1: Detection on low level (falling edge)

This bit must be configured when WUPEN2 = 0.

Access can be secured by WUP2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

0: Detection on high level (rising edge)

1: Detection on low level (falling edge)

This bit must be configured when WUPEN1 = 0.

Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

0: Detection on high level (rising edge)

1: Detection on low level (falling edge)

11.10.8 PWR wake-up control register 3 (PWR_WUCR3)

Address offset: 0x01C

Reset value: 0x0000 0000 (reset value not affected by exit from Standby mode)

Access: 14 AHB clock cycles added compared to a standard AHB access

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:14 WUSEL8[1:0] : Wake-up and interrupt pin WKUP8 selection

This field must be configured when WUPEN8 = 0.

Access can be secured by WUP8SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

00: reserved

01: WKUP8_1

10: WKUP8_2

11: WKUP8_3 (internal source, does not generate a WKUP interrupt)

Bits 13:12 WUSEL7[1:0] : Wake-up and interrupt pin WKUP7 selection

This field must be configured when WUPEN7 = 0.

Access can be secured by WUP7SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

00: WKUP7_0

01: WKUP7_1

10: reserved

11: WKUP7_3 (internal source, does not generate a WKUP interrupt)

Bits 11:10 WUSEL6[1:0] : Wake-up and interrupt pin WKUP6 selection

This field must be configured when WUPEN6 = 0.

Access can be secured by WUP6SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

00: WKUP6_0

01: WKUP6_1

10: reserved

11: WKUP6_3 (internal source, does not generate a WKUP interrupt)

Bits 9:8 WUSEL5[1:0] : Wake-up and interrupt pin WKUP5 selection

This field must be configured when WUPEN5 = 0.

Access can be secured by WUP5SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

00: reserved

01: WKUP5_1

10: WKUP5_2

11: reserved

This field must be configured when WUPEN4 = 0.

Access can be secured by WUP4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

00: WKUP4_0
01: WKUP4_1
10: reserved
11: reserved

This field must be configured when WUPEN3 = 0.

Access can be secured by WUP3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

00: reserved
01: WKUP3_1
10: WKUP3_2
11: reserved

This field must be configured when WUPEN2 = 0.

Access can be secured by WUP2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

00: WKUP2_0
01: WKUP2_1
10: reserved
11: reserved

This field must be configured when WUPEN1 = 0.

Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

00: WKUP1_0
01: WKUP1_1
10: reserved
11: reserved

11.10.9 PWR disable Backup domain register (PWR_DBPR)

Address offset: 0x028

Reset value: 0x0000 0000

Access to this register can be protected by PWR VBSEC and SPRIV or NSPRIV.

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 DBP : Disable Backup domain write protection

In reset state, all registers in the Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers. Before disabling Backup domain access, make sure any write access to the domain has finished.

0: Write access to Backup domain disabled

1: Write access to Backup domain enabled

11.10.10 PWR security configuration register (PWR_SECCFGR)

Address offset: 0x030

Reset value: 0x0000 0000

When the system is secure (TZEN = 1), this register can be written only by a secure privileged access if SPRIV = 1, and by a secure privileged or unprivileged access if SPRIV = 0. A non-secure write access generates an illegal access event and data are not written. This register can be read by secure or non-secure, privileged, or unprivileged access.

When the system is not secure (TZEN = 0), this register is read as 0 and register writes are ignored.

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 VBSEC : Backup domain secure protection

0: PWR_DBPR can be read and written with secure or non-secure access.

1: PWR_DBPR can be read and written only with secure access.

Bit 13 VDMSEC : Voltage detection secure protection

0: PWR_SVMCR and PWR_CR3 can be read and written with secure or non-secure access.

1: PWR_SVMCR and PWR_CR3 can be read and written only with secure access.

Bit 12 LPMSEC : Low-power modes secure protection

0: PWR_CR1, PWR_CR2 and CSSF in the PWR_SR can be read and written with secure or non-secure access.

1: PWR_CR1, PWR_CR2, and CSSF in the PWR_SR can be read and written only with secure access.

Bits 11:8 Reserved, must be kept at reset value.

Bit 7 WUP8SEC : WUP8 secure protection

0: Bits related to the WKUP8 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access.

1: Bits related to the WKUP8 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access.

Bit 6 WUP7SEC : WUP7 secure protection

0: Bits related to the WKUP7 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access.

1: Bits related to the WKUP7 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access.

Bit 5 WUP6SEC : WUP6 secure protection

0: Bits related to the WKUP6 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access.

1: Bits related to the WKUP6 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access.

Bit 4 WUP5SEC : WUP5 secure protection

0: Bits related to the WKUP5 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access.

1: Bits related to the WKUP5 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access.

Bit 3 WUP4SEC : WUP4 secure protection

0: Bits related to the WKUP4 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access.

1: Bits related to the WKUP4 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access.

Bit 2 WUP3SEC : WUP3 secure protection

0: Bits related to the WKUP3 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access.

1: Bits related to the WKUP3 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access.

Bit 1 WUP2SEC : WUP2 secure protection

0: Bits related to the WKUP2 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access.

1: Bits related to the WKUP2 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access.

Bit 0 WUP1SEC : WUP1 secure protection

0: Bits related to the WKUP1 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access.

1: Bits related to the WKUP1 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access.

11.10.11 PWR privilege control register (PWR_PRIVCFGR)

Address offset: 0x034

Reset value: 0x0000 0000

This register can be written only by a privileged access. It can be read by privileged or unprivileged access.

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 NSPRIV : PWR non-secure functions privilege configuration

This bit is set and reset by software.

It can be written only by privileged access, secure or non-secure.

0: Read and write to PWR non-secure functions can be done by privileged or unprivileged access.

1: Read and write to PWR non-secure functions can be done by privileged access only.

Bit 0 SPRIV : PWR secure functions privilege configuration

This bit is set and reset by software.

It can be written only by a secure privileged access.

0: Read and write to PWR secure functions can be done by privileged or unprivileged access.

1: Read and write to PWR secure functions can be done by privileged access only.

11.10.12 PWR status register (PWR_SR)

Address offset: 0x038

Power on reset value: 0x0000 0000

System reset value: 0b0000 0000 0000 0000 0000 0000 0000 0X00

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 STOP2F : Stop 2 mode peripherals power down flag

This bit is set by hardware when the device enters Stop 2 mode at the same time as the Stop 2 mode peripherals are powered down by hardware. It is cleared by software by writing 1 to the CSSF bit.

0: The device did not enter Stop 2 mode.

1: The device entered Stop 2 mode.

Bit 2 SBF : Standby flag

This bit is set by hardware when the device enters the Standby mode and the CPU restarts from its reset vector. It is cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset.

0: The device did not enter Standby mode.

1: The device entered Standby mode.

Bit 1 STOPF : Stop flag

This bit is set by hardware when the device enters a Stop or Standby mode at the same time as the sysclk has been set by hardware to select HSI16. It is cleared by software by writing 1 to the CSSF bit and by hardware when SBF is set.

0: The device did not enter any Stop mode.

1: The device entered a Stop mode.

Bit 0 CSSF : Clear Stop and Standby flags

Access can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

Writing 1 to this bit clears the STOPF, STOP2F, and SBF flags.

11.10.13 PWR supply voltage monitoring status register (PWR_SVMR)

Address offset: 0x03C

Reset value: 0x0000 8000

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 ACTVOS : VOS currently applied to V _CORE

This field provides the last VOS value.

0: Range 2 (lowest power)

1: Range 1 (highest frequency)

Bit 15 ACTVOSRDY : Voltage level ready for currently used VOS

0: V _CORE is above or below the current voltage scaling provided by ACTVOS.

1: V _CORE is equal to the current voltage scaling provided by ACTVOS

Note: Following a write to VOS, it takes one hclk clock cycle for ACTVOSRDY to be updated.

Bits 14:5 Reserved, must be kept at reset value.

Bit 4 PVDO : Programmable voltage detector output

0: V _DD is equal or above the PVD threshold selected by PVDLS[2:0].

1: V _DD is below the PVD threshold selected by PVDLS[2:0].

Bits 3:2 Reserved, must be kept at reset value.

Bit 1 REGS : Regulator selection

0: LDO selected

1: SMPS selected

Note that this bit is reserved on STM32WBA62/64xx devices.

Bit 0 Reserved, must be kept at reset value.

11.10.14 PWR wake-up status register (PWR_WUSR)

Address offset: 0x044

Reset value: 0x0000 0000 (reset value not affected by exit from Standby modes)

Access: 14 AHB clock cycles added compared to a standard AHB access

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 WUF8 : Wake-up and interrupt pending flag 8

This bit is set when a wake-up event is detected on WKUP8 pin. This bit is cleared by writing 1 in the CWUF8 bit of PWR_WUSCR when WUSEL8 \( \neq \) 11, or by hardware when WUPEN8 = 0.

When WUSEL8 = 11, this bit is cleared by hardware when all associated internal wake-up sources are cleared.

When WUSEL8 = 11, no WKUP interrupt is generated

Bit 6 WUF7 : Wake-up and interrupt pending flag 7

This bit is set when a wake-up event is detected on WKUP7 pin. This bit is cleared by writing 1 in the CWUF7 bit of PWR_WUSCR when WUSEL7 \( \neq \) 11, or by hardware when WUPEN7 = 0.

When WUSEL7 = 11, this bit is cleared by hardware when all associated internal wake-up sources are cleared. When WUSEL7 = 11, no WKUP interrupt is generated.

Bit 5 WUF6 : Wake-up and interrupt pending flag 6

This bit is set when a wake-up event is detected on WKUP6 pin. This bit is cleared by writing 1 in the CWUF6 bit of PWR_WUSCR when WUSEL6 \( \neq \) 11, or by hardware when WUPEN6 = 0.

When WUSEL6 = 11, this bit is cleared by hardware when all associated internal wake-up sources are cleared. When WUSEL6 = 11, no WKUP interrupt is generated

Bit 4 WUF5 : Wake-up and interrupt pending flag 5

This bit is set when a wake-up event is detected on WKUP5 pin. This bit is cleared by writing 1 in the CWUF5 bit of PWR_WUSCR or by hardware when WUPEN5 = 0.

Bit 3 WUF4 : Wake-up and interrupt pending flag 4

This bit is set when a wake-up event is detected on WKUP4 pin. This bit is cleared by writing 1 in the CWUF4 bit of PWR_WUSCR or by hardware when WUPEN4 = 0.

Bit 2 WUF3 : Wake-up and interrupt pending flag 3

This bit is set when a wake-up event is detected on WKUP3 pin. This bit is cleared by writing 1 in the CWUF3 bit of PWR_WUSCR or by hardware when WUPEN3 = 0.

Bit 1 WUF2 : Wake-up and interrupt pending flag 2

This bit is set when a wake-up event is detected on WKUP2 pin. This bit is cleared by writing 1 in the CWUF2 bit of PWR_WUSCR or by hardware when WUPEN2 = 0.

Bit 0 WUF1 : Wake-up and interrupt pending flag 1

This bit is set when a wake-up event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of PWR_WUSCR or by hardware when WUPEN1 = 0.

11.10.15 PWR wake-up status clear register (PWR_WUSCR)

Address offset: 0x048

Reset value: 0x0000 0000

Access: 14 AHB clock cycles added compared to a standard AHB access

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 CWUF8: Clear wake-up flag 8

Access can be secured by WUP8SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

Writing 1 to this bit clears the WUF8 flag in PWR_WUSR.

Bit 6 CWUF7: Clear wake-up flag 7

Access can be secured by WUP7SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

Writing 1 to this bit clears the WUF7 flag in PWR_WUSR.

Bit 5 CWUF6: Clear wake-up flag 6

Access can be secured by WUP6SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

Writing 1 to this bit clears the WUF6 flag in PWR_WUSR.

Bit 4 CWUF5: Clear wake-up flag 5

Access can be secured by WUP5SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

Writing 1 to this bit clears the WUF5 flag in PWR_WUSR.

Bit 3 CWUF4: Clear wake-up flag 4

Access can be secured by WUP4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

Writing 1 to this bit clears the WUF4 flag in PWR_WUSR.

Bit 2 CWUF3: Clear wake-up flag 3

Access can be secured by WUP3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

Writing 1 to this bit clears the WUF3 flag in PWR_WUSR.

Bit 1 CWUF2 : Clear wake-up flag 2

Access can be secured by WUP2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

Writing 1 to this bit clears the WUF2 flag in PWR_WUSR.

Bit 0 CWUF1 : Clear wake-up flag 1

Access can be secured by WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

Writing 1 to this bit clears the WUF1 flag in PWR_WUSR.

11.10.16 PWR port A Standby IO retention enable register (PWR_IORETENRA)

Address offset: 0x050

Reset value: 0x0000 0000 (reset value not affected by exit Standby mode)

Access: 14 AHB clock cycles added compared to a standard AHB access

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EN[15:0] : Port A Standby GPIO retention enable

Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

0: PAy Standby GPIO retention feature disabled.

1: PAy Standby GPIO retention feature enabled.

Note: Bits 4 and 3 are reserved on STM32WBA63xx devices, and bits 4 and 0 are reserved on STM32WBA64xx devices.

11.10.17 PWR port A Standby IO retention status register (PWR_IORETRA)

Address offset: 0x054

Reset value: 0x0000 0000 (reset value not affected by exit Standby mode)

Access: 14 AHB clock cycles added compared to a standard AHB access

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 RET[15:0] : Port A Standby GPIO retention active

Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

• 1: Set by hardware when Standby GPIO PAy is enabled in PWR_IORETENRA and Standby mode is entered. Standby GPIO retention PAy active.
• 0: Cleared by software, writing 0. Standby GPIO retention PAy disabled.

Note: Bits 4 and 3 are reserved on STM32WBA63xx devices, and bits 4 and 0 are reserved on STM32WBA64xx devices.

11.10.18 PWR port B Standby IO retention enable register (PWR_IORETENRB)

Address offset: 0x058

Reset value: 0x0000 0000 (reset value not affected by exit Standby mode)

Access: 14 AHB clock cycles added compared to a standard AHB access

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EN[15:0] : Port B Standby GPIO retention enable

Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

• 0: PBy Standby GPIO retention feature disabled.
• 1: PBy Standby GPIO retention feature enabled.

Note: Bits 13, 11 and 10 are reserved on STM32WBA63xx devices, and bits 9 and 7 to 5 are reserved on STM32WBA64xx devices.

11.10.19 PWR port B Standby IO retention status register (PWR_IORETRB)

Address offset: 0x05C

Reset value: 0x0000 0000 (reset value not affected by exit Standby mode)

Access: 14 AHB clock cycles added compared to a standard AHB access

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 RET[15:0] : Port B Standby GPIO retention active

Access can be secured by GPIOB SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

1: Set by hardware when Standby GPIO PBy is enabled in PWR_IORETENRB and Standby mode is entered. Standby GPIO retention PBy active.

0: Cleared by software, writing 0. Standby GPIO retention PBy disabled.

Note: Bits 13, 11 and 10 are reserved on STM32WBA63xx devices, and bits 9 and 7 to 5 are reserved on STM32WBA64xx devices.

11.10.20 PWR port C Standby IO retention enable register (PWR_IORETENRC)

Address offset: 0x060

Reset value: 0x0000 0000 (reset value not affected by exit Standby mode)

Access: 14 AHB clock cycles added compared to a standard AHB access

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EN[15:0] : Port C Standby GPIO retention enable

Access can be secured by GPIOC SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

0: PCy Standby GPIO retention feature disabled.

1: PCy Standby GPIO retention feature enabled.

Bits 12:0 are reserved on STM32WBA63/64xx devices.

11.10.21 PWR port C Standby IO retention status register (PWR_IORETRC)

Address offset: 0x064

Reset value: 0x0000 0000 (reset value not affected by exit Standby mode)

Access: 14 AHB clock cycles added compared to a standard AHB access

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 RET[15:0] : Port C Standby GPIO retention active

Access can be secured by GPIOC SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

1: Set by hardware when Standby GPIO PCy is enabled in PWR_IORETENRC and Standby mode is entered. Standby GPIO retention PCy active.

0: Cleared by software, writing 0. Standby GPIO retention PCy disabled.

Bits 12:0 are reserved on STM32WBA63/64xx devices.

11.10.22 PWR port D Standby IO retention enable register (PWR_IORETENRD)

Address offset: 0x068

Reset value: 0x0000 0000 (reset value not affected by exit Standby mode)

Access: 14 AHB clock cycles added compared to a standard AHB access

This register is reserved on STM32WBA63xx devices.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EN[15:0] : Port D Standby GPIO retention enable

Access can be secured by GPIOD SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secured with SPRIV or when non-secure with NSPRIV.

0: PDy Standby GPIO retention feature disabled.

1: PDy Standby GPIO retention feature enabled.

Note: Bits 15, 13:10, and 5:0 are reserved on STM32WBA64xx devices.

11.10.23 PWR port D Standby IO retention status register (PWR_IORETRD)

Address offset: 0x06C

Reset value: 0x0000 0000 (reset value not affected by exit Standby mode)

Access: 14 AHB clock cycles added compared to a standard AHB access

This register is reserved on STM32WBA63xx devices.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 RET[15:0] : Port D Standby GPIO retention active

Access can be secured by GPIOD SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secured with SPRIV or when non-secure with NSPRIV.

1: Set by hardware when Standby GPIO PDy is enabled in PWR_IORETENRD and Standby mode is entered. Standby GPIO retention PDy active.

0: Cleared by software, writing 0. Standby GPIO retention PDy disabled.

Note: Bits 15, 13:10, and 5:0 are reserved on STM32WBA64xx devices.

11.10.24 PWR port E Standby IO retention enable register (PWR_IORETENRE)

Address offset: 0x070

Reset value: 0x0000 0000 (reset value not affected by exit Standby mode)

Access: 14 AHB clock cycles added compared to a standard AHB access

This register is reserved on STM32WBA63/64xx devices.

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:0 EN[6:0] : Port E Standby GPIO retention enable

Access can be secured by GPIOE SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

0: PEy Standby GPIO retention feature disabled.

1: PEy Standby GPIO retention feature enabled.

11.10.25 PWR port E Standby IO retention status register (PWR_IORETRE)

Address offset: 0x074

Reset value: 0x0000 0000 (reset value not affected by exit Standby mode)

Access: 14 AHB clock cycles added compared to a standard AHB access

This register is reserved on STM32WBA63/64xx devices.

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:0 RET[6:0] : Port E Standby GPIO retention active

Access can be secured by GPIOE SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

1: Set by hardware when Standby GPIO PEy is enabled in PWR_IORETENRE and Standby mode is entered. Standby GPIO retention PEy active.

0: Cleared by software, writing 0. Standby GPIO retention PEy disabled.

11.10.26 PWR port G Standby IO retention enable register (PWR_IORETENRG)

Address offset: 0x080

Reset value: 0x0000 0000 (reset value not affected by exit Standby mode)

Access: 14 AHB clock cycles added compared to a standard AHB access

This register is reserved on STM32WBA63/64xx devices.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:2 EN[15:2] : Port G Standby GPIO retention enable

Access can be secured by GPIOG SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

0: PGy Standby GPIO retention feature disabled.

1: PGy Standby GPIO retention feature enabled.

Bits 1:0 Reserved, must be kept at reset value.

11.10.27 PWR port G Standby IO retention status register (PWR_IORETRG)

Address offset: 0x084

Reset value: 0x0000 0000 (reset value not affected by exit Standby mode)

Access: 14 AHB clock cycles added compared to a standard AHB access

This register is reserved on STM32WBA63/64xx devices.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:2 RET[15:2] : Port G Standby GPIO retention active

Access can be secured by GPIOG SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

1: Set by hardware when Standby GPIO PGy is enabled in PWR_IORETENRG and Standby mode is entered. Standby GPIO retention PGy active.

0: Cleared by software, writing 0. Standby GPIO retention PGy disabled.

Bits 1:0 Reserved, must be kept at reset value.

11.10.28 PWR port H Standby IO retention enable register (PWR_IORETENRH)

Address offset: 0x088

Reset value: 0x0000 0000 (reset value not affected by exit Standby mode)

Access: 14 AHB clock cycles added compared to a standard AHB access

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 EN3 : Port H Standby GPIO retention enable

Access can be secured by GPIOH SEC3. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

0: PHy Standby GPIO retention feature disabled.

1: PHy Standby GPIO retention feature enabled.

Bits 2:0 Reserved, must be kept at reset value.

11.10.29 PWR port H Standby IO retention status register (PWR_IORETRH)

Address offset: 0x08C

Reset value: 0x0000 0000 (reset value not affected by exit Standby mode)

Access: 14 AHB clock cycles added compared to a standard AHB access

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 RET3 : Port H Standby GPIO retention active

Access can be secured by GPIOH SEC3. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

1: Set by hardware when Standby GPIO PHY is enabled in PWR_IORETENRH and Standby mode is entered. Standby GPIO retention PHY active.

0: Cleared by software, writing 0. Standby GPIO retention PHY disabled.

Bits 2:0 Reserved, must be kept at reset value.

11.10.30 PWR 2.4 GHz RADIO status and control register (PWR_RADIOSCR)

Address offset: 0x100

Reset value: 0x0000 0000

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 REGPABYPEN : regulator REG_VDDHPA bypass enable.

This bit must be written only when the VDDHPA regulator is not used.

When REGPASEL = 0 this bit has no meaning.

When REGPASEL = 1, allow bypassing the REG_VDDHPA regulator when V _DDHPA 1.2 V is requested and input voltage is V _DD11 .

Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

0: 2.4 GHz RADIO PA supplied by REG_VDDHPA regulator output voltage.

1: 2.4 GHz RADIO PA 1.2 V supplied directly from internal V _DD11 (available only when REGPASEL = 1)

Note that this bit is reserved on STM32WBA62/64xx devices.

Bit 23 REGPASEL : regulator REG_VDDHPA input supply selection.

This bit must be written only when the VDDHPA regulator is not used.

Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

0: VDDRFP A pin selected as regulator REG_VDDHPA input supply.

1: regulator REG_VDDHPA input supply selection between V _{DDRFP A} and V _DD11 , dependent on requested regulated output voltage. see Table 79: 2.4 GHz RADIO supply configuration .

Must be set only when device SMPS is used to generate V _DD11 .

Note that this bit is reserved on STM32WBA62/64xx devices.

Bits 22:16 Reserved, must be kept at reset value.

Bit 15 REGPARDYVDDRFP A : Ready bit for V _DDHPA voltage level when selecting VDDRFP A input.

0: Not ready, V _DDHPA voltage level < REGPAVOS selected supply level

1: Ready, V _DDHPA voltage level ≥ REGPAVOS selected supply level

Note: REGPARDYVDDRFP A does not allow to detect correct V _DDHPA voltage level when requested to lower the level.

Bit 14 REGPARDYV11 : Ready bit for V _DDHPA voltage level when selecting V _DD11 input.

0: Not ready, V _DDHPA voltage level < REGPAVOS selected supply level

1: Ready, V _DDHPA voltage level ≥ REGPAVOS selected supply level

Note that this bit is reserved on STM32WBA62/64xx devices.

Note: REGPARDYV11 does not allow to detect correct V _DDHPA voltage level when requested to lower the level.

Bit 13 Reserved, must be kept at reset value.

Bits 12:8 RFVDDHPA[4:0] : 2.4 GHz RADIO VDDHPA control word.

Bits [3:0] see Table 78: PA output power table format for definition.

Bit [4] rf_event.

Bits 7:4 Reserved, must be kept at reset value.

Bit 3 ENCMODE : 2.4 GHz RADIO encryption function operating mode

0: 2.4 GHz RADIO encryption function disabled

1: 2.4 GHz RADIO encryption function enabled

Bit 2 PHYMODE : 2.4 GHz RADIO PHY operating mode

0: 2.4 GHz RADIO Sleep mode

1: 2.4 GHz RADIO Standby mode

Bits 1:0 MODE[1:0] : 2.4 GHz RADIO operating mode.

00: 2.4 GHz RADIO deep sleep mode

01: 2.4 GHz RADIO Sleep mode

1x: 2.4 GHz RADIO Active mode

11.10.31 PWR Stop 2 peripheral IOs retention register (PWR_S2RETR)

Address offset: 0x104

Reset value: 0x0000 0000

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 PTASR : PTA interface output signals state retention in Stop 2 mode active.

Access can be secured by GTZC_TZSC PTACONVSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

1: Set by hardware when Stop 2 mode PTA retention is enabled in PTASREN and Stop 2 mode is entered. Stop 2 PTA output signals retention active.

0: Cleared by software, writing 0. Stop 2 PTA output signals retention disabled.

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 PTASREN : PTA output signals Stop 2 mode retention enable

Access can be secured by GTZC_TZSC PTACONVSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with SPRIV or when non-secure with NSPRIV.

0: PTA output signals Stop 2 retention feature disabled.

1: PTA output signals Stop 2 retention feature enabled.

11.10.32 PWR register map

Table 100. PWR register map and reset values

Table 100. PWR register map and reset values (continued)