RM0515-STM32WBA6

This document is addressed to application developers. It provides complete information on how to use the STM32WBA62xx, STM32WBA63xx, STM32WBA64xx, and STM32WBA65xx (hereinafter referred to as STM32WBA6xxx) microcontrollers, including ST state-of-the-art patented technology, and featuring 2.4 GHz wireless radio, memory and peripherals.

The STM32WBA6xxx are microcontrollers based on a single core (Arm ® Cortex ® -M33), with the following memory configurations:

For information on the Arm ® Cortex ® -M33 core, refer to the Cortex ® -M33 Technical Reference Manual available on http://infocenter.arm.com .

Contents

1Documentation conventions . . . . .78
1.1General information . . . . .78
1.2List of abbreviations for registers . . . . .78
1.3Register reset value . . . . .78
1.4Glossary . . . . .79
2Memory and bus architecture . . . . .80
2.1System architecture . . . . .80
2.1.1CPU C-bus . . . . .81
2.1.2CPU S-bus . . . . .81
2.1.3GPDMA1-bus . . . . .81
2.1.4USB OTG_HS-bus . . . . .82
2.1.5Bus matrix . . . . .82
2.1.6AHB/APB bridges . . . . .82
2.2TrustZone ® security architecture . . . . .82
2.2.1Default TrustZone security state . . . . .84
2.2.2TrustZone peripheral classification . . . . .84
2.3Memory organization . . . . .87
2.3.1Introduction . . . . .87
2.3.2Memory map and register boundary addresses . . . . .88
2.3.3Embedded SRAM . . . . .93
2.3.4Flash memory overview . . . . .93
3System security . . . . .94
3.1Key security features . . . . .94
3.2Secure firmware install . . . . .95
3.3Secure boot . . . . .95
3.3.1Unique boot entry and BOOT_LOCK . . . . .95
3.3.2Immutable root of trust in system flash memory . . . . .96
3.4Secure firmware update . . . . .96
3.5Resource isolation using TrustZone . . . . .96
3.5.1TrustZone security architecture . . . . .97
3.5.2Armv8-M security extension of Cortex-M33 . . . . .97
3.5.3Memory and peripheral allocation using IDAU/SAU . . . . .98
3.5.4Memory and peripheral allocation using GTZC . . . . .100
3.5.5Managing security in TrustZone-aware peripherals . . . . .102
3.5.6Activating TrustZone security . . . . .109
3.5.7Deactivating TrustZone security . . . . .109
3.6Isolation of other resources . . . . .110
3.6.1Temporal isolation using secure hide protection (HDP) . . . . .110
3.6.2RSSLIB functions . . . . .110
3.6.3Resource isolation using Cortex privileged mode . . . . .111
3.7Secure execution . . . . .115
3.7.1Memory protection unit (MPU) . . . . .115
3.7.2Embedded flash memory write protection . . . . .115
3.7.3Tamper detection and response . . . . .116
3.8Secure storage . . . . .118
3.8.1Hardware secret key management . . . . .119
3.9Unique ID . . . . .119
3.10Crypto engines . . . . .119
3.10.1Crypto engines features . . . . .120
3.10.2Secure AES coprocessor (SAES) . . . . .121
3.11Product life cycle . . . . .121
3.11.1Life-cycle management with readout protection (RDP) . . . . .122
3.11.2Recommended option byte settings . . . . .125
3.12Access controlled debug . . . . .125
3.12.1Debug protection with readout protection (RDP) . . . . .125
3.13Software intellectual property protection and collaborative development . . . . .126
3.13.1Software intellectual property protection with RDP . . . . .126
3.13.2Other software intellectual property protections . . . . .127
4Boot modes . . . . .128
5Global TrustZone controller (GTZC) . . . . .130
5.1Introduction . . . . .130
5.2GTZC main features . . . . .130
5.3GTZC implementation . . . . .132
5.4GTZC functional description . . . . .133
5.4.1GTZC block diagram . . . . .133
5.8.3GTZC1 MPCBB security configuration for superblock n register (GTZC1_MPCBB_SECCFGGRn) .....173
5.8.4GTZC1 MPCBB privileged configuration for superblock n register (GTZC1_MPCBB_PRIVCFGGRn) .....173
5.8.5GTZC1 MPCBB1 and MPCBB2 register map .....175
5.8.6GTZC1 MPCBB6 register map .....177
6RAMs configuration controller (RAMCFG) .....178
6.1Introduction .....178
6.2RAMCFG main features .....178
6.3RAMCFG functional description .....178
6.3.1Internal SRAMs features .....178
6.3.2Internal SRAM parity .....179
6.3.3Internal SRAM write protection .....180
6.3.4Internal SRAM read access latency .....180
6.3.5Internal SRAM erase .....181
6.4RAMCFG low-power modes .....181
6.5RAMCFG interrupts .....181
6.6RAMCFG registers .....182
6.6.1RAMCFG SRAM1 control register (RAMCFG_M1CR) .....182
6.6.2RAMCFG SRAM1 interrupt status register (RAMCFG_M1ISR) .....182
6.6.3RAMCFG SRAMx erase key register (RAMCFG_MxERKEYR) .....183
6.6.4RAMCFG SRAM2 control register (RAMCFG_M2CR) .....183
6.6.5RAMCFG SRAM2 interrupt enable register (RAMCFG_M2IER) .....184
6.6.6RAMCFG SRAM2 interrupt status register (RAMCFG_M2ISR) .....185
6.6.7RAMCFG SRAM2 parity error address register (RAMCFG_M2PEAR) .....185
6.6.8RAMCFG SRAM2 interrupt clear register (RAMCFG_M2ICR) .....186
6.6.9RAMCFG SRAM2 write protection register 1 (RAMCFG_M2WPR1) .....186
6.6.10RAMCFG SRAM2 write protection register 2 (RAMCFG_M2WPR2) .....187
6.6.11RAMCFG register map .....188
7Embedded flash memory (FLASH) .....189
7.1Introduction .....189
7.2FLASH main features .....189
7.3FLASH functional description .....190
7.9.6FLASH bank 2 power-down key register (FLASH_PDKEY2R) . . . . .233
7.9.7FLASH status register (FLASH_NSSR) . . . . .233
7.9.8FLASH secure status register (FLASH_SECSR) . . . . .235
7.9.9FLASH control register (FLASH_NSCR1) . . . . .236
7.9.10FLASH secure control register (FLASH_SECCR1) . . . . .238
7.9.11FLASH ECC register (FLASH_ECCR) . . . . .239
7.9.12FLASH operation status register (FLASH_OPSR) . . . . .240
7.9.13FLASH control 2 register (FLASH_NSCR2) . . . . .242
7.9.14FLASH secure control 2 register (FLASH_SECCR2) . . . . .242
7.9.15FLASH option register (FLASH_OPTR) . . . . .243
7.9.16FLASH boot address 0 register (FLASH_NSBOOTADD0R) . . . . .245
7.9.17FLASH boot address 1 register (FLASH_NSBOOTADD1R) . . . . .246
7.9.18FLASH secure boot address 0 register (FLASH_SECBOOTADD0R) . . . . .246
7.9.19FLASH bank 1 secure watermark register 1 (FLASH_SECWM1R1) . . . . .247
7.9.20FLASH bank 1 secure watermark register 2 (FLASH_SECWM1R2) . . . . .248
7.9.21FLASH WRP bank 1 area A address register (FLASH_WRP1AR) . . . . .248
7.9.22FLASH WRP bank 1 area B address register (FLASH_WRP1BR) . . . . .249
7.9.23FLASH bank 2 secure watermark register 1 (FLASH_SECWM2R1) . . . . .250
7.9.24FLASH bank 2 secure watermark register 2 (FLASH_SECWM2R2) . . . . .250
7.9.25FLASH WRP bank 2 area A address register (FLASH_WRP2AR) . . . . .251
7.9.26FLASH WRP bank 2 area B address register (FLASH_WRP2BR) . . . . .251
7.9.27FLASH OEM1 key register 1 (FLASH_OEM1KEYR1) . . . . .252
7.9.28FLASH OEM1 key register 2 (FLASH_OEM1KEYR2) . . . . .253
7.9.29FLASH OEM2 key register 1 (FLASH_OEM2KEYR1) . . . . .253
7.9.30FLASH OEM2 key register 2 (FLASH_OEM2KEYR2) . . . . .254
7.9.31FLASH bank 1 secure block based register x (FLASH_SECB1Rx) . . . . .254
7.9.32FLASH bank 2 secure block based register x (FLASH_SECB2Rx) . . . . .255
7.9.33FLASH secure HDP control register (FLASH_SECHDPCR) . . . . .255
7.9.34FLASH privilege configuration register (FLASH_PRIVCFGR) . . . . .256
7.9.35FLASH bank 1 privilege block based register x
(FLASH_PRIVB1Rx) . . . . .		257
7.9.36FLASH bank 2 privilege block based register x
(FLASH_PRIVB2Rx) . . . . .		257
7.9.37FLASH register map . . . . .258
8Instruction cache (ICACHE) . . . . .263
8.1ICACHE introduction . . . . .263
8.2ICACHE main features . . . . .263
8.3ICACHE implementation . . . . .264
8.4ICACHE functional description . . . . .264
8.4.1ICACHE block diagram . . . . .265
8.4.2ICACHE reset and clocks . . . . .265
8.4.3ICACHE TAG memory . . . . .266
8.4.4Direct-mapped ICACHE (1-way cache) . . . . .267
8.4.5ICACHE enable . . . . .268
8.4.6Cacheable and noncacheable traffic . . . . .268
8.4.7Address remapping . . . . .269
8.4.8Cacheable accesses . . . . .271
8.4.9Dual-master cache . . . . .272
8.4.10ICACHE security . . . . .272
8.4.11ICACHE maintenance . . . . .272
8.4.12ICACHE performance monitoring . . . . .273
8.4.13ICACHE boot . . . . .273
8.5ICACHE low-power modes . . . . .273
8.6ICACHE error management and interrupts . . . . .274
8.7ICACHE registers . . . . .274
8.7.1ICACHE control register (ICACHE_CR) . . . . .274
8.7.2ICACHE status register (ICACHE_SR) . . . . .275
8.7.3ICACHE interrupt enable register (ICACHE_IER) . . . . .276
8.7.4ICACHE flag clear register (ICACHE_FCR) . . . . .276
8.7.5ICACHE hit monitor register (ICACHE_HMONR) . . . . .277
8.7.6ICACHE miss monitor register (ICACHE_MMONR) . . . . .277
8.7.7ICACHE region x configuration register (ICACHE_CRRx) . . . . .277
8.7.8ICACHE register map . . . . .278
9Radio system . . . . .280
9.1Introduction . . . . .280
9.2Main features . . . . .280
9.32.4 GHz RADIO implementation . . . . .281
9.4Functional description . . . . .281
9.4.1Block diagram . . . . .281
9.4.2Pins and internal signals . . . . .281
9.4.3Transmit output power . . . . .282
9.4.4Bluetooth AoA and AoD .....283
9.4.5RXTX data SRAM access .....283
9.5Low-power modes .....283
10PTA converter (PTACONV) .....285
10.1PTACONV introduction .....285
10.2PTACONV main features .....285
10.3PTACONV functional description .....285
10.3.1PTACONV block diagram .....286
10.3.2PTACONV pins and internal signals .....287
10.4PTACONV in low-power modes .....287
10.5PTACONV protocols .....288
10.5.1PTACONV interface with the 2.4 GHz RADIO .....291
10.6PTACONV registers .....292
10.6.1PTACONV active control register (PTACONV_ACTCR) .....292
10.6.2PTACONV priority control register (PTACONV_PRICR) .....293
10.6.3PTACONV control register (PTACONV_CR) .....293
10.6.4PTACONV register map .....295
11Power control (PWR) .....296
11.1Introduction .....296
11.2PWR main features .....296
11.3PWR pins and internal signals .....297
11.4PWR power supplies and supply domains .....299
11.4.1External power supplies .....300
11.4.2Application power supply schemes .....301
11.4.3Power-up and power-down power sequences .....302
11.4.4Independent analog peripherals supply .....303
11.4.5Independent GPIOG[15:2] I/O supply .....303
11.4.6Independent USB transceiver supply .....303
11.4.7USB OTG power management .....304
11.4.8Radio peripherals supply .....304
11.4.9Backup domain .....305
11.4.10Internal regulators .....305
11.5PWR system supply voltage regulation .....305
11.5.1SMPS and LDO embedded regulators .....305
11.5.2LDO and SMPS versus reset, voltage scaling, and low-power modes306
11.5.3LDO and SMPS step-down converter fast startup306
11.5.4Dynamic voltage scaling management306
11.5.5Deep sleep 2.4 GHz RADIO PA regulator307
11.6PWR power supply supervision308
11.6.1Brownout reset (BOR)308
11.6.2Programmable voltage detector (PVD)309
11.7PWR power management311
11.7.1PWR power modes311
11.7.2PWR background autonomous mode (BAM)318
11.7.3PWR Run mode320
11.7.4PWR low-power modes321
11.7.5PWR Sleep mode322
11.7.6PWR Stop 0 mode323
11.7.7PWR Stop 1 mode327
11.7.8PWR Stop 2 mode328
11.7.9PWR Standby mode330
11.7.10Power modes output pins333
11.8PWR security and privileged protection333
11.8.1PWR security protection333
11.8.2PWR privileged protection335
11.9PWR interrupts336
11.10PWR registers337
11.10.1PWR control register 1 (PWR_CR1)337
11.10.2PWR control register 2 (PWR_CR2)338
11.10.3PWR control register 3 (PWR_CR3)339
11.10.4PWR voltage scaling register (PWR_VOSR)340
11.10.5PWR supply voltage monitoring control register (PWR_SVMCR)342
11.10.6PWR wake-up control register 1 (PWR_WUCR1)343
11.10.7PWR wake-up control register 2 (PWR_WUCR2)344
11.10.8PWR wake-up control register 3 (PWR_WUCR3)345
11.10.9PWR disable Backup domain register (PWR_DBPR)347
11.10.10PWR security configuration register (PWR_SECCFGR)348
11.10.11PWR privilege control register (PWR_PRIVCFGR)349
11.10.12PWR status register (PWR_SR)350
11.10.13PWR supply voltage monitoring status register (PWR_SVMSR)351
11.10.14PWR wake-up status register (PWR_WUSR) . . . . .351
11.10.15PWR wake-up status clear register (PWR_WUSCR) . . . . .353
11.10.16PWR port A Standby IO retention enable register
(PWR_IORETENRA) . . . . .		354
11.10.17PWR port A Standby IO retention status register (PWR_IORETRA) . . .354
11.10.18PWR port B Standby IO retention enable register
(PWR_IORETENRB) . . . . .		355
11.10.19PWR port B Standby IO retention status register (PWR_IORETRB) . . .355
11.10.20PWR port C Standby IO retention enable register
(PWR_IORETENRC) . . . . .		356
11.10.21PWR port C Standby IO retention status register (PWR_IORETRC) . . .356
11.10.22PWR port D Standby IO retention enable register
(PWR_IORETENRD) . . . . .		357
11.10.23PWR port D Standby IO retention status register . . . (PWR_IORETRD)358
11.10.24PWR port E Standby IO retention enable register
(PWR_IORETENRE) . . . . .		358
11.10.25PWR port E Standby IO retention status register (PWR_IORETRE) . . .359
11.10.26PWR port G Standby IO retention enable register
(PWR_IORETENRG) . . . . .		359
11.10.27PWR port G Standby IO retention status register (PWR_IORETRG) . . .360
11.10.28PWR port H Standby IO retention enable register
(PWR_IORETENRH) . . . . .		360
11.10.29PWR port H Standby IO retention status register (PWR_IORETRH) . . .361
11.10.30PWR 2.4 GHz RADIO status and control register
(PWR_RADIOSCR) . . . . .		361
11.10.31PWR Stop 2 peripheral IOs retention register (PWR_S2RETR) . . . . .363
11.10.32PWR register map . . . . .364
12Reset and clock control (RCC) . . . . .367
12.1Introduction . . . . .367
12.2RCC pins and internal signals . . . . .367
12.3RCC reset functional description . . . . .367
12.3.1Power reset . . . . .367
12.3.2System reset . . . . .368
12.3.3Backup domain reset . . . . .369
12.3.4Individual peripheral reset . . . . .369
12.3.5CPU reset . . . . .369
12.4RCC clocks functional description . . . . .369
12.4.1HSE32 clock with trimming . . . . .371
12.4.2HSI16 clock . . . . .373
12.4.3PLL1 . . . . .374
12.4.4LSE clock . . . . .375
12.4.5LSI clock . . . . .377
12.4.6System clock (SYSCLK) selection . . . . .378
12.4.7Clock source frequency versus voltage scaling . . . . .380
12.4.8HSE32 clock security system (HSECSS) . . . . .380
12.4.9LSE clock security system on (LSECSS) . . . . .380
12.4.10ADC kernel clock . . . . .381
12.4.11RTC and TAMP kernel clock . . . . .381
12.4.122.4 GHz RADIO bus clock . . . . .382
12.4.132.4 GHz RADIO kernel clocks . . . . .382
12.4.14Timer kernel clock . . . . .383
12.4.15Independent watchdog kernel clock . . . . .383
12.4.16USB OTG_HS clock . . . . .384
12.4.17SysTick calibration value register . . . . .384
12.4.18Clock-out capability . . . . .384
12.4.19Internal/external clock measurement . . . . .385
12.4.20Audio synchronization . . . . .386
12.4.21Peripherals clock gating and autonomous mode . . . . .388
12.5RCC security and privilege functional description . . . . .390
12.5.1RCC TrustZone® security protection modes . . . . .390
12.5.2RCC privilege protection modes . . . . .392
12.6RCC low-power modes . . . . .393
12.7RCC interrupts . . . . .394
12.8RCC registers . . . . .395
12.8.1RCC clock control register (RCC_CR) . . . . .395
12.8.2RCC internal clock sources calibration register 3 (RCC_ICSCR3) . . . . .397
12.8.3RCC clock configuration register 1 (RCC_CFGR1) . . . . .398
12.8.4RCC clock configuration register 2 (RCC_CFGR2) . . . . .399
12.8.5RCC clock configuration register 3 (RCC_CFGR3) . . . . .400
12.8.6RCC PLL1 configuration register (RCC_PLL1CFGR) . . . . .401
12.8.7RCC PLL1 dividers register (RCC_PLL1DIVR) . . . . .403
12.8.8RCC PLL1 fractional divider register (RCC_PLL1FRACR) . . . . .404
12.8.9RCC clock interrupt enable register (RCC_CIER) . . . . .405
12.8.10RCC clock interrupt flag register (RCC_CIFR) . . . . .406
12.8.11RCC clock interrupt clear register (RCC_CICR) . . . . .408
12.8.12RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . .410
12.8.13RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . .410
12.8.14RCC AHB4 peripheral reset register (RCC_AHB4RSTR) . . . . .413
12.8.15RCC AHB5 peripheral reset register (RCC_AHB5RSTR) . . . . .414
12.8.16RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . .414
12.8.17RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . .416
12.8.18RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .417
12.8.19RCC APB7 peripheral reset register (RCC_APB7RSTR) . . . . .418
12.8.20RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . .420
12.8.21RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . .422
12.8.22RCC AHB4 peripheral clock enable register (RCC_AHB4ENR) . . . . .425
12.8.23RCC AHB5 peripheral clock enable register (RCC_AHB5ENR) . . . . .426
12.8.24RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . . .427
12.8.25RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . . .429
12.8.26RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .430
12.8.27RCC APB7 peripheral clock enable register (RCC_APB7ENR) . . . . .431
12.8.28RCC AHB1 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB1SMENR) . . . . .		433
12.8.29RCC AHB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB2SMENR) . . . . .		435
12.8.30RCC AHB4 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB4SMENR) . . . . .		439
12.8.31RCC AHB5 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB5SMENR) . . . . .		439
12.8.32RCC APB1 peripheral clocks enable in Sleep and Stop modes
register 1 (RCC_APB1SMENR1) . . . . .		440
12.8.33RCC APB1 peripheral clocks enable in Sleep and Stop modes
register 2 (RCC_APB1SMENR2) . . . . .		443
12.8.34RCC APB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_APB2SMENR) . . . . .		444
12.8.35RCC APB7 peripheral clock enable in Sleep and Stop modes register
(RCC_APB7SMENR) . . . . .		445
12.8.36RCC peripherals independent clock configuration register 1
(RCC_CCIPR1) . . . . .		448
12.8.37RCC peripherals independent clock configuration register 2
(RCC_CCIPR2) . . . . .		451
12.8.38RCC peripherals independent clock configuration register 3
(RCC_CCIPR3) . . . . .		452
12.8.39RCC Backup domain control register (RCC_BDCR1) . . . . .454
12.8.40RCC control/status register (RCC_CSR) . . . . .458
12.8.41RCC Backup domain control register (RCC_BDCR2) . . . . .460
12.8.42RCC secure configuration register (RCC_SECCFGR) . . . . .461
12.8.43RCC privilege configuration register (RCC_PRIVCFGR) . . . . .462
12.8.44RCC audio synchronization control register (RCC_ASCR) . . . . .463
12.8.45RCC audio synchronization interrupt enable register (RCC_ASIER) . . . . .464
12.8.46RCC audio synchronization status register (RCC_ASSR) . . . . .464
12.8.47RCC audio synchronization counter register (RCC_ASCNTR) . . . . .465
12.8.48RCC audio synchronization auto-reload register (RCC_ASARR) . . . . .465
12.8.49RCC audio synchronization capture register (RCC_ASCAR) . . . . .466
12.8.50RCC audio synchronization compare register (RCC_ASCOR) . . . . .466
12.8.51RCC clock configuration register 2 (RCC_CFGR4) . . . . .467
12.8.52RCC RADIO peripheral clock enable register (RCC_RADIOENR) . . . . .468
12.8.53RCC external clock sources calibration register 1(RCC_ECSCR1) . . . . .469
12.8.54RCC register map . . . . .470
13Hardware semaphore (HSEM) . . . . .476
13.1HSEM introduction . . . . .476
13.2HSEM main features . . . . .476
13.3Functional description . . . . .477
13.3.1HSEM block diagram . . . . .477
13.3.2HSEM internal signals . . . . .477
13.3.3HSEM lock procedures . . . . .477
13.3.4HSEM write/read/read lock register address . . . . .479
13.3.5HSEM unlock procedures . . . . .479
13.3.6HSEM LOCKID semaphore clear . . . . .480
13.3.7HSEM interrupts . . . . .480
13.3.8Semaphore attributes . . . . .482
13.4HSEM registers . . . . .484
13.4.1HSEM register semaphore x (HSEM_Rx) . . . . .484
13.4.2HSEM read lock register semaphore x (HSEM_RLRx) . . . . .486
13.4.3HSEM nonsecure interrupt enable register (HSEM_IER) . . . . .487
13.4.4HSEM nonsecure interrupt clear register (HSEM_ICR) . . . . .488
13.4.5HSEM nonsecure interrupt status register (HSEM_ISR) . . . . .488
13.4.6HSEM nonsecure interrupt status register (HSEM_MISR) . . . . .489
13.4.7HSEM secure interrupt enable register (HSEM_SIER) . . . . .490
13.4.8HSEM secure interrupt clear register (HSEM_SICR) . . . . .490
13.4.9HSEM secure interrupt status register (HSEM_SISR) . . . . .491
13.4.10HSEM secure masked interrupt status register (HSEM_SMISR) . . . .492
13.4.11HSEM security configuration register (HSEM_SECCFGR) . . . . .492
13.4.12HSEM privilege configuration register (HSEM_PRIVCFGR) . . . . .493
13.4.13HSEM clear register (HSEM_CR) . . . . .494
13.4.14HSEM clear semaphore key register (HSEM_KEYR) . . . . .494
13.4.15HSEM register map . . . . .496
14General-purpose I/Os (GPIO) . . . . .498
14.1GPIO introduction . . . . .498
14.2GPIO main features . . . . .498
14.3GPIO implementation . . . . .498
14.4GPIO functional description . . . . .499
14.4.1GPIO general-purpose I/O . . . . .500
14.4.2GPIO pin alternate function multiplexer and mapping . . . . .501
14.4.3GPIO port additional function multiplexer . . . . .501
14.4.4GPIO port control registers . . . . .502
14.4.5GPIO port data registers . . . . .502
14.4.6GPIO data bitwise handling . . . . .502
14.4.7GPIO locking mechanism . . . . .502
14.4.8GPIO alternate function input/output . . . . .503
14.4.9GPIO external interrupt/wake-up lines . . . . .503
14.4.10GPIO input configuration . . . . .503
14.4.11GPIO output configuration . . . . .504
14.4.12GPIO alternate function configuration . . . . .504
14.4.13GPIO analog configuration . . . . .505
14.4.14High-speed low-voltage mode (HSLV) . . . . .505
14.4.15GPIO compensation cell . . . . .506
14.4.16GPIO standby retention . . . . .506
14.4.17GPIO using the LSE oscillator pins as GPIOs . . . . .506
14.4.18GPIO using GPIO pins with RTC . . . . .506
14.4.19GPIO using PH3 as GPIO . . . . .506
14.4.20GPIO using PD6 and PD7 . . . . .506
14.4.21GPIO TrustZone ® security . . . . .507
14.4.22GPIO privileged and unprivileged modes . . . . .508
14.5GPIO port A to B registers . . . . .509
14.5.1GPIO port x mode register (GPIOx_MODER) (x = A to B) . . . . .509
14.5.2GPIO port x output type register (GPIOx_OTYPER) (x = A to B) . . . . .509
14.5.3GPIO port x output speed register (GPIOx_OSPEEDR) (x = A to B) . . .510
14.5.4GPIO port x pull-up/pull-down register (GPIOx_PUPDR) (x = A to B) . . .511
14.5.5GPIO port x input data register (GPIOx_IDR) (x = A to B) . . . . .512
14.5.6GPIO port x output data register (GPIOx_ODR) (x = A to B) . . . . .512
14.5.7GPIO port x bit set/reset register (GPIOx_BSRR) (x = A to B) . . . . .512
14.5.8GPIO port x configuration lock register (GPIOx_LCKR) (x = A to B) . . .513
14.5.9GPIO port x alternate function low register (GPIOx_AFRL)
(x = A to B) . . . . .		514
14.5.10GPIO port x alternate function high register (GPIOx_AFRH)
(x = A to B) . . . . .		515
14.5.11GPIO port x bit reset register (GPIOx_BRR) (x = A to B) . . . . .516
14.5.12GPIO port x secure configuration register (GPIOx_SECCFGR)
(x = A to B) . . . . .		517
14.5.13GPIOA to B register map . . . . .518
14.6GPIO port C registers . . . . .520
14.6.1GPIO port C mode register (GPIOC_MODER) . . . . .520
14.6.2GPIO port C output type register (GPIOC_OTYPER) . . . . .520
14.6.3GPIO port C output speed register (GPIOC_OSPEEDR) . . . . .521
14.6.4GPIO port C pull-up/pull-down register (GPIOC_PUPDR) . . . . .522
14.6.5GPIO port C input data register (GPIOC_IDR) . . . . .523
14.6.6GPIO port C output data register (GPIOC_ODR) . . . . .523
14.6.7GPIO port C bit set/reset register (GPIOC_BSRR) . . . . .523
14.6.8GPIO port C configuration lock register (GPIOC_LCKR) . . . . .524
14.6.9GPIO port C alternate function low register (GPIOC_AFRL) . . . . .525
14.6.10GPIO port C alternate function high register (GPIOC_AFRH) . . . . .526
14.6.11GPIO port C bit reset register (GPIOC_BRR) . . . . .527
14.6.12GPIO port C secure configuration register (GPIOC_SECCFGR) . . . . .528
14.6.13GPIOC register map . . . . .529
14.7GPIO port D registers . . . . .530
14.7.1GPIO port D mode register (GPIOD_MODER) . . . . .530
14.7.2GPIO port D output type register (GPIOD_OTYPER) . . . . .530
14.7.3GPIO port D output speed register (GPIOD_OSPEEDR) . . . . .531
14.7.4GPIO port D pull-up/pull-down register (GPIOD_PUPDR) . . . . .532
14.7.5GPIO port D input data register (GPIOD_IDR) . . . . .533
14.7.6GPIO port D output data register (GPIOD_ODR) . . . . .533
14.7.7GPIO port D bit set/reset register (GPIOD_BSRR) . . . . .533
14.7.8GPIO port D configuration lock register (GPIOD_LCKR) . . . . .534
14.7.9GPIO port D alternate function low register (GPIOD_AFRL) . . . . .535
14.7.10GPIO port D alternate function high register (GPIO_D_AFRH) . . . . .536
14.7.11GPIO port D bit reset register (GPIO_D_BRR) . . . . .537
14.7.12GPIO port D high-speed low-voltage register (GPIO_D_HSLVR) . . . . .538
14.7.13GPIO port D secure configuration register (GPIO_D_SECCFGR) . . . . .538
14.7.14GPIO_D register map . . . . .539
14.8GPIO port E registers . . . . .540
14.8.1GPIO port E mode register (GPIO_E_MODER) . . . . .540
14.8.2GPIO port E output type register (GPIO_E_OTYPER) . . . . .540
14.8.3GPIO port E output speed register (GPIO_E_OSPEEDR) . . . . .541
14.8.4GPIO port E pull-up/pull-down register (GPIO_E_PUPDR) . . . . .541
14.8.5GPIO port E input data register (GPIO_E_IDR) . . . . .542
14.8.6GPIO port E output data register (GPIO_E_ODR) . . . . .542
14.8.7GPIO port E bit set/reset register (GPIO_E_BSRR) . . . . .543
14.8.8GPIO port E configuration lock register (GPIO_E_LCKR) . . . . .543
14.8.9GPIO port E alternate function low register (GPIO_E_AFRL) . . . . .544
14.8.10GPIO port E bit reset register (GPIO_E_BRR) . . . . .545
14.8.11GPIO port E high-speed low-voltage register (GPIO_E_HSLVR) . . . . .546
14.8.12GPIO port E secure configuration register (GPIO_E_SECCFGR) . . . . .546
14.8.13GPIO_E register map . . . . .548
14.9GPIO port G registers . . . . .549
14.9.1GPIO port G mode register (GPIO_G_MODER) . . . . .549
14.9.2GPIO port G output type register (GPIO_G_OTYPER) . . . . .549
14.9.3GPIO port G output speed register (GPIO_G_OSPEEDR) . . . . .550
14.9.4GPIO port G pull-up/pull-down register (GPIO_G_PUPDR) . . . . .551
14.9.5GPIO port G input data register (GPIO_G_IDR) . . . . .552
14.9.6GPIO port G output data register (GPIO_G_ODR) . . . . .552
14.9.7GPIO port G bit set/reset register (GPIO_G_BSRR) . . . . .552
14.9.8GPIO port G configuration lock register (GPIO_G_LCKR) . . . . .553
14.9.9GPIO port G alternate function low register (GPIO_G_AFRL) . . . . .554
14.9.10GPIO port G alternate function high register (GPIO_G_AFRH) . . . . .555
14.9.11GPIO port G bit reset register (GPIO_G_BRR) . . . . .556
14.9.12GPIO port G high-speed low-voltage register (GPIO_G_HSLVR) . . . . .557
14.9.13GPIO port G secure configuration register (GPIO_G_SECCFGR) . . . . .557
14.9.14GPIO_G register map . . . . .559
14.10GPIO port H registers . . . . .560
14.10.1GPIO port H mode register (GPIO_H_MODER) . . . . .560
14.10.2GPIO port H output type register (GPIO_H_OTYPER) . . . . .560
14.10.3GPIO port H output speed register (GPIOH_OSPEEDR)560
14.10.4GPIO port H pull-up/pull-down register (GPIOH_PUPDR)561
14.10.5GPIO port H input data register (GPIOH_IDR)562
14.10.6GPIO port H output data register (GPIOH_ODR)562
14.10.7GPIO port H bit set/reset register (GPIOH_BSRR)563
14.10.8GPIO port H configuration lock register (GPIOH_LCKR)563
14.10.9GPIO port H alternate function low register (GPIOH_AFRL)564
14.10.10GPIO port H bit reset register (GPIOH_BRR)565
14.10.11GPIO port H secure configuration register (GPIOH_SECCFGR)566
14.10.12GPIOH register map567
15System configuration controller (SYSCFG)568
15.1SYSCFG main features568
15.2SYSCFG functional description568
15.2.1I/O compensation cell management568
15.2.2Configuring the USB OTG_HS PHY569
15.2.3SYSCFG TrustZone® security and privilege570
15.3SYSCFG registers572
15.3.1SYSCFG secure configuration register (SYSCFG_SECCFGR)572
15.3.2SYSCFG configuration register 1 (SYSCFG_CFGR1)572
15.3.3SYSCFG FPU interrupt mask register (SYSCFG_FPUIMR)574
15.3.4SYSCFG CPU nonsecure lock register (SYSCFG_CNSLCKR)575
15.3.5SYSCFG CPU secure lock register (SYSCFG_CSLCKR)575
15.3.6SYSCFG configuration register 2 (SYSCFG_CFGR2)576
15.3.7SYSCFG memory erase status register (SYSCFG MESR)577
15.3.8SYSCFG compensation cell control/status register
(SYSCFG_CCCSR)		578
15.3.9SYSCFG compensation cell value register (SYSCFG_CCVR)579
15.3.10SYSCFG compensation cell code register (SYSCFG_CCCR)580
15.3.11SYSCFG RSS command register (SYSCFG_RSSCMDR)581
15.3.12SYSCFG USB OTG_HS PHY control register
(SYSCFG_OTGHSPHYCR)		581
15.3.13SYSCFG USB OTG_HS PHY tune register 2
(SYSCFG_OTGHSPHYTUNER2)		582
15.3.14SYSCFG register map584
16Peripherals interconnect matrix586
16.1Introduction586
16.2Connection summary . . . . .586
16.3Interconnection details . . . . .587
16.3.1Master to slave interconnection for timers . . . . .587
16.3.2Triggers to ADC4 . . . . .588
16.3.3ADC4 analog watchdog as trigger to timers . . . . .588
16.3.4Clock sources to timers . . . . .589
16.3.5Triggers to low-power timers . . . . .590
16.3.6USB OTG_HS trigger to timer . . . . .590
16.3.7Internal analog signals to analog peripheral . . . . .591
16.3.8System errors as break signals to timers . . . . .591
16.3.9Triggers to GPDMA1 . . . . .591
16.3.10Internal tamper sources . . . . .592
16.3.11Triggers to communication peripherals . . . . .592
16.3.12Output from tamper . . . . .593
16.3.13Timers generating IRTIM signal . . . . .593
16.3.14From encryption keys to AES/SAES . . . . .594
16.3.15Blanking sources to comparators . . . . .594
16.3.16Comparators as inputs, triggers or break signals to timers . . . . .594
17General purpose direct memory access controller (GPDMA) . . . . .596
17.1GPDMA introduction . . . . .596
17.2GPDMA main features . . . . .596
17.3GPDMA implementation . . . . .597
17.3.1GPDMA channels . . . . .597
17.3.2GPDMA autonomous mode in low-power modes . . . . .598
17.3.3GPDMA requests . . . . .598
17.3.4GPDMA block requests . . . . .600
17.3.5GPDMA triggers . . . . .601
17.4GPDMA functional description . . . . .602
17.4.1GPDMA block diagram . . . . .602
17.4.2GPDMA channel state and direct programming without any linked-list . . . . .602
17.4.3GPDMA channel suspend and resume . . . . .603
17.4.4GPDMA channel abort and restart . . . . .604
17.4.5GPDMA linked-list data structure . . . . .605
17.4.6Linked-list item transfer execution . . . . .608
17.4.7GPDMA channel state and linked-list programming
in run-to-completion mode . . . . .		608

18 Nested vectored interrupt controller (NVIC) . . . . . 661

19Extended interrupts and event controller (EXTI) . . . . .665
19.1EXTI main features . . . . .665
19.2EXTI block diagram . . . . .665
19.2.1EXTI connections between peripherals and CPU . . . . .667
19.2.2EXTI interrupt/event mapping . . . . .667
19.3EXTI functional description . . . . .668
19.3.1EXTI configurable event input wake-up . . . . .668
19.3.2EXTI mux selection . . . . .669
19.4EXTI functional behavior . . . . .670
19.5EXTI event protection . . . . .670
19.5.1EXTI security protection . . . . .671
19.5.2EXTI privilege protection . . . . .671
19.6EXTI registers . . . . .672
19.6.1EXTI rising trigger selection register (EXTI_RTSR1) . . . . .672
19.6.2EXTI falling trigger selection register (EXTI_FTSR1) . . . . .673
19.6.3EXTI software interrupt event register (EXTI_SWIER1) . . . . .673
19.6.4EXTI rising edge pending register (EXTI_RPR1) . . . . .674
19.6.5EXTI falling edge pending register (EXTI_FPR1) . . . . .675
19.6.6EXTI security configuration register (EXTI_SECCFGR1) . . . . .675
19.6.7EXTI privilege configuration register (EXTI_PRIVCFGR1) . . . . .676
19.6.8EXTI external interrupt selection register (EXTI_EXTICR1) . . . . .676
19.6.9EXTI external interrupt selection register (EXTI_EXTICR2) . . . . .678
19.6.10EXTI external interrupt selection register (EXTI_EXTICR3) . . . . .680
19.6.11EXTI external interrupt selection register (EXTI_EXTICR4) . . . . .681
19.6.12EXTI lock register (EXTI_LOCKR) . . . . .683
19.6.13EXTI CPU wake-up with interrupt mask register (EXTI_IMR1) . . . . .683
19.6.14EXTI CPU wake-up with event mask register (EXTI_EMR1) . . . . .684
19.6.15EXTI register map . . . . .685
20Cyclic redundancy check calculation unit (CRC) . . . . .687
20.1CRC introduction . . . . .687
20.2CRC main features . . . . .687
20.3CRC functional description . . . . .688
20.3.1CRC block diagram . . . . .688
20.3.2CRC internal signals . . . . .688
20.3.3CRC operation . . . . .688
20.4CRC in low-power modes . . . . .690
20.5CRC registers . . . . .690
20.5.1CRC data register (CRC_DR) . . . . .690
20.5.2CRC independent data register (CRC_IDR) . . . . .690
20.5.3CRC control register (CRC_CR) . . . . .691
20.5.4CRC initial value (CRC_INIT) . . . . .692
20.5.5CRC polynomial (CRC_POL) . . . . .692
20.5.6CRC register map . . . . .693
21Analog-to-digital converter (ADC4) . . . . .694
21.1ADC introduction . . . . .694
21.2ADC main features . . . . .694
21.3ADC implementation . . . . .695
21.4ADC functional description . . . . .697
21.4.1ADC block diagram . . . . .697
21.4.2ADC pins and internal signals . . . . .698
21.4.3ADC voltage regulator (ADVREGEN) . . . . .699
21.4.4Calibration (ADCAL) . . . . .699
21.4.5ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .701
21.4.6ADC clock (PRESC[3:0]) . . . . .703
21.4.7ADC connectivity . . . . .704
21.4.8Configuring the ADC . . . . .705
21.4.9Channel selection (CHSEL, SCANDIR, CHSELRMOD) . . . . .705
21.4.10Programmable sampling time (SMPx[2:0]) . . . . .706
21.4.11Single conversion mode (CONT = 0) . . . . .707
21.4.12Continuous conversion mode (CONT = 1) . . . . .707
21.4.13Starting conversions (ADSTART) . . . . .708
21.4.14Timings . . . . .709
21.4.15Stopping an ongoing conversion (ADSTP) . . . . .710
21.4.16Conversion on external trigger and trigger polarity
(EXTSEL, EXTEN) . . . . .		710
21.4.17Discontinuous mode (DISCEN) . . . . .711
21.4.18Programmable resolution (RES) - fast conversion mode . . . . .711
21.4.19End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . .712
21.4.20End of conversion sequence (EOS flag) . . . . .713
21.4.21Example timing diagrams (single/continuous modes
hardware/software triggers) . . . . .		713
21.4.22Low-frequency trigger mode . . . . .715
21.4.23Data management . . . . .715
21.4.24Low-power features . . . . .719
21.4.25Analog window watchdog . . . . .723
21.4.26Oversampler . . . . .727
21.4.27Temperature sensor and internal reference voltage . . . . .730
21.5ADC in low-power modes . . . . .733
21.6ADC interrupts . . . . .733
21.7ADC registers . . . . .735
21.7.1ADC interrupt and status register (ADC_ISR) . . . . .735
21.7.2ADC interrupt enable register (ADC_IER) . . . . .736
21.7.3ADC control register (ADC_CR) . . . . .739
21.7.4ADC configuration register 1 (ADC_CFGR1) . . . . .741
21.7.5ADC configuration register 2 (ADC_CFGR2) . . . . .744
21.7.6ADC sampling time register (ADC_SMPR) . . . . .745
21.7.7ADC watchdog threshold register (ADC_AWD1TR) . . . . .746
21.7.8ADC watchdog threshold register (ADC_AWD2TR) . . . . .747
21.7.9ADC channel selection register [alternate] (ADC_CHSELR) . . . . .748
21.7.10ADC channel selection register [alternate] (ADC_CHSELR) . . . . .748
21.7.11ADC watchdog threshold register (ADC_AWD3TR) . . . . .750
21.7.12ADC data register (ADC_DR) . . . . .751
21.7.13ADC power register (ADC_PWR) . . . . .751
21.7.14ADC Analog Watchdog 2 Configuration register (ADC_AWD2CR) . . . . .752
21.7.15ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR) . . . . .752
21.7.16ADC Calibration factor (ADC_CALFACT) . . . . .753
21.7.17ADC common configuration register (ADC_CCR) . . . . .753
21.7.18ADC register map . . . . .754
22Voltage reference buffer (VREFBUF) . . . . .757
22.1VREFBUF introduction . . . . .757
22.2VREFBUF implementation . . . . .757
22.3VREFBUF functional description . . . . .757
22.4VREFBUF trimming . . . . .758
22.5VREFBUF registers . . . . .760
22.5.1VREFBUF control and status register (VREFBUF_CSR) . . . . .760
22.5.2VREFBUF calibration control register (VREFBUF_CCR) . . . . .761
22.5.3VREFBUF register map . . . . .761
23Comparator (COMP) . . . . .762
23.1COMP introduction . . . . .762
23.2COMP main features . . . . .762
23.3COMP implementation . . . . .762
23.4COMP functional description . . . . .763
23.4.1COMP block diagram . . . . .763
23.4.2COMP pins and internal signals . . . . .763
23.4.3Comparator LOCK mechanism . . . . .765
23.4.4Window comparator . . . . .765
23.4.5Hysteresis . . . . .766
23.4.6Comparator output-blanking function . . . . .766
23.4.7COMP power and speed modes . . . . .767
23.4.8Scaler function . . . . .767
23.5COMP low-power modes . . . . .768
23.6COMP interrupts . . . . .768
23.7COMP registers . . . . .769
23.7.1COMP1 control and status register (COMP1_CSR) . . . . .769
23.7.2COMP2 control and status register (COMP2_CSR) . . . . .770
23.7.3COMP register map . . . . .772
24Touch sensing controller (TSC) . . . . .773
24.1TSC introduction . . . . .773
24.2TSC main features . . . . .773
24.3TSC functional description . . . . .773
24.3.1TSC block diagram . . . . .773
24.3.2Surface charge transfer acquisition overview . . . . .774
24.3.3Reset and clocks . . . . .777
24.3.4Charge transfer acquisition sequence . . . . .777
24.3.5Spread spectrum feature . . . . .778
24.3.6Max count error . . . . .779
24.3.7Sampling capacitor I/O and channel I/O mode selection . . . . .779
24.3.8Acquisition mode . . . . .780
24.3.9I/O hysteresis and analog switch control . . . . .780
24.4TSC low-power modes . . . . .781
24.5TSC interrupts .....781
24.6TSC registers .....781
24.6.1TSC control register (TSC_CR) .....781
24.6.2TSC interrupt enable register (TSC_IER) .....784
24.6.3TSC interrupt clear register (TSC_ICR) .....784
24.6.4TSC interrupt status register (TSC_ISR) .....785
24.6.5TSC I/O hysteresis control register (TSC_IOHCR) .....785
24.6.6TSC I/O analog switch control register
(TSC_IOASCR) .....		786
24.6.7TSC I/O sampling control register (TSC_IOSCR) .....786
24.6.8TSC I/O channel control register (TSC_IOCCR) .....787
24.6.9TSC I/O group control status register (TSC_IOGCSR) .....787
24.6.10TSC I/O group x counter register (TSC_IOGxCR) .....788
24.6.11TSC register map .....788
25True random number generator (RNG) .....790
25.1RNG introduction .....790
25.2RNG main features .....790
25.3RNG functional description .....791
25.3.1RNG block diagram .....791
25.3.2RNG internal signals .....791
25.3.3Random number generation .....792
25.3.4RNG initialization .....794
25.3.5RNG operation .....795
25.3.6RNG clocking .....797
25.3.7Error management .....797
25.3.8RNG low-power use .....798
25.4RNG interrupts .....798
25.5RNG processing time .....799
25.6RNG entropy source validation .....799
25.6.1Introduction .....799
25.6.2Validation conditions .....799
25.7RNG registers .....801
25.7.1RNG control register (RNG_CR) .....801
25.7.2RNG status register (RNG_SR) .....803
25.7.3RNG data register (RNG_DR) .....804
25.7.4RNG noise source control register (RNG_NSCR) . . . . .804
25.7.5RNG health test control register x (RNG_HTCRx) . . . . .805
25.7.6RNG register map . . . . .806
26AES hardware accelerator (AES) . . . . .807
26.1AES introduction . . . . .807
26.2AES main features . . . . .807
26.3AES implementation . . . . .808
26.4AES functional description . . . . .808
26.4.1AES block diagram . . . . .808
26.4.2AES internal signals . . . . .809
26.4.3AES reset and clocks . . . . .809
26.4.4AES symmetric cipher implementation . . . . .809
26.4.5AES encryption or decryption typical usage . . . . .810
26.4.6AES authenticated encryption, decryption, and cipher-based message authentication . . . . .812
26.4.7AES ciphertext stealing and data padding . . . . .812
26.4.8AES suspend and resume operations . . . . .813
26.4.9AES basic chaining modes (ECB, CBC) . . . . .814
26.4.10AES counter (CTR) mode . . . . .817
26.4.11AES Galois/counter mode (GCM) . . . . .820
26.4.12AES Galois message authentication code (GMAC) . . . . .824
26.4.13AES counter with CBC-MAC (CCM) . . . . .825
26.4.14AES key sharing with secure AES co-processor . . . . .830
26.4.15AES data registers and data swapping . . . . .831
26.4.16AES key registers . . . . .833
26.4.17AES initialization vector registers . . . . .833
26.4.18AES error management . . . . .834
26.5AES in low-power modes . . . . .835
26.6AES interrupts . . . . .835
26.7AES DMA requests . . . . .836
26.8AES processing latency . . . . .837
26.9AES registers . . . . .838
26.9.1AES control register (AES_CR) . . . . .838
26.9.2AES status register (AES_SR) . . . . .840
26.9.3AES data input register (AES_DINR) . . . . .841
26.9.4AES data output register (AES_DOUTR) . . . . .842
26.9.5AES key register 0 (AES_KEYR0) . . . . .842
26.9.6AES key register 1 (AES_KEYR1) . . . . .843
26.9.7AES key register 2 (AES_KEYR2) . . . . .843
26.9.8AES key register 3 (AES_KEYR3) . . . . .843
26.9.9AES initialization vector register 0 (AES_IVR0) . . . . .844
26.9.10AES initialization vector register 1 (AES_IVR1) . . . . .844
26.9.11AES initialization vector register 2 (AES_IVR2) . . . . .844
26.9.12AES initialization vector register 3 (AES_IVR3) . . . . .845
26.9.13AES key register 4 (AES_KEYR4) . . . . .845
26.9.14AES key register 5 (AES_KEYR5) . . . . .845
26.9.15AES key register 6 (AES_KEYR6) . . . . .846
26.9.16AES key register 7 (AES_KEYR7) . . . . .846
26.9.17AES suspend registers (AES_SUSPRx) . . . . .846
26.9.18AES interrupt enable register (AES_IER) . . . . .847
26.9.19AES interrupt status register (AES_ISR) . . . . .848
26.9.20AES interrupt clear register (AES_ICR) . . . . .849
26.9.21AES register map . . . . .849
27Secure AES coprocessor (SAES) . . . . .852
27.1SAES introduction . . . . .852
27.2SAES main features . . . . .852
27.3SAES implementation . . . . .853
27.4SAES functional description . . . . .853
27.4.1SAES block diagram . . . . .853
27.4.2SAES internal signals . . . . .854
27.4.3SAES reset and clocks . . . . .855
27.4.4SAES symmetric cipher implementation . . . . .855
27.4.5SAES encryption or decryption typical usage . . . . .856
27.4.6SAES authenticated encryption, decryption, and cipher-based message authentication . . . . .858
27.4.7SAES ciphertext stealing and data padding . . . . .859
27.4.8SAES suspend and resume operations . . . . .859
27.4.9SAES basic chaining modes (ECB, CBC) . . . . .860
27.4.10SAES counter (CTR) mode . . . . .864
27.4.11SAES Galois/counter mode (GCM) . . . . .866
27.4.12SAES Galois message authentication code (GMAC) . . . . .870
28.2HASH main features . . . . .907
28.3HASH implementation . . . . .908
28.4HASH functional description . . . . .908
28.4.1HASH block diagram . . . . .908
28.4.2HASH internal signals . . . . .909
28.4.3About secure hash algorithms . . . . .909
28.4.4Message data feeding . . . . .909
28.4.5Message digest computing . . . . .911
28.4.6Message padding . . . . .912
28.4.7HMAC operation . . . . .914
28.4.8HASH suspend/resume operations . . . . .916
28.4.9HASH DMA interface . . . . .918
28.4.10HASH error management . . . . .918
28.4.11HASH processing time . . . . .918
28.5HASH in low-power modes . . . . .919
28.6HASH interrupts . . . . .919
28.7HASH registers . . . . .920
28.7.1HASH control register (HASH_CR) . . . . .920
28.7.2HASH data input register (HASH_DIN) . . . . .921
28.7.3HASH start register (HASH_STR) . . . . .922
28.7.4HASH digest registers . . . . .923
28.7.5HASH interrupt enable register (HASH_IMR) . . . . .924
28.7.6HASH status register (HASH_SR) . . . . .925
28.7.7HASH context swap registers . . . . .926
28.7.8HASH register map . . . . .927
29Public key accelerator (PKA) . . . . .929
29.1PKA introduction . . . . .929
29.2PKA main features . . . . .929
29.3PKA functional description . . . . .930
29.3.1PKA block diagram . . . . .930
29.3.2PKA internal signals . . . . .930
29.3.3PKA reset and clocks . . . . .930
29.3.4PKA public key acceleration . . . . .931
29.3.5Typical applications for PKA . . . . .933
29.3.6PKA procedure to perform an operation . . . . .935

30 Advanced-control timers (TIM1) . . . . . 962

30.2TIM1 main features . . . . .963
30.3TIM1 functional description . . . . .964
30.3.1Block diagram . . . . .964
30.3.2TIM1 pins and internal signals . . . . .965
30.3.3Time-base unit . . . . .969
30.3.4Counter modes . . . . .971
30.3.5Repetition counter . . . . .983
30.3.6External trigger input . . . . .984
30.3.7Clock selection . . . . .985
30.3.8Capture/compare channels . . . . .989
30.3.9Input capture mode . . . . .992
30.3.10PWM input mode . . . . .993
30.3.11Forced output mode . . . . .994
30.3.12Output compare mode . . . . .994
30.3.13PWM mode . . . . .996
30.3.14Asymmetric PWM mode . . . . .1004
30.3.15Combined PWM mode . . . . .1005
30.3.16Combined 3-phase PWM mode . . . . .1006
30.3.17Complementary outputs and dead-time insertion . . . . .1007
30.3.18Using the break function . . . . .1010
30.3.19Bidirectional break inputs . . . . .1016
30.3.20Clearing the tim_ocxref signal on an external event . . . . .1017
30.3.216-step PWM generation . . . . .1019
30.3.22One-pulse mode . . . . .1020
30.3.23Retriggerable One-pulse mode . . . . .1022
30.3.24Pulse on compare mode . . . . .1023
30.3.25Encoder interface mode . . . . .1025
30.3.26Direction bit output . . . . .1042
30.3.27Clock drift measurement . . . . .1043
30.3.28UIF bit remapping . . . . .1043
30.3.29Timer input XOR function . . . . .1044
30.3.30Interfacing with Hall sensors . . . . .1044
30.3.31Timer synchronization . . . . .1046
30.3.32ADC triggers . . . . .1051
30.3.33ADC synchronization . . . . .1051
30.3.34DMA burst mode . . . . .1052
30.3.35TIM1 DMA requests . . . . .1053
30.3.36Debug mode1053
30.4TIM1 low-power modes1054
30.5TIM1 interrupts1054
30.6TIM1 registers1055
30.6.1TIM1 control register 1 (TIM1_CR1)1055
30.6.2TIM1 control register 2 (TIM1_CR2)1056
30.6.3TIM1 slave mode control register (TIM1_SMCR)1060
30.6.4TIM1 DMA/interrupt enable register (TIM1_DIER)1064
30.6.5TIM1 status register (TIM1_SR)1065
30.6.6TIM1 event generation register (TIM1_EGR)1068
30.6.7TIM1 capture/compare mode register 1 (TIM1_CCMR1)1069
30.6.8TIM1 capture/compare mode register 1 [alternate]
(TIM1_CCMR1)		1071
30.6.9TIM1 capture/compare mode register 2 (TIM1_CCMR2)1074
30.6.10TIM1 capture/compare mode register 2 [alternate]
(TIM1_CCMR2)		1075
30.6.11TIM1 capture/compare enable register (TIM1_CCER)1078
30.6.12TIM1 counter (TIM1_CNT)1082
30.6.13TIM1 prescaler (TIM1_PSC)1082
30.6.14TIM1 autoreload register (TIM1_ARR)1083
30.6.15TIM1 repetition counter register (TIM1_RCR)1083
30.6.16TIM1 capture/compare register 1 (TIM1_CCR1)1084
30.6.17TIM1 capture/compare register 2 (TIM1_CCR2)1084
30.6.18TIM1 capture/compare register 3 (TIM1_CCR3)1085
30.6.19TIM1 capture/compare register 4 (TIM1_CCR4)1086
30.6.20TIM1 break and dead-time register (TIM1_BDTR)1087
30.6.21TIM1 capture/compare register 5 (TIM1_CCR5)1091
30.6.22TIM1 capture/compare register 6 (TIM1_CCR6)1092
30.6.23TIM1 capture/compare mode register 3 (TIM1_CCMR3)1093
30.6.24TIM1 timer deadtime register 2 (TIM1_DTR2)1094
30.6.25TIM1 timer encoder control register (TIM1_ECR)1095
30.6.26TIM1 timer input selection register (TIM1_TISEL)1096
30.6.27TIM1 alternate function option register 1 (TIM1_AF1)1097
30.6.28TIM1 alternate function register 2 (TIM1_AF2)1100
30.6.29TIM1 DMA control register (TIM1_DCR)1102
30.6.30TIM1 DMA address for full transfer (TIM1_DMAR)1104
30.6.31TIM1 register map1104
31General-purpose timers (TIM2/TIM3/TIM4) . . . . .1107
31.1TIM2/TIM3/TIM4 introduction . . . . .1107
31.2TIM2/TIM3/TIM4 main features . . . . .1107
31.3TIM2/TIM3/TIM4 implementation . . . . .1108
31.4TIM2/TIM3/TIM4 functional description . . . . .1109
31.4.1Block diagram . . . . .1109
31.4.2TIM2/TIM3/TIM4 pins and internal signals . . . . .1110
31.4.3Time-base unit . . . . .1113
31.4.4Counter modes . . . . .1115
31.4.5Clock selection . . . . .1127
31.4.6Capture/compare channels . . . . .1131
31.4.7Input capture mode . . . . .1133
31.4.8PWM input mode . . . . .1134
31.4.9Forced output mode . . . . .1135
31.4.10Output compare mode . . . . .1135
31.4.11PWM mode . . . . .1137
31.4.12Asymmetric PWM mode . . . . .1145
31.4.13Combined PWM mode . . . . .1146
31.4.14Clearing the tim_ocxref signal on an external event . . . . .1147
31.4.15One-pulse mode . . . . .1149
31.4.16Retriggerable one-pulse mode . . . . .1150
31.4.17Pulse on compare mode . . . . .1151
31.4.18Encoder interface mode . . . . .1153
31.4.19Direction bit output . . . . .1171
31.4.20Clock drift measurement . . . . .1172
31.4.21UIF bit remapping . . . . .1172
31.4.22Timer input XOR function . . . . .1173
31.4.23Timers and external trigger synchronization . . . . .1173
31.4.24Timer synchronization . . . . .1177
31.4.25ADC triggers . . . . .1182
31.4.26ADC synchronization . . . . .1183
31.4.27DMA burst mode . . . . .1184
31.4.28TIM2/TIM3/TIM4 DMA requests . . . . .1185
31.4.29Debug mode . . . . .1185
31.4.30TIM2/TIM3/TIM4 low-power modes . . . . .1185
31.4.31TIM2/TIM3/TIM4 interrupts . . . . .1186
31.5TIM2/TIM3/TIM4 registers . . . . .1187
31.5.1TIMx control register 1 (TIMx_CR1)(x = 2 to 4) . . . . .1187
31.5.2TIMx control register 2 (TIMx_CR2)(x = 2 to 4) . . . . .1188
31.5.3TIMx slave mode control register (TIMx_SMCR)(x = 2 to 4) . . . . .1190
31.5.4TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 4) . . . . .1194
31.5.5TIMx status register (TIMx_SR)(x = 2 to 4) . . . . .1195
31.5.6TIMx event generation register (TIMx_EGR)(x = 2 to 4) . . . . .1197
31.5.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 4) . . . . .1198
31.5.8TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 2 to 4) . . . . .		1200
31.5.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 4) . . . . .1202
31.5.10TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 2 to 4) . . . . .		1203
31.5.11TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 4) . . . . .1206
31.5.12TIM3 counter (TIM3_CNT) . . . . .1207
31.5.13TIMx counter (TIMx_CNT)(x = 2, 4) . . . . .1208
31.5.14TIMx prescaler (TIMx_PSC)(x = 2 to 4) . . . . .1208
31.5.15TIM3 autoreload register (TIM3_ARR) . . . . .1209
31.5.16TIMx autoreload register (TIMx_ARR)(x = 2, 4) . . . . .1209
31.5.17TIM3 capture/compare register 1 (TIM3_CCR1) . . . . .1210
31.5.18TIMx capture/compare register 1 (TIMx_CCR1)(x = 2, 4) . . . . .1211
31.5.19TIM3 capture/compare register 2 (TIM3_CCR2) . . . . .1211
31.5.20TIMx capture/compare register 2 (TIMx_CCR2)(x = 2, 4) . . . . .1212
31.5.21TIM3 capture/compare register 3 (TIM3_CCR3) . . . . .1213
31.5.22TIMx capture/compare register 3 (TIMx_CCR3)(x = 2, 4) . . . . .1214
31.5.23TIM3 capture/compare register 4 (TIM3_CCR4) . . . . .1215
31.5.24TIMx capture/compare register 4 (TIMx_CCR4)(x = 2, 4) . . . . .1216
31.5.25TIMx timer encoder control register (TIMx_ECR)(x = 2 to 4) . . . . .1217
31.5.26TIMx timer input selection register (TIMx_TISEL)(x = 2 to 4) . . . . .1218
31.5.27TIMx alternate function register 1 (TIMx_AF1)(x = 2 to 4) . . . . .1219
31.5.28TIMx alternate function register 2 (TIMx_AF2)(x = 2 to 4) . . . . .1220
31.5.29TIMx DMA control register (TIMx_DCR)(x = 2 to 4) . . . . .1221
31.5.30TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 4) . . . . .1222
31.5.31TIMx register map . . . . .1223
32General purpose timers (TIM16/TIM17) . . . . .1226
32.1TIM16/TIM17 introduction . . . . .1226
32.2TIM16/TIM17 main features . . . . .1226
32.3TIM16/TIM17 functional description . . . . .1227
32.3.1Block diagram . . . . .1227
32.3.2TIM16/TIM17 pins and internal signals . . . . .1227
32.3.3Time-base unit . . . . .1230
32.3.4Counter modes . . . . .1232
32.3.5Repetition counter . . . . .1236
32.3.6Clock selection . . . . .1237
32.3.7Capture/compare channels . . . . .1239
32.3.8Input capture mode . . . . .1241
32.3.9Forced output mode . . . . .1242
32.3.10Output compare mode . . . . .1242
32.3.11PWM mode . . . . .1244
32.3.12Complementary outputs and dead-time insertion . . . . .1249
32.3.13Using the break function . . . . .1251
32.3.14Bidirectional break input . . . . .1256
32.3.15Clearing the tim_ocxref signal on an external event . . . . .1257
32.3.166-step PWM generation . . . . .1258
32.3.17One-pulse mode . . . . .1260
32.3.18UIF bit remapping . . . . .1261
32.3.19Using timer output as trigger for other timers (TIM16/TIM17 only) . . . . .1261
32.3.20DMA burst mode . . . . .1262
32.3.21TIM16/TIM17 DMA requests . . . . .1263
32.3.22Debug mode . . . . .1263
32.4TIM16/TIM17 low-power modes . . . . .1263
32.5TIM16/TIM17 interrupts . . . . .1263
32.6TIM16/TIM17 registers . . . . .1265
32.6.1TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . .1265
32.6.2TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . .1266
32.6.3TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . .1267
32.6.4TIMx status register (TIMx_SR)(x = 16 to 17) . . . . .1268
32.6.5TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . .1269
32.6.6TIMx capture/compare mode register 1 (TIMx_CCMR1)
(x = 16 to 17) . . . . .		1270
32.6.7TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . .		1271
32.6.8TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . . . .1273
32.6.9TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . .1276
32.6.10TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . .1276
32.6.11TIMx auto-reautoreload register (TIMx_ARR)(x = 16 to 17) . . . . .1277
32.6.12TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . .1277
32.6.13TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . .1278
32.6.14TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . .1279
32.6.15TIMx timer deadtime register 2 (TIMx_DTR2)(x = 16 to 17) . . . . .1282
32.6.16TIMx input selection register (TIMx_TISEL)(x = 16 to 17) . . . . .1283
32.6.17TIMx alternate function register 1 (TIMx_AF1)(x = 16 to 17) . . . . .1283
32.6.18TIMx alternate function register 2 (TIMx_AF2)(x = 16 to 17) . . . . .1286
32.6.19TIMx option register 1 (TIMx_OR1)(x = 16 to 17) . . . . .1286
32.6.20TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . .1287
32.6.21TIM16/TIM17 DMA address for full transfer
(TIMx_DMAR)(x = 16 to 17) . . . . .		1288
32.6.22TIM16/TIM17 register map . . . . .1289
33Low-power timer (LPTIM) . . . . .1291
33.1LPTIM introduction . . . . .1291
33.2LPTIM main features . . . . .1291
33.3LPTIM implementation . . . . .1292
33.4LPTIM functional description . . . . .1293
33.4.1LPTIM block diagram . . . . .1293
33.4.2LPTIM pins and internal signals . . . . .1293
33.4.3LPTIM input and trigger mapping . . . . .1295
33.4.4LPTIM reset and clocks . . . . .1296
33.4.5Glitch filter . . . . .1296
33.4.6Prescaler . . . . .1297
33.4.7Trigger multiplexer . . . . .1297
33.4.8Operating mode . . . . .1298
33.4.9Timeout function . . . . .1300
33.4.10Waveform generation . . . . .1300
33.4.11Register update . . . . .1301
33.4.12Counter mode . . . . .1302
33.4.13Timer enable . . . . .1303
33.4.14Timer counter reset . . . . .1303
33.4.15Encoder mode . . . . .1304
33.4.16Repetition counter . . . . .1305
33.4.17Capture/compare channels . . . . .1306
33.4.18Input capture mode . . . . .1307
33.4.19PWM mode . . . . .1309
33.4.20Autonomous mode . . . . .1311
33.4.21DMA requests . . . . .1312
33.4.22Debug mode . . . . .1313
33.5LPTIM low-power modes . . . . .1313
33.6LPTIM interrupts . . . . .1313
33.7LPTIM registers . . . . .1314
33.7.1LPTIMx interrupt and status register [alternate] (LPTIMx_ISR)
(x = 1, 2) . . . . .		1315
33.7.2LPTIMx interrupt and status register [alternate] (LPTIMx_ISR)
(x = 1, 2) . . . . .		1317
33.7.3LPTIMx interrupt clear register [alternate] (LPTIMx_ICR)
(x = 1, 2) . . . . .		1319
33.7.4LPTIMx interrupt clear register [alternate] (LPTIMx_ICR)
(x = 1, 2) . . . . .		1320
33.7.5LPTIMx interrupt enable register [alternate] (LPTIMx_DIER)
(x = 1, 2) . . . . .		1322
33.7.6LPTIMx interrupt enable register [alternate] (LPTIMx_DIER)
(x = 1, 2) . . . . .		1323
33.7.7LPTIM configuration register (LPTIM_CFGR) . . . . .1325
33.7.8LPTIM control register (LPTIM_CR) . . . . .1328
33.7.9LPTIM compare register 1 (LPTIM_CCR1) . . . . .1329
33.7.10LPTIM autoreload register (LPTIM_ARR) . . . . .1329
33.7.11LPTIM counter register (LPTIM_CNT) . . . . .1330
33.7.12LPTIM configuration register 2 (LPTIM_CFGR2) . . . . .1330
33.7.13LPTIM repetition register (LPTIM_RCR) . . . . .1331
33.7.14LPTIM capture/compare mode register 1 (LPTIM_CCMR1) . . . . .1332
33.7.15LPTIM compare register 2 (LPTIM_CCR2) . . . . .1334
33.7.16LPTIM register map . . . . .1335
34Infrared interface (IRTIM) . . . . .1337
35Independent watchdog (IWDG) . . . . .1338
35.1IWDG introduction . . . . .1338
35.2IWDG main features . . . . .1338
35.3IWDG implementation . . . . .1338
35.4IWDG functional description . . . . .1339
35.4.1IWDG block diagram . . . . .1339
35.4.2IWDG internal signals . . . . .1340
35.4.3Software and hardware watchdog modes . . . . .1340
35.4.4Window option . . . . .1341
35.4.5Debug . . . . .1344
35.4.6Register access protection . . . . .1344
35.5IWDG low power modes . . . . .1345
35.6IWDG interrupts . . . . .1345
35.7IWDG registers . . . . .1347
35.7.1IWDG key register (IWDG_KR) . . . . .1348
35.7.2IWDG prescaler register (IWDG_PR) . . . . .1348
35.7.3IWDG reload register (IWDG_RLR) . . . . .1349
35.7.4IWDG status register (IWDG_SR) . . . . .1349
35.7.5IWDG window register (IWDG_WINR) . . . . .1351
35.7.6IWDG early wake-up interrupt register (IWDG_EWCR) . . . . .1351
35.7.7IWDG register map . . . . .1353
36System window watchdog (WWDG) . . . . .1354
36.1WWDG introduction . . . . .1354
36.2WWDG main features . . . . .1354
36.3WWDG implementation . . . . .1354
36.4WWDG functional description . . . . .1355
36.4.1WWDG block diagram . . . . .1355
36.4.2WWDG internal signals . . . . .1355
36.4.3Enabling the watchdog . . . . .1355
36.4.4Controlling the down-counter . . . . .1356
36.4.5How to program the watchdog timeout . . . . .1356
36.4.6Debug mode . . . . .1357
36.5WWDG low-power modes . . . . .1358
36.6WWDG interrupts . . . . .1358
36.7WWDG registers . . . . .1358
36.7.1WWDG control register (WWDG_CR) . . . . .1359
36.7.2WWDG configuration register (WWDG_CFR) . . . . .1359
36.7.3WWDG status register (WWDG_SR) . . . . .1360
36.7.4WWDG register map . . . . .1360
37Real-time clock (RTC) . . . . .1361
37.1RTC introduction . . . . .1361
37.2RTC main features . . . . .1361
37.3RTC functional description . . . . .1361
37.3.1RTC block diagram . . . . .1361
37.3.2RTC pins and internal signals . . . . .1363
37.3.3GPIOs controlled by the RTC and TAMP . . . . .1364
37.3.4RTC secure protection modes . . . . .1366
37.3.5RTC privilege protection modes . . . . .1368
37.3.6Clock and prescalers . . . . .1369
37.3.7Real-time clock and calendar . . . . .1370
37.3.8Calendar ultra-low power mode . . . . .1371
37.3.9Programmable alarms . . . . .1371
37.3.10Periodic auto-wake-up . . . . .1371
37.3.11RTC initialization and configuration . . . . .1372
37.3.12Reading the calendar . . . . .1375
37.3.13Resetting the RTC . . . . .1376
37.3.14RTC synchronization . . . . .1377
37.3.15RTC reference clock detection . . . . .1377
37.3.16RTC smooth digital calibration . . . . .1378
37.3.17Timestamp function . . . . .1380
37.3.18Calibration clock output . . . . .1381
37.3.19Tamper and alarm output . . . . .1381
37.4RTC low-power modes . . . . .1382
37.5RTC interrupts . . . . .1382
37.6RTC registers . . . . .1384
37.6.1RTC time register (RTC_TR) . . . . .1384
37.6.2RTC date register (RTC_DR) . . . . .1385
37.6.3RTC subsecond register (RTC_SSR) . . . . .1386
37.6.4RTC initialization control and status register (RTC_ICSR) . . . . .1387
37.6.5RTC prescaler register (RTC_PRER) . . . . .1389
37.6.6RTC wake-up timer register (RTC_WUTR) . . . . .1390
37.6.7RTC control register (RTC_CR) . . . . .1390
37.6.8RTC privilege mode control register (RTC_PRIVCFGR) . . . . .1394
37.6.9RTC secure configuration register (RTC_SECCFGR) . . . . .1396
37.6.10RTC write protection register (RTC_WPR) . . . . .1397
37.6.11RTC calibration register (RTC_CALR) . . . . .1398
37.6.12RTC shift control register (RTC_SHIFTR) . . . . .1399
37.6.13RTC timestamp time register (RTC_TSTR) . . . . .1400
37.6.14RTC timestamp date register (RTC_TSDR) . . . . .1401
37.6.15RTC timestamp subsecond register (RTC_TSSSR) . . . . .1402
37.6.16RTC alarm A register (RTC_ALRMAR) . . . . .1402
37.6.17RTC alarm A subsecond register (RTC_ALRMASSR) . . . . .1404
37.6.18RTC alarm B register (RTC_ALRMBR) . . . . .1405
37.6.19RTC alarm B subsecond register (RTC_ALRMBSSR) . . . . .1406
37.6.20RTC status register (RTC_SR) . . . . .1407
37.6.21RTC nonsecure masked interrupt status register (RTC_MISR) . . . . .1408
37.6.22RTC secure masked interrupt status register (RTC_SMISR) . . . . .1409
37.6.23RTC status clear register (RTC_SCR) . . . . .1410
37.6.24RTC alarm A binary mode register (RTC_ALRABINR) . . . . .1411
37.6.25RTC alarm B binary mode register (RTC_ALRBBINR) . . . . .1412
37.6.26RTC register map . . . . .1413
38Tamper and backup registers (TAMP) . . . . .1415
38.1TAMP introduction . . . . .1415
38.2TAMP main features . . . . .1415
38.3TAMP functional description . . . . .1416
38.3.1TAMP block diagram . . . . .1416
38.3.2TAMP pins and internal signals . . . . .1417
38.3.3GPIOs controlled by the RTC and TAMP . . . . .1420
38.3.4TAMP register write protection . . . . .1420
38.3.5TAMP secure protection modes . . . . .1420
38.3.6Backup registers protection zones . . . . .1421
38.3.7TAMP privilege protection modes . . . . .1421
38.3.8Boot hardware key (BHK) . . . . .1422
38.3.9Tamper detection . . . . .1422
38.3.10TAMP backup registers and other device secrets erase . . . . .1422
38.3.11Tamper detection configuration and initialization . . . . .1424
38.4TAMP low-power modes . . . . .1430
38.5TAMP interrupts . . . . .1431
38.6TAMP registers . . . . .1431
38.6.1TAMP control register 1 (TAMP_CR1) . . . . .1431
38.6.2TAMP control register 2 (TAMP_CR2) . . . . .1433
38.6.3TAMP control register 3 (TAMP_CR3) . . . . .1436
38.6.4TAMP filter control register (TAMP_FLTCR) . . . . .1437
38.6.5TAMP active tamper control register 1 (TAMP_ATCR1) . . . . .1438
38.6.6TAMP active tamper seed register (TAMP_ATSEEDR) . . . . .1441
38.6.7TAMP active tamper output register (TAMP_ATOR) . . . . .1442
38.6.8TAMP active tamper control register 2 (TAMP_ATCR2) . . . . .1442
38.6.9TAMP secure configuration register (TAMP_SECCFGR) . . . . .1445
38.6.10TAMP privilege configuration register (TAMP_PRIVCFGR) . . . . .1446
38.6.11TAMP interrupt enable register (TAMP_IER) . . . . .1447
38.6.12TAMP status register (TAMP_SR) . . . . .1449
38.6.13TAMP nonsecure masked interrupt status register (TAMP_MISR) . . . . .1451
38.6.14TAMP secure masked interrupt status register (TAMP_SMISR) . . . . .1452
38.6.15TAMP status clear register (TAMP_SCR) . . . . .1454
38.6.16TAMP monotonic counter 1 register (TAMP_COUNT1R) . . . . .1456
38.6.17TAMP resources protection configuration register (TAMP_RPCFGR) . . . . .1456
38.6.18TAMP backup x register (TAMP_BKPxR) . . . . .1457
38.6.19TAMP register map . . . . .1459
39Inter-integrated circuit interface (I2C) . . . . .1461
39.1I2C introduction . . . . .1461
39.2I2C main features . . . . .1461
39.3I2C implementation . . . . .1462
39.4I2C functional description . . . . .1462
39.4.1I2C block diagram . . . . .1463
39.4.2I2C pins and internal signals . . . . .1463
39.4.3I2C clock requirements . . . . .1465
39.4.4I2C mode selection . . . . .1465
39.4.5I2C initialization . . . . .1466
39.4.6I2C reset . . . . .1470
39.4.7I2C data transfer . . . . .1471
39.4.8I2C target mode . . . . .1473
39.4.9I2C controller mode . . . . .1482
39.4.10I2C_TIMINGR register configuration examples . . . . .1493
39.4.11SMBus specific features . . . . .1495
39.4.12SMBus initialization . . . . .1497
39.4.13SMBus I2C_TIMEOUTR register configuration examples . . . . .1499
39.4.14SMBus target mode . . . . .1500
39.4.15SMBus controller mode . . . . .1503
39.4.16Autonomous mode . . . . .1506
39.4.17Error conditions . . . . .1508
39.5I2C in low-power modes . . . . .1509
39.6I2C interrupts . . . . .1510
39.7I2C DMA requests . . . . .1510
39.7.1Transmission using DMA . . . . .1510
39.7.2Reception using DMA . . . . .1511
39.7.3Controller event control using DMA . . . . .1511
39.8I2C debug modes . . . . .1512
39.9I2C registers . . . . .1512
39.9.1I2C control register 1 (I2C_CR1) . . . . .1512
39.9.2I2C control register 2 (I2C_CR2) . . . . .1515
39.9.3I2C own address 1 register (I2C_OAR1) . . . . .1517
39.9.4I2C own address 2 register (I2C_OAR2) . . . . .1517
39.9.5I2C timing register (I2C_TIMINGR) . . . . .1518
39.9.6I2C timeout register (I2C_TIMEOUTR) . . . . .1519
39.9.7I2C interrupt and status register (I2C_ISR) . . . . .1520
39.9.8I2C interrupt clear register (I2C_ICR) . . . . .1523
39.9.9I2C PEC register (I2C_PECR) . . . . .1524
39.9.10I2C receive data register (I2C_RXDR) . . . . .1524
39.9.11I2C transmit data register (I2C_TXDR) . . . . .1525
39.9.12I2C autonomous mode control register (I2C_AUTOCR) . . . . .1525
39.9.13I2C register map . . . . .1527
40Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . .1529
40.1USART introduction . . . . .1529
40.2USART main features . . . . .1529
40.3USART extended features . . . . .1530
40.4USART implementation . . . . .1530
40.5USART functional description . . . . .1532
40.5.1USART block diagram . . . . .1532
40.5.2USART pins and internal signals . . . . .1532
40.5.3USART clocks . . . . .1535
40.5.4USART character description . . . . .1535
40.5.5USART FIFOs and thresholds . . . . .1537
40.5.6USART transmitter . . . . .1537
40.5.7USART receiver . . . . .1540
40.5.8USART baud rate generation . . . . .1547
40.5.9Tolerance of the USART receiver to clock deviation . . . . .1549
40.5.10USART auto baud rate detection . . . . .1550
40.5.11USART multiprocessor communication . . . . .1552
40.5.12USART Modbus communication . . . . .1554
40.5.13USART parity control . . . . .1555
40.5.14USART LIN (local interconnection network) mode . . . . .1556
40.5.15USART synchronous mode . . . . .1558
40.5.16USART single-wire half-duplex communication . . . . .1562
40.5.17USART receiver timeout . . . . .1562
40.5.18USART smartcard mode . . . . .1563
40.5.19USART IrDA SIR ENDEC block . . . . .1567
40.5.20Continuous communication using USART and DMA . . . . .1570
40.5.21RS232 hardware flow control and RS485 driver enable . . . . .1572
40.5.22USART autonomous mode . . . . .1574
40.6USART in low-power modes . . . . .1576
40.7USART interrupts . . . . .1577
40.8USART registers . . . . .1579
40.8.1USART control register 1 (USART_CR1) . . . . .1579
40.8.2USART control register 1 [alternate] (USART_CR1) . . . . .1583
40.8.3USART control register 2 (USART_CR2) . . . . .1586
40.8.4USART control register 3 (USART_CR3) . . . . .1590
40.8.5USART control register 3 [alternate] (USART_CR3) . . . . .1594
40.8.6USART baud rate register (USART_BRR) . . . . .1597
40.8.7USART guard time and prescaler register (USART_GTPR) . . . . .1598
40.8.8USART receiver timeout register (USART_RTOR) . . . . .1599
40.8.9USART request register (USART_RQR) . . . . .1600
40.8.10USART interrupt and status register (USART_ISR) . . . . .1601
40.8.11USART interrupt and status register [alternate] (USART_ISR) . . . . .1607
40.8.12USART interrupt flag clear register (USART_ICR) . . . . .1612
40.8.13USART receive data register (USART_RDR) . . . . .1613
40.8.14USART transmit data register (USART_TDR) . . . . .1614
40.8.15USART prescaler register (USART_PRESC) . . . . .1614
40.8.16USART autonomous mode control register (USART_AUTOCR) . . . .1615
40.8.17USART register map . . . . .1616
41Low-power universal asynchronous receiver transmitter (LPUART) . . . . .1618
41.1LPUART introduction . . . . .1618
41.2LPUART main features . . . . .1618
41.3LPUART implementation . . . . .1619
41.4LPUART functional description . . . . .1621
41.4.1LPUART block diagram . . . . .1621
41.4.2LPUART pins and internal signals . . . . .1622
41.4.3LPUART clocks . . . . .1624
41.4.4LPUART character description . . . . .1624
41.4.5LPUART FIFOs and thresholds . . . . .1626
41.4.6LPUART transmitter . . . . .1626
41.4.7LPUART receiver . . . . .1630
41.4.8LPUART baud rate generation . . . . .1634
41.4.9Tolerance of the LPUART receiver to clock deviation . . . . .1635
41.4.10LPUART multiprocessor communication . . . . .1636
41.4.11LPUART parity control . . . . .1638
41.4.12LPUART single-wire half-duplex communication . . . . .1639
41.4.13Continuous communication using DMA and LPUART . . . . .1639
41.4.14RS232 hardware flow control and RS485 driver enable . . . . .1642
41.4.15LPUART autonomous mode . . . . .1644
41.5LPUART in low-power modes . . . . .1646
41.6LPUART interrupts . . . . .1647
41.7LPUART registers . . . . .1648
41.7.1LPUART control register 1 (LPUART_CR1) . . . . .1648
41.7.2LPUART control register 1 [alternate] (LPUART_CR1) . . . . .1651
41.7.3LPUART control register 2 (LPUART_CR2) . . . . .1654
41.7.4LPUART control register 3 (LPUART_CR3) . . . . .1656
41.7.5LPUART control register 3 [alternate] (LPUART_CR3) . . . . .1658
41.7.6LPUART baud rate register (LPUART_BRR) . . . . .1660
41.7.7LPUART request register (LPUART_RQR) . . . . .1660
41.7.8LPUART interrupt and status register (LPUART_ISR) . . . . .1661
41.7.9LPUART interrupt and status register [alternate] (LPUART_ISR) . . . . .1666
41.7.10LPUART interrupt flag clear register (LPUART_ICR) . . . . .1669
41.7.11LPUART receive data register (LPUART_RDR) . . . . .1670
41.7.12LPUART transmit data register (LPUART_TDR) . . . . .1670
41.7.13LPUART prescaler register (LPUART_PRESC) . . . . .1671
41.7.14LPUART autonomous mode control register (LPUART_AUTOCR) . . . . .1672
41.7.15LPUART register map . . . . .1672
42Serial peripheral interface (SPI) . . . . .1675
42.1SPI introduction . . . . .1675
42.2SPI main features . . . . .1675
42.3SPI implementation . . . . .1676
42.4SPI functional description . . . . .1677
42.4.1SPI block diagram . . . . .1677
42.4.2SPI pins and internal signals . . . . .1678
42.4.3SPI communication general aspects . . . . .1680
42.4.4Communications between one master and one slave . . . . .1680
42.4.5Standard multislave communication . . . . .1683
42.4.6Multimaster communication . . . . .1686
42.4.7Slave select (NSS pin) management . . . . .1687
42.4.8Ready pin (RDY) management . . . . .1691
42.4.9Communication formats . . . . .1691
42.4.10Configuring the SPI . . . . .1693
42.4.11Enabling the SPI . . . . .1694
42.4.12SPI data transmission and reception procedures . . . . .1695
42.4.13Disabling the SPI . . . . .1699
42.4.14Communication using DMA (direct memory addressing) . . . . .1700
42.4.15Autonomous mode . . . . .1701
42.5SPI specific modes and control . . . . .1703
42.5.1TI mode . . . . .1703
42.5.2SPI error flags . . . . .1704
42.5.3CRC computation . . . . .1707
42.6SPI in low-power modes . . . . .1708
42.7SPI interrupts . . . . .1709
42.8SPI registers . . . . .1710
42.8.1SPI control register 1 (SPI_CR1) . . . . .1710
42.8.2SPI control register 2 (SPI_CR2) . . . . .1712

43 Serial audio interface (SAI) . . . . . 1728

43.6SAI interrupts . . . . .1765
43.7SAI registers . . . . .1766
43.7.1SAI configuration register 1 (SAI_ACR1) . . . . .1766
43.7.2SAI configuration register 2 (SAI_ACR2) . . . . .1768
43.7.3SAI frame configuration register (SAI_AFRCR) . . . . .1770
43.7.4SAI slot register (SAI_ASLOTR) . . . . .1771
43.7.5SAI interrupt mask register (SAI_AIM) . . . . .1772
43.7.6SAI status register (SAI_ASR) . . . . .1774
43.7.7SAI clear flag register (SAI_ACLRFR) . . . . .1776
43.7.8SAI data register (SAI_ADR) . . . . .1777
43.7.9SAI configuration register 1 (SAI_BCR1) . . . . .1777
43.7.10SAI configuration register 2 (SAI_BCR2) . . . . .1780
43.7.11SAI frame configuration register (SAI_BFRCR) . . . . .1782
43.7.12SAI slot register (SAI_BSLOTR) . . . . .1783
43.7.13SAI interrupt mask register (SAI_BIM) . . . . .1784
43.7.14SAI status register (SAI_BSR) . . . . .1785
43.7.15SAI clear flag register (SAI_BCLRFR) . . . . .1787
43.7.16SAI data register (SAI_BDR) . . . . .1788
43.7.17SAI PDM control register (SAI_PDMCR) . . . . .1789
43.7.18SAI PDM delay register (SAI_PDMPLY) . . . . .1790
43.7.19SAI register map . . . . .1792
44USB on-the-go high-speed (OTG) . . . . .1794
44.1OTG introduction . . . . .1794
44.2OTG main features . . . . .1795
44.2.1General features . . . . .1795
44.2.2Host-mode features . . . . .1796
44.2.3Peripheral-mode features . . . . .1796
44.3OTG implementation . . . . .1796
44.4OTG functional description . . . . .1797
44.4.1OTG block diagram . . . . .1797
44.4.2OTG pin and internal signals . . . . .1797
44.4.3OTG core . . . . .1798
44.4.4OTG detections . . . . .1798
44.4.5High-speed OTG PHY connected to OTG . . . . .1798
44.4.6Battery charging detection . . . . .1798
44.14.13OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . .1846
44.14.14OTG receive FIFO size register (OTG_GRXFSIZ) . . . . .1847
44.14.15OTG host non-periodic transmit FIFO size register [alternate]
(OTG_HNPTXFSIZ) . . . . .		1848
44.14.16Endpoint 0 transmit FIFO size [alternate] (OTG_DIEPTXF0) . . . . .1848
44.14.17OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS) . . . . .		1849
44.14.18OTG general core configuration register (OTG_GCCFG) . . . . .1850
44.14.19OTG core ID register (OTG_CID) . . . . .1851
44.14.20OTG core LPM configuration register (OTG_GLPMCFG) . . . . .1852
44.14.21OTG host periodic transmit FIFO size register
(OTG_HPTXFSIZ) . . . . .		1856
44.14.22OTG device IN endpoint transmit FIFO x size register
(OTG_DIEPTXFx) . . . . .		1856
44.14.23Host-mode registers . . . . .1856
44.14.24OTG host configuration register (OTG_HCFG) . . . . .1857
44.14.25OTG host frame interval register (OTG_HFIR) . . . . .1857
44.14.26OTG host frame number/frame time remaining register
(OTG_HFNUM) . . . . .		1858
44.14.27OTG_Host periodic transmit FIFO/queue status register
(OTG_HPTXSTS) . . . . .		1859
44.14.28OTG host all channels interrupt register (OTG_HAINT) . . . . .1860
44.14.29OTG host all channels interrupt mask register
(OTG_HAINTMSK) . . . . .		1860
44.14.30OTG host port control and status register (OTG_HPRT) . . . . .1861
44.14.31OTG host channel x characteristics register (OTG_HCCHARx) . . . . .1863
44.14.32OTG host channel x split control register (OTG_HCSPLTx) . . . . .1864
44.14.33OTG host channel x interrupt register (OTG_HCINTx) . . . . .1865
44.14.34OTG host channel x interrupt mask register (OTG_HCINTMSKx) . . . . .1866
44.14.35OTG host channel x transfer size register (OTG_HCTSIZx) . . . . .1867
44.14.36OTG host channel x DMA address register(OTG_HCDMAx) . . . . .1868
44.14.37Device-mode registers . . . . .1868
44.14.38OTG device configuration register (OTG_DCFG) . . . . .1868
44.14.39OTG device control register (OTG_DCTL) . . . . .1870
44.14.40OTG device status register (OTG_DSTS) . . . . .1872
44.14.41OTG device IN endpoint common interrupt mask register
(OTG_DIEPMSK) . . . . .		1873
44.14.42OTG device OUT endpoint common interrupt mask register
(OTG_DOEPMSK) . . . . .		1874
44.14.43OTG device all endpoints interrupt register (OTG_DAIN) . . . . .1875
44.14.44OTG all endpoints interrupt mask register
(OTG_DAINTEMSK) .....		1876
44.14.45OTG device threshold control register (OTG_DTHRCTL) .....1876
44.14.46OTG device IN endpoint FIFO empty interrupt mask register
(OTG_DIEPEMPMSK) .....		1877
44.14.47OTG device IN endpoint x control register [alternate]
(OTG_DIEPCTLx) .....		1878
44.14.48OTG device IN endpoint x control register [alternate]
(OTG_DIEPCTLx) .....		1880
44.14.49OTG device IN endpoint x interrupt register (OTG_DIEPINTx) .....1882
44.14.50OTG device IN endpoint 0 transfer size register
(OTG_DIEPTSIZ0) .....		1883
44.14.51OTG device IN endpoint x DMA address register
(OTG_DIEPDMAx) .....		1884
44.14.52OTG device IN endpoint transmit FIFO status register
(OTG_DTXFSTSx) .....		1884
44.14.53OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) .1885
44.14.54OTG device control OUT endpoint 0 control register
(OTG_DOEPCTL0) .....		1885
44.14.55OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) ..1887
44.14.56OTG device OUT endpoint 0 transfer size register
(OTG_DOEPTSIZ0) .....		1889
44.14.57OTG device OUT endpoint x DMA address register
(OTG_DOEPDMAx) .....		1890
44.14.58OTG device OUT endpoint x control register [alternate]
(OTG_DOEPCTLx) .....		1890
44.14.59OTG device OUT endpoint x control register [alternate]
(OTG_DOEPCTLx) .....		1892
44.14.60OTG device OUT endpoint x transfer size register
(OTG_DOEPTSIZx) .....		1894
44.14.61OTG power and clock gating control register (OTG_PCGCCTL) ..1895
44.14.62OTG power and clock gating control register 1 (OTG_PCGCCTL1) .1896
44.14.63OTG register map .....1897
44.15OTG programming model .....1904
44.15.1Core initialization .....1904
44.15.2Host initialization .....1905
44.15.3Device initialization .....1906
44.15.4DMA mode .....1906
44.15.5Host programming model .....1906
44.15.6Device programming model .....1939
44.15.7Worst case response time .....1959
44.15.8OTG programming model .....1961
45Debug support (DBG) .....1962
45.1DBG introduction and main features .....1962
45.2DBG functional description .....1963
45.2.1DBG block diagram .....1963
45.2.2DBG pins and internal signals .....1963
45.2.3DBG reset and clocks .....1963
45.2.4DBG power domains .....1964
45.2.5DBG low-power modes .....1964
45.2.6DBG security .....1964
45.2.7Serial-wire and JTAG debug port .....1966
45.2.8JTAG debug port .....1967
45.2.9Serial-wire debug port .....1969
45.3Debug port registers .....1970
45.3.1DP identification register [alternate] (DP_PIDR) .....1971
45.3.2DP abort register [alternate] (DP_ABORTR) .....1972
45.3.3DP control and status register (DP_CTRLSTATR) .....1972
45.3.4DP data link control register (DP_DLCR) .....1974
45.3.5DP target identification register (DP_TARGETIDR) .....1974
45.3.6DP data link protocol identification register (DP_DLPIDR) .....1975
45.3.7DP resend register (DP_EVENSTATR) .....1975
45.3.8DP resend register (DP_RESENR) .....1976
45.3.9DP access port select register (DP_SELECTR) .....1976
45.3.10DP read buffer register (DP_BUFFR) .....1977
45.3.11DP register map and reset values .....1977
45.4Access port .....1979
45.4.1Access port registers .....1979
45.4.2AP control/status word register (APx_CSWR) (x = 0 to 1) .....1980
45.4.3AP transfer address register (APx_TAR) (x = 0 to 1) .....1981
45.4.4AP data read/write register (APx_DRWR) (x = 0 to 1) .....1981
45.4.5AP banked data registers y (APx_BDyR) (x = 0 to 1) .....1981
45.4.6AP configuration register (APx_CFGR) (x = 0 to 1) .....1982
45.4.7AP base address register (APx_BASER) (x = 0 to 1) .....1982
45.4.8AP identification register (APx_IDR) (x = 0 to 1) .....1983
45.4.9Access port register map and reset values .....1984
45.5System debug AP0 features .....1985
45.5.1System debug ROM table . . . . .1985
45.5.2System debug memory type register (SYSROM_MEMTYPER) . . . . .1986
45.5.3System debug CoreSight peripheral identity register 4
(SYSROM_PIDR4) . . . . .		1986
45.5.4System debug CoreSight peripheral identity register 0
(SYSROM_PIDR0) . . . . .		1987
45.5.5System debug CoreSight peripheral identity register 1
(SYSROM_PIDR1) . . . . .		1987
45.5.6System debug CoreSight peripheral identity register 2
(SYSROM_PIDR2) . . . . .		1988
45.5.7System debug CoreSight peripheral identity register 3
(SYSROM_PIDR3) . . . . .		1988
45.5.8System debug CoreSight component identity register 0
(SYSROM_CIDR0) . . . . .		1989
45.5.9System debug CoreSight peripheral identity register 1
(SYSROM_CIDR1) . . . . .		1989
45.5.10System debug CoreSight component identity register 2
(SYSROM_CIDR2) . . . . .		1990
45.5.11System debug CoreSight component identity register 3
(SYSROM_CIDR3) . . . . .		1990
45.5.12System debug ROM table register map and reset values . . . . .1991
45.6Cortex-M33 AP1 features . . . . .1992
45.6.1CPU ROM tables . . . . .1992
45.6.2MCU and processor ROM memory type register
(ROM_MEMTYPER) . . . . .		1994
45.6.3MCU and processor ROM CoreSight peripheral identity register 4
(ROM_PIDR4) . . . . .		1995
45.6.4MCU and processor ROM CoreSight peripheral identity register 0
(ROM_PIDR0) . . . . .		1995
45.6.5MCU and processor ROM CoreSight peripheral identity register 1
(ROM_PIDR1) . . . . .		1996
45.6.6MCU and processor ROM CoreSight peripheral identity register 2
(ROM_PIDR2) . . . . .		1996
45.6.7MCU and processor ROM CoreSight peripheral identity register 3
(ROM_PIDR3) . . . . .		1997
45.6.8MCU and processor ROM CoreSight component identity register 0
(ROM_CIDR0) . . . . .		1997
45.6.9MCU and processor ROM CoreSight peripheral identity register 1
(ROM_CIDR1) . . . . .		1998
45.6.10MCU and processor ROM CoreSight component identity register 2
(ROM_CIDR2) . . . . .		1998
45.6.11MCU and processor ROM CoreSight component identity register 3 (ROM_CIDR3) . . . . .1999
45.6.12MCU and processor ROM tables register map and reset values . . . . .2000
45.7Data watchpoint and trace unit (DWT) . . . . .2001
45.7.1DWT control register (DWT_CTRLR) . . . . .2002
45.7.2DWT cycle count register (DWT_CYCCNTR) . . . . .2003
45.7.3DWT CPI count register (DWT_CPICNTR) . . . . .2004
45.7.4DWT exception count register (DWT_EXCCNTR) . . . . .2004
45.7.5DWT sleep count register (DWT_SLP CNTR) . . . . .2004
45.7.6DWT LSU count register (DWT_LSUCNTR) . . . . .2005
45.7.7DWT fold count register (DWT_FOLDCNTR) . . . . .2005
45.7.8DWT program counter sample register (DWT_PCSR) . . . . .2006
45.7.9DWT comparator register x (DWT_COMPxR) . . . . .2006
45.7.10DWT function register 0(DWT_FUNCTR0) . . . . .2006
45.7.11DWT device type architecture register (DWT_DEVARCHR) . . . . .2010
45.7.12DWT device type register 4 (DWT_DEVTYPE) . . . . .2011
45.7.13DWT CoreSight peripheral identity register 4 (DWT_PIDR4) . . . . .2011
45.7.14DWT CoreSight peripheral identity register 0 (DWT_PIDR0) . . . . .2012
45.7.15DWT CoreSight peripheral identity register 1 (DWT_PIDR1) . . . . .2012
45.7.16DWT CoreSight peripheral identity register 2 (DWT_PIDR2) . . . . .2013
45.7.17DWT CoreSight peripheral identity register 3 (DWT_PIDR3) . . . . .2013
45.7.18DWT CoreSight component identity register 0 (DWT_CIDR0) . . . . .2014
45.7.19DWT CoreSight peripheral identity register 1 (DWT_CIDR1) . . . . .2014
45.7.20DWT CoreSight component identity register 2 (DWT_CIDR2) . . . . .2014
45.7.21DWT CoreSight component identity register 3 (DWT_CIDR3) . . . . .2015
45.7.22DWT register map and reset values . . . . .2016
45.8Instrumentation trace macrocell (ITM) . . . . .2019
45.8.1ITM registers . . . . .2019
45.8.2ITM stimulus register x (ITM_STIMRx) . . . . .2019
45.8.3ITM trace enable register (ITM_TER) . . . . .2020
45.8.4ITM trace privilege register (ITM_TPR) . . . . .2020
45.8.5ITM trace control register (ITM_TCR) . . . . .2021
45.8.6ITM device type architecture register (ITM_DEVARCHR) . . . . .2022
45.8.7ITM device type register 4 (ITM_DEVTYPE) . . . . .2022
45.8.8ITM CoreSight peripheral identity register 4 (ITM_PIDR4) . . . . .2023
45.8.9ITM CoreSight peripheral identity register 0 (ITM_PIDR0) . . . . .2023
45.8.10ITM CoreSight peripheral identity register 1 (ITM_PIDR1) . . . . .2023
45.8.11ITM CoreSight peripheral identity register 2 (ITM_PIDR2) . . . . .2024
45.8.12ITM CoreSight peripheral identity register 3 (ITM_PIDR3) . . . . .2024
45.8.13ITM CoreSight component identity register 0 (ITM_CIDR0) . . . . .2025
45.8.14ITM CoreSight peripheral identity register 1 (ITM_CIDR1) . . . . .2025
45.8.15ITM CoreSight component identity register 2 (ITM_CIDR2) . . . . .2025
45.8.16ITM CoreSight component identity register 3 (ITM_CIDR3) . . . . .2026
45.8.17ITM register map and reset values . . . . .2027
45.9Breakpoint unit (BPU) . . . . .2029
45.9.1BPU control register (BPU_CTRLR) . . . . .2029
45.9.2BPU comparator x register (BPU_COMPxR) . . . . .2029
45.9.3BPU device type architecture register (BPU_DEVARCHR) . . . . .2030
45.9.4BPU device type register 4 (BPU_DEVTYPER) . . . . .2030
45.9.5BPU CoreSight peripheral identity register 4 (BPU_PIDR4) . . . . .2031
45.9.6BPU CoreSight peripheral identity register 0 (BPU_PIDR0) . . . . .2031
45.9.7BPU CoreSight peripheral identity register 1 (BPU_PIDR1) . . . . .2031
45.9.8BPU CoreSight peripheral identity register 2 (BPU_PIDR2) . . . . .2032
45.9.9BPU CoreSight peripheral identity register 3 (BPU_PIDR3) . . . . .2032
45.9.10BPU CoreSight component identity register 0 (BPU_CIDR0) . . . . .2033
45.9.11BPU CoreSight peripheral identity register 1 (BPU_CIDR1) . . . . .2033
45.9.12BPU CoreSight component identity register 2 (BPU_CIDR2) . . . . .2033
45.9.13BPU CoreSight component identity register 3 (BPU_CIDR3) . . . . .2034
45.9.14BPU register map and reset values . . . . .2035
45.10Embedded Trace Macrocell (ETM) . . . . .2036
45.10.1ETM registers . . . . .2036
45.10.2ETM register map and reset values . . . . .2059
45.11Trace port interface unit (TPIU) . . . . .2062
45.11.1TPIU registers . . . . .2063
45.11.2TPIU supported port size register (TPIU_SSPSR) . . . . .2063
45.11.3TPIU current port size register (TPIU_CSPSR) . . . . .2064
45.11.4TPIU asynchronous clock prescaler register (TPIU_ACPR) . . . . .2064
45.11.5TPIU selected pin protocol register (TPIU_SPPR) . . . . .2064
45.11.6TPIU formatter and flush status register (TPIU_FFSR) . . . . .2065
45.11.7TPIU formatter and flush control register (TPIU_FFCR) . . . . .2065
45.11.8TPIU formatter synchronization counter register (TPIU_FSCR) . . . . .2066
45.11.9TPIU claim tag set register (TPIU_CLAIMSETR) . . . . .2067
45.11.10TPIU claim tag clear register (TPIU_CLAIMCLR) . . . . .2067
45.11.11TPIU device configuration register (TPIU_DEVIDR) . . . . .2068
45.11.12TPIU device type identifier register (TPIU_DEVTYPE)2068
45.11.13TPIU CoreSight peripheral identity register 4 (TPIU_PIDR4)2069
45.11.14TPIU CoreSight peripheral identity register 0 (TPIU_PIDR0)2069
45.11.15TPIU CoreSight peripheral identity register 1 (TPIU_PIDR1)2069
45.11.16TPIU CoreSight peripheral identity register 2 (TPIU_PIDR2)2070
45.11.17TPIU CoreSight peripheral identity register 3 (TPIU_PIDR3)2070
45.11.18TPIU CoreSight component identity register 0 (TPIU_CIDR0)2071
45.11.19TPIU CoreSight peripheral identity register 1 (TPIU_CIDR1)2071
45.11.20TPIU CoreSight component identity register 2 (TPIU_CIDR2)2071
45.11.21TPIU CoreSight component identity register 3 (TPIU_CIDR3)2072
45.11.22TPIU register map and reset values2073
45.12Cross trigger interface (CTI)2075
45.12.1CTI registers2076
45.12.2CTI register map and reset values2086
45.13Microcontroller debug unit (DBGMCU)2088
45.13.1DBGMCU access2088
45.13.2Device ID2088
45.13.3Part number codification2088
45.13.4Low-power mode emulation2088
45.13.5Low-power mode status2090
45.13.6Peripheral clock freeze2090
45.13.7DBGMCU registers2091
45.13.8DBGMCU register map and reset values2103
45.14References2105
46Device electronic signature (DESIG)2106
46.1Device electronic signature registers2106
46.1.1DESIG package data register (DESIG_PKGR)2106
46.1.2DESIG 96-bit unique device ID register 1 (DESIG_UIDR1)2106
46.1.3DESIG 96-bit unique device ID register 2 (DESIG_UIDR2)2107
46.1.4DESIG 96-bit unique device ID register 3 (DESIG_UIDR3)2107
46.1.5DESIG temperature calibration 1 register (DESIG_TSCAL1R)2107
46.1.6DESIG temperature calibration 2 register (DESIG_TSCAL2R)2108
46.1.7DESIG FLASH size data register (DESIG_FLASHSIZER)2108
46.1.8DESIG internal voltage reference calibration register
(DESIG_VREFINTCALR)		2109

46.1.9 DESIG voltage reference buffer calibration register
(DESIG_VREFBUFCALR) . . . . . 2109

46.1.10 DESIG resistor calibration register (DESIG_RCALR) . . . . . 2110

46.1.11 DESIG radio gain calibration register (DESIG_RFGAINCALR) . . . . . 2110

46.1.12 DESIG IEEE 64-bit unique device ID register 1 (DESIG_UID64R1) . 2110

46.1.13 DESIG IEEE 64-bit unique device ID register 2 (DESIG_UID64R2) . 2111

46.1.14 DESIG register map . . . . . 2112

47 Important security notice . . . . . 2113

48 Revision history . . . . . 2114

List of tables

Table 1.Bus matrix access arbitration . . . . .82
Table 2.Memory map security attribution example vs. SAU configuration regions . . . . .83
Table 3.Securable peripherals by TZSC . . . . .84
Table 4.TrustZone-aware peripherals . . . . .86
Table 5.Memory map and peripheral register boundary addresses . . . . .89
Table 6.Configuring security attributes with IDAU and SAU . . . . .99
Table 7.MPCBBx resources . . . . .101
Table 8.DMA channel use (security) . . . . .104
Table 9.Secure alternate function between peripherals and allocated I/Os . . . . .106
Table 10.Nonsecure peripheral functions not connected to secure I/Os . . . . .107
Table 11.Nonsecure peripheral functions that can be connected to secure I/Os . . . . .107
Table 12.TrustZone-aware DBGMCU accesses management . . . . .108
Table 13.DMA channel use (privilege). . . . .113
Table 14.Internal tampers in TAMP . . . . .116
Table 15.Effect of low-power modes on TAMP . . . . .118
Table 16.Accelerated cryptographic operations . . . . .120
Table 17.Main product life-cycle transitions. . . . .122
Table 18.Typical product life-cycle phases . . . . .122
Table 19.OEM key RDP unlocking methods . . . . .124
Table 20.Debug protection with RDP . . . . .125
Table 21.Software intellectual property protection with RDP. . . . .127
Table 22.Boot modes when TrustZone is disabled (TZEN = 0). . . . .128
Table 23.Boot modes when TrustZone is enabled (TZEN = 1) . . . . .128
Table 24.Boot space versus RDP protection. . . . .129
Table 25.GTZC features . . . . .132
Table 26.GTZC subblocks. . . . .132
Table 27.MPCBB resource assignment. . . . .133
Table 28.GTZC interrupt request. . . . .136
Table 29.GTZC1 TZSC register map and reset values . . . . .150
Table 30.GTZC1 TZIC register map and reset values. . . . .170
Table 31.GTZC1 MPCBB1 and MPCBB2 register map and reset values. . . . .175
Table 32.GTZC1 MPCBB6 register map and reset values . . . . .177
Table 33.SRAMs features . . . . .179
Table 34.SRAM parity access error. . . . .180
Table 35.SRAM parity error bus master ID . . . . .180
Table 36.Number of wait states versus hclk frequency and voltage range scaling . . . . .180
Table 37.Effect of low-power modes on RAMCFG . . . . .181
Table 38.RAMCFG interrupt requests . . . . .181
Table 39.RAMCFG register map and reset values . . . . .188
Table 40.Flash module 2-Mbyte dual bank organization. . . . .191
Table 41.Flash module 1-Mbyte dual bank organization. . . . .191
Table 42.Wait states according to CPU clock (HCLK1) frequency (LPM = 0). . . . .193
Table 43.Wait states according to CPU clock (HCLK1) frequency (LPM = 1). . . . .193
Table 44.Program and erase suspend control. . . . .202
Table 45.Flash operation interrupted by a system reset . . . . .205
Table 46.User option byte organization mapping . . . . .206
Table 47.Default secure option bytes after TZEN activation . . . . .209
Table 48.Secure watermark-based area . . . . .210
Table 49.Secure hide protection . . . . .211
Table 50.Flash security state . . . . .212
Table 51.WRP protection. . . . .216
Table 52.Flash memory readout protection status (TZEN=0) . . . . .216
Table 53.Access status vs. protection level and execution modes when TZEN = 0 . . . . .217
Table 54.Flash memory readout protection status (TZEN = 1) . . . . .218
Table 55.Access status vs. protection level and execution modes when TZEN = 1 . . . . .220
Table 56.Flash memory access vs. RDP level when TrustZone is active (TZEN = 1) . . . . .225
Table 57.Flash memory access vs. RDP level when TrustZone is disabled (TZEN = 0) . . . . .225
Table 58.Flash memory mass erase versus RDP level when TrustZone is active (TZEN = 1) . . . . .226
Table 59.Flash system memory, OTP and RSS accesses . . . . .226
Table 60.Flash registers access . . . . .227
Table 61.Flash page access versus privilege mode . . . . .227
Table 62.Flash bank erase versus privilege mode . . . . .227
Table 63.SECBBxRy registers access when TrustZone is active (TZEN = 1) . . . . .227
Table 64.PRIVBBxRy registers access when TrustZone is active (TZEN = 1) . . . . .228
Table 65.PRIVBBxRy registers access when TrustZone is disabled (TZEN = 0) . . . . .228
Table 66.Flash interrupt requests . . . . .228
Table 67.FLASH register map and reset values . . . . .258
Table 68.ICACHE features . . . . .264
Table 69.TAG memory dimensioning parameters
for n-way set associative operating mode (default) . . . . .		266
Table 70.TAG memory dimensioning parameters for direct-mapped cache mode . . . . .267
Table 71.ICACHE cacheability for AHB transaction . . . . .269
Table 72.Memory configurations . . . . .269
Table 73.ICACHE remap region size, base address, and remap address . . . . .270
Table 74.ICACHE interrupts . . . . .274
Table 75.ICACHE register map and reset values . . . . .278
Table 76.2.4 GHz RADIO implementation . . . . .281
Table 77.Input/output pins . . . . .281
Table 78.PA output power table format . . . . .282
Table 79.2.4 GHz RADIO supply configuration . . . . .283
Table 80.Effect of low-power modes on the 2.4 GHz RADIO . . . . .284
Table 81.2.4 PTACONV input/output pins . . . . .287
Table 82.PTACONV internal input/output signals . . . . .287
Table 83.Effect of low-power modes on the PTACONV . . . . .287
Table 84.2.4 PTACONV timing parameters . . . . .291
Table 85.PTACONV register map and reset values . . . . .295
Table 86.PWR input/output pins . . . . .297
Table 87.PWR internal input/output signals . . . . .297
Table 88.PWR wake-up source selection . . . . .298
Table 89.Low-power modes summary . . . . .315
Table 90.Functionalities depending on the working mode . . . . .316
Table 91.Sleep mode . . . . .323
Table 92.Stop 0 mode . . . . .325
Table 93.Stop 1 mode . . . . .327
Table 94.Stop 2 mode . . . . .329
Table 95.GPIO retention pin with pull-up and pull-down . . . . .331
Table 96.Standby mode . . . . .332
Table 97.Power modes output states versus MCU power modes . . . . .333
Table 98.PWR security configuration summary . . . . .334
Table 99.PWR interrupt requests . . . . .336
Table 100.PWR register map and reset values . . . . .364
Table 101.RCC input/output signals connected to package pins or balls . . . . .367
Table 102.LSI clock selection . . . . .377
Table 103.SYSCLK and bus maximum frequency . . . . .378
Table 104.Clock source maximum frequency . . . . .380
Table 105.2.4 GHz RADIO bus clock control . . . . .382
Table 106.Autonomous peripherals . . . . .389
Table 107.RCC security configuration summary . . . . .391
Table 108.Interrupt sources and control . . . . .394
Table 109.RCC register map and reset values . . . . .470
Table 110.HSEM internal input/output signals . . . . .477
Table 111.Semaphore attributes . . . . .482
Table 112.Authorized AHB bus master ID . . . . .483
Table 113.HSEM register map and reset values . . . . .496
Table 114.GPIO implementation . . . . .498
Table 115.Port bit configuration . . . . .500
Table 116.GPIO secured bits . . . . .508
Table 117.GPIOA to B register map and reset values . . . . .518
Table 118.GPIOC register map and reset values . . . . .529
Table 119.GPIO D register map and reset values . . . . .539
Table 120.GPIOE register map and reset values . . . . .548
Table 121.GPIOG register map and reset values . . . . .559
Table 122.GPIOH register map and reset values . . . . .567
Table 123.Effect of low-power modes on I/O compensation . . . . .569
Table 124.TrustZone security and privilege register accesses . . . . .570
Table 125.BOOSTEN and ANASWVDD set/reset . . . . .574
Table 126.SYSCFG register map and reset values . . . . .584
Table 127.Peripherals interconnect matrix . . . . .586
Table 128.GPDMA1 channel implementation . . . . .598
Table 129.GPDMA1 autonomous mode and wake-up in low-power modes . . . . .598
Table 130.Programmed GPDMA1 request . . . . .598
Table 131.Programmed GPDMA1 request as a block request . . . . .600
Table 132.Programmed GPDMA1 trigger . . . . .601
Table 133.Programmed GPDMA source/destination burst . . . . .621
Table 134.Programmed data handling . . . . .624
Table 135.Effect of low-power modes on GPDMA . . . . .637
Table 136.GPDMA interrupt requests . . . . .638
Table 137.GPDMA register map and reset values . . . . .659
Table 138.STM32WBA6xxx vector table . . . . .661
Table 139.EXTI pin overview . . . . .666
Table 140.EVG pin overview . . . . .666
Table 141.EXTI line connections . . . . .667
Table 142.Masking functionality . . . . .670
Table 143.Register protection overview . . . . .670
Table 144.EXTI register map sections . . . . .672
Table 145.EXTI register map and reset values . . . . .685
Table 146.CRC internal input/output signals . . . . .688
Table 147.Effect of low-power modes on CRC . . . . .690
Table 148.CRC register map and reset values . . . . .693
Table 149.ADC features . . . . .695
Table 150.Memory location of the temperature sensor calibration values . . . . .696
Table 151.Memory location of the internal reference voltage sensor . . . . .696
calibration value . . . . .696
Table 152. ADC input/output pins . . . . .698
Table 153. ADC internal input/output signals . . . . .698
Table 154. ADC interconnection . . . . .698
Table 155. Latency between trigger and start of conversion . . . . .703
Table 156. Configuring the trigger polarity . . . . .710
Table 157. \( t_{SAR} \) timings depending on resolution . . . . .712
Table 158. Analog watchdog comparison . . . . .724
Table 159. Analog watchdog 1 channel selection . . . . .724
Table 160. Maximum output results vs N and M. Grayed values indicates truncation . . . . .728
Table 161. Effect of low-power modes on the ADC . . . . .733
Table 162. ADC wake-up and interrupt requests . . . . .734
Table 163. ADC register map and reset values . . . . .754
Table 164. VREFBUF typical values . . . . .757
Table 165. VREF buffer modes . . . . .758
Table 166. VREFBUF trimming data . . . . .759
Table 167. VREFBUF register map and reset values . . . . .761
Table 168. COMP instances on devices . . . . .762
Table 169. COMP1 non-inverting input assignment . . . . .763
Table 170. COMP1 inverting input assignment . . . . .764
Table 171. COMP2 non-inverting input assignment . . . . .764
Table 172. COMP2 inverting input assignment . . . . .764
Table 173. COMP1 output-blanking PWM assignment . . . . .765
Table 174. COMP2 output-blanking PWM assignment . . . . .765
Table 175. Comparator behavior in the low-power modes . . . . .768
Table 176. Interrupt control bits . . . . .769
Table 177. COMP register map and reset values . . . . .772
Table 178. Acquisition sequence summary . . . . .776
Table 179. Spread spectrum deviation versus AHB clock frequency . . . . .778
Table 180. I/O state depending on its mode and IODEF bit value . . . . .779
Table 181. Effect of low-power modes on TSC . . . . .781
Table 182. Interrupt control bits . . . . .781
Table 183. TSC register map and reset values . . . . .788
Table 184. RNG internal input/output signals . . . . .791
Table 185. RNG interrupt requests . . . . .799
Table 186. RNG configurations . . . . .800
Table 187. Additional health test configurations . . . . .800
Table 188. Configuration selection . . . . .800
Table 189. RNG register map and reset map . . . . .806
Table 190. AES versus SAES features . . . . .808
Table 191. AES internal input/output signals . . . . .809
Table 192. AES approved symmetric key functions . . . . .809
Table 193. Counter mode initialization vector definition . . . . .819
Table 194. Initialization of IV registers in GCM mode . . . . .821
Table 195. GCM last block definition . . . . .821
Table 196. Initialization of IV registers in CCM mode . . . . .828
Table 197. AES data swapping example . . . . .831
Table 198. Key endianness in AES_KEYRx registers (128/256-bit keys) . . . . .833
Table 199. IVI bitfield spread over AES_IVRx registers . . . . .834
Table 200. Effect of low-power modes on AES . . . . .835
Table 201. AES interrupt requests . . . . .836
Table 202. Processing latency for ECB, CBC and CTR . . . . .837
Table 203.Processing latency for GCM and CCM (in clock cycles) . . . . .837
Table 204.AES register map and reset values . . . . .849
Table 205.AES versus SAES features . . . . .853
Table 206.SAES internal input/output signals . . . . .854
Table 207.SAES approved symmetric key functions . . . . .855
Table 208.Counter mode initialization vector definition . . . . .865
Table 209.Initialization of IV registers in GCM mode . . . . .868
Table 210.GCM last block definition . . . . .868
Table 211.Initialization of IV registers in CCM mode . . . . .874
Table 212.AES data swapping example . . . . .883
Table 213.Key endianness in SAES_KEYRx registers (128/256-bit keys) . . . . .885
Table 214.IVI bitfield spread over SAES_IVRx registers . . . . .887
Table 215.Effect of low-power modes on SAES . . . . .889
Table 216.SAES interrupt requests . . . . .889
Table 217.Processing latency for ECB, CBC and CTR . . . . .890
Table 218.Processing latency for GCM and CCM (in SAES kernel clock cycles) . . . . .891
Table 219.SAES register map and reset values . . . . .905
Table 220.HASH internal input/output signals . . . . .909
Table 221.Hash processor outputs . . . . .912
Table 222.Processing time (in clock cycle) . . . . .918
Table 223.Effect of low-power modes on HASH . . . . .919
Table 224.HASH interrupt requests . . . . .919
Table 225.HASH register map and reset values . . . . .927
Table 226.Internal input/output signals . . . . .930
Table 227.PKA integer arithmetic functions list . . . . .931
Table 228.PKA prime field (Fp) elliptic curve functions list . . . . .932
Table 229.Example of 'a' curve coefficient for ECC Fp scalar . . . . .938
Table 230.Montgomery parameter computation . . . . .938
Table 231.Modular addition . . . . .939
Table 232.Modular subtraction . . . . .939
Table 233.Montgomery multiplication . . . . .940
Table 234.Modular exponentiation (normal mode) . . . . .941
Table 235.Modular exponentiation (fast mode) . . . . .941
Table 236.Modular exponentiation (protected mode) . . . . .942
Table 237.Modular inversion . . . . .942
Table 238.Modular reduction . . . . .943
Table 239.Arithmetic addition . . . . .943
Table 240.Arithmetic subtraction . . . . .943
Table 241.Arithmetic multiplication . . . . .944
Table 242.Arithmetic comparison . . . . .944
Table 243.CRT exponentiation . . . . .945
Table 244.Point on elliptic curve Fp check . . . . .946
Table 245.ECC Fp scalar multiplication . . . . .946
Table 246.ECDSA sign - Inputs . . . . .948
Table 247.ECDSA sign - Outputs . . . . .948
Table 248.Extended ECDSA sign - additional outputs . . . . .949
Table 249.ECDSA verification - inputs . . . . .949
Table 250.ECDSA verification - outputs . . . . .950
Table 251.ECC complete addition . . . . .950
Table 252.ECC double base ladder . . . . .951
Table 253.ECC projective to affine . . . . .952
Table 254.Family of supported curves for ECC operations . . . . .953
Table 255.Modular exponentiation . . . . .954
Table 256.ECC scalar multiplication . . . . .954
Table 257.ECDSA signature average computation time . . . . .955
Table 258.ECDSA verification average computation times . . . . .955
Table 259.ECC double base ladder average computation times . . . . .955
Table 260.ECC projective to affine average computation times . . . . .955
Table 261.ECC complete addition average computation times . . . . .955
Table 262.Point on elliptic curve Fp check average computation times . . . . .955
Table 263.Montgomery parameters average computation times . . . . .956
Table 264.Effect of low-power modes on PKA . . . . .956
Table 265.PKA interrupt requests . . . . .956
Table 266.PKA register map and reset values . . . . .961
Table 267.TIM input/output pins . . . . .965
Table 268.TIM internal input/output signals . . . . .965
Table 269.Interconnect to the tim_ti1 input multiplexer . . . . .967
Table 270.Interconnect to the tim_ti2 input multiplexer . . . . .967
Table 271.Interconnect to the tim_ti3 input multiplexer . . . . .967
Table 272.Interconnect to the tim_ti4 input multiplexer . . . . .967
Table 273.Internal trigger connection . . . . .967
Table 274.Interconnect to the tim_etr input multiplexer . . . . .968
Table 275.Timer break interconnect . . . . .968
Table 276.Timer break2 interconnect . . . . .969
Table 277.System break interconnect . . . . .969
Table 278.Interconnect to the ocref_clr input multiplexer . . . . .969
Table 279.CCR and ARR register change dithering pattern . . . . .1002
Table 280.CCR register change dithering pattern in center-aligned PWM mode . . . . .1003
Table 281.Behavior of timer outputs versus tim_brk/tim_brk2 inputs . . . . .1015
Table 282.Break protection disarming conditions . . . . .1017
Table 283.Counting direction versus encoder signals (CC1P = CC2P = 0) . . . . .1026
Table 284.Counting direction versus encoder signals and polarity settings . . . . .1030
Table 285.DMA request . . . . .1053
Table 286.Effect of low-power modes on TIM1 . . . . .1054
Table 287.Interrupt requests . . . . .1054
Table 288.Output control bits for complementary tim_ocx and tim_ocxn channels
with break feature . . . . .		1081
Table 289.TIM1 register map and reset values . . . . .1104
Table 290.General purpose timers . . . . .1108
Table 291.TIM input/output pins . . . . .1110
Table 292.TIM internal input/output signals . . . . .1110
Table 293.Interconnect to the tim_ti1 input multiplexer . . . . .1111
Table 294.Interconnect to the tim_ti2 input multiplexer . . . . .1111
Table 295.Interconnect to the tim_ti3 input multiplexer . . . . .1111
Table 296.Interconnect to the tim_ti4 input multiplexer . . . . .1112
Table 297.TIMx internal trigger connection . . . . .1112
Table 298.Interconnect to the tim_etr input multiplexer . . . . .1112
Table 299.Interconnect to the tim_ocref_clr input multiplexer . . . . .1113
Table 300.CCR and ARR register change dithering pattern . . . . .1144
Table 301.CCR register change dithering pattern in center-aligned PWM mode . . . . .1145
Table 302.Counting direction versus encoder signals(CC1P = CC2P = 0) . . . . .1154
Table 303.Counting direction versus encoder signals and polarity settings . . . . .1159
Table 304.DMA request . . . . .1185
Table 305.Effect of low-power modes on TIM2/TIM3/TIM4 . . . . .1185
Table 306.Interrupt requests . . . . .1186
Table 307.Output control bit for standard tim_ocx channels . . . . .1207
Table 308.TIM2/TIM3/TIM4 register map and reset values . . . . .1223
Table 309.TIM input/output pins . . . . .1227
Table 310.TIM internal input/output signals . . . . .1228
Table 311.Interconnect to the tim_ti1 input multiplexer . . . . .1229
Table 312.Timer break interconnect . . . . .1229
Table 313.System break interconnect . . . . .1229
Table 314.Interconnect to the ocref_clr input multiplexer . . . . .1230
Table 315.CCR and ARR register change dithering pattern . . . . .1248
Table 316.Break protection disarming conditions . . . . .1256
Table 317.DMA request . . . . .1263
Table 318.Effect of low-power modes on TIM16/TIM17 . . . . .1263
Table 319.Interrupt requests . . . . .1264
Table 320.Output control bits for complementary tim_oc1 and tim_oc1n channels with break feature (TIM16/TIM17) . . . . .1275
Table 321.TIM16/TIM17 register map and reset values . . . . .1289
Table 322.LPTIM features . . . . .1292
Table 323.LPTIM1/2 input/output pins . . . . .1293
Table 324.LPTIM1/2 internal signals . . . . .1294
Table 325.LPTIM1/2 external trigger connections . . . . .1295
Table 326.LPTIM1/2 input 1 connections . . . . .1295
Table 327.LPTIM1/2 input 2 connections . . . . .1295
Table 328.LPTIM1/2 input capture 1 connections . . . . .1295
Table 329.LPTIM1/2 input capture 2 connections . . . . .1296
Table 330.Prescaler division ratios . . . . .1297
Table 331.Encoder counting scenarios . . . . .1304
Table 332.Input capture Glitch filter latency (in counter step unit) . . . . .1308
Table 333.Effect of low-power modes on the LPTIM . . . . .1313
Table 334.Interrupt events . . . . .1314
Table 335.LPTIM register map and reset values . . . . .1335
Table 336.IWDG features . . . . .1338
Table 337.IWDG delays versus actions . . . . .1339
Table 338.IWDG internal input/output signals . . . . .1340
Table 339.Effect of low power modes on IWDG . . . . .1345
Table 340.IWDG interrupt request . . . . .1347
Table 341.IWDG register map and reset values . . . . .1353
Table 342.WWDG features . . . . .1354
Table 343.WWDG internal input/output signals . . . . .1355
Table 344.Low-power mode description . . . . .1358
Table 345.WWDG interrupt requests . . . . .1358
Table 346.WWDG register map and reset values . . . . .1360
Table 347.RTC input/output pins . . . . .1363
Table 348.RTC internal input/output signals . . . . .1363
Table 349.RTC interconnection . . . . .1364
Table 350.RTC pin PC13 configuration . . . . .1364
Table 351.RTC_OUT mapping . . . . .1366
Table 352.Effect of low-power modes on RTC . . . . .1382
Table 353.RTC pins functionality over modes . . . . .1382
Table 354.Nonsecure interrupt requests . . . . .1383
Table 355.Secure interrupt requests . . . . .1383
Table 356.RTC register map and reset values . . . . .1413
Table 357.TAMP input/output pins . . . . .1417
Table 358.TAMP internal input/output signals . . . . .1417
Table 359.TAMP interconnection . . . . .1418
Table 360.Device resource x tamper protection . . . . .1424
Table 361.Active tamper output change period . . . . .1427
Table 362.Minimum ATPER value . . . . .1428
Table 363.Active tamper filtered pulse duration . . . . .1429
Table 364.Effect of low-power modes on TAMP . . . . .1430
Table 365.TAMP pins functionality over modes . . . . .1431
Table 366.Interrupt requests . . . . .1431
Table 367.TAMP register map and reset values . . . . .1459
Table 368.I2C implementation . . . . .1462
Table 369.I2C input/output pins . . . . .1463
Table 370.I2C internal input/output signals . . . . .1464
Table 371.I2C1, I2C2, and I2C4 interconnection . . . . .1464
Table 372.I2C3 interconnection . . . . .1464
Table 373.Comparison of analog and digital filters . . . . .1467
Table 374.I 2 C-bus and SMBus specification data setup and hold times . . . . .1469
Table 375.I2C configuration . . . . .1473
Table 376.I 2 C-bus and SMBus specification clock timings . . . . .1484
Table 377.Timing settings for f I2CCLK of 8 MHz . . . . .1494
Table 378.Timing settings for f I2CCLK of 16 MHz . . . . .1494
Table 379.SMBus timeout specifications . . . . .1496
Table 380.SMBus with PEC configuration . . . . .1498
Table 381.TIMEOUTA[11:0] for maximum t TIMEOUT of 25 ms . . . . .1499
Table 382.TIMEOUTB[11:0] for maximum t LOW:SEXT and t LOW:MEXT of 8 ms . . . . .1499
Table 383.TIMEOUTA[11:0] for maximum t IDLE of 50 µs . . . . .1499
Table 384.Effect of low-power modes to I2C . . . . .1509
Table 385.I2C interrupt requests . . . . .1510
Table 386.I2C register map and reset values . . . . .1527
Table 387.Instance implementation on STM32WBA6xxx . . . . .1530
Table 388.USART/LPUART features . . . . .1530
Table 389.USART/UART input/output pins . . . . .1533
Table 390.USART internal input/output signals . . . . .1534
Table 391.USART interconnection (USART1/2) . . . . .1534
Table 392.Noise detection from sampled data . . . . .1546
Table 393.Tolerance of the USART receiver when BRR [3:0] = 0000 . . . . .1550
Table 394.Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . .1550
Table 395.USART frame formats . . . . .1555
Table 396.Effect of low-power modes on the USART . . . . .1576
Table 397.USART interrupt requests . . . . .1577
Table 398.USART register map and reset values . . . . .1616
Table 399.Instance implementation on STM32WBA6xxx . . . . .1619
Table 400.USART/LPUART features . . . . .1619
Table 401.LPUART input/output pins . . . . .1622
Table 402.LPUART internal input/output signals . . . . .1622
Table 403.LPUART interconnections (LPUART1) . . . . .1623
Table 404.Error calculation for programmed baud rates at lpuart_ker_ck_pres= 32.768 kHz . . . . .1634
Table 405.Tolerance of the LPUART receiver . . . . .1635
Table 407.Effect of low-power modes on the LPUART . . . . .1646
Table 408.LPUART interrupt requests . . . . .1647
Table 409.LPUART register map and reset values . . . . .1672
Table 410.SPI features . . . . .1676
Table 411.SPI input/output pins. . . . .1678
Table 412.SPI internal input/output signals . . . . .1679
Table 413.SPI interconnection (SPI1 and SPI2) . . . . .1679
Table 414.SPI interconnection (SPI3) . . . . .1680
Table 415.Effect of low-power modes on the SPI . . . . .1708
Table 416.SPI wake-up and interrupt requests . . . . .1710
Table 417.SPI register map and reset values . . . . .1727
Table 418.SAI features . . . . .1729
Table 419.SAI internal input/output signals . . . . .1731
Table 420.SAI input/output pins. . . . .1731
Table 421.MCLK_x activation conditions. . . . .1739
Table 422.Clock generator programming examples . . . . .1742
Table 423.SAI_A configuration for TDM mode . . . . .1749
Table 424.TDM frame configuration examples . . . . .1751
Table 425.SOPD pattern . . . . .1754
Table 426.Parity bit calculation . . . . .1754
Table 427.Audio sampling frequency versus symbol rates . . . . .1755
Table 428.Effect of low-power modes on SAI . . . . .1764
Table 429.SAI interrupt sources . . . . .1765
Table 430.SAI register map and reset values . . . . .1792
Table 431.OTG speeds supported . . . . .1795
Table 432.OTG implementation. . . . .1796
Table 433.OTG input/output pins. . . . .1797
Table 434.OTG input/output signals . . . . .1798
Table 435.Compatibility of STM32 low power modes with the OTG . . . . .1809
Table 436.Core global control and status registers (CSRs). . . . .1817
Table 437.Host-mode control and status registers (CSRs) . . . . .1818
Table 438.Device-mode control and status registers . . . . .1819
Table 439.Data FIFO (DFIFO) access register map . . . . .1821
Table 440.Power and clock gating control and status registers . . . . .1822
Table 441.TRDT values. . . . .1828
Table 442.Minimum duration for soft disconnect. . . . .1871
Table 443.OTG register map and reset values . . . . .1897
Table 444.JTAG/Serial-wire debug port pins. . . . .1963
Table 445.Single-wire trace port pins . . . . .1963
Table 446.Debug features control . . . . .1965
Table 447.JTAG-DP data registers . . . . .1968
Table 448.Packet request . . . . .1970
Table 449.ACK response. . . . .1970
Table 450.Data transfer. . . . .1970
Table 451.DP register map and reset values . . . . .1977
Table 452.AP register map and reset values. . . . .1984
Table 453.System debug ROM table. . . . .1985
Table 454.System debug ROM register map and reset values . . . . .1991
Table 455.MCU ROM table . . . . .1992
Table 456.Processor ROM table . . . . .1993
Table 457.ROM table register map and reset values . . . . .2000
Table 458.DWT register map and reset values . . . . .2016
Table 459.ITM register map and reset values . . . . .2027
Table 460.BPU register map and reset values . . . . .2035
Table 461.ETM register map and reset values . . . . .2059
Table 462.TPIU register map and reset values . . . . .2073
Table 463.CTI inputs . . . . .2075
Table 464.CTI outputs . . . . .2075
Table 465.CTI register map and reset values . . . . .2086
Table 466.Low-power debug overview . . . . .2089
Table 467.Low-power mode status flags . . . . .2090
Table 468.Peripheral clock freeze control . . . . .2090
Table 469.Access to peripheral clock freeze control . . . . .2091
Table 470.DBGMCU register map and reset values . . . . .2103
Table 471.DESIG register map and reset values . . . . .2112
Table 472.Document revision history . . . . .2114

List of figures

Figure 1.System architecture . . . . .81
Figure 2.Memory map . . . . .88
Figure 3.Secure/nonsecure partitioning using TrustZone technology . . . . .97
Figure 4.Sharing memory map between CPU in secure and nonsecure state . . . . .98
Figure 5.Secure world transition and memory partitioning . . . . .99
Figure 6.Global TrustZone framework and TrustZone awareness . . . . .100
Figure 7.Flash memory TrustZone protections . . . . .103
Figure 8.Flash memory secure HDP area . . . . .110
Figure 9.Key management principle . . . . .118
Figure 10.Device life-cycle security . . . . .121
Figure 11.RDP level transition scheme . . . . .123
Figure 12.Collaborative development principle . . . . .126
Figure 13.GTZC block diagram . . . . .132
Figure 14.GTZC block diagram . . . . .134
Figure 15.MPCBB block diagram . . . . .135
Figure 16.Flash memory security attributes and protections
in case of no bank swap (SWAP_BANK = 0) . . . . .		214
Figure 17.Flash memory security attributes and protections
in case of bank swap (SWAP_BANK = 1) . . . . .		214
Figure 18.RDP level transition scheme when TrustZone is disabled (TZEN = 0) . . . . .221
Figure 19.RDP level transition scheme when TrustZone is enabled (TZEN = 1) . . . . .222
Figure 20.ICACHE block diagram . . . . .265
Figure 21.ICACHE TAG and data memories functional view . . . . .267
Figure 22.ICACHE remapping address mechanism . . . . .270
Figure 23.Radio system block diagram . . . . .281
Figure 24.Transmit path and output power control . . . . .282
Figure 25.Bluetooth AoA/AoD antennas control . . . . .283
Figure 26.PTACONV block diagram . . . . .286
Figure 27.4-wire PTA grant protocol . . . . .288
Figure 28.4-wire PTA deny protocol . . . . .289
Figure 29.3-wire time-multiplexed PTA_STATUS . . . . .290
Figure 30.Power supply overview . . . . .299
Figure 31.Application power supply schemes . . . . .302
Figure 32.Brownout reset waveform . . . . .309
Figure 33.PVD thresholds . . . . .310
Figure 34.Operating modes . . . . .313
Figure 35.Simplified diagram of the reset circuit . . . . .368
Figure 36.Clock tree . . . . .371
Figure 37.HSE 32 clock sources . . . . .373
Figure 38.LSE 32 clock sources . . . . .376
Figure 39.Radio control . . . . .383
Figure 40.Audio synchronization counter block diagram . . . . .387
Figure 41.Audio synchronization timing example . . . . .387
Figure 42.HSEM block diagram . . . . .477
Figure 43.Procedure state diagram . . . . .478
Figure 44.Interrupt state diagram . . . . .481
Figure 45.Structure of 3 V- or 5 V-tolerant GPIO (TT or FT) . . . . .499
Figure 46.Input floating / pull-up / pull-down configurations . . . . .503
Figure 47.Output configuration . . . . .504
Figure 48.Alternate function configuration . . . . .505
Figure 49.High-impedance analog configuration . . . . .505
Figure 50.I/O compensation cell block diagram . . . . .569
Figure 51.GPDMA block diagram . . . . .602
Figure 52.GPDMA channel direct programming without linked-list (GPDMA_CxLLR = 0) . . . . .603
Figure 53.GPDMA channel suspend and resume sequence . . . . .604
Figure 54.GPDMA channel abort and restart sequence . . . . .605
Figure 55.Static linked-list data structure (all Uxx = 1)
of a linear addressing channel x . . . . .		607
Figure 56.GPDMA dynamic linked-list data structure
of a linear addressing channel x . . . . .		607
Figure 57.GPDMA channel execution and linked-list programming
in run-to-completion mode (GPDMA_CxCR.LSM = 0) . . . . .		610
Figure 58.Inserting a LLI n with an auxiliary GPDMA channel y . . . . .612
Figure 59.GPDMA channel execution and linked-list programming
in link step mode (GPDMA_CxCR.LSM = 1) . . . . .		614
Figure 60.Building LLI n+1 : GPDMA dynamic linked-lists in link step mode . . . . .615
Figure 61.Replace with a new LLI n in register file in link step mode . . . . .616
Figure 62.Replace with a new LLI n and LLI n+1 in memory in link step mode (option 1) . . . . .617
Figure 63.Replace with a new LLI n and LLI n+1 in memory in link step mode (option 2) . . . . .618
Figure 64.GPDMA channel execution and linked-list programming . . . . .620
Figure 65.GPDMA arbitration policy . . . . .628
Figure 66.Trigger hit, memorization, and overrun waveform . . . . .631
Figure 67.GPDMA circular buffer programming: update of the memory start address
with a linear addressing channel . . . . .		632
Figure 68.Shared GPDMA channel with circular buffering: update of the memory
start address with a linear addressing channel . . . . .		633
Figure 69.EXTI block diagram . . . . .666
Figure 70.Configurable event trigger logic CPU wake-up . . . . .668
Figure 71.EXTI mux GPIO selection . . . . .669
Figure 72.CRC calculation unit block diagram . . . . .688
Figure 73.ADC block diagram . . . . .697
Figure 74.ADC calibration . . . . .700
Figure 75.Calibration factor forcing . . . . .701
Figure 76.Enabling/disabling the ADC . . . . .702
Figure 77.ADC clock scheme . . . . .703
Figure 78.ADC4 connectivity . . . . .704
Figure 79.Analog-to-digital conversion time . . . . .709
Figure 80.ADC conversion timings . . . . .709
Figure 81.Stopping an ongoing conversion . . . . .710
Figure 82.Single conversions of a sequence, software trigger . . . . .713
Figure 83.Continuous conversion of a sequence, software trigger . . . . .714
Figure 84.Single conversions of a sequence, hardware trigger . . . . .714
Figure 85.Continuous conversions of a sequence, hardware trigger . . . . .715
Figure 86.Data alignment and resolution (oversampling disabled: OVSE = 0) . . . . .716
Figure 87.Example of overrun (OVR) . . . . .717
Figure 88.Wait conversion mode (continuous mode, software trigger) . . . . .719
Figure 89.Auto-off mode state diagram . . . . .721
Figure 90.ADC behavior with WAIT = 0 and AUTOFF = 1 . . . . .721
Figure 91.ADC behavior with WAIT = 1 and AUTOFF = 1 . . . . .722
Figure 92.Autonomous mode state diagram . . . . .723
Figure 93.Analog watchdog guarded area . . . . .724
Figure 94.ADC_AWDx_OUT signal generation . . . . .725
Figure 95.ADC_AWDx_OUT signal generation (AWDx flag not cleared by software) . . . . .726
Figure 96.ADC_AWDx_OUT signal generation (on a single channel) . . . . .726
Figure 97.Analog watchdog threshold update . . . . .727
Figure 98.20-bit to 16-bit result truncation . . . . .727
Figure 99.Numerical example with 5-bits shift and rounding . . . . .728
Figure 100.Triggered oversampling mode (TOVS bit = 1) . . . . .730
Figure 101.Temperature sensor and VREFINT channel block diagram . . . . .731
Figure 102.VREFBUF block diagram . . . . .757
Figure 103.Comparator block diagrams . . . . .763
Figure 104.Window mode . . . . .766
Figure 105.Comparator hysteresis . . . . .766
Figure 106.Comparator output blanking . . . . .767
Figure 107.Scaler . . . . .768
Figure 108.TSC block diagram . . . . .774
Figure 109.Surface charge transfer analog I/O group structure . . . . .775
Figure 110.Sampling capacitor voltage variation . . . . .776
Figure 111.Charge transfer acquisition sequence . . . . .777
Figure 112.Spread spectrum variation principle . . . . .778
Figure 113.RNG block diagram . . . . .791
Figure 114.NIST SP800-90B entropy source model . . . . .792
Figure 115.RNG initialization overview . . . . .795
Figure 116.AES block diagram . . . . .808
Figure 117.Encryption/ decryption typical usage . . . . .810
Figure 118.Typical operation with authentication . . . . .812
Figure 119.Example of suspend mode management . . . . .813
Figure 120.ECB encryption . . . . .814
Figure 121.ECB decryption . . . . .814
Figure 122.CBC encryption . . . . .815
Figure 123.CBC decryption . . . . .815
Figure 124.Message construction in CTR mode . . . . .818
Figure 125.CTR encryption . . . . .818
Figure 126.Message construction in GCM . . . . .820
Figure 127.GCM authenticated encryption . . . . .821
Figure 128.Message construction in GMAC mode . . . . .824
Figure 129.GMAC authentication mode . . . . .825
Figure 130.Message construction in CCM mode . . . . .826
Figure 131.CCM mode authenticated encryption . . . . .827
Figure 132.128-bit block construction according to the data type . . . . .832
Figure 133.SAES block diagram . . . . .854
Figure 134.Encryption/ decryption typical usage . . . . .856
Figure 135.Typical operation with authentication . . . . .858
Figure 136.Example of suspend mode management . . . . .859
Figure 137.ECB encryption . . . . .860
Figure 138.ECB decryption . . . . .860
Figure 139.CBC encryption . . . . .861
Figure 140.CBC decryption . . . . .861
Figure 141.Message construction in CTR mode . . . . .864
Figure 142.CTR encryption . . . . .865
Figure 143.Message construction in GCM . . . . .866
Figure 144.GCM authenticated encryption . . . . .868
Figure 145. Message construction in GMAC mode . . . . .871
Figure 146. GMAC authentication mode . . . . .871
Figure 147. Message construction in CCM mode . . . . .872
Figure 148. CCM mode authenticated encryption . . . . .874
Figure 149. Operation with wrapped keys for SAES in ECB and CBC modes . . . . .877
Figure 150. Operation with wrapped keys for SAES in CTR mode . . . . .880
Figure 151. Usage of Shared-key mode . . . . .881
Figure 152. 128-bit block construction according to the data type. . . . .884
Figure 153. Key protection mechanisms . . . . .886
Figure 154. HASH block diagram . . . . .908
Figure 155. Message data swapping feature. . . . .910
Figure 156. HASH suspend/resume mechanism. . . . .916
Figure 157. PKA block diagram . . . . .930
Figure 158. Advanced-control timer block diagram . . . . .964
Figure 159. Counter timing diagram with prescaler division change from 1 to 2 . . . . .970
Figure 160. Counter timing diagram with prescaler division change from 1 to 4 . . . . .971
Figure 161. Counter timing diagram, internal clock divided by 1 . . . . .972
Figure 162. Counter timing diagram, internal clock divided by 2 . . . . .973
Figure 163. Counter timing diagram, internal clock divided by 4 . . . . .973
Figure 164. Counter timing diagram, internal clock divided by N. . . . .974
Figure 165. Counter timing diagram, update event when ARPE = 0
(TIMx_ARR not preloaded). . . . .		974
Figure 166. Counter timing diagram, update event when ARPE = 1
(TIMx_ARR preloaded). . . . .		975
Figure 167. Counter timing diagram, internal clock divided by 1 . . . . .976
Figure 168. Counter timing diagram, internal clock divided by 2 . . . . .977
Figure 169. Counter timing diagram, internal clock divided by 4 . . . . .977
Figure 170. Counter timing diagram, internal clock divided by N. . . . .978
Figure 171. Counter timing diagram, update event when repetition counter is not used. . . . .978
Figure 172. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .980
Figure 173. Counter timing diagram, internal clock divided by 2 . . . . .980
Figure 174. Counter timing diagram, internal clock divided by 4, TIMx_ARR = 0x36 . . . . .981
Figure 175. Counter timing diagram, internal clock divided by N. . . . .981
Figure 176. Counter timing diagram, update event with ARPE = 1 (counter underflow) . . . . .982
Figure 177. Counter timing diagram, Update event with ARPE = 1 (counter overflow) . . . . .983
Figure 178. Update rate examples depending on mode and TIMx_RCR register settings . . . . .984
Figure 180. Control circuit in normal mode, internal clock divided by 1 . . . . .986
Figure 181. tim_ti2 external clock connection example . . . . .986
Figure 182. Control circuit in external clock mode 1 . . . . .987
Figure 183. External trigger input block . . . . .988
Figure 184. Control circuit in external clock mode 2 . . . . .989
Figure 185. Capture/compare channel (example: channel 1 input stage). . . . .989
Figure 186. Capture/compare channel 1 main circuit . . . . .990
Figure 187. Output stage of capture/compare channel (channel 1, idem ch. 2, 3 and 4) . . . . .991
Figure 188. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .991
Figure 189. PWM input mode timing . . . . .994
Figure 190. Output compare mode, toggle on tim_oc1 . . . . .996
Figure 191. Edge-aligned PWM waveforms (ARR = 8) . . . . .997
Figure 192. Center-aligned PWM waveforms (ARR = 8). . . . .998
Figure 193. Dithering principle . . . . .999
Figure 194. Data format and register coding in dithering mode. . . . .1000
Figure 195. PWM resolution vs frequency . . . . .1001
Figure 196. PWM dithering pattern . . . . .1002
Figure 197. Dithering effect on duty cycle in center-aligned PWM mode . . . . .1003
Figure 198. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .1005
Figure 199. Combined PWM mode on channel 1 and 3 . . . . .1006
Figure 200. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .1007
Figure 201. Complementary output with symmetrical dead-time insertion . . . . .1008
Figure 202. Asymmetrical deadtime . . . . .1009
Figure 203. Dead-time waveforms with delay greater than the negative pulse . . . . .1009
Figure 204. Dead-time waveforms with delay greater than the positive pulse. . . . .1009
Figure 205. Break and Break2 circuitry overview . . . . .1012
Figure 206. Various output behavior in response to a break event on tim_brk (OSSI = 1) . . . . .1014
Figure 207. PWM output state following tim_brk and tim_brk2 assertion (OSSI = 1) . . . . .1015
Figure 208. PWM output state following tim_brk assertion (OSSI = 0) . . . . .1016
Figure 209. Output redirection (tim_brk2 request not represented). . . . .1017
Figure 210. tim_ocref_clr input selection multiplexer. . . . .1018
Figure 211. Clearing TIMx tim_ocxref . . . . .1019
Figure 212. 6-step generation, COM example (OSSR = 1) . . . . .1020
Figure 213. Example of one pulse mode. . . . .1021
Figure 214. Retriggerable one-pulse mode . . . . .1022
Figure 215. Pulse generator circuitry. . . . .1023
Figure 216. Pulse generation on compare event, for edge-aligned and encoder modes . . . . .1024
Figure 217. Extended pulsewidth in case of concurrent triggers . . . . .1025
Figure 218. Example of counter operation in encoder interface mode. . . . .1027
Figure 219. Example of encoder interface mode with tim_ti1fp1 polarity inverted. . . . .1027
Figure 220. Quadrature encoder counting modes . . . . .1028
Figure 221. Direction plus clock encoder mode. . . . .1029
Figure 222. Directional clock encoder mode (CC1P = CC2P = 0). . . . .1029
Figure 223. Directional clock encoder mode (CC1P = CC2P = 1). . . . .1030
Figure 224. Index gating options . . . . .1031
Figure 225. Jittered Index signals . . . . .1031
Figure 226. Index generation for IPOS[1:0] = 11 . . . . .1032
Figure 227. Counter reading with index gated on channel A (IPOS[1:0] = 11) . . . . .1032
Figure 228. Counter reading with index ungated (IPOS[1:0] = 00) . . . . .1033
Figure 229. Counter reading with index gated on channel A and B. . . . .1033
Figure 230. Encoder mode behavior in case of narrow index pulse (IPOS[1:0] = 11). . . . .1034
Figure 231. Counter reset Narrow index pulse (closer view, ARR = 0x07) . . . . .1035
Figure 232. Index behavior in x1 and x2 mode (IPOS[1:0] = 01). . . . .1036
Figure 233. Directional index sensitivity. . . . .1036
Figure 234. Counter reset as function of FIDX bit setting . . . . .1037
Figure 235. Index blanking. . . . .1037
Figure 236. Index behavior in clock + direction mode, IPOS[0] = 1. . . . .1038
Figure 237. Index behavior in directional clock mode, IPOS[0] = 1 . . . . .1038
Figure 238. State diagram for quadrature encoded signals. . . . .1039
Figure 239. Up-counting encoder error detection . . . . .1040
Figure 240. Down-counting encode error detection. . . . .1041
Figure 241. Encoder mode change with preload transferred on update (SMSPS = 0) . . . . .1042
Figure 242. Clock drift measure using directional clock mode. . . . .1043
Figure 243. Measuring time interval between edges on three signals. . . . .1044
Figure 244. Example of Hall sensor interface . . . . .1046
Figure 245. Control circuit in reset mode . . . . .1047
Figure 246. Control circuit in Gated mode . . . . .1048
Figure 247. Control circuit in trigger mode . . . . .1049
Figure 248. Control circuit in external clock mode 2 + trigger mode . . . . .1050
Figure 249. General-purpose timer block diagram . . . . .1109
Figure 250. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1114
Figure 251. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1115
Figure 252. Counter timing diagram, internal clock divided by 1 . . . . .1116
Figure 253. Counter timing diagram, internal clock divided by 2 . . . . .1116
Figure 254. Counter timing diagram, internal clock divided by 4 . . . . .1117
Figure 255. Counter timing diagram, internal clock divided by N . . . . .1117
Figure 256. Counter timing diagram, Update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .1118
Figure 257. Counter timing diagram, Update event when ARPE = 1 (TIMx_ARR preloaded). . . . .1119
Figure 258. Counter timing diagram, internal clock divided by 1 . . . . .1120
Figure 259. Counter timing diagram, internal clock divided by 2 . . . . .1121
Figure 260. Counter timing diagram, internal clock divided by 4 . . . . .1121
Figure 261. Counter timing diagram, internal clock divided by N . . . . .1122
Figure 262. Counter timing diagram, Update event . . . . .1122
Figure 263. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .1124
Figure 264. Counter timing diagram, internal clock divided by 2 . . . . .1124
Figure 265. Counter timing diagram, internal clock divided by 4, TIMx_ARR = 0x36 . . . . .1125
Figure 266. Counter timing diagram, internal clock divided by N . . . . .1125
Figure 267. Counter timing diagram, Update event with ARPE = 1 (counter underflow). . . . .1126
Figure 268. Counter timing diagram, Update event with ARPE = 1 (counter overflow). . . . .1127
Figure 269. Control circuit in normal mode, internal clock divided by 1 . . . . .1128
Figure 270. tim_ti2 external clock connection example . . . . .1128
Figure 271. Control circuit in external clock mode 1 . . . . .1129
Figure 272. External trigger input block . . . . .1130
Figure 273. Control circuit in external clock mode 2 . . . . .1131
Figure 274. Capture/compare channel (example: channel 1 input stage). . . . .1131
Figure 275. Capture/compare channel 1 main circuit . . . . .1132
Figure 276. Output stage of capture/compare channel (channel 1, idem ch.2, 3 and 4). . . . .1132
Figure 277. PWM input mode timing . . . . .1135
Figure 278. Output compare mode, toggle on tim_oc1 . . . . .1137
Figure 279. Edge-aligned PWM waveforms (ARR = 8). . . . .1138
Figure 280. Center-aligned PWM waveforms (ARR = 8). . . . .1139
Figure 281. Dithering principle . . . . .1140
Figure 282. Data format and register coding in dithering mode . . . . .1141
Figure 283. PWM resolution vs frequency (16-bit mode). . . . .1142
Figure 284. PWM resolution vs frequency (32-bit mode). . . . .1142
Figure 285. PWM dithering pattern . . . . .1143
Figure 286. Dithering effect on duty cycle in center-aligned PWM mode . . . . .1144
Figure 287. Generation of two phase-shifted PWM signals with 50% duty cycle . . . . .1146
Figure 288. Combined PWM mode on channels 1 and 3 . . . . .1147
Figure 289. OCREF_CLR input selection multiplexer . . . . .1148
Figure 290. Clearing TIMx tim_ocxref . . . . .1148
Figure 291. Example of One-pulse mode . . . . .1149
Figure 292. Retriggerable one-pulse mode . . . . .1151
Figure 293. Pulse generator circuitry . . . . .1152
Figure 294. Pulse generation on compare event, for edge-aligned and encoder modes . . . . .1152
Figure 295. Extended pulse width in case of concurrent triggers . . . . .1153
Figure 296. Example of counter operation in encoder interface mode . . . . .1155
Figure 297. Example of encoder interface mode with tim_ti1fp1 polarity inverted . . . . .1155
Figure 298. Quadrature encoder counting modes . . . . .1156
Figure 299. Direction plus clock encoder mode . . . . .1157
Figure 300. Directional clock encoder mode (CC1P = CC2P = 0) . . . . .1158
Figure 301. Directional clock encoder mode (CC1P = CC2P = 1) . . . . .1158
Figure 302. Index gating options . . . . .1160
Figure 303. Jittered Index signals . . . . .1160
Figure 304. Index generation for IPOS[1:0] = 11 . . . . .1161
Figure 305. Counter reading with index gated on channel A (IPOS[1:0] = 11) . . . . .1161
Figure 306. Counter reading with index ungated (IPOS[1:0] = 00) . . . . .1162
Figure 307. Counter reading with index gated on channel A and B. . . . .1162
Figure 308. Encoder mode behavior in case of narrow index pulse (IPOS[1:0] = 11) . . . . .1163
Figure 309. Counter reset Narrow index pulse (closer view, ARR = 0x07) . . . . .1164
Figure 310. Index behavior in x1 and x2 mode (IPOS[1:0] = 01) . . . . .1165
Figure 311. Directional index sensitivity . . . . .1165
Figure 312. Counter reset as function of FIDX bit setting . . . . .1166
Figure 313. Index blanking . . . . .1166
Figure 314. Index behavior in clock + direction mode, IPOS[0] = 1 . . . . .1167
Figure 315. Index behavior in directional clock mode, IPOS[0] = 1 . . . . .1167
Figure 316. State diagram for quadrature encoded signals . . . . .1168
Figure 317. Up-counting encoder error detection . . . . .1169
Figure 318. Down-counting encode error detection . . . . .1170
Figure 319. Encoder mode change with preload transferred on update (SMSPS = 0) . . . . .1171
Figure 320. Clock drift measure using directional clock mode . . . . .1172
Figure 321. Control circuit in reset mode . . . . .1174
Figure 322. Control circuit in gated mode . . . . .1175
Figure 323. Control circuit in trigger mode . . . . .1175
Figure 324. Control circuit in external clock mode 2 + trigger mode . . . . .1177
Figure 325. Master/Slave timer example . . . . .1177
Figure 326. Master/slave connection example with 1 channel only timers . . . . .1178
Figure 327. Gating TIM_slv with tim_oc1ref of TIM_mstr . . . . .1179
Figure 328. Gating TIM_slv with Enable of TIM_mstr . . . . .1180
Figure 329. Triggering TIM_slv with update of TIM_mstr . . . . .1181
Figure 330. Triggering TIM_slv with Enable of TIM_mstr . . . . .1181
Figure 331. Triggering TIM_mstr and TIM_slv with TIM_mstr tim_ti1 input . . . . .1182
Figure 332. TIM16/TIM17 block diagram . . . . .1227
Figure 333. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1231
Figure 334. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1231
Figure 335. Counter timing diagram, internal clock divided by 1 . . . . .1233
Figure 336. Counter timing diagram, internal clock divided by 2 . . . . .1233
Figure 337. Counter timing diagram, internal clock divided by 4 . . . . .1234
Figure 338. Counter timing diagram, internal clock divided by N . . . . .1234
Figure 339. Counter timing diagram, update event when ARPE = 0
(TIMx_ARR not preloaded) . . . . .		1235
Figure 340. Counter timing diagram, update event when ARPE = 1
(TIMx_ARR preloaded) . . . . .		1236
Figure 341. Update rate examples depending on mode and TIMx_RCR register settings . . . . .1237
Figure 342. Control circuit in normal mode, internal clock divided by 1 . . . . .1238
Figure 343. tim_ti2 external clock connection example . . . . .1238
Figure 344. Control circuit in external clock mode 1 . . . . .1239
Figure 345. Capture/compare channel (example: channel 1 input stage) . . . . .1240
Figure 346. Capture/compare channel 1 main circuit . . . . .1240
Figure 347. Output stage of capture/compare channel (channel 1) . . . . .1241
Figure 348. Output compare mode, toggle on tim_oc1 . . . . .1244
Figure 349. Edge-aligned PWM waveforms (ARR = 8) . . . . .1245
Figure 350. Dithering principle . . . . .1246
Figure 351. Data format and register coding in dithering mode . . . . .1246
Figure 352. PWM resolution vs frequency . . . . .1247
Figure 353. PWM dithering pattern . . . . .1248
Figure 354. Complementary output with symmetrical dead-time insertion. . . . .1250
Figure 355. Asymmetrical deadtime . . . . .1250
Figure 356. Dead-time waveforms with delay greater than the negative pulse. . . . .1251
Figure 357. Dead-time waveforms with delay greater than the positive pulse. . . . .1251
Figure 358. Break circuitry overview . . . . .1253
Figure 359. Output behavior in response to a break event on tim_brk . . . . .1255
Figure 360. Output redirection . . . . .1257
Figure 361. tim_ocref_clr input selection multiplexer. . . . .1258
Figure 362. 6-step generation, COM example (OSSR = 1) . . . . .1259
Figure 363. Example of one pulse mode. . . . .1260
Figure 364. LPTIM block diagram (1) . . . . .1293
Figure 365. Glitch filter timing diagram . . . . .1297
Figure 366. LPTIM output waveform, single-counting mode configuration
when repetition register content is different than zero (with PRELOAD = 1) . . . . .		1299
Figure 367. LPTIM output waveform, single-counting mode configuration
and Set-once mode activated (WAVE bit is set). . . . .		1299
Figure 368. LPTIM output waveform, Continuous counting mode configuration . . . . .1300
Figure 369. Waveform generation . . . . .1301
Figure 370. Encoder mode counting sequence . . . . .1305
Figure 371. Continuous counting mode when repetition register LPTIM_RCR
different from zero (with PRELOAD = 1). . . . .		1306
Figure 372. Capture/compare input stage (channel 1) . . . . .1307
Figure 373. Capture/compare output stage (channel 1) . . . . .1307
Figure 374. Edge-aligned PWM mode (PRELOAD = 1) . . . . .1309
Figure 375. Edge-aligned PWM waveforms (ARR=8 and CCxP = 0) . . . . .1310
Figure 376. PWM mode with immediate update versus preloaded update . . . . .1311
Figure 377. IRTIM internal hardware connections with TIM16 and TIM17 . . . . .1337
Figure 378. Independent watchdog block diagram . . . . .1339
Figure 379. Reset timing due to timeout . . . . .1341
Figure 380. Reset timing due to refresh in the not allowed area . . . . .1342
Figure 381. Changing PR, RL, and performing a refresh (1) . . . . .1343
Figure 382. Window comparator update (1) . . . . .1344
Figure 383. Independent watchdog interrupt timing diagram. . . . .1346
Figure 384. Early wake-up comparator update (1) . . . . .1347
Figure 385. Watchdog block diagram . . . . .1355
Figure 386. Window watchdog timing diagram . . . . .1357
Figure 387. RTC block diagram . . . . .1362
Figure 388. TAMP block diagram . . . . .1416
Figure 389. Backup registers protection zones . . . . .1421
Figure 390. Tamper sampling with precharge pulse . . . . .1426
Figure 391. Low level detection with precharge and filtering . . . . .1426
Figure 392. Active tamper filtering . . . . .1428
Figure 393. Block diagram . . . . .1463
Figure 394. I 2 C-bus protocol . . . . .1466
Figure 395. Setup and hold timings . . . . .1468
Figure 396. I2C initialization flow . . . . .1470
Figure 397. Data reception . . . . .1471
Figure 398. Data transmission . . . . .1472
Figure 399.Target initialization flow . . . . .1475
Figure 400.Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . .1477
Figure 401.Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . .1478
Figure 402.Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . .1479
Figure 403.Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . .1480
Figure 404.Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . .1481
Figure 405.Transfer bus diagrams for I2C target receiver
(mandatory events only) . . . . .		1481
Figure 406.Controller clock generation . . . . .1483
Figure 407.Controller initialization flow . . . . .1485
Figure 408.10-bit address read access with HEAD10R = 0 . . . . .1485
Figure 409.10-bit address read access with HEAD10R = 1 . . . . .1486
Figure 410.Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes. . . . .1487
Figure 411.Transfer sequence flow for I2C controller transmitter, N > 255 bytes. . . . .1488
Figure 412.Transfer bus diagrams for I2C controller transmitter
(mandatory events only) . . . . .		1489
Figure 413.Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes . . . . .1491
Figure 414.Transfer sequence flow for I2C controller receiver, N > 255 bytes. . . . .1492
Figure 415.Transfer bus diagrams for I2C controller receiver
(mandatory events only) . . . . .		1493
Figure 416.Timeout intervals for \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \) . . . . .1497
Figure 417.Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . .1500
Figure 418.Transfer bus diagram for SMBus target transmitter (SBC = 1). . . . .1501
Figure 419.Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . .1502
Figure 420.Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . .1503
Figure 421.Bus transfer diagrams for SMBus controller transmitter . . . . .1504
Figure 422.Bus transfer diagrams for SMBus controller receiver . . . . .1506
Figure 423.USART block diagram . . . . .1532
Figure 424.Word length programming . . . . .1536
Figure 425.Configurable stop bits . . . . .1538
Figure 426.TC/TXE behavior when transmitting . . . . .1540
Figure 427.Start bit detection when oversampling by 16 or 8. . . . .1541
Figure 428.usart_ker_ck clock divider block diagram. . . . .1544
Figure 429.Data sampling when oversampling by 16. . . . .1545
Figure 430.Data sampling when oversampling by 8. . . . .1546
Figure 431.Mute mode using Idle line detection . . . . .1553
Figure 432.Mute mode using address mark detection . . . . .1554
Figure 433.Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . .1557
Figure 434.Break detection in LIN mode vs. Framing error detection. . . . .1558
Figure 435.USART example of synchronous master transmission. . . . .1559
Figure 436.USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . .		1559
Figure 437.USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . .		1560
Figure 438.USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . .		1561
Figure 439.ISO 7816-3 asynchronous protocol . . . . .1563
Figure 440.Parity error detection using the 1.5 stop bits . . . . .1565
Figure 441.IrDA SIR ENDEC block diagram. . . . .1569
Figure 442.IrDA data modulation (3/16) - normal mode . . . . .1569
Figure 443.Transmission using DMA . . . . .1571
Figure 444.Reception using DMA. . . . .1572
Figure 445. Hardware flow control between two USARTs . . . . .1572
Figure 446. RS232 RTS flow control . . . . .1573
Figure 447. RS232 CTS flow control . . . . .1574
Figure 448. LPUART block diagram . . . . .1621
Figure 449. LPUART word length programming . . . . .1625
Figure 450. Configurable stop bits . . . . .1627
Figure 451. TC/TXE behavior when transmitting . . . . .1629
Figure 452. lpuart_ker_ck clock divider block diagram . . . . .1633
Figure 453. Mute mode using Idle line detection . . . . .1637
Figure 454. Mute mode using address mark detection . . . . .1638
Figure 455. Transmission using DMA . . . . .1640
Figure 456. Reception using DMA . . . . .1641
Figure 457. Hardware flow control between two LPUARTs . . . . .1642
Figure 458. RS232 RTS flow control . . . . .1642
Figure 459. RS232 CTS flow control . . . . .1643
Figure 460. SPI block diagram . . . . .1677
Figure 461. Full-duplex single master/ single slave application . . . . .1681
Figure 462. Half-duplex single master/ single slave application . . . . .1681
Figure 463. Simplex single master / single slave application
(master in transmit-only / slave in receive-only mode) . . . . .		1683
Figure 464. Master and three independent slaves connected in star topology . . . . .1684
Figure 465. Master and three slaves connected in circular (daisy chain) topology . . . . .1686
Figure 466. Multimaster application . . . . .1687
Figure 467. Scheme of NSS control logic . . . . .1689
Figure 468. Data flow timing control (SSOE = 1, SSOM = 0, SSM = 0) . . . . .1689
Figure 469. NSS interleaving pulses between data (SSOE = 1, SSOM = 1, SSM = 0) . . . . .1690
Figure 470. Data clock timing diagram . . . . .1692
Figure 471. Data alignment when data size is not equal to 8, 16 or 32 bits . . . . .1693
Figure 472. TI mode transfer . . . . .1703
Figure 473. Optional configurations of the slave behavior when an underrun condition is detected . . . . .1705
Figure 474. SAI functional block diagram . . . . .1730
Figure 475. Audio frame . . . . .1733
Figure 476. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .1736
Figure 477. FS role is start of frame (FSDEF = 0) . . . . .1737
Figure 478. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .1738
Figure 479. First bit offset . . . . .1738
Figure 480. Audio block clock generator overview . . . . .1740
Figure 481. PDM typical connection and timing . . . . .1744
Figure 482. Detailed PDM interface block diagram . . . . .1745
Figure 483. Start-up sequence . . . . .1746
Figure 484. SAI_ADR format in TDM mode, 32-bit slot width . . . . .1747
Figure 485. SAI_ADR format in TDM mode, 16-bit slot width . . . . .1748
Figure 486. SAI_ADR format in TDM mode, 8-bit slot width . . . . .1749
Figure 487. AC'97 audio frame . . . . .1752
Figure 488. SPDIF format . . . . .1753
Figure 489. SAI_xDR register ordering . . . . .1754
Figure 490. Data companding hardware in an audio block in the SAI . . . . .1757
Figure 491. Tristate strategy on SD output line on an inactive slot . . . . .1759
Figure 492. Tristate on output data line in a protocol like I2S . . . . .1760
Figure 493. Overrun detection error . . . . .1761
Figure 494. FIFO underrun event . . . . .1761
Figure 495. OTG high-speed block diagram . . . . .1797
Figure 496. OTG A-B device connection . . . . .1799
Figure 497. OTG peripheral-only connection . . . . .1800
Figure 498. OTG host-only connection . . . . .1804
Figure 499. SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . .1808
Figure 500. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . .1810
Figure 501. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . .1811
Figure 502. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . .1812
Figure 503. Interrupt hierarchy . . . . .1816
Figure 504. Transmit FIFO write task . . . . .1909
Figure 505. Receive FIFO read task . . . . .1910
Figure 506. Normal bulk/control OUT/SETUP . . . . .1911
Figure 507. Bulk/control IN transactions . . . . .1915
Figure 508. Normal interrupt OUT . . . . .1918
Figure 509. Normal interrupt IN . . . . .1923
Figure 510. Isochronous OUT transactions . . . . .1925
Figure 511. Isochronous IN transactions . . . . .1928
Figure 512. Normal bulk/control OUT/SETUP transactions - DMA . . . . .1930
Figure 513. Normal bulk/control IN transaction - DMA . . . . .1932
Figure 514. Normal interrupt OUT transactions - DMA mode . . . . .1933
Figure 515. Normal interrupt IN transactions - DMA mode . . . . .1934
Figure 516. Normal isochronous OUT transaction - DMA mode . . . . .1935
Figure 517. Normal isochronous IN transactions - DMA mode . . . . .1936
Figure 518. Receive FIFO packet read . . . . .1942
Figure 519. Processing a SETUP packet . . . . .1944
Figure 520. Bulk OUT transaction . . . . .1951
Figure 521. TRDT max timing case . . . . .1960
Figure 522. Block diagram of debug support infrastructure . . . . .1963
Figure 523. JTAG TAP state machine . . . . .1967
Figure 524. AP0: CoreSight topology . . . . .1985
Figure 525. CPU CoreSight topology . . . . .1994
Figure 526. Trace port interface unit (TPIU) . . . . .2063
Figure 527. Embedded cross trigger . . . . .2075

Chapters