17. Comparator (COMP)

17.1 Introduction

The devices embed COMP1 and COMP2 (the last on STM32U073xx and STM32U083xx only) ultra-low-power comparators.

The comparators can be used for a variety of functions including:

• Wakeup from low-power mode triggered by an analog signal,
• Analog signal conditioning,
• Cycle-by-cycle current control loop when combined with a PWM output from a timer.

17.2 COMP main features

• Each comparator has configurable plus and minus inputs used for flexible voltage selection:
- – Multiplexed I/O pins
- – DAC Channel1
- – Internal reference voltage and three submultiple values (1/4, 1/2, 3/4) provided by scaler (buffered voltage divider)
• Programmable hysteresis
• Programmable speed / consumption
• The outputs can be redirected to an I/O or to timer inputs for triggering:
- – Break events for fast PWM shutdowns
• Comparator outputs with blanking source
• The two comparators can be combined in a window comparator
• Each comparator has interrupt generation capability with wakeup from Sleep and Stop modes (through the EXTI controller)

17.3 COMP functional description

17.3.1 COMP block diagram

The block diagram of the comparators is shown in Figure 66 .

Figure 66. Comparator block diagram

Figure 66. Comparator block diagram. The diagram shows the internal architecture of the COMPx block. It includes a 32-bit APB bus, comp_pclk, COMPx_INPy, compy_inp, COMPx_INMy, DAC_CH1, V_REFINT, 3/4 V_REFINT, 1/2 V_REFINT, 1/4 V_REFINT, COMPx_INPSEL, COMPx_WINMODE, compx_inp, COMPx_INMSEL, compx_inm, COMPx, COMPx_POLARITY, COMPx_VALUE, Blank source, COMPx_WINOUT, compx_out, COMPx_OUT GPIO alternate function, Wakeup EXTI line interrupt, and TIMERS. The diagram is labeled MSv71273V1.

17.3.2 COMP pins and internal signals

The I/Os used as comparators inputs must be configured in analog mode in the GPIOs registers.

The comparator output can be connected to the I/Os using the alternate function channel given in “Alternate function mapping” table in the datasheet. The output can also be internally redirected to a variety of timer input for the following purposes:

• Emergency shut-down of PWM signals, using BKIN and BKIN2 inputs
• Cycle-by-cycle current control, using OCREF_CLR inputs
• Input capture for timing measures

It is possible to have the comparator output simultaneously redirected internally and externally.

Table 88. COMP internal input/output signals

Signal name	Signal type	Description
compx_inm	Analog input	Inverting input source for COMPx
compy_inp	Analog input	Noninverting input for COMPy
comp_pclk	Digital input	APB clock for both COMP channels
compx_out	Digital output	COMPx output

Table 89. COMP1 noninverting input assignment

COMP1_INP	COMP1 INPSEL[2:0] ⁽¹⁾
COMP1_INP1	000
COMP1_INP2	001
COMP1_INP3	010
COMP1_INP4	011
COMP1_INP5	100
Not connected	101

1. Other combinations are reserved.

Table 90. COMP1 inverting input assignment

COMP1_INM	COMP1 INMSEL[3:0] ⁽¹⁾
$\frac{1}{4} V_{REFINT}$	0000
$\frac{1}{2} V_{REFINT}$	0001
$\frac{3}{4} V_{REFINT}$	0010
$V_{REFINT}$	0011
DAC Channel1	0100
COMP1_INM1	0101
COMP1_INM2	0110
COMP1_INM3	0111
COMP1_INM4	1000
COMP1_INM5	1001

1. Other combinations are reserved.

Table 91. COMP2 noninverting input assignment

COMP2_INP	COMP2 INPSEL[1:0]
COMP2_INP1	00
COMP2_INP2	01
COMP2_INP3	10
COMP2_INP4	11

Table 92. COMP2 inverting input assignment

COMP2_INM	COMP2 INMSEL[3:0] ⁽¹⁾
$\frac{1}{4} V_{REFINT}$	0000
$\frac{1}{2} V_{REFINT}$	0001
$\frac{3}{4} V_{REFINT}$	0010
$V_{REFINT}$	0011

Table 92. COMP2 inverting input assignment (continued)

COMP2_INM	COMP2_INMSEL[3:0] ⁽¹⁾
DAC Channel1	0100
COMP2_INM1	0101
COMP2_INM2	0110
COMP2_INM3	0111
COMP2_INM4	1000
COMP2_INM5	1001

1. Other combinations are reserved.

17.3.3 COMP reset and clocks

The COMP clock provided by the clock controller is synchronous with the APB clock.

There is no clock enable control bit provided in the RCC controller. Reset and clock enable bits are common for COMP and SYSCFG.

Important: The polarity selection logic and the output redirection to the port works independently from the APB clock. This allows the comparator to work even in Stop mode.

17.3.4 Comparator LOCK mechanism

The comparators can be used for safety purposes, such as over-current or thermal protection. For applications having specific functional safety requirements, it is necessary to insure that the comparator programming cannot be altered in case of spurious register access or program counter corruption.

For this purpose, the comparator control and status registers can be write-protected (read-only).

Once the programming is completed, the COMPx LOCK bit can be set to 1. This causes the whole register to become read-only, including the COMPx LOCK bit.

The write protection can only be reset by a MCU reset.

17.3.5 Window comparator

The purpose of window comparator is to monitor the analog voltage if it is within specified voltage range defined by lower and upper threshold.

COMP1 and COMP2 can combine to create a window comparator. The monitored analog voltage is connected to the noninverting (plus) inputs of comparators connected together and the upper and lower threshold voltages are connected to the inverting (minus) inputs of the comparators. Two noninverting inputs can be connected internally together by enabling WINMODE bit to save one IO for other purposes.

Figure 67. Window mode

Schematic diagram of window mode using two comparators, COMPx and COMPy. COMPx has WINMODE = 0 and its output (COMPx_VALUE) is connected to one input of an OR gate. COMPy has WINMODE = 1 and its output (COMPy_VALUE) is connected to the other input of the same OR gate. The output of the OR gate is COMPx_OUT. The input is connected to COMPx_INP and COMPy_INP. The upper threshold is connected to COMPx_INM and the lower threshold is connected to COMPy_INM. Labels indicate COMPx WINOUT = 1 and COMPy WINOUT = 0.

17.3.6 Hysteresis

The comparator includes a programmable hysteresis to avoid spurious output transitions in case of noisy signals. The hysteresis can be disabled if it is not needed (for instance when exiting from low-power mode) to be able to force the hysteresis value using external components.

Figure 68. Comparator hysteresis

Timing diagram showing the effect of hysteresis on a comparator. The top graph shows the input signal (INP) oscillating between INM and INM - V_hyst. The bottom graph shows the output signal (COMP_OUT) as a square wave that transitions only when the input crosses the hysteresis thresholds, preventing spurious transitions due to noise.

17.3.7 Comparator output blanking function

The purpose of the blanking function is to prevent the current regulation to trip upon short current spikes at the beginning of the PWM period (typically the recovery current in power switches anti parallel diodes). It consists of a selection of a blanking window which is a timer output compare signal. The selection is done by software (refer to the comparator register description for possible blanking signals). Then, the complementary of the blanking signal is ANDed with the comparator output to provide the wanted comparator output. See the example provided in the figure below.

Figure 69. Comparator output blanking

Timing diagram for comparator output blanking. The diagram shows five waveforms: PWM, Current limit, Current, Raw comp output, and Final comp output. The PWM signal is a square wave. The Current limit is a dashed horizontal line. The Current signal is a sawtooth-like waveform that rises and falls, crossing the Current limit line. The Raw comp output is a pulse that goes high when the Current signal crosses the Current limit line. The Blanking window is a pulse that is high during the rising edge of the Current signal. The Final comp output is the AND of the Raw comp output and the inverted Blanking window signal. Below the waveforms, a logic diagram shows an AND gate with inputs 'Comp out' and 'Blank' (inverted). The output of the AND gate is labeled 'Comp out (to TIM_BK ...)'. The diagram is labeled MS30964V1.

17.3.8 COMP power and speed modes

COMPx power consumption versus propagation delay can be adjusted to have the optimum trade-off for a given application.

The PWRMODE[1:0] bitfields of the COMPx_CSR registers allow setting the comparators to high speed with full power or medium speed with medium power. Refer to Section 17.6: COMP registers .

17.4 COMP low-power modes

Table 93. Comparator behavior in the low-power modes

Mode	Description
Sleep	No effect on the comparators. Comparator interrupts cause the device to exit the Sleep mode.
Low-power run	No effect.
Low-power sleep	No effect. COMP interrupts cause the device to exit the Low-power sleep mode.
Stop 0	No effect on the comparators. Comparator interrupts cause the device to exit the Stop mode.
Stop 1

Table 93. Comparator behavior in the low-power modes (continued)

Mode	Description
Standby	The COMP registers are powered down and must be reinitialized after exiting Standby or Shutdown mode.
Shutdown

17.5 COMP interrupts

The comparator outputs are internally connected to the Extended interrupts and events controller. Each comparator has its own EXTI line and can generate either interrupts or events. The same mechanism is used to exit from low-power modes.

Refer to Interrupt and events section for more details.

To enable COMPx interrupt, it is required to follow this sequence:

1. Configure and enable the EXTI line corresponding to the COMPx output event in interrupt mode and select the rising, falling or both edges sensitivity
2. Configure and enable the NVIC IRQ channel mapped to the corresponding EXTI lines
3. Enable COMPx.

Table 94. Interrupt control bits

Interrupt event	Enable control bit	Exit from Sleep mode	Exit from Stop modes	Exit from Standby mode
COMP1 output	Through EXTI	Yes	Yes	N/A
COMP2 output	Through EXTI	Yes	Yes	N/A

17.6 COMP registers

17.6.1 Comparator 1 control and status register (COMP1_CSR)

Address offset: 0x00

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK	VALUE	Res.	Res.	Res.	Res.	Res.	BLANKSEL[4:0]					PWRMODE[1:0]	HYST[1:0]
rs	r						rw	rw	rw	rw	rw	rw	rw	rw	rw

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POLARITY	WINOUT	Res.	Res.	WINMODE	INPSEL[2:0]				INMSEL[3:0]				Res.	Res.	EN
rw	rw			rw	rw	rw	rw	rw	rw	rw	rw				rw

Bit 31 LOCK : COMP1_CSR register lock

This bit is set by software and cleared by a system reset. It locks the comparator 3 control bits. When locked, all register bits are read-only.

0: Not locked

1: Locked

Bit 30 VALUE : Comparator 1 output status

This bit is read-only. It reflects the level of the comparator 1 output after the polarity selector and blanking, as indicated in Figure 66 .

Bits 29:25 Reserved, must be kept at reset value.

Bits 24:20 BLANKSEL[4:0] : Comparator 1 blanking source selector

This bitfield is controlled by software (if not locked). It selects the blanking source:

00000: No blanking

00001: TIM1 OC4 enabled as blanking source

00010: TIM1 OC5 enabled as blanking source

00100: TIM2 OC3 enabled as blanking source

01000: TIM3 OC3 enabled as blanking source

10000: TIM15 OC2 enabled as blanking source

Others: Reserved, must not be used

Bits 19:18 PWRMODE[1:0] : Comparator 1 power mode selector

This bitfield is controlled by software (if not locked). It selects the power consumption and as a consequence the speed of the comparator 1:

00: High speed/high power

01-10: Medium speed/medium power

11: Low speed/low power

Bits 17:16 HYST[1:0] : Comparator 1 hysteresis selector

This bitfield is controlled by software (if not locked). It selects the hysteresis of the comparator 1:

00: No hysteresis

01: Low hysteresis

10: Medium hysteresis

11: High hysteresis

Bit 15 POLARITY : Comparator 1 polarity selector

This bit is controlled by software (if not locked). It selects the comparator 1 output polarity:

0: Non-inverted

1: Inverted

Bit 14 WINOUT : Comparator 1 output selector

This bit is controlled by software (if not locked). It selects the comparator 1 output:

0: COMP1_VALUE

1: COMP1_VALUE XOR COMP2_VALUE (required for window mode, see Figure 67 )

Bits 13:12 Reserved, must be kept at reset value.

Bit 11 WINMODE : Comparator 1 noninverting input selector for window mode

This bit is controlled by software (if not locked). It selects the signal for COMP1_INP input of the comparator 1:

0: Signal selected with INPSEL[2:0] bitfield of this register

1: COMP2_INP signal of the comparator 2 (required for window mode, see Figure 67 )

Bits 10:8 INPSEL[2:0] : Comparator 1 signal selector for noninverting input

This bitfield is controlled by software (if not locked). It selects the signal for the noninverting input COMP1_INP of the comparator 1 (also see the WINMODE bit):

Refer to Table 89: COMP1 noninverting input assignment .

Bits 7:4 INMSEL[3:0] : Comparator 1 signal selector for inverting input INM

This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP1_INM of the comparator 1:

Refer to Table 90: COMP1 inverting input assignment .

Bits 3:1 Reserved, must be kept at reset value.

Bit 0 EN : Comparator 1 enable bit

This bit is controlled by software (if not locked). It enables the comparator 1:

0: Disable

1: Enable

17.6.2 Comparator 2 control and status register (COMP2_CSR)

Address offset: 0x04

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK	VALUE	Res.	Res.	Res.	Res.	Res.	BLANKSEL[4:0]					PWRMODE[1:0]		HYST[1:0]
rs	r						rw	rw	rw	rw	rw	rw	rw	rw	rw

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POLARITY	WINOUT	Res.	Res.	WINMODE	Res.	INPSEL[1:0]		INMSEL[3:0]				Res.	Res.	Res.	EN
rw	rw			rw		rw	rw	rw	rw	rw	rw				rw

Bit 31 LOCK : COMP2_CSR register lock

This bit is set by software and cleared by a system reset. It locks the comparator 3 control bits. When locked, all register bits are read-only.

0: Not locked

1: Locked

Bit 30 VALUE : Comparator 2 output status

This bit is read-only. It reflects the level of the comparator 2 output after the polarity selector and blanking, as indicated in Figure 66 .

Bits 29:25 Reserved, must be kept at reset value.

Bits 24:20 BLANKSEL[4:0] : Comparator 2 blanking source selector

This bitfield is controlled by software (if not locked). It selects the blanking source:

00000: No blanking

00001: TIM1_OC4 enabled as blanking source

00010: TIM1_OC5 enabled as blanking source

00100: TIM2_OC3 enabled as blanking source

01000: TIM3_OC3 enabled as blanking source

10000: TIM15_OC2 enabled as blanking source

Others: Reserved, must not be used

Bits 19:18 PWRMODE[1:0] : Comparator 2 power mode selector

This bitfield is controlled by software (if not locked). It selects the power consumption and as a consequence the speed of the comparator 2:

00: High speed/high power

01-10: Medium speed/medium power

11: Low speed/low power

Bits 17:16 HYST[1:0] : Comparator 2 hysteresis selector

This bitfield is controlled by software (if not locked). It selects the hysteresis of the comparator 2:

00: No hysteresis

01: Low hysteresis

10: Medium hysteresis

11: High hysteresis

Bit 15 POLARITY : Comparator 2 polarity selector

This bit is controlled by software (if not locked). It selects the comparator 2 output polarity:

0: Non-inverted

1: Inverted

Bit 14 WINOUT : Comparator 2 output selector

This bit is controlled by software (if not locked). It selects the comparator 2 output:

0: COMP2_VALUE

1: COMP1_VALUE XOR COMP2_VALUE (required for window mode, see Figure 67 )

Bits 13:12 Reserved, must be kept at reset value.

Bit 11 WINMODE : Comparator 2 noninverting input selector for window mode

This bit is controlled by software (if not locked). It selects the signal for COMP2_INP input of the comparator 2:

0: Signal selected with INPSEL[1:0] bitfield of this register

1: COMP1_INP signal of the comparator 1 (required for window mode, see Figure 67 )

Bit 10 Reserved, must be kept at reset value.

Bits 9:8 INPSEL[1:0] : Comparator 2 signal selector for noninverting input

This bitfield is controlled by software (if not locked). It selects the signal for the noninverting input COMP2_INP of the comparator 2 (also see the WINMODE bit):

Refer to Table 91: COMP2 noninverting input assignment .

Bits 7:4 INMSEL[3:0] : Comparator 2 signal selector for inverting input INM

This bitfield is controlled by software (if not locked). It selects the signal for the inverting input COMP2_INM of the comparator 2:

Refer to Table 92: COMP2 inverting input assignment .

Bits 3:1 Reserved, must be kept at reset value.

Bit 0 EN : Comparator 2 enable bit

This bit is controlled by software (if not locked). It enables the comparator 2:

0: Disable

1: Enable

17.6.3 COMP register map

The following table summarizes the comparator registers.

The comparator registers share SYSCFG peripheral register base addresses.

Table 95. COMP register map and reset values

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x00	COMP1_CSR	LOCK	VALUE	Res.	Res.	Res.	Res.	Res.	BLANKSEL[4:0]					PWRMODE[1:0]		HYST[1:0]		POL	WINOUT	Res.	Res.	WINMODE	INPSEL[2:0]			INMSEL[3:0]				Res.	Res.	Res.	EN
0x00	Reset value	0	0						0	0	0	0	0	0	0	0	0	0	0			0	0	0	0	0	0	0	0				0
0x04	COMP2_CSR	LOCK	VALUE	Res.	Res.	Res.	Res.	Res.	BLANKSEL[4:0]					PWRMODE[1:0]		HYST[1:0]		POL	WINOUT	Res.	Res.	WINMODE	INPSEL[2:0]			INMSEL[3:0]				Res.	Res.	Res.	EN
0x04	Reset value	0	0						0	0	0	0	0	0	0	0	0	0	0			0	0	0	0	0	0	0	0				0

Refer to Section 2.2 on page 55 for the register boundary addresses.