15. Digital-to-analog converter (DAC)

15.1 Introduction

The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data can be left- or right-aligned. The DAC features one single channel. An input reference pin, VREF+ (shared with others analog peripherals) is available for better resolution. An internal reference can also be set on the same input. Refer to voltage reference buffer (VREFBUF) section.

The DACx_OUT1 pin can be used as general purpose input/output (GPIO) when the DAC output is disconnected from output pad and connected to an on-chip peripheral. The DAC output buffer can be optionally enabled to obtain a high drive output current. A calibration can be applied on the DAC output channel. The DAC output channel supports a low power mode, the sample and hold mode.

15.2 DAC main features

The DAC main features are the following (see Figure 58: DAC block diagram )

• One DAC interface, one output channel
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave and Triangular-wave generation
• DMA capability including DMA underrun error detection
• External triggers for conversion
• DAC output channel buffered/unbuffered modes
• Buffer offset calibration
• The DAC output can be disconnected from the DACx_OUT1 output pin
• DAC output connection to on-chip peripherals
• Sample and hold mode for low power operation in Stop mode
• Input voltage reference from VREF+ pin or internal VREFBUF reference

Figure 58 shows the block diagram of a DAC channel and Table 78 gives the pin description.

15.3 DAC implementation

Table 77. DAC features

DAC features	DAC
Dual channel	-
Output buffer	X
I/O connection	DAC_OUT1 to PA4
Maximum sampling time	1 Msps
Autonomous mode	-
VREF+ pin	X

15.4 DAC functional description

15.4.1 DAC block diagram

Figure 58. DAC block diagram

Figure 58. DAC block diagram. The diagram shows the internal architecture of the DAC. On the left, a 32-bit APB bus connects to 'Control registers and logic channel1'. This block has inputs for dac_ch1_trg1 through dac_ch1_trg15, dac_ch1_dma, dac_unr_it, dac_pclk, and dac_hold_ck. It outputs TRIG, TSEL1 [3:0] bits, and a 12-bit signal to the 'DAC converter'. Above the DAC converter are 'Offset calibration' blocks for OTRIM1[4:0] bits, MODE1 bits, and DOR1. The 'DAC converter' is connected to a 'Buffer' and 'Sample and hold registers' (containing TSAMPLE1, THOLD1, and TREFRESH1). The Buffer outputs DAC_OUT1. The Sample and hold registers output dac_out1. Power pins VDD and Vss are shown at the top and bottom respectively. VREF+ is shown on the right. The diagram is labeled MSV61355V6.

1. MODE1 bits in the DAC_MCR control the output mode and allow switching between the normal mode in buffer/unbuffered configuration and the sample and hold mode.

15.4.2 DAC pins and internal signals

The DAC includes:

• One output channel
• The DACx_OUT1 can be disconnected from the output pin and used as an ordinary GPIO
• The dac_outx can use an internal pin connection to on-chip peripherals such as comparator, operational amplifier and ADC (if available).
• DAC output channel buffered or non buffered
• Sample and hold block and registers operational in Stop mode, using the LSI clock source (dac_hold_ck) for static conversion.

The DAC includes one output channel. The output channel can be connected to on-chip peripherals such as comparator, operational amplifier and ADC (if available). In this case, the DAC output channel can be disconnected from the DACx_OUT1 output pin and the corresponding GPIO can be used for another purpose.

The DAC output can be buffered or not. The sample and hold block and its associated registers can run in Stop mode using the LSI clock source (dac_hold_ck).

Table 78. DAC input/output pins

Pin name	Signal type	Remarks
VREF+	Input, analog positive reference	The higher/positive reference voltage for the DAC, $V_{REF+} \leq V_{DDAmax}$ (refer to datasheet)
VDD	Input, analog supply	Analog power supply
VSS	Input, analog supply ground	Ground for analog power supply
DACx_OUT1	Analog output signal	DACx channel1 analog output

Table 79. DAC internal input/output signals

Internal signal name	Signal type	Description
dac_ch1_dma	Bidirectional	DAC channel1 DMA request/acknowledge
dac_ch1_trgx (x = 1 to 14)	Inputs	DAC channel1 trigger inputs/acknowledge
dac_unr_it	Output	DAC underrun interrupt
dac_pclk	Input	DAC peripheral clock
dac_hold_ck	Input	DAC low-power clock used in sample and hold mode
dac_out1	Analog output	DAC channel1 output for on-chip peripherals

Table 80. DAC interconnection

Signal name	Source	Source type
dac_hold_ck	ck_lsi	LSI clock
dac_ch1_trg1	tim1_trgo	Internal signal from on-chip timers TIM1_TGO_CKTIM

Table 80. DAC interconnection (continued)

Signal name	Source	Source type
dac_ch1_trg2	tim2_trgo	Internal signal from on-chip timers TIM2_TGO_CKTIM
dac_ch1_trg3	tim3_trgo	internal signal from on-chip timers TIM3_TGO_CKTIM
dac_ch1_trg5	tim6_trgo	internal signal from on-chip timers TIM6_TGO_CKTIM
dac_ch1_trg6	tim7_trgo	internal signal from on-chip timers TIM7_TGO_CKTIM
dac_ch1_trg8	tim15_trgo	internal signal from on-chip timers TIM15_TGO_CKTIM
dac_ch1_trg11	lptim1_out	Internal signal from on-chip timers LPTIM1_OUT
dac_ch1_trg12	lptim2_out	Internal signal from on-chip timers LPTIM2_OUT
dac_ch1_trg14	exti9	External pin EXTI[9]

15.4.3 DAC channel enable

The DAC channel can be powered on by setting its corresponding EN1 bit in the DAC_CR register. The DAC channel is then enabled after a $t_{\text{WAKEUP}}$ startup time.

Note: The EN1 bit enables the analog DAC channel1 only. The DAC channel1 digital interface is enabled even if the EN1 bit is reset.

15.4.4 DAC data format

Depending on the selected configuration mode, the data have to be written into the specified register as described below:

• Single DAC channel
There are three possibilities:
- – 8-bit right alignment: the software has to load data into the DAC_DHR8R1[7:0] bits (stored into the DHR1[11:4] bits)
- – 12-bit left alignment: the software has to load data into the DAC_DHR12L1 [15:4] bits (stored into the DHR1[11:0] bits)
- – 12-bit right alignment: the software has to load data into the DAC_DHR12R1 [11:0] bits (stored into the DHR1[11:0] bits)

Depending on the loaded DAC_DHRyyxx register, the data written by the user is shifted and stored into the corresponding DAC_DHR1 (data holding registerx, which are internal non-memory-mapped registers). The DAC_DHR1 register is then loaded into the DAC_DOR1 register either automatically, by software trigger or by an external event trigger.

Figure 59. Data registers in single DAC channel mode

Figure 59: Data registers in single DAC channel mode. A diagram showing three rows of a 32-bit register (bits 31 to 0). The first row is labeled '8-bit right aligned' and shows bits 7-0 shaded. The second row is labeled '12-bit left aligned' and shows bits 31-20 shaded. The third row is labeled '12-bit right aligned' and shows bits 19-0 shaded. The label 'ai14710b' is in the bottom right corner.

15.4.5 DAC conversion

The DAC_DOR1 cannot be written directly and any data transfer to the DAC channel1 must be performed by loading the DAC_DHR1 register (write operation to DAC_DHR8R1, DAC_DHR12L1, DAC_DHR12R1).

Data stored in the DAC_DHR1 register are automatically transferred to the DAC_DOR1 register after one dac_pclk clock cycle, if no hardware trigger is selected (TEN1 bit in DAC_CR register is reset). However, when a hardware trigger is selected (TEN1 bit in DAC_CR register is set) and a trigger occurs, the transfer is performed three dac_pclk clock cycles after the trigger signal.

When DAC_DOR1 is loaded with the DAC_DHR1 contents, the analog output voltage becomes available after a time $t_{\text{SETTLING}}$ that depends on the power supply voltage and the analog output load.

Figure 60. Timing diagram for conversion with trigger disabled TEN = 0

Figure 60: Timing diagram for conversion with trigger disabled TEN = 0. A timing diagram showing three signals: 'Bus clock' (a square wave), 'DHR' (Digital-to-Analog Register), and 'DOR' (Data Output Register). The DHR signal shows a value of 0x1AC being written. The DOR signal shows the value 0x1AC being updated one clock cycle later. The time interval between the DOR update and the 'Output voltage available on DAC_OUT pin' is labeled as t_SETTLING. The label 'MSV45319V2' is in the bottom right corner.

15.4.6 DAC output voltage

Digital inputs are converted to output voltages on a linear conversion between 0 and $V_{\text{REF+}}$ .

The analog output voltage on the DAC channel pin is determined by the following equation:

\text{DAC output} = V_{\text{REF}} \times \frac{\text{DOR}}{4096}

where all voltages are expressed in Volt.

15.4.7 DAC trigger selection

If the TEN1 control bit is set, the conversion can then be triggered by an external event (timer counter, external interrupt line). The TSEL1[3:0] control bits determine which out of 16 possible events triggers the conversion as shown in TSEL1[3:0] bits of the DAC_CR register. These events can be either the software trigger or hardware triggers. Refer to the interconnection table in Section 15.4.2 .

Each time a DAC interface detects a rising edge on the selected trigger source (refer to the table below), the last data stored into the DAC_DHR1 register are transferred into the DAC_DOR1 register. The DAC_DOR1 register is updated three dac_pclk cycles after the trigger occurs.

If the software trigger is selected, the conversion starts once the SWTRIG bit is set. SWTRIG is reset by hardware once the DAC_DOR1 register has been loaded with the DAC_DHR1 register contents.

Note: TSEL1[3:0] bit cannot be changed when the EN1 bit is set.

When software trigger is selected, the transfer from the DAC_DHR1 register to the DAC_DOR1 register takes only one dac_pclk clock cycle.

15.4.8 DMA requests

The DAC channel has a DMA capability. One DMA channel is used to service DAC channel DMA request.

When an external trigger (but not a software trigger) occurs while the DMAEN1 bit is set, the value of the DAC_DHR1 register is transferred into the DAC_DOR1 register when the transfer is complete, and a DMA request is generated.

As DAC_DHR1 to DAC_DOR1 data transfer occurred before the DMA request, the very first data has to be written to the DAC_DHR1 before the first trigger event occurs.

DMA underrun

The DAC DMA request is not queued so that if a second external trigger arrives before the acknowledgment for the first external trigger is received (first request), then no new request is issued and the DMA channel1 underrun flag DMAUDR1 in the DAC_SR register is set, reporting the error condition. The DAC channel1 continues to convert old data.

The software must clear the DMAUDR1 flag by writing 1, clear the DMAEN bit of the used DMA stream and re-initialize both DMA and DAC channel1 to restart the transfer correctly. The software must modify the DAC trigger conversion frequency or lighten the DMA workload to avoid a new DMA underrun. Finally, the DAC conversion can be resumed by enabling both DMA data transfer and conversion trigger.

For DAC channel1, an interrupt is also generated if its corresponding DMAUDRIE1 bit in the DAC_CR register is enabled.

15.4.9 Noise generation

In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift register) is available. DAC noise generation is selected by setting WAVE1[1:0] to 01. The preloaded value in LFSR is 0xAA. This register is updated three dac_pclk clock cycles after each trigger event, following a specific calculation algorithm.

Figure 61. DAC LFSR register calculation algorithm

Diagram of the DAC LFSR register calculation algorithm. It shows a 12-bit shift register with cells numbered 11 down to 0. The output of cell 0 is fed back through an XOR gate and also through a series of taps labeled X^12, X^6, X^4, X, and X^0. The output of the XOR gate is fed back into cell 11. The outputs of cells 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, and 0 are connected to a 12-input NOR gate. The output of the NOR gate is also fed back into cell 11. The diagram is labeled ai14713c.

The LFSR value, that may be masked partially or totally by means of the MAMP1[3:0] bits in the DAC_CR register, is added up to the DAC_DHR1 contents without overflow and this value is then transferred into the DAC_DOR1 register.

If LFSR is 0x0000, a 1 is injected into it (antilock-up mechanism).

It is possible to reset LFSR wave generation by resetting the WAVE1[1:0] bits.

Figure 62. DAC conversion (SW trigger enabled) with LFSR wave generation

Timing diagram showing four signals over time: Bus clock (a periodic square wave), DHR (Digital Hold Register, showing a value of 0x00), DOR (Digital Output Register, showing values 0xAAA and 0xD55), and SWTRIG (Software Trigger, showing two pulses). The DOR signal changes its value from 0xAAA to 0xD55 upon a rising edge of the SWTRIG signal. The diagram is labeled MSV45320V2.

Note: The DAC trigger must be enabled for noise generation by setting the TEN1 bit in the DAC_CR register.

15.4.10 Triangle-wave generation

It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. DAC triangle-wave generation is selected by setting WAVE1[1:0] to 10. The amplitude is configured through the MAMP1[3:0] bits in the DAC_CR register. An internal triangle counter is incremented three dac_pclk clock cycles after each trigger event. The value of this counter is then added to the DAC_DHR1 register without overflow and the sum is transferred into the DAC_DOR1 register. The triangle counter is incremented as long as it is less than the maximum amplitude defined by the MAMP1[3:0] bits. Once the configured amplitude is reached, the counter is decremented down to 0, then incremented again and so on.

It is possible to reset triangle wave generation by resetting the WAVE1[1:0] bits.

Figure 63. DAC triangle wave generation

The graph shows a triangular waveform. The vertical axis represents the DAC output value, with labels for '0', 'DAC_DHR1 base value', and 'MAMP1[3:0] max amplitude+ DAC_DHR1 base value'. The horizontal axis represents time. The waveform starts at the base value, rises linearly to the maximum amplitude, and then falls linearly back towards the base value. The rising slope is labeled 'Incrementation' and the falling slope is labeled 'Decrementation'. The text 'MSv61371V1' is in the bottom right corner.

Figure 63: DAC triangle wave generation graph showing a triangular waveform oscillating between a base value and a maximum amplitude.

Figure 64. DAC conversion (SW trigger enabled) with triangle wave generation

The timing diagram shows four signals over time: 'Bus clock' (a periodic square wave), 'DHR' (Digital-to-Analog Register), 'DOR' (Data Output Register), and 'SWTRIG' (Software Trigger). The DHR signal is initially 0xABE. The DOR signal starts at 0xABE, then changes to 0xABF, and then to 0xAC0. The SWTRIG signal is a pulse that triggers the conversion. Vertical dashed lines indicate the timing of the conversions. The text 'MS45321V2' is in the bottom right corner.

Figure 64: Timing diagram for DAC conversion with triangle wave generation, showing Bus clock, DHR, DOR, and SWTRIG signals.

Note: The DAC trigger must be enabled for triangle wave generation by setting the TEN1 bit in the DAC_CR register.

The MAMP1[3:0] bits must be configured before enabling the DAC, otherwise they cannot be changed.

15.4.11 DAC channel modes

The DAC channel can be configured in normal mode or sample and hold mode. The output buffer can be enabled to obtain a high drive capability. Before enabling output buffer, the voltage offset needs to be calibrated. This calibration is performed at the factory (loaded after reset) and can be adjusted by software during application operation.

Normal mode

In normal mode, there are four combinations, by changing the buffer state and by changing the DACx_OUT1 pin interconnections.

To enable the output buffer, the MODE1[2:0] bits in DAC_MCR register must be:

• 000: DAC is connected to the external pin
• 001: DAC is connected to external pin and to on-chip peripherals

To disable the output buffer, the MODE1[2:0] bits in DAC_MCR register must be:

• 010: DAC is connected to the external pin
• 011: DAC is connected to on-chip peripherals

Sample and hold mode

In sample and hold mode, the DAC core converts data on a triggered conversion, and then holds the converted voltage on a capacitor. When not converting, the DAC cores and buffer are completely turned off between samples and the DAC output is tri-stated, therefore reducing the overall power consumption. A stabilization period, which value depends on the buffer state, is required before each new conversion.

In this mode, the DAC core and all corresponding logic and registers are driven by the LSI low-speed clock (dac_hold_ck) in addition to the dac_pclk clock, allowing using the DAC channel in deep low power modes such as Stop mode.

The LSI low-speed clock (dac_hold_ck) must not be stopped when the sample and hold mode is enabled.

The sample/hold mode operations can be divided into three phases:

1. Sample phase: the sample/hold element is charged to the desired voltage. The charging time depends on capacitor value (internal or external, selected by the user). The sampling time is configured with the TSAMPLE1[9:0] bits in DAC_SHSR1 register. During the write of the TSAMPLE1[9:0] bits, the BWST1 bit in DAC_SR register is set to 1 to synchronize between both clocks domains (APB and low speed clock) and allowing the software to change the value of sample phase during the DAC channel operation
2. Hold phase: the DAC output channel is tri-stated, the DAC core and the buffer are turned off, to reduce the current consumption. The hold time is configured with the THOLD1[9:0] bits in DAC_SHHR register
3. Refresh phase: the refresh time is configured with the TREFRESH1[7:0] bits in DAC_SHRR register

The timings for the three phases above are in units of LSI clock periods. As an example, to configure a sample time of 350 $\mu\text{s}$ , a hold time of 2 ms and a refresh time of 100 $\mu\text{s}$ assuming LSI $\sim 32$ KHz is selected:

• 12 cycles are required for sample phase: TSAMPLE1[9:0] = 11.
• 62 cycles are required for hold phase: THOLD1[9:0] = 62.
• and 4 cycles are required for refresh period: TREFRESH1[7:0] = 4.

In this example, the power consumption is reduced by almost a factor of 15 versus normal modes.

The formulas to compute the right sample and refresh timings are described in the table below, the Hold time depends on the leakage current.

Table 81. Sample and refresh timings

Buffer State	$t_{\text{SAMP}}^{(1)(2)}$	$t_{\text{REFRESH}}^{(2)(3)}$
Enable	$7 \mu\text{s} + (10 * R_{\text{BON}} * C_{\text{SH}})$	$7 \mu\text{s} + (R_{\text{BON}} * C_{\text{SH}}) * \ln(2 * N_{\text{LSB}})$
Disable	$3 \mu\text{s} + (10 * R_{\text{BOFF}} * C_{\text{SH}})$	$3 \mu\text{s} + (R_{\text{BOFF}} * C_{\text{SH}}) * \ln(2 * N_{\text{LSB}})$

1. In the above formula, the settling to the desired code value with $\frac{1}{2}$ LSB or accuracy requires 10 constant time for 12 bits resolution. For 8-bit resolution, the settling time is 7 constant time.
2. $C_{\text{SH}}$ is the capacitor in sample and hold mode.
3. The tolerated voltage drop during the hold phase “Vd” is represented by the number of LSBs after the capacitor discharging with the output leakage current. The settling back to the desired value with $\frac{1}{2}$ LSB error accuracy requires $\ln(2 * N_{\text{lsb}})$ constant time of the DAC.

Example of the sample and refresh time calculation with output buffer on

The values used in the example below are provided as indication only. Refer to the product datasheet for product data.

C_{\text{SH}} = 100 \text{ nF}

V_{\text{DD}} = 3.0 \text{ V}

Sampling phase:

t_{\text{SAMP}} = 7 \mu\text{s} + (10 * 2000 * 100 * 10^{-9}) = 2.007 \text{ ms}

(where $R_{\text{BON}} = 2 \text{ k}\Omega$ )

Refresh phase:

t_{\text{REFRESH}} = 7 \mu\text{s} + (2000 * 100 * 10^{-9}) * \ln(2 * 10) = 606.1 \mu\text{s}

(where $N_{\text{LSB}} = 10$ (10 LSB drop during the hold phase))

Hold phase:

D_V = i_{\text{leak}} * t_{\text{hold}} / C_{\text{SH}} = 0.0073 \text{ V} \text{ (10 LSB of 12bit at 3 V)}

i_{\text{leak}} = 150 \text{ nA} \text{ (worst case on the IO leakage on all the temperature range)}

t_{\text{hold}} = 0.0073 * 100 * 10^{-9} / (150 * 10^{-9}) = 4.867 \text{ ms}

Figure 65. DAC sample and hold mode phase diagram

Figure 65. DAC sample and hold mode phase diagram. The diagram illustrates the DAC output voltage, dac_hold_ck, and DAC state over time. It shows four distinct phases: Sampling phase, Hold phase, Refresh phase, and a second Sampling phase. In the Sampling phase, the DAC output voltage rises from V2 towards V1, and the DAC state is ON. During the Hold phase, the voltage stays near Vd, and the DAC state is OFF. In the Refresh phase, the voltage rises slightly and then falls, with the DAC state being ON briefly. The dac_hold_ck is a continuous high-frequency square wave clock signal throughout all phases.

Like in normal mode, the sample and hold mode has different configurations.

To enable the output buffer, MODE1[2:0] bits in DAC_MCR register must be set to:

• 100: DAC is connected to the external pin
• 101: DAC is connected to external pin and to on chip peripherals

To disable the output buffer, MODE1[2:0] bits in DAC_MCR register must be set to:

• 110: DAC is connected to external pin and to on chip peripherals
• 111: DAC is connected to on chip peripherals

When MODE1[2:0] bits are equal to 111, an internal capacitor, $C_{Lint}$ , holds the voltage output of the DAC core and then drive it to on-chip peripherals.

All sample and hold phases are interruptible, and any change in DAC_DHR1 immediately triggers a new sample phase.

Table 82. Channel output modes summary

		Mode	Buffer	Output connections
0	0	Normal mode	Enabled	Connected to external pin
0	1		Enabled	Connected to external pin and to on chip-peripherals (such as comparators)
1	0		Disabled	Connected to external pin
1	1		Disabled	Connected to on chip peripherals (such as comparators)

Table 82. Channel output modes summary (continued)

MODE1[2:0]			Mode	Buffer	Output connections
1	0	0	Sample and hold mode	Enabled	Connected to external pin
1	0	1		Enabled	Connected to external pin and to on chip peripherals (such as comparators)
1	1	0		Disabled	Connected to external pin and to on chip peripherals (such as comparators)
1	1	1		Disabled	Connected to on chip peripherals (such as comparators)

15.4.12 DAC channel buffer calibration

The transfer function for an N-bit digital-to-analog converter (DAC) is:

V_{out} = \left( (D / 2^N) \times G \times V_{REF} \right) + V_{OS}

Where $V_{OUT}$ is the analog output, $$ D $$ is the digital input, $$ G $$ is the gain, $V_{REF}$ is the nominal full-scale voltage, and $V_{OS}$ is the offset voltage. For an ideal DAC channel, $$ G = 1 $$ and $V_{OS} = 0$ .

Due to output buffer characteristics, the voltage offset may differ from part-to-part and introduce an absolute offset error on the analog output. To compensate the $V_{OS}$ , a calibration is required by a trimming technique.

The calibration is only valid when the DAC channel is operating with buffer enabled (MODE1[2:0] = 0b000 or 0b001 or 0b100 or 0b101). if applied in other modes when the buffer is off, it has no effect. During the calibration:

• The buffer output is disconnected from the pin internal/external connections and put in tristate mode (HiZ).
• The buffer acts as a comparator to sense the middle-code value 0x800 and compare it to $V_{REF+}/2$ signal through an internal bridge, then toggle its output signal to 0 or 1 depending on the comparison result (CAL_FLAG1 bit).

Two calibration techniques are provided:

• Factory trimming (default setting)
The DAC buffer offset is factory trimmed. The default value of OTRIM1[4:0] bits in DAC_CCR register is the factory trimming value and it is loaded once DAC digital interface is reset.
• User trimming
The user trimming can be done when the operating conditions differs from nominal factory trimming conditions and in particular when $V_{DDA}$ voltage, temperature, $V_{REF+}$ values change and can be done at any point during application by software.

Note: Refer to the datasheet for more details of the nominal factory trimming conditions.

In addition, when $V_{DD}$ is removed (example the device enters in Standby or VBAT modes) the calibration is required.

The steps to perform a user trimming calibration are as below:

1. If the DAC channel is active, write 0 to EN1 bit in DAC_CR to disable the channel.
2. Select a mode where the buffer is enabled, by writing to DAC_MCR register, MODE1[2:0] = 0b000 or 0b001 or 0b100 or 0b101.
3. Start the DAC channel calibration, by setting the CEN1 bit in DAC_CR register to 1.
4. Apply a trimming algorithm:
1. a) Write a code into OTRIM1[4:0] bits, starting by 0b00000.
2. b) Wait for $t_{TRIM}$ delay.
3. c) Check if CAL_FLAG1 bit in DAC_SR is set to 1.
4. d) Until the CAL_FLAG1 is read as 1 or the maximum trimming code is reached, increment OTRIM1[4:0] and repeat substeps from (b) to (d).

The software algorithm may use either a successive approximation or dichotomy techniques to compute and set the content of OTRIM1[4:0] bits in a faster way.

Note: A $t_{TRIM}$ delay must be respected between the write to the OTRIM1[4:0] bits and the read of the CAL_FLAG1 bit in DAC_SR register in order to get a correct value. This parameter is specified into datasheet electrical characteristics section.

If $V_{DDA}$ , $V_{REF+}$ and temperature conditions do not change during device operation while it enters more often in Standby and VBAT modes, the software may store the OTRIM1[4:0] bits found in the first user calibration in the flash or in back-up registers. then to load/write them directly when the device power is back again thus avoiding to wait for a new calibration time.

When CEN1 bit is set, it is not allowed to set EN1 bit.

15.4.13 DAC channel conversion modes

Four conversion modes are possible.

Independent trigger without wave generation

To configure the DAC in this conversion mode, the following sequence is required:

1. Set the DAC channel trigger enable bit, TEN1.
2. Configure the trigger sources by setting different values in the TSEL1[3:0] bits.
3. Load the DAC channel data into the desired DHR registers (DAC_DHR12R1, DAC_DHR12L1 or DAC_DHR8R1).

When a DAC channel trigger arrives, the DHR1 register is transferred into DAC_DOR1 (three $dac\_pclk$ clock cycles later).

Independent trigger with single LFSR generation

To configure the DAC in this conversion mode, the following sequence is required:

1. Set the DAC channel trigger enable bit, TEN1.
2. Configure the trigger sources by setting different values in the TSEL1[3:0] bits.
3. Configure the DAC channel WAVE1[1:0] bits as 01 and the same LFSR mask value in the MAMP1[3:0] bits.
4. Load the DAC channel data into the desired DHR register (DAC_DHR12R1, DAC_DHR12L1 or DAC_DHR8R1).

When a DAC channel trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three dac_pclk clock cycles later). Then the LFSR1 counter is updated.

Independent trigger with single triangle generation

To configure the DAC in this conversion mode, the following sequence is required:

1. Set the DAC channel trigger enable bits, TEN1.
2. Configure the trigger sources by setting different values in the TSEL1[3:0] bits.
3. Configure the DAC channel WAVE1[1:0] bits as 1x and the same maximum amplitude value in the MAMP1[3:0] bits.
4. Load the DAC channel data into the desired DHR register (DAC_DHR12R1, DAC_DHR12L1 or DAC_DHR8R1).

When a DAC channel trigger arrives, the DAC channel triangle counter, with the same triangle amplitude, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three dac_pclk clock cycles later). The DAC channel triangle counter is then updated.

Independent trigger with single sawtooth generation

To configure the DAC in this conversion mode, the following sequence is required:

1. Configure the trigger sources by setting different values in STRSTTRIGSEL1[3:0] and STINCTRIGSEL1[3:0] bits.
2. Configure the DAC channel WAVE1[1:0] bits to 11 and set the same STRSTDATA1[11:0], STINCDATA1[15:0] and STDIR1 values for each register.

When a DAC channel trigger arrives, the DAC channel sawtooth counter updates the DHR1 register and transfers it into DAC_DOR1 (three APB clock cycles later).

15.5 DAC in low-power modes

Table 83. Effect of low-power modes on DAC

Mode	Description
Sleep	No effect, DAC used with DMA
Stop 0 / Stop 1	The DAC remains active with a static value if the sample and hold mode is selected using LSI clock.
Stop 2	The DAC registers content is lost and must be reinitialized after exiting Stop 2. The DAC must be disabled before entering Stop 2.
Standby	The DAC peripheral is powered down and must be reinitialized after exiting Standby or Shutdown mode.
Shutdown

15.6 DAC interrupts

Table 84. DAC interrupts

Interrupt acronym	Interrupt event	Event flag	Enable control bit	Interrupt clear method	Exit Sleep mode	Exit Stop mode	Exit Standby mode
DAC	DMA underrun	DMAUDR1	DMAUDRIE1	Write DMAUDRx = 1	Yes	No	No

15.7 DAC registers

Refer to Section 1 on page 51 for a list of abbreviations used in register descriptions.

The peripheral registers have to be accessed by words (32-bit).

15.7.1 DAC control register (DAC_CR)

Address offset: 0x00

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	CEN1	DMAUDRIE1	DMAEN1	MAMP1[3:0]				WAVE1[1:0]		TSEL1[3]	TSEL1[2]	TSEL1[1]	TSEL1[0]	TEN1	EN1
	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:16 Reserved, must be kept at reset value.

Bit 15 Reserved, must be kept at reset value.

Bit 14 CEN1 : DAC channel1 calibration enable

This bit is set and cleared by software to enable/disable DAC channel1 calibration, it can be written only if bit EN1 = 0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.

0: DAC channel1 in normal operating mode

1: DAC channel1 in calibration mode

Bit 13 DMAUDRIE1 : DAC channel1 DMA Underrun Interrupt enable

This bit is set and cleared by software.

0: DAC channel1 DMA Underrun Interrupt disabled

1: DAC channel1 DMA Underrun Interrupt enabled

Bit 12 DMAEN1 : DAC channel1 DMA enable

This bit is set and cleared by software.

0: DAC channel1 DMA mode disabled

1: DAC channel1 DMA mode enabled

Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector

These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode.

0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1

0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3

0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7

0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15

0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31

0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63

0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127

0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255

1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511

1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023

1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047

≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

Bits 7:6 WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable

These bits are set and cleared by software.

00: wave generation disabled

01: Noise wave generation enabled

10: Triangle wave generation enabled

11: Reserved

Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).

Bits 5:2 TSEL1[3:0]: DAC channel1 trigger selection

These bits select the external event used to trigger DAC channel1

0000: SWTRIG1

0001: dac_ch1_trg1

0010: dac_ch1_trg2

...

1111: dac_ch1_trg15

Refer to the trigger selection tables in Section 15.4.2: DAC pins and internal signals for details on trigger configuration and mapping.

Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).

Bit 1 TEN1: DAC channel1 trigger enable

This bit is set and cleared by software to enable/disable DAC channel1 trigger.

0: DAC channel1 trigger disabled and data written into the DAC_DHR1 register are transferred one dac_pclk clock cycle later to the DAC_DOR1 register

1: DAC channel1 trigger enabled and data from the DAC_DHR1 register are transferred three dac_pclk clock cycles later to the DAC_DOR1 register

Note: When software trigger is selected, the transfer from the DAC_DHR1 register to the DAC_DOR1 register takes only one dac_pclk clock cycle.

Bit 0 EN1: DAC channel1 enable

This bit is set and cleared by software to enable/disable DAC channel1.

0: DAC channel1 disabled

1: DAC channel1 enabled

15.7.2 DAC software trigger register (DAC_SWTRGR)

Address offset: 0x04

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	SWTRIG1
															w

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 Reserved, must be kept at reset value.

Bit 0 SWTRIG1 : DAC channel1 software trigger

This bit is set by software to trigger the DAC in software trigger mode.

0: No trigger

1: Trigger

Note: This bit is cleared by hardware (one dac_pclk clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register.

15.7.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1)

Address offset: 0x08

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	DACC1DHR[11:0]
				rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 DACC1DHR[11:0] : DAC channel1 12-bit right-aligned data

These bits are written by software. They specify 12-bit data for DAC channel1.

15.7.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)

Address offset: 0x0C

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DACC1DHR[11:0]												Res.	Res.	Res.	Res.
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:4 DACC1DHR[11:0] : DAC channel1 12-bit left-aligned data

These bits are written by software.

They specify 12-bit data for DAC channel1.

Bits 3:0 Reserved, must be kept at reset value.

15.7.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)

Address offset: 0x10

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	DACC1DHR[7:0]
								rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 DACC1DHR[7:0] : DAC channel1 8-bit right-aligned data

These bits are written by software. They specify 8-bit data for DAC channel1.

15.7.6 DAC channel1 data output register (DAC_DOR1)

Address offset: 0x2C

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	DACC1DOR[11:0]
				r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 DACC1DOR[11:0] : DAC channel1 data output

These bits are read-only, they contain data output for DAC channel1.

15.7.7 DAC status register (DAC_SR)

Address offset: 0x34

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BWST1	CAL_FLAG1	DMAUDR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
r	r	rc_w1

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 BWST1 : DAC channel1 busy writing sample time flag

This bit is systematically set just after sample and hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3 LSI periods of synchronization).

0: There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written

1: There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written

Bit 14 CAL_FLAG1 : DAC channel1 calibration offset status

This bit is set and cleared by hardware

0: calibration trimming value is lower than the offset correction value

1: calibration trimming value is equal or greater than the offset correction value

Bit 13 DMAUDR1 : DAC channel1 DMA underrun flag

This bit is set by hardware and cleared by software (by writing it to 1).

0: No DMA underrun error condition occurred for DAC channel1

1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

Bit 12 Reserved, must be kept at reset value.

Bit 11 Reserved, must be kept at reset value.

Bits 10:0 Reserved, must be kept at reset value.

15.7.8 DAC calibration control register (DAC_CCR)

Address offset: 0x38

Reset value: 0x0000 00XX

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OTRIM1[4:0]
											rw	rw	rw	rw	rw

Bits 31:5 Reserved, must be kept at reset value.

Bits 4:0 OTRIM1[4:0] : DAC channel1 offset trimming value

15.7.9 DAC mode control register (DAC_MCR)

Address offset: 0x3C

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	MODE1[2:0]
													rw	rw	rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 Reserved, must be kept at reset value.

Bit 8 Reserved, must be kept at reset value.

Bits 7:3 Reserved, must be kept at reset value.

Bits 2:0 MODE1[2:0] : DAC channel1 mode

These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1 = 0 and bit CEN1 = 0 in the DAC_CR register). If EN1 = 1 or CEN1 = 1 the write operation is ignored.

They can be set and cleared by software to select the DAC channel1 mode:

– DAC channel1 in normal mode
- 000: DAC channel1 is connected to external pin with Buffer enabled
- 001: DAC channel1 is connected to external pin and to on chip peripherals with Buffer enabled
- 010: DAC channel1 is connected to external pin with Buffer disabled
- 011: DAC channel1 is connected to on chip peripherals with Buffer disabled
– DAC channel1 in sample & hold mode
- 100: DAC channel1 is connected to external pin with Buffer enabled
- 101: DAC channel1 is connected to external pin and to on chip peripherals with Buffer enabled
- 110: DAC channel1 is connected to external pin and to on chip peripherals with Buffer disabled
- 111: DAC channel1 is connected to on chip peripherals with Buffer disabled

Note: This register can be modified only when EN1 = 0.

15.7.10 DAC channel1 sample and hold sample time register (DAC_SHSR1)

Address offset: 0x40

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	TSAMPLE1[9:0]
						rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:10 Reserved, must be kept at reset value.

Bits 9:0 TSAMPLE1[9:0] : DAC channel1 sample time (only valid in sample and hold mode)

These bits can be written when the DAC channel1 is disabled or also during normal operation. In the latter case, the write can be done only when BWST1 of DAC_SR register is low. If BWST1 = 1, the write operation is ignored.

Note: It represents the number of LSI clocks to perform a sample phase. Sampling time = (TSAMPLE1[9:0] + 1) x LSI clock period.

15.7.11 DAC sample and hold time register (DAC_SHHR)

Address offset: 0x48

Reset value: 0x0001 0001

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	THOLD1[9:0]
						rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:10 Reserved, must be kept at reset value.

Bits 9:0 THOLD1[9:0] : DAC channel1 hold time (only valid in sample and hold mode)

Hold time = (THOLD[9:0]) x LSI clock period

Note: This register can be modified only when EN1 = 0.

Note: These bits can be written only when the DAC channel is disabled and in normal operating mode (when bit EN1 = 0 and bit CEN1 = 0 in the DAC_CR register). If EN1 = 1 or CEN1 = 1 the write operation is ignored.

15.7.12 DAC sample and hold refresh time register (DAC_SHRR)

Address offset: 0x4C

Reset value: 0x0001 0001

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	TREFRESH1[7:0]
								rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 TREFRESH1[7:0] : DAC channel1 refresh time (only valid in sample and hold mode)

Refresh time = (TREFRESH[7:0]) x LSI clock period

Note: This register can be modified only when EN1 = 0.

15.7.13 DAC register map

Table 85 summarizes the DAC registers.

Table 85. DAC register map and reset values

Offset	Register name reset value	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x00	DAC_CR	Res.	Res.	Res.	Res.	Res.		Res.	Res.	Res.		Res.	Res.		Res.	Res.	Res.	Res.	CEN1	DMAUDRIE1	DMAEN1	Res.	MAMP1[3:0]				WAVE1[1:0]		TSEL1[3:1]			TSEL1[0]	TEN1	EN1
0x00	Reset value																		0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x04	DAC_SWTRGR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	SWTRIG1
0x04	Reset value																																0
0x08	DAC_DHR12R1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	DACC1DHR[11:0]
0x08	Reset value																					0	0	0	0	0	0	0	0	0	0	0	0
0x0C	DAC_DHR12L1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	DACC1DHR[11:0]												Res.	Res.	Res.	Res.
0x0C	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0
0x10	DAC_DHR8R1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	DACC1DHR[7:0]
0x10	Reset value																									0	0	0	0	0	0	0	0
0x14 - 0x1C	Reserved	Res.
0x20 - 0x28	Reserved	Res.
0x2C	DAC_DOR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	DACC1DOR[11:0]
0x2C	Reset value																					0	0	0	0	0	0	0	0	0	0	0	0
0x30	Reserved	Res.
0x34	DAC_SR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	BWST1	CAL_FLAG1	DMAUDR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
0x34	Reset value																	0	0	0
0x38	DAC_CCR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	OTRIM1[4]	OTRIM1[3]	OTRIM1[2]	OTRIM1[1]	OTRIM1[0]
0x38	Reset value																												X	X	X	X	X
0x3C	DAC_MCR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	MODE1[2:0]
0x3C	Reset value																														0	0	0

Table 85. DAC register map and reset values (continued)

Offset	Register name reset value	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1
0x40	DAC_SHSR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	TSAMPLE1[9:0]
0x40	Reset value																							0	0	0	0	0	0	0	0	0
0x44	Reserved	Res.
0x48	DAC_SHHR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	THOLD1[9:0]
0x48	Reset value																							0	0	0	0	0	0	0	0	1
0x4C	DAC_SHRR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	TREFRESH1[7:0]
0x4C	Reset value																								0	0	0	0	0	0	0	1
0x50-0x54	Reserved	Res.
0x58-0x60	Reserved	Res.
0x64-0x68	Reserved	Res.

Refer to Section 2.2 for the register boundary addresses.