11. Nested vectored interrupt controller (NVIC)

11.1 Main features

• 32 maskable interrupt channels (not including the sixteen Cortex®-M0+ system exceptions)
• 4 programmable priority levels (2 bits of interrupt priority are used)
• Low-latency exception and interrupt handling
• Power management control
• Implementation of system control registers

The NVIC and the processor core interface are closely coupled, which enables low-latency interrupt processing and efficient processing of late arriving interrupts.

All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to the programming manual PM0223.

11.2 SysTick calibration value register

The SysTick calibration value is set to 1000, which gives a reference time base of 1 ms with the SysTick clock set to 1 MHz.

11.3 Interrupt and exception vectors

Table 55 is the vector table. Information pertaining to a peripheral only applies to devices containing that peripheral.

Table 55. Vector table ⁽¹⁾

Position	Priority	Type of priority	Acronym	Description	Address
-	-	-	-	Reserved	0x0000_0000
-	-3	fixed	Reset	Reset	0x0000_0004
-	-2	fixed	NMI_Handler	Non maskable interrupt. The SRAM parity error, flash ECC double err., HSE CSS and LSE CSS are linked to the NMI vector.	0x0000_0008
-	-1	fixed	HardFault_Handler	All class of fault	0x0000_000C
-	-	-	-	Reserved	0x0000_0010 0x0000_0014 0x0000_0018 0x0000_001C 0x0000_0020 0x0000_0024 0x0000_0028
-	3	settable	SVC_Handler	System service call via SVC instruction	0x0000_002C

Table 55. Vector table⁽¹⁾(continued)

Position	Priority	Type of priority	Acronym	Description	Address
-	-	-	-	Reserved	0x0000_0030 0x0000_0034
-	5	settable	PendSV_Handler	Pendable request for system service	0x0000_0038
-	6	settable	SysTick_Handler	System tick timer	0x0000_003C
0	7	settable	WWDG/IWDG	Window watchdog and independent watchdog interrupt	0x0000_0040
1	8	settable	PVD/PVM	PVD/PVM1/PVM2/PVM4 interrupt (combined with EXTI lines 16 & 19 & 20 & 21)	0x0000_0044
2	9	settable	RTC/TAMP	RTC and TAMP interrupts (combined EXTI lines 19 & 21)	0x0000_0048
3	10	settable	FLASH	Flash global interrupt	0x0000_004C
4	11	settable	RCC/CRS	RCC and CRS global interrupt	0x0000_0050
5	12	settable	EXTI0_1	EXTI lines 0 & 1 interrupt	0x0000_0054
6	13	settable	EXTI2_3	EXTI lines 2 & 3 interrupt	0x0000_0058
7	14	settable	EXTI4_15	EXTI lines 4 to 15 interrupt	0x0000_005C
8	15	settable	USB	USB global interrupt (combined with EXTI line 33)	0x0000_0060
9	16	settable	DMA1_Channel1	DMA1 channel 1 interrupt	0x0000_0064
10	17	settable	DMA1_Channel2_3	DMA1 channel 2 & 3 interrupts	0x0000_0068
11	18	settable	DMA1_Channel4_5_6_7/DMAMUX/DMA2_Channel1_2_3_4_5	DMA1 channel 4, 5, 6, 7, DMAMUX, DMA2 channel 1, 2, 3, 4, 5 interrupts	0x0000_006C
12	19	settable	ADC/COMP	ADC and COMP interrupts (ADC combined with EXTI lines 17 & 18)	0x0000_0070
13	20	settable	TIM1_BRK_UP_TRG_COM	TIM1 break, update, trigger and commutation interrupts	0x0000_0074
14	21	settable	TIM1_CC	TIM1 Capture Compare interrupt	0x0000_0078
15	22	settable	TIM2	TIM2 global interrupt	0x0000_007C
16	23	settable	TIM3	TIM3 global interrupt	0x0000_0080
17	24	settable	TIM6/DAC/LPTIM1	TIM6, LPTIM1 and DAC global interrupt (combined with EXTI line 29)	0x0000_0084
18	25	settable	TIM7/LPTIM2	TIM7 and LPTIM2 global interrupt (combined with EXTI line 30)	0x0000_0088
19	26	settable	TIM15/LPTIM3	TIM15 and LPTIM3 global interrupt (combined with EXTI line 29)	0x0000_008C
20	27	settable	TIM16	TIM16 global interrupt	0x0000_0090
21	28	settable	TSC	TSC global interrupt	0x0000_0094

Table 55. Vector table⁽¹⁾(continued)

Position	Priority	Type of priority	Acronym	Description	Address
22	29	settable	LCD	LCD global interrupt (combined with EXTI line 32)	0x0000_0098
23	30	settable	I2C1	I2C1 global interrupt (combined with EXTI line 23)	0x0000_009C
24	31	settable	I2C2/I2C3/I2C4	I2C2/3/4 global interrupt	0x0000_00A0
25	32	settable	SPI1	SPI1 global interrupt	0x0000_00A4
26	33	settable	SPI2/SPI3	SPI2/3 global interrupt	0x0000_00A8
27	34	settable	USART1	USART1 global interrupt (combined with EXTI line 25)	0x0000_00AC
28	35	settable	USART2/LPUART2	USART2 and LPUART2 global interrupt (combined with EXTI lines 26 & 35)	0x0000_00B0
29	36	settable	USART3/LPUART1	USART3 and LPUART1 global interrupt (combined with EXTI lines 24 & 28)	0x0000_00B4
30	37	settable	USART4/LPUART3	USART4 and LPUART3 global interrupt (combined with EXTI lines 20 & 34)	0x0000_00B8
31	38	settable	AES/RNG	AES and RNG global interrupts	0x0000_00BC

1. The grayed cells correspond to the Cortex ^®-M0+ system exceptions.