8. System configuration controller (SYSCFG)

The devices feature a set of configuration registers. The main purposes of the system configuration controller are the following:

• • Enabling/disabling I ² C Fast Mode Plus on some I/O ports
• • Enabling/disabling the analog switch booster
• • Configuring the IR modulation signal and its output polarity
• • Remapping of some I/O ports
• • Remapping the memory located at the beginning of the code area
• • Flag pending interrupts from each interrupt line
• • Managing robustness feature

8.1 SYSCFG registers

8.1.1 SYSCFG configuration register 1 (SYSCFG_CFGR1)

This register is used for specific configurations of memory and DMA requests remap and to control special I/O features.

Two bits are used to configure the type of memory accessible at address 0x0000 0000. These bits are used to select the physical remap by software and so, bypass the hardware BOOT selection. After reset these bits take the value selected by the actual boot mode configuration.

In the reset value, X is the memory mode selected by the actual boot mode configuration.

Address offset: 0x00

Reset value: 0x0000 000X

Bits 31:25 Reserved, must be kept at reset value.

This bit is set and cleared by software. It enables I ² C FM+ driving capability on I/O ports configured as I2C3 through GPIOx_AFR registers.

0: Disable

1: Enable

With this bit in disable state, the I ² C FM+ driving capability on I/O ports configured as I2C3 can be enabled through their corresponding I2Cx_FMP bit. When I ² C FM+ is enabled, the speed control is ignored.

Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.

This bit is set and cleared by software. It enables I ² C FM+ driving capability on PA10 I/O port.

0: Disable

1: Enable

With this bit in disable state, the I ² C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I ² C FM+ is enabled, the speed control is ignored.

Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.

This bit is set and cleared by software. It enables I ² C FM+ driving capability on PA9 I/O port.

0: Disable

1: Enable

With this bit in disable state, the I ² C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I ² C FM+ is enabled, the speed control is ignored.

Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.

Bits 21:20 Reserved, must be kept at reset value.

This bit is set and cleared by software. It enables I ² C FM+ driving capability on PB9 I/O port.

0: Disable

1: Enable

With this bit in disable state, the I ² C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I ² C FM+ is enabled, the speed control is ignored.

Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.

This bit is set and cleared by software. It enables I ² C FM+ driving capability on PB8 I/O port.

0: Disable

1: Enable

With this bit in disable state, the I ² C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I ² C FM+ is enabled, the speed control is ignored.

Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.

Bit 17 I2C_PB7_FMP : Fast Mode Plus (FM+) enable for PB7

This bit is set and cleared by software. It enables I ² C FM+ driving capability on PB7 I/O port.

0: Disable

1: Enable

With this bit in disable state, the I ² C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I ² C FM+ is enabled, the speed control is ignored.

Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.

Bit 16 I2C_PB6_FMP : Fast Mode Plus (FM+) enable for PB6

This bit is set and cleared by software. It enables I ² C FM+ driving capability on PB6 I/O port.

0: Disable

1: Enable

With this bit in disable state, the I ² C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I ² C FM+ is enabled, the speed control is ignored.

Note: This control bit is kept for legacy reasons. It is recommended to use the FMP bit of the I2Cx_CR1 register instead.

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 BOOSTEN : I/O analog switch voltage booster enable

This bit selects the way of supplying I/O analog switches:

0: V _DD

1: Dedicated voltage booster (supplied by V _DD )

When using the analog inputs, setting to 0 is recommended for high V _DD , setting to 1 for low V _DD (less than 2.4 V).

Bits 7:6 IR_MOD[1:0] : IR modulation envelope signal selection

This bitfield selects the signal for IR modulation envelope:

00: TIM16

01: USART1

10: USART4

11: Reserved

Bit 5 Reserved, must be kept at reset value.

Bit 4 PA12_RMP : PA12 pin remapping

This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port.

0: No remap (PA12)

1: Remap (PA10)

Bit 3 PA11_RMP : PA11 pin remapping

This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port.

0: No remap (PA11)

1: Remap (PA9)

Bit 2 Reserved, must be kept at reset value.

Bits 1:0 MEM_MODE[1:0] : Memory mapping selection bits

These bits are set and cleared by software. They control the memory internal mapping at address 0x0000 0000. After reset these bits take on the value selected by the actual boot mode configuration. Refer to Section 2.5: Boot configuration for more details.

X0: Main flash memory mapped at 0x0000 0000

01: System flash memory mapped at 0x0000 0000

11: Embedded SRAM mapped at 0x0000 0000

8.1.2 SYSCFG configuration register 2 (SYSCFG_CFGR2)

Address offset: 0x18

System reset value: 0x0000 0000

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 SPF : SRAM1 parity error flag

This bit is set by hardware when an SRAM1 parity error is detected. It is cleared by software by writing 1.

0: No SRAM1 parity error detected

1: SRAM1 parity error detected

Bit 7 BKPF : Backup SRAM2 parity error flag

This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software by writing 1.

0: No SRAM2 parity error detected

1: SRAM2 parity error detected

Bits 6:5 Reserved, must be kept at reset value.

Bit 4 BKPL : Backup SRAM2 parity lock

This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/15/16 Break input.

0: SRAM2 parity error disconnected from TIM1/15/16 Break input

1: SRAM2 parity error connected to TIM1/15/16 Break input

Bit 3 ECCL : ECC error lock bit

This bit is set by software and cleared by a system reset. It can be used to enable and lock the flash memory ECC 2-bit error detection signal connection to TIM1/15/16 Break input.

0: ECC error disconnected from TIM1/15/16 Break input

1: ECC error connected to TIM1/15/16 Break input

Bit 2 PVDL : PVD lock enable bit

This bit is set by software and cleared by a system reset. It can be used to enable and lock the PVD connection to TIM1/15/16 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register.

0: PVD interrupt disconnected from TIM1/15/16 Break input. PVDE and PLS[2:0] bits can be programmed by the application.

1: PVD interrupt connected to TIM1/15/16 Break input, PVDE and PLS[2:0] bits are read only.

Bit 1 SPL : SRAM1 parity lock bit

This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM1 parity error signal connection to TIM1/15/16 Break input.

0: SRAM1 parity error disconnected from TIM1/15/16 Break input

1: SRAM1 parity error connected to TIM1/15/16 Break input

Bit 0 CLL : Cortex ^® -M0+ LOCKUP bit enable bit

This bit is set by software and cleared by a system reset. It can be used to enable and lock the connection of Cortex ^® -M0+ LOCKUP (Hardfault) output to TIM1/15/16 Break input.

0: Cortex ^® -M0+ LOCKUP output disconnected from TIM1/15/16 Break input

1: Cortex ^® -M0+ LOCKUP output connected to TIM1/15/16 Break input

8.1.3 SYSCFG SRAM2 control and status register (SYSCFG_SCSR)

Address offset: 0x1C

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 SRAM2BSY : SRAM2 busy by erase operation

0: No SRAM2 erase operation is ongoing

1: SRAM2 erase operation is ongoing

Bit 0 SRAM2ER : SRAM2 erase

Setting this bit starts a hardware SRAM2 erase operation. This bit is automatically cleared at the end of the SRAM2 erase operation.

Note: This bit is write-protected; setting this bit is possible only after the correct key sequence is written in the SYSCFG_SKR register.

8.1.4 SYSCFG SRAM2 key register (SYSCFG_SKR)

Address offset: 0x20

System reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 KEY[7:0] : SRAM2 write protection key for software erase

The following steps are required to unlock the write protection of the SRAM2ER bit in the SYSCFG_CFGR2 register:

1. 1. Write "0xCA" into KEY[7:0]
2. 2. Write "0x53" into KEY[7:0]

Writing a wrong key reactivates the write protection.

8.1.5 SYSCFG TSC comparator register (SYSCFG_TSCCR)

Address offset: 0x24

Reset value: 0x0000 0000

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 TSC_ICTRL : I/O control in comparator mode

The I/O control in comparator mode can be overwritten by hardware.

0: I/O configured through the corresponding control register

1: I/O configured as analog when TSC AF is activated

Bit 4 G7_IO1 : Comparator mode for group 7 on I/O 2

0: Disabled

1: Enable connection of PA9 to COMP1

Bit 3 G6_IO1 : Comparator mode for group 6 on I/O 1

0: Disabled

1: Enable connection of PD10 to COMP2

Bit 2 G4_IO3 : Comparator mode for group 4 on I/O 1

0: Disabled

1: Enable connection of PC6 to COMP1

Bit 1 G2_IO3 : Comparator mode for group 2 on I/O 3

0: Disabled

1: Enable connection of PB6 to COMP2

Bit 0 G2_IO1 : Comparator mode for group 2 on I/O 1

0: Disabled

1: Enable connection of PB4 to COMP2

8.1.6 SYSCFG interrupt line 0 status register (SYSCFG_ITLINE0)

A dedicated set of registers is implemented on the device to collect all pending interrupt sources associated with each interrupt line into a single register. This allows users to check by single read which peripheral requires service in case more than one source is associated to the interrupt line.

All bits in those registers are read only, set by hardware when there is corresponding interrupt request pending and cleared by resetting the interrupt source flags in the peripheral registers.

Address offset: 0x80

System reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 WWDG : Window watchdog interrupt pending flag

8.1.7 SYSCFG interrupt line 1 status register (SYSCFG_ITLINE1)

Address offset: 0x84

System reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 PVMOUT4 : DAC supply monitoring interrupt request pending (EXTI line 21)

Bit 2 PVMOUT3 : ADC supply monitoring interrupt request pending (EXTI line 20)

Bit 1 PVMOUT1 : V _DDUSB supply monitoring interrupt request pending (EXTI line 19)

Bit 0 PVDOUT : PVD supply monitoring interrupt request pending (EXTI line 16).

8.1.8 SYSCFG interrupt line 2 status register (SYSCFG_ITLINE2)

Address offset: 0x88

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 RTC : RTC interrupt request pending (EXTI line 19)

Bit 0 TAMP : Tamper interrupt request pending (EXTI line 21)

8.1.9 SYSCFG interrupt line 3 status register (SYSCFG_ITLINE3)

Address offset: 0x8C

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 FLASH_ITF : Flash interface interrupt request pending

Bit 0 FLASH_ECC : Flash interface ECC interrupt request pending

8.1.10 SYSCFG interrupt line 4 status register (SYSCFG_ITLINE4)

Address offset: 0x90

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 CRS : CRS interrupt request pending

Bit 0 RCC : Reset and clock control interrupt request pending

8.1.11 SYSCFG interrupt line 5 status register (SYSCFG_ITLINE5)

Address offset: 0x94

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 EXTI1 : EXTI line 1 interrupt request pending

Bit 0 EXTI0 : EXTI line 0 interrupt request pending

8.1.12 SYSCFG interrupt line 6 status register (SYSCFG_ITLINE6)

Address offset: 0x98

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 EXTI3 : EXTI line 3 interrupt request pending

Bit 0 EXTI2 : EXTI line 2 interrupt request pending

8.1.13 SYSCFG interrupt line 7 status register (SYSCFG_ITLINE7)

Address offset: 0x9C

System reset value: 0x0000 0000

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 EXTI15 : EXTI line 15 interrupt request pending

Bit 10 EXTI14 : EXTI line 14 interrupt request pending

Bit 9 EXTI13 : EXTI line 13 interrupt request pending

Bit 8 EXTI12 : EXTI line 12 interrupt request pending

Bit 7 EXTI11 : EXTI line 11 interrupt request pending

Bit 6 EXTI10 : EXTI line 10 interrupt request pending

Bit 5 EXTI9 : EXTI line 9 interrupt request pending

Bit 4 EXTI8 : EXTI line 8 interrupt request pending

Bit 3 EXTI7 : EXTI line 7 interrupt request pending

Bit 2 EXTI6 : EXTI line 6 interrupt request pending

Bit 1 EXTI5 : EXTI line 5 interrupt request pending

Bit 0 EXTI4 : EXTI line 4 interrupt request pending

8.1.14 SYSCFG interrupt line 8 status register (SYSCFG_ITLINE8)

Address offset: 0xA0

System reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 USB : USB interrupt request pending

8.1.15 SYSCFG interrupt line 9 status register (SYSCFG_ITLINE9)

Address offset: 0xA4

System reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 DMA1_CH1 : DMA1 channel 1 interrupt request pending

8.1.16 SYSCFG interrupt line 10 status register (SYSCFG_ITLINE10)

Address offset: 0xA8

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 DMA1_CH3 : DMA1 channel 3 interrupt request pending

Bit 0 DMA1_CH2 : DMA1 channel 2 interrupt request pending

8.1.17 SYSCFG interrupt line 11 status register (SYSCFG_ITLINE11)

Address offset: 0xAC

System reset value: 0x0000 0000

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 DMA2_CH5 : DMA2 channel 5 interrupt request pending

Bit 8 DMA2_CH4 : DMA2 channel 4 interrupt request pending

Bit 7 DMA2_CH3 : DMA2 channel 3 interrupt request pending

Bit 6 DMA2_CH2 : DMA2 channel 2 interrupt request pending

Bit 5 DMA2_CH1 : DMA2 channel 1 interrupt request pending

Bit 4 DMA1_CH7 : DMA1 channel 7 interrupt request pending

Bit 3 DMA1_CH6 : DMA1 channel 6 interrupt request pending

Bit 2 DMA1_CH5 : DMA1 channel 5 interrupt request pending

Bit 1 DMA1_CH4 : DMA1 channel 4 interrupt request pending

Bit 0 DMAMUX : DMAMUX interrupt request pending

8.1.18 SYSCFG interrupt line 12 status register (SYSCFG_ITLINE12)

Address offset: 0xB0

System reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 COMP2 : Comparator 2 interrupt request pending (EXTI line 18)

Bit 1 COMP1 : Comparator 1 interrupt request pending (EXTI line 17)

Bit 0 ADC : ADC interrupt request pending

8.1.19 SYSCFG interrupt line 13 status register (SYSCFG_ITLINE13)

Address offset: 0xB4

System reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 TIM1_BRK : Timer 1 break interrupt request pending

Bit 2 TIM1_UPD : Timer 1 update interrupt request pending

Bit 1 TIM1_TRG : Timer 1 trigger interrupt request pending

Bit 0 TIM1_CCU : Timer 1 commutation interrupt request pending

8.1.20 SYSCFG interrupt line 14 status register (SYSCFG_ITLINE14)

Address offset: 0xB8

System reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 TIM1_CC4 : Timer 1 capture compare 4 interrupt request pending

Bit 2 TIM1_CC3 : Timer 1 capture compare 3 interrupt request pending

Bit 1 TIM1_CC2 : Timer 1 capture compare 2 interrupt request pending

Bit 0 TIM1_CC1 : Timer 1 capture compare 1 interrupt request pending

8.1.21 SYSCFG interrupt line 15 status register (SYSCFG_ITLINE15)

Address offset: 0xBC

System reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 TIM2 : Timer 2 interrupt request pending

8.1.22 SYSCFG interrupt line 16 status register (SYSCFG_ITLINE16)

Address offset: 0xC0

System reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 TIM3 : Timer 3 interrupt request pending

8.1.23 SYSCFG interrupt line 17 status register (SYSCFG_ITLINE17)

Address offset: 0xC4

System reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 LPTIM1 : Low-power timer 1 interrupt request pending (EXTI line 29)

Bit 1 DAC : DAC underrun interrupt request pending

Bit 0 TIM6 : Timer 6 interrupt request pending

8.1.24 SYSCFG interrupt line 18 status register (SYSCFG_ITLINE18)

Address offset: 0xC8

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 LPTIM2 : Low-power timer 2 interrupt request pending (EXTI line 30)

Bit 0 TIM7 : Timer 7 interrupt request pending

8.1.25 SYSCFG interrupt line 19 status register (SYSCFG_ITLINE19)

Address offset: 0xCC

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 LPTIM3 : Low-power timer 3 interrupt request pending

Bit 0 TIM15 : Timer 15 interrupt request pending

8.1.26 SYSCFG interrupt line 20 status register (SYSCFG_ITLINE20)

Address offset: 0xD0

System reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 TIM16 : Timer 16 interrupt request pending

8.1.27 SYSCFG interrupt line 21 status register (SYSCFG_ITLINE21)

Address offset: 0xD4

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 TSC_EOA : TSC end of acquisition interrupt request pending

Bit 0 TSC_MCE : TSC max count error interrupt request pending

8.1.28 SYSCFG interrupt line 22 status register (SYSCFG_ITLINE22)

Address offset: 0xD8

System reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 LCD : LCD interrupt request pending

8.1.29 SYSCFG interrupt line 23 status register (SYSCFG_ITLINE23)

Address offset: 0xDC

System reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 I2C1 : I2C1 interrupt request pending (EXTI line 33)

8.1.30 SYSCFG interrupt line 24 status register (SYSCFG_ITLINE24)

Address offset: 0xE0

System reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 I2C3 : I2C3 interrupt request pending (EXTI line 23)

Bit 1 I2C4 : I2C4 interrupt request pending

Bit 0 I2C2 : I2C2 interrupt request pending

8.1.31 SYSCFG interrupt line 25 status register (SYSCFG_ITLINE25)

Address offset: 0xE4

System reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 SPI1 : SPI1 interrupt request pending

8.1.32 SYSCFG interrupt line 26 status register (SYSCFG_ITLINE26)

Address offset: 0xE8

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 SPI3 : SPI3 interrupt request pending

Bit 0 SPI2 : SPI2 interrupt request pending

8.1.33 SYSCFG interrupt line 27 status register (SYSCFG_ITLINE27)

Address offset: 0xEC

System reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 USART1 : USART1 interrupt request pending, combined with EXTI line 25

8.1.34 SYSCFG interrupt line 28 status register (SYSCFG_ITLINE28)

Address offset: 0xF0

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 LPUART2 : LPUART2 interrupt request pending (EXTI line 31)

Bit 0 USART2 : USART2 interrupt request pending (EXTI line 35)

8.1.35 SYSCFG interrupt line 29 status register (SYSCFG_ITLINE29)

Address offset: 0xF4

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 LPUART1 : LPUART1 interrupt request pending (EXTI line 30)

Bit 0 USART3 : USART3 interrupt request pending

8.1.36 SYSCFG interrupt line 30 status register (SYSCFG_ITLINE30)

Address offset: 0xF8

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 LPUART3 : LPUART3 interrupt request pending (EXTI line 32)

Bit 0 USART4 : USART4 interrupt request pending

8.1.37 SYSCFG interrupt line 31 status register (SYSCFG_ITLINE31)

Address offset: 0xFC

System reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 AES : AES interrupt request pending

Bit 0 RNG : RNG interrupt request pending

8.1.38 SYSCFG register map

The following table gives the SYSCFG register map and the reset values.

Table 42. SYSCFG register map and reset values

Table 42. SYSCFG register map and reset values (continued)

Table 42. SYSCFG register map and reset values (continued)

Refer to Section 2.2 on page 55 for the register boundary addresses.