8. System configuration controller (SYSCFG) . . . . . 243

8.1SYSCFG registers . . . . .243
8.1.1SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . .243
8.1.2SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . .246
8.1.3SYSCFG SRAM2 control and status register (SYSCFG_SCSR) . . . .247
8.1.4SYSCFG SRAM2 key register (SYSCFG_SKR) . . . . .248
8.1.5SYSCFG TSC comparator register (SYSCFG_TSCCR) . . . . .248
8.1.6SYSCFG interrupt line 0 status register (SYSCFG_ITLINE0) . . . . .249
8.1.7SYSCFG interrupt line 1 status register (SYSCFG_ITLINE1) . . . . .249
8.1.8SYSCFG interrupt line 2 status register (SYSCFG_ITLINE2) . . . . .250
8.1.9SYSCFG interrupt line 3 status register (SYSCFG_ITLINE3) . . . . .250
8.1.10SYSCFG interrupt line 4 status register (SYSCFG_ITLINE4) . . . . .251
8.1.11SYSCFG interrupt line 5 status register (SYSCFG_ITLINE5) . . . . .251
8.1.12SYSCFG interrupt line 6 status register (SYSCFG_ITLINE6) . . . . .251
8.1.13SYSCFG interrupt line 7 status register (SYSCFG_ITLINE7) . . . . .252
8.1.14SYSCFG interrupt line 8 status register (SYSCFG_ITLINE8) . . . . .252
8.1.15SYSCFG interrupt line 9 status register (SYSCFG_ITLINE9) . . . . .253
8.1.16SYSCFG interrupt line 10 status register (SYSCFG_ITLINE10) . . . . .253
8.1.17SYSCFG interrupt line 11 status register (SYSCFG_ITLINE11) . . . . .254
8.1.18SYSCFG interrupt line 12 status register (SYSCFG_ITLINE12) . . . . .254
8.1.19SYSCFG interrupt line 13 status register (SYSCFG_ITLINE13) . . . . .255
8.1.20SYSCFG interrupt line 14 status register (SYSCFG_ITLINE14) . . . . .255
8.1.21SYSCFG interrupt line 15 status register (SYSCFG_ITLINE15) . . . . .256
8.1.22SYSCFG interrupt line 16 status register (SYSCFG_ITLINE16) . . . . .256
8.1.23SYSCFG interrupt line 17 status register (SYSCFG_ITLINE17) . . . . .256
8.1.24SYSCFG interrupt line 18 status register (SYSCFG_ITLINE18) . . . . .257
8.1.25SYSCFG interrupt line 19 status register (SYSCFG_ITLINE19) . . . . .257
8.1.26SYSCFG interrupt line 20 status register (SYSCFG_ITLINE20) . . . . .257
8.1.27SYSCFG interrupt line 21 status register (SYSCFG_ITLINE21) . . . . .258
8.1.28SYSCFG interrupt line 22 status register (SYSCFG_ITLINE22) . . . . .258
8.1.29SYSCFG interrupt line 23 status register (SYSCFG_ITLINE23) . . . . .258
8.1.30SYSCFG interrupt line 24 status register (SYSCFG_ITLINE24) . . . . .259
8.1.31SYSCFG interrupt line 25 status register (SYSCFG_ITLINE25) . . . . .259
8.1.32SYSCFG interrupt line 26 status register (SYSCFG_ITLINE26) . . . . .259
8.1.33SYSCFG interrupt line 27 status register (SYSCFG_ITLINE27) . . . . .260
8.1.34SYSCFG interrupt line 28 status register (SYSCFG_ITLINE28) . . . . .260
8.1.35SYSCFG interrupt line 29 status register (SYSCFG_ITLINE29) . . . . .261
8.1.36SYSCFG interrupt line 30 status register (SYSCFG_ITLINE30) . . . . .261
8.1.37SYSCFG interrupt line 31 status register (SYSCFG_ITLINE31) . . . . .261
8.1.38SYSCFG register map . . . . .262
9Direct memory access controller (DMA) . . . . .265
9.1Introduction . . . . .265
9.2DMA main features . . . . .265
9.3DMA implementation . . . . .266
9.3.1DMA . . . . .266
9.3.2DMA request mapping . . . . .266
9.4DMA functional description . . . . .267
9.4.1DMA block diagram . . . . .267
9.4.2DMA pins and internal signals . . . . .267
9.4.3DMA transfers . . . . .268
9.4.4DMA arbitration . . . . .269
9.4.5DMA channels . . . . .269
9.4.6DMA data width, alignment, and endianness . . . . .273
9.4.7DMA error management . . . . .274
9.5DMA interrupts . . . . .275
9.6DMA registers . . . . .275
9.6.1DMA interrupt status register (DMA_ISR) . . . . .275
9.6.2DMA interrupt flag clear register (DMA_IFCR) . . . . .277
9.6.3DMA channel x configuration register (DMA_CCRx) . . . . .279
9.6.4DMA channel x number of data to transfer register (DMA_CNDTRx) . . . . .281
9.6.5DMA channel x peripheral address register (DMA_CPARx) . . . . .282
9.6.6DMA channel x memory address register (DMA_CMARx) . . . . .283
9.6.7DMA register map . . . . .283
10DMA request multiplexer (DMAMUX) . . . . .286
10.1Introduction . . . . .286
10.2DMAMUX main features . . . . .287
10.3DMAMUX implementation . . . . .287
10.3.1DMAMUX instantiation . . . . .287
10.3.2DMAMUX mapping . . . . .287
10.4DMAMUX functional description . . . . .290
10.4.1DMAMUX block diagram . . . . .290
10.4.2DMAMUX signals . . . . .291
10.4.3DMAMUX channels . . . . .291
10.4.4DMAMUX request line multiplexer . . . . .291
10.4.5DMAMUX request generator . . . . .294
10.5DMAMUX interrupts . . . . .295
10.6DMAMUX registers . . . . .296
10.6.1DMAMUX request line multiplexer channel x configuration register
(DMAMUX_CxCR) . . . . .		296
10.6.2DMAMUX request line multiplexer interrupt channel status register
(DMAMUX_CSR) . . . . .		297
10.6.3DMAMUX request line multiplexer interrupt clear flag register
(DMAMUX_CFR) . . . . .		297
10.6.4DMAMUX request generator channel x configuration register
(DMAMUX_RGxCR) . . . . .		298
10.6.5DMAMUX request generator interrupt status register
(DMAMUX_RGSR) . . . . .		299
10.6.6DMAMUX request generator interrupt clear flag register
(DMAMUX_RGCFR) . . . . .		299
10.6.7DMAMUX register map . . . . .300
11Nested vectored interrupt controller (NVIC) . . . . .302
11.1Main features . . . . .302
11.2SysTick calibration value register . . . . .302
11.3Interrupt and exception vectors . . . . .302
12Extended interrupt and event controller (EXTI) . . . . .305
12.1EXTI main features . . . . .305
12.2EXTI block diagram . . . . .305
12.2.1EXTI connections between peripherals and CPU . . . . .307
12.3EXTI functional description . . . . .307
12.3.1EXTI configurable event input wake-up . . . . .308
12.3.2EXTI direct event input wake-up . . . . .309
12.3.3EXTI mux . . . . .309
12.4EXTI functional behavior . . . . .311
12.5EXTI registers . . . . .312
12.5.1EXTI rising trigger selection register (EXTI_RTSR1) . . . . .312
12.5.2EXTI falling trigger selection register 1 (EXTI_FTSR1) . . . . .313
12.5.3EXTI software interrupt event register 1 (EXTI_SWIER1) . . . . .313
12.5.4EXTI rising edge pending register 1 (EXTI_RPR1) . . . . .314
12.5.5EXTI falling edge pending register 1 (EXTI_FPR1) . . . . .314
12.5.6EXTI external interrupt selection register x (EXTI_EXTICRx) . . . . .315
12.5.7EXTI CPU wake-up with interrupt mask register (EXTI_IMR1) . . . . .316
12.5.8EXTI CPU wake-up with event mask register (EXTI_EMR1) . . . . .316
12.5.9EXTI CPU wake-up with interrupt mask register (EXTI_IMR2) . . . . .317
12.5.10EXTI CPU wake-up with event mask register (EXTI_EMR2) . . . . .317
12.5.11EXTI register map . . . . .318
13Cyclic redundancy check calculation unit (CRC) . . . . .320
13.1Introduction . . . . .320
13.2CRC main features . . . . .320
13.3CRC functional description . . . . .321
13.3.1CRC block diagram . . . . .321
13.3.2CRC internal signals . . . . .321
13.3.3CRC operation . . . . .321
13.4CRC registers . . . . .323
13.4.1CRC data register (CRC_DR) . . . . .323
13.4.2CRC independent data register (CRC_IDR) . . . . .323
13.4.3CRC control register (CRC_CR) . . . . .324
13.4.4CRC initial value (CRC_INIT) . . . . .325
13.4.5CRC polynomial (CRC_POL) . . . . .325
13.4.6CRC register map . . . . .326
14Analog-to-digital converter (ADC) . . . . .327
14.1Introduction . . . . .327
14.2ADC main features . . . . .328
14.3ADC implementation . . . . .329
14.4ADC functional description . . . . .330
14.4.1ADC pins and internal signals . . . . .331
14.4.2ADC voltage regulator (ADVREGEN) . . . . .332
14.9.3Triggered mode361
14.10Temperature sensor and internal reference voltage361
14.11Battery voltage monitoring364
14.12ADC interrupts364
14.13ADC registers366
14.13.1ADC interrupt and status register (ADC_ISR)366
14.13.2ADC interrupt enable register (ADC_IER)367
14.13.3ADC control register (ADC_CR)369
14.13.4ADC configuration register 1 (ADC_CFGR1)371
14.13.5ADC configuration register 2 (ADC_CFGR2)374
14.13.6ADC sampling time register (ADC_SMPR)376
14.13.7ADC watchdog threshold register (ADC_AWD1TR)377
14.13.8ADC watchdog threshold register (ADC_AWD2TR)377
14.13.9ADC channel selection register (ADC_CHSELR)377
14.13.10ADC channel selection register [alternate] (ADC_CHSELR)378
14.13.11ADC watchdog threshold register (ADC_AWD3TR)380
14.13.12ADC data register (ADC_DR)381
14.13.13ADC analog watchdog 2 configuration register (ADC_AWD2CR)381
14.13.14ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR)382
14.13.15ADC calibration factor (ADC_CALFACT)382
14.13.16ADC common configuration register (ADC_CCR)383
14.14ADC register map384
15Digital-to-analog converter (DAC)387
15.1Introduction387
15.2DAC main features387
15.3DAC implementation388
15.4DAC functional description388
15.4.1DAC block diagram388
15.4.2DAC pins and internal signals389
15.4.3DAC channel enable390
15.4.4DAC data format390
15.4.5DAC conversion391
15.4.6DAC output voltage391
15.4.7DAC trigger selection392
15.4.8DMA requests392

16 Voltage reference buffer (VREFBUF) ..... 411

17 Comparator (COMP) ..... 414

17.3COMP functional description . . . . .415
17.3.1COMP block diagram . . . . .415
17.3.2COMP pins and internal signals . . . . .415
17.3.3COMP reset and clocks . . . . .417
17.3.4Comparator LOCK mechanism . . . . .417
17.3.5Window comparator . . . . .417
17.3.6Hysteresis . . . . .418
17.3.7Comparator output blanking function . . . . .418
17.3.8COMP power and speed modes . . . . .419
17.4COMP low-power modes . . . . .419
17.5COMP interrupts . . . . .420
17.6COMP registers . . . . .421
17.6.1Comparator 1 control and status register (COMP1_CSR) . . . . .421
17.6.2Comparator 2 control and status register (COMP2_CSR) . . . . .422
17.6.3COMP register map . . . . .425
18Operational amplifiers (OPAMP) . . . . .426
18.1Introduction . . . . .426
18.2OPAMP main features . . . . .426
18.3OPAMP functional description . . . . .426
18.3.1OPAMP reset and clocks . . . . .426
18.3.2Initial configuration . . . . .427
18.3.3Signal routing . . . . .427
18.3.4OPAMP modes . . . . .427
18.3.5Calibration . . . . .431
18.4OPAMP low-power modes . . . . .433
18.5OPAMP registers . . . . .434
18.5.1OPAMP1 control/status register (OPAMP1_CSR) . . . . .434
18.5.2OPAMP1 offset trimming register in normal mode (OPAMP1_OTR) . . . . .435
18.5.3OPAMP1 offset trimming register in low-power mode
(OPAMP1_LPOTR) . . . . .		435
18.5.4OPAMP register map . . . . .436
19Liquid crystal display controller (LCD) . . . . .437
19.1LCD introduction . . . . .437
19.2LCD main features . . . . .437
20.5.1Comparator usage overview .....474
20.6TSC interrupts .....477
20.7TSC registers .....477
20.7.1TSC control register (TSC_CR) .....477
20.7.2TSC interrupt enable register (TSC_IER) .....480
20.7.3TSC interrupt clear register (TSC_ICR) .....481
20.7.4TSC interrupt status register (TSC_ISR) .....481
20.7.5TSC I/O hysteresis control register (TSC_IOHCR) .....482
20.7.6TSC I/O analog switch control register
(TSC_IOASCR) .....		482
20.7.7TSC I/O sampling control register (TSC_IOSCR) .....483
20.7.8TSC I/O channel control register (TSC_IOCCR) .....483
20.7.9TSC I/O group control status register (TSC_IOGCSR) .....484
20.7.10TSC I/O group x counter register (TSC_IOGxCR) .....484
20.7.11TSC register map .....485
21True random number generator (RNG) .....487
21.1Introduction .....487
21.2RNG main features .....487
21.3RNG functional description .....488
21.3.1RNG block diagram .....488
21.3.2RNG internal signals .....488
21.3.3Random number generation .....488
21.3.4RNG initialization .....491
21.3.5RNG operation .....492
21.3.6RNG clocking .....494
21.3.7Error management .....494
21.3.8RNG low-power use .....495
21.4RNG interrupts .....496
21.5RNG processing time .....496
21.6RNG entropy source validation .....497
21.6.1Introduction .....497
21.6.2Validation conditions .....497
21.7RNG registers .....498
21.7.1RNG control register (RNG_CR) .....498
21.7.2RNG status register (RNG_SR) .....500
21.7.3RNG data register (RNG_DR) .....501
21.7.4RNG noise source control register (RNG_NSCR) .....502
21.7.5RNG health test control register (RNG_HTCR) .....502
21.7.6RNG register map .....503
22AES hardware accelerator (AES) .....504
22.1Introduction .....504
22.2AES main features .....504
22.3AES implementation .....504
22.4AES functional description .....505
22.4.1AES block diagram .....505
22.4.2AES internal signals .....505
22.4.3AES cryptographic core .....505
22.4.4AES procedure to perform a cipher operation .....511
22.4.5AES decryption round key preparation .....514
22.4.6AES ciphertext stealing and data padding .....514
22.4.7AES task suspend and resume .....515
22.4.8AES basic chaining modes (ECB, CBC) .....515
22.4.9AES counter (CTR) mode .....520
22.4.10AES Galois/counter mode (GCM) .....522
22.4.11AES Galois message authentication code (GMAC) .....527
22.4.12AES counter with CBC-MAC (CCM) .....529
22.4.13AES data registers and data swapping .....534
22.4.14AES key registers .....537
22.4.15AES initialization vector registers .....537
22.4.16AES DMA interface .....537
22.4.17AES error management .....539
22.5AES interrupts .....539
22.6AES processing latency .....540
22.7AES registers .....541
22.7.1AES control register (AES_CR) .....541
22.7.2AES status register (AES_SR) .....543
22.7.3AES data input register (AES_DINR) .....544
22.7.4AES data output register (AES_DOUTR) .....545
22.7.5AES key register 0 (AES_KEYR0) .....546
22.7.6AES key register 1 (AES_KEYR1) .....546
22.7.7AES key register 2 (AES_KEYR2) . . . . .547
22.7.8AES key register 3 (AES_KEYR3) . . . . .547
22.7.9AES initialization vector register 0 (AES_IVR0) . . . . .547
22.7.10AES initialization vector register 1 (AES_IVR1) . . . . .548
22.7.11AES initialization vector register 2 (AES_IVR2) . . . . .548
22.7.12AES initialization vector register 3 (AES_IVR3) . . . . .548
22.7.13AES key register 4 (AES_KEYR4) . . . . .549
22.7.14AES key register 5 (AES_KEYR5) . . . . .549
22.7.15AES key register 6 (AES_KEYR6) . . . . .549
22.7.16AES key register 7 (AES_KEYR7) . . . . .550
22.7.17AES suspend registers (AES_SUSPxR) . . . . .550
22.7.18AES register map . . . . .551
23Advanced-control timer (TIM1) . . . . .553
23.1TIM1 introduction . . . . .553
23.2TIM1 main features . . . . .554
23.3TIM1 functional description . . . . .556
23.3.1Time-base unit . . . . .556
23.3.2Counter modes . . . . .558
23.3.3Repetition counter . . . . .569
23.3.4External trigger input . . . . .571
23.3.5Clock selection . . . . .572
23.3.6Capture/compare channels . . . . .576
23.3.7Input capture mode . . . . .578
23.3.8PWM input mode . . . . .579
23.3.9Forced output mode . . . . .580
23.3.10Output compare mode . . . . .581
23.3.11PWM mode . . . . .582
23.3.12Asymmetric PWM mode . . . . .585
23.3.13Combined PWM mode . . . . .586
23.3.14Combined 3-phase PWM mode . . . . .587
23.3.15Complementary outputs and dead-time insertion . . . . .588
23.3.16Using the break function . . . . .590
23.3.17Bidirectional break inputs . . . . .596
23.3.18Clearing the OCxREF signal on an external event . . . . .598
23.3.196-step PWM generation . . . . .599
23.3.20One-pulse mode . . . . .600
23.3.21Retriggerable one pulse mode . . . . .601
23.3.22Encoder interface mode . . . . .602
23.3.23UIF bit remapping . . . . .604
23.3.24Timer input XOR function . . . . .605
23.3.25Interfacing with Hall sensors . . . . .605
23.3.26Timer synchronization . . . . .608
23.3.27ADC synchronization . . . . .612
23.3.28DMA burst mode . . . . .612
23.3.29Debug mode . . . . .613
23.4TIM1 registers . . . . .614
23.4.1TIM1 control register 1 (TIM1_CR1) . . . . .614
23.4.2TIM1 control register 2 (TIM1_CR2) . . . . .615
23.4.3TIM1 slave mode control register
(TIM1_SMCR) . . . . .		618
23.4.4TIM1 DMA/interrupt enable register
(TIM1_DIER) . . . . .		620
23.4.5TIM1 status register (TIM1_SR) . . . . .622
23.4.6TIM1 event generation register (TIM1_EGR) . . . . .624
23.4.7TIM1 capture/compare mode register 1 (TIM1_CCMR1) . . . . .625
23.4.8TIM1 capture/compare mode register 1 [alternate]
(TIM1_CCMR1) . . . . .		626
23.4.9TIM1 capture/compare mode register 2 (TIM1_CCMR2) . . . . .629
23.4.10TIM1 capture/compare mode register 2 [alternate]
(TIM1_CCMR2) . . . . .		630
23.4.11TIM1 capture/compare enable register
(TIM1_CCER) . . . . .		631
23.4.12TIM1 counter (TIM1_CNT) . . . . .635
23.4.13TIM1 prescaler (TIM1_PSC) . . . . .635
23.4.14TIM1 auto-reload register (TIM1_ARR) . . . . .635
23.4.15TIM1 repetition counter register (TIM1_RCR) . . . . .636
23.4.16TIM1 capture/compare register 1
(TIM1_CCR1) . . . . .		636
23.4.17TIM1 capture/compare register 2
(TIM1_CCR2) . . . . .		637
23.4.18TIM1 capture/compare register 3
(TIM1_CCR3) . . . . .		637
23.4.19TIM1 capture/compare register 4
(TIM1_CCR4) . . . . .		638
23.4.20TIM1 break and dead-time register
(TIM1_BDTR) . . . . .		638
23.4.21TIM1 DMA control register (TIM1_DCR) .....642
23.4.22TIM1 DMA address for full transfer (TIM1_DMAR) .....643
23.4.23TIM1 option register 1 (TIM1_OR1) .....644
23.4.24TIM1 capture/compare mode register 3 (TIM1_CCMR3) .....644
23.4.25TIM1 capture/compare register 5 (TIM1_CCR5) .....645
23.4.26TIM1 capture/compare register 6 (TIM1_CCR6) .....646
23.4.27TIM1 alternate function option register 1 (TIM1_AF1) .....647
23.4.28TIM1 Alternate function register 2 (TIM1_AF2) .....648
23.4.29TIM1 timer input selection register (TIM1_TISEL) .....650
23.4.30TIM1 register map .....651
24General-purpose timers (TIM2/TIM3) .....654
24.1TIM2/TIM3 introduction .....654
24.2TIM2/TIM3 main features .....654
24.3TIM2/TIM3 functional description .....656
24.3.1Time-base unit .....656
24.3.2Counter modes .....658
24.3.3Clock selection .....668
24.3.4Capture/Compare channels .....672
24.3.5Input capture mode .....674
24.3.6PWM input mode .....675
24.3.7Forced output mode .....676
24.3.8Output compare mode .....676
24.3.9PWM mode .....677
24.3.10Asymmetric PWM mode .....681
24.3.11Combined PWM mode .....681
24.3.12Clearing the OCxREF signal on an external event .....682
24.3.13One-pulse mode .....684
24.3.14Retriggerable one pulse mode .....685
24.3.15Encoder interface mode .....686
24.3.16UIF bit remapping .....688
24.3.17Timer input XOR function .....688
24.3.18Timers and external trigger synchronization .....689
24.3.19Timer synchronization . . . . .692
24.3.20DMA burst mode . . . . .697
24.3.21Debug mode . . . . .698
24.4TIM2/TIM3 registers . . . . .699
24.4.1TIMx control register 1 (TIMx_CR1)(x = 2 to 3) . . . . .699
24.4.2TIMx control register 2 (TIMx_CR2)(x = 2 to 3) . . . . .700
24.4.3TIMx slave mode control register (TIMx_SMCR)(x = 2 to 3) . . . . .702
24.4.4TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 3) . . . . .705
24.4.5TIMx status register (TIMx_SR)(x = 2 to 3) . . . . .706
24.4.6TIMx event generation register (TIMx_EGR)(x = 2 to 3) . . . . .708
24.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 3) . . . . .709
24.4.8TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 2 to 3) . . . . .		711
24.4.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 3) . . . . .713
24.4.10TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 2 to 3) . . . . .		714
24.4.11TIMx capture/compare enable register
(TIMx_CCER)(x = 2 to 3) . . . . .		715
24.4.12TIMx counter (TIMx_CNT)(x = 2 to 3) . . . . .716
24.4.13TIMx counter [alternate] (TIMx_CNT)(x = 2 to 3) . . . . .717
24.4.14TIMx prescaler (TIMx_PSC)(x = 2 to 3) . . . . .717
24.4.15TIMx auto-reload register (TIMx_ARR)(x = 2 to 3) . . . . .718
24.4.16TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 3) . . . . .718
24.4.17TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 3) . . . . .718
24.4.18TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 3) . . . . .719
24.4.19TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 3) . . . . .719
24.4.20TIMx DMA control register (TIMx_DCR)(x = 2 to 3) . . . . .720
24.4.21TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 3) . . . . .721
24.4.22TIM2 option register 1 (TIM2_OR1) . . . . .721
24.4.23TIM3 option register 1 (TIM3_OR1) . . . . .721
24.4.24TIM2 alternate function option register 1 (TIM2_AF1) . . . . .722
24.4.25TIM3 alternate function option register 1 (TIM3_AF1) . . . . .722
24.4.26TIM2 timer input selection register (TIM2_TISEL) . . . . .723
24.4.27TIM3 timer input selection register (TIM3_TISEL) . . . . .723
24.4.28TIMx register map . . . . .725
25Basic timers (TIM6/TIM7) . . . . .728
25.1TIM6/TIM7 introduction . . . . .728
25.2TIM6/TIM7 main features . . . . .728
25.3TIM6/TIM7 functional description . . . . .729
25.3.1Time-base unit . . . . .729
25.3.2Counting mode . . . . .731
25.3.3UIF bit remapping . . . . .734
25.3.4Clock source . . . . .734
25.3.5Debug mode . . . . .735
25.4TIM6/TIM7 registers . . . . .735
25.4.1TIMx control register 1 (TIMx_CR1)(x = 6 to 7) . . . . .735
25.4.2TIMx control register 2 (TIMx_CR2)(x = 6 to 7) . . . . .737
25.4.3TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) . . . . .737
25.4.4TIMx status register (TIMx_SR)(x = 6 to 7) . . . . .738
25.4.5TIMx event generation register (TIMx_EGR)(x = 6 to 7) . . . . .738
25.4.6TIMx counter (TIMx_CNT)(x = 6 to 7) . . . . .738
25.4.7TIMx prescaler (TIMx_PSC)(x = 6 to 7) . . . . .739
25.4.8TIMx auto-reload register (TIMx_ARR)(x = 6 to 7) . . . . .739
25.4.9TIMx register map . . . . .740
26General-purpose timers (TIM15/TIM16) . . . . .741
26.1TIM15/TIM16 introduction . . . . .741
26.2TIM15 main features . . . . .741
26.3TIM16 main features . . . . .742
26.4TIM15/TIM16 functional description . . . . .745
26.4.1Time-base unit . . . . .745
26.4.2Counter modes . . . . .747
26.4.3Repetition counter . . . . .751
26.4.4Clock selection . . . . .752
26.4.5Capture/compare channels . . . . .754
26.4.6Input capture mode . . . . .756
26.4.7PWM input mode (only for TIM15) . . . . .757
26.4.8Forced output mode . . . . .758
26.4.9Output compare mode . . . . .759
26.4.10PWM mode . . . . .760
26.4.11Combined PWM mode (TIM15 only) . . . . .761
26.4.12Complementary outputs and dead-time insertion . . . . .762
26.4.13Using the break function . . . . .764
26.4.14Bidirectional break inputs . . . . .769
26.4.156-step PWM generation . . . . .770
26.4.16One-pulse mode . . . . .772
26.4.17Retriggerable one pulse mode (TIM15 only) . . . . .773
26.4.18UIF bit remapping . . . . .774
26.4.19Timer input XOR function (TIM15 only) . . . . .775
26.4.20External trigger synchronization (TIM15 only) . . . . .776
26.4.21Slave mode – combined reset + trigger mode . . . . .778
26.4.22DMA burst mode . . . . .778
26.4.23Timer synchronization (TIM15) . . . . .780
26.4.24Using timer output as trigger for other timers (TIM16) . . . . .780
26.4.25Debug mode . . . . .780
26.5TIM15 registers . . . . .781
26.5.1TIM15 control register 1 (TIM15_CR1) . . . . .781
26.5.2TIM15 control register 2 (TIM15_CR2) . . . . .782
26.5.3TIM15 slave mode control register (TIM15_SMCR) . . . . .784
26.5.4TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .785
26.5.5TIM15 status register (TIM15_SR) . . . . .786
26.5.6TIM15 event generation register (TIM15_EGR) . . . . .788
26.5.7TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . .789
26.5.8TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . .		790
26.5.9TIM15 capture/compare enable register (TIM15_CCER) . . . . .793
26.5.10TIM15 counter (TIM15_CNT) . . . . .796
26.5.11TIM15 prescaler (TIM15_PSC) . . . . .796
26.5.12TIM15 auto-reload register (TIM15_ARR) . . . . .796
26.5.13TIM15 repetition counter register (TIM15_RCR) . . . . .797
26.5.14TIM15 capture/compare register 1 (TIM15_CCR1) . . . . .797
26.5.15TIM15 capture/compare register 2 (TIM15_CCR2) . . . . .798
26.5.16TIM15 break and dead-time register (TIM15_BDTR) . . . . .798
26.5.17TIM15 DMA control register (TIM15_DCR) . . . . .801
26.5.18TIM15 DMA address for full transfer (TIM15_DMAR) . . . . .801
26.5.19TIM15 alternate register 1 (TIM15_AF1) . . . . .802
26.5.20TIM15 input selection register (TIM15_TISEL) . . . . .803
26.5.21TIM15 register map . . . . .804
26.6TIM16 registers . . . . .806
26.6.1TIM16 control register 1 (TIM16_CR1) . . . . .806
26.6.2TIM16 control register 2 (TIM16_CR2) .....807
26.6.3TIM16 DMA/interrupt enable register (TIM16_DIER) .....808
26.6.4TIM16 status register (TIM16_SR) .....809
26.6.5TIM16 event generation register (TIM16_EGR) .....810
26.6.6TIM16 capture/compare mode register 1 (TIM16_CCMR1) .....811
26.6.7TIM16 capture/compare mode register 1 [alternate] (TIM16_CCMR1) .....812
26.6.8TIM16 capture/compare enable register (TIM16_CCER) .....814
26.6.9TIM16 counter (TIM16_CNT) .....816
26.6.10TIM16 prescaler (TIM16_PSC) .....817
26.6.11TIM16 auto-reload register (TIM16_ARR) .....817
26.6.12TIM16 repetition counter register (TIM16_RCR) .....818
26.6.13TIM16 capture/compare register 1 (TIM16_CCR1) .....818
26.6.14TIM16 break and dead-time register (TIM16_BDTR) .....819
26.6.15TIM16 DMA control register (TIM16_DCR) .....822
26.6.16TIM16 DMA address for full transfer (TIM16_DMAR) .....822
26.6.17TIM16 alternate function register 1 (TIM16_AF1) .....823
26.6.18TIM16 input selection register (TIM16_TISEL) .....824
26.6.19TIM16 register map .....825
27Low-power timer (LPTIM) .....827
27.1Introduction .....827
27.2LPTIM main features .....827
27.3LPTIM implementation .....828
27.4LPTIM functional description .....829
27.4.1LPTIM block diagram .....829
27.4.2LPTIM pins and internal signals .....830
27.4.3LPTIM input and trigger mapping .....832
27.4.4LPTIM reset and clocks .....833
27.4.5Glitch filter .....834
27.4.6Prescaler .....835
27.4.7Trigger multiplexer .....835
27.4.8Operating mode .....836
27.4.9Timeout function .....838
27.4.10Waveform generation .....838
27.4.11Register update .....839
27.4.12Counter mode .....840
27.4.13Timer enable .....840
29Independent watchdog (IWDG) . . . . .882
29.1Introduction . . . . .882
29.2IWDG main features . . . . .882
29.3IWDG implementation . . . . .882
29.4IWDG functional description . . . . .883
29.4.1IWDG block diagram . . . . .883
29.4.2IWDG internal signals . . . . .884
29.4.3Software and hardware watchdog modes . . . . .884
29.4.4Window option . . . . .885
29.4.5Debug . . . . .888
29.4.6Register access protection . . . . .888
29.5IWDG low power modes . . . . .889
29.6IWDG interrupts . . . . .889
29.7IWDG registers . . . . .891
29.7.1IWDG key register (IWDG_KR) . . . . .892
29.7.2IWDG prescaler register (IWDG_PR) . . . . .892
29.7.3IWDG reload register (IWDG_RLR) . . . . .893
29.7.4IWDG status register (IWDG_SR) . . . . .893
29.7.5IWDG window register (IWDG_WINR) . . . . .895
29.7.6IWDG early wake-up interrupt register (IWDG_EWCR) . . . . .895
29.7.7IWDG register map . . . . .897
30System window watchdog (WWDG) . . . . .898
30.1Introduction . . . . .898
30.2WWDG main features . . . . .898
30.3WWDG implementation . . . . .898
30.4WWDG functional description . . . . .899
30.4.1WWDG block diagram . . . . .899
30.4.2WWDG internal signals . . . . .899
30.4.3Enabling the watchdog . . . . .900
30.4.4Controlling the down-counter . . . . .900
30.4.5How to program the watchdog timeout . . . . .900
30.4.6Debug mode . . . . .901
30.5WWDG interrupts . . . . .902
30.6WWDG registers . . . . .902
30.6.1WWDG control register (WWDG_CR) . . . . .902
30.6.2WWDG configuration register (WWDG_CFR) . . . . .903
30.6.3WWDG status register (WWDG_SR) . . . . .903
30.6.4WWDG register map . . . . .904
31Real-time clock (RTC) . . . . .905
31.1Introduction . . . . .905
31.2RTC main features . . . . .905
31.3RTC functional description . . . . .905
31.3.1RTC block diagram . . . . .905
31.3.2RTC pins and internal signals . . . . .907
31.3.3GPIOs controlled by the RTC and TAMP . . . . .908
31.3.4Clock and prescalers . . . . .910
31.3.5Real-time clock and calendar . . . . .911
31.3.6Calendar ultra-low power mode . . . . .912
31.3.7Programmable alarms . . . . .912
31.3.8Periodic auto-wake-up . . . . .912
31.3.9RTC initialization and configuration . . . . .913
31.3.10Reading the calendar . . . . .916
31.3.11Resetting the RTC . . . . .917
31.3.12RTC synchronization . . . . .917
31.3.13RTC reference clock detection . . . . .917
31.3.14RTC smooth digital calibration . . . . .918
31.3.15Timestamp function . . . . .920
31.3.16Calibration clock output . . . . .921
31.3.17Tamper and alarm output . . . . .922
31.4RTC low-power modes . . . . .922
31.5RTC interrupts . . . . .923
31.6RTC registers . . . . .923
31.6.1RTC time register (RTC_TR) . . . . .924
31.6.2RTC date register (RTC_DR) . . . . .925
31.6.3RTC subsecond register (RTC_SSR) . . . . .926
31.6.4RTC initialization control and status register (RTC_ICSR) . . . . .926
31.6.5RTC prescaler register (RTC_PRER) . . . . .928
31.6.6RTC wake-up timer register (RTC_WUTR) . . . . .929
31.6.7RTC control register (RTC_CR) . . . . .929
31.6.8RTC write protection register (RTC_WPR) . . . . .933
31.6.9RTC calibration register (RTC_CALR) . . . . .933
31.6.10RTC shift control register (RTC_SHIFTR) . . . . .934
31.6.11RTC timestamp time register (RTC_TSTR) . . . . .935
31.6.12RTC timestamp date register (RTC_TSDR) . . . . .936
31.6.13RTC timestamp subsecond register (RTC_TSSSR) . . . . .936
31.6.14RTC alarm A register (RTC_ALRMAR) . . . . .937
31.6.15RTC alarm A subsecond register (RTC_ALRMASSR) . . . . .938
31.6.16RTC alarm B register (RTC_ALRMBR) . . . . .939
31.6.17RTC alarm B subsecond register (RTC_ALRMBSSR) . . . . .940
31.6.18RTC status register (RTC_SR) . . . . .941
31.6.19RTC masked interrupt status register (RTC_MISR) . . . . .942
31.6.20RTC status clear register (RTC_SCR) . . . . .943
31.6.21RTC alarm A binary mode register (RTC_ALRABINR) . . . . .944
31.6.22RTC alarm B binary mode register (RTC_ALRBBINR) . . . . .944
31.6.23RTC register map . . . . .945
32Tamper and backup registers (TAMP) . . . . .947
32.1Introduction . . . . .947
32.2TAMP main features . . . . .947
32.3TAMP functional description . . . . .948
32.3.1TAMP block diagram . . . . .948
32.3.2TAMP pins and internal signals . . . . .949
32.3.3GPIOs controlled by the RTC and TAMP . . . . .950
32.3.4TAMP register write protection . . . . .950
32.3.5Tamper detection . . . . .950
32.3.6TAMP backup registers and other device secrets erase . . . . .951
32.3.7Tamper detection configuration and initialization . . . . .952
32.4TAMP low-power modes . . . . .954
32.5TAMP interrupts . . . . .955
32.6TAMP registers . . . . .955
32.6.1TAMP control register 1 (TAMP_CR1) . . . . .955
32.6.2TAMP control register 2 (TAMP_CR2) . . . . .957
32.6.3TAMP control register 3 (TAMP_CR3) . . . . .959
32.6.4TAMP filter control register (TAMP_FLTCR) . . . . .960
32.6.5TAMP interrupt enable register (TAMP_IER) . . . . .961
33.8.8I2C receive data register (I2C_RXDR) .....1013
33.8.9I2C transmit data register (I2C_TXDR) .....1014
33.8.10I2C register map .....1015
34Universal synchronous/asynchronous receiver transmitter (USART/UART) .....1016
34.1Introduction .....1016
34.2USART main features .....1016
34.3USART extended features .....1017
34.4USART implementation .....1017
34.5USART functional description .....1019
34.5.1USART block diagram .....1019
34.5.2USART pins and internal signals .....1019
34.5.3USART clocks .....1021
34.5.4USART character description .....1021
34.5.5USART FIFOs and thresholds .....1024
34.5.6USART transmitter .....1024
34.5.7USART receiver .....1027
34.5.8USART baud rate generation .....1034
34.5.9Tolerance of the USART receiver to clock deviation .....1036
34.5.10USART auto baud rate detection .....1037
34.5.11USART multiprocessor communication .....1039
34.5.12USART Modbus communication .....1041
34.5.13USART parity control .....1042
34.5.14USART LIN (local interconnection network) mode .....1043
34.5.15USART synchronous mode .....1045
34.5.16USART single-wire half-duplex communication .....1049
34.5.17USART receiver timeout .....1049
34.5.18USART smartcard mode .....1050
34.5.19USART IrDA SIR ENDEC block .....1054
34.5.20Continuous communication using USART and DMA .....1057
34.5.21RS232 hardware flow control and RS485 driver enable .....1059
34.5.22USART low-power management .....1062
34.6USART in low-power modes .....1065
34.7USART interrupts .....1065
34.8USART registers .....1068

35 Low-power universal asynchronous receiver transmitter (LPUART) . . . . . 1106

35.4.15LPUART low-power management . . . . .1131
35.5LPUART in low-power modes . . . . .1134
35.6LPUART interrupts . . . . .1135
35.7LPUART registers . . . . .1136
35.7.1LPUART control register 1 (LPUART_CR1) . . . . .1136
35.7.2LPUART control register 1 [alternate] (LPUART_CR1) . . . . .1139
35.7.3LPUART control register 2 (LPUART_CR2) . . . . .1142
35.7.4LPUART control register 3 (LPUART_CR3) . . . . .1144
35.7.5LPUART control register 3 [alternate] (LPUART_CR3) . . . . .1147
35.7.6LPUART baud rate register (LPUART_BRR) . . . . .1149
35.7.7LPUART request register (LPUART_RQR) . . . . .1149
35.7.8LPUART interrupt and status register (LPUART_ISR) . . . . .1150
35.7.9LPUART interrupt and status register [alternate] (LPUART_ISR) . . . . .1155
35.7.10LPUART interrupt flag clear register (LPUART_ICR) . . . . .1158
35.7.11LPUART receive data register (LPUART_RDR) . . . . .1159
35.7.12LPUART transmit data register (LPUART_TDR) . . . . .1159
35.7.13LPUART prescaler register (LPUART_PRESC) . . . . .1160
35.7.14LPUART register map . . . . .1161
36Serial peripheral interface (SPI) . . . . .1163
36.1Introduction . . . . .1163
36.2SPI main features . . . . .1163
36.3SPI implementation . . . . .1164
36.4SPI functional description . . . . .1164
36.4.1General description . . . . .1164
36.4.2Communications between one master and one slave . . . . .1165
36.4.3Standard multislave communication . . . . .1167
36.4.4Multimaster communication . . . . .1168
36.4.5Slave select (NSS) pin management . . . . .1169
36.4.6Communication formats . . . . .1170
36.4.7Configuration of SPI . . . . .1172
36.4.8Procedure for enabling SPI . . . . .1173
36.4.9Data transmission and reception procedures . . . . .1173
36.4.10SPI status flags . . . . .1183
36.4.11SPI error flags . . . . .1184
36.4.12NSS pulse mode . . . . .1185
36.4.13TI mode1185
36.4.14CRC calculation1186
36.5SPI interrupts1188
36.6SPI registers1189
36.6.1SPI control register 1 (SPIx_CR1)1189
36.6.2SPI control register 2 (SPIx_CR2)1191
36.6.3SPI status register (SPIx_SR)1193
36.6.4SPI data register (SPIx_DR)1194
36.6.5SPI CRC polynomial register (SPIx_CRCPR)1195
36.6.6SPI Rx CRC register (SPIx_RXCRCR)1195
36.6.7SPI Tx CRC register (SPIx_TXCRCR)1195
36.6.8SPI register map1197
37Universal serial bus full-speed device interface (USB)1198
37.1Introduction1198
37.2USB main features1198
37.3USB implementation1198
37.4USB functional description1199
37.4.1USB block diagram1199
37.4.2USB pins and internal signals1200
37.4.3USB reset and clocks1200
37.4.4General description and Device mode functionality1200
37.4.5Description of USB blocks used in both Device and Host modes1201
37.4.6Description of host frame scheduler (HFS) specific to Host mode1202
37.5Programming considerations for Device and Host modes1203
37.5.1Generic USB Device programming1203
37.5.2System and power-on reset1204
37.5.3Double-buffered endpoints and usage in Device mode1211
37.5.4Double buffered channels: usage in Host mode1213
37.5.5Isochronous transfers in Device mode1214
37.5.6Isochronous transfers in Host mode1215
37.5.7Suspend/resume events1216
37.6USB registers1220
37.6.1USB control register (USB_CNTR)1220
37.6.2USB interrupt status register (USB_ISTR)1223
37.6.3USB frame number register (USB_FNR)1227
37.6.4USB Device address (USB_DADDR) . . . . .1227
37.6.5USB LPM control and status register (USB_LPMCSR) . . . . .1228
37.6.6USB battery charging detector (USB_BCDR) . . . . .1229
37.6.7USB endpoint/channel n register (USB_CHEPnR) . . . . .1230
37.6.8USB register map . . . . .1239
37.7USBFSRAM registers . . . . .1240
37.7.1Channel/endpoint transmit buffer descriptor n
(USB_CHEP_TXRXBD_n) . . . . .		1241
37.7.2Channel/endpoint receive buffer descriptor n [alternate]
(USB_CHEP_TXRXBD_n) . . . . .		1241
37.7.3Channel/endpoint receive buffer descriptor n
(USB_CHEP_RXTXBD_n) . . . . .		1243
37.7.4Channel/endpoint transmit buffer descriptor n [alternate]
(USB_CHEP_RXTXBD_n) . . . . .		1244
37.7.5USBFSRAM register map . . . . .1245
38Debug support (DBG) . . . . .1246
38.1Introduction . . . . .1246
38.2DBG functional description . . . . .1246
38.2.1DBG block diagram . . . . .1246
38.2.2DBG pins and internal signals . . . . .1247
38.2.3ID codes and locking mechanism . . . . .1247
38.2.4DBG reset and clocks . . . . .1247
38.2.5DBG power domains . . . . .1248
38.2.6Debug in low-power modes . . . . .1248
38.2.7Security . . . . .1248
38.3Serial-wire debug port (SW-DP) . . . . .1249
38.3.1Serial-wire debug port . . . . .1249
38.3.2Debug port registers . . . . .1250
38.3.3DEBUG port registers . . . . .1251
38.3.4Debug port register map and reset values . . . . .1257
38.4Access ports . . . . .1258
38.4.1Access port registers . . . . .1258
38.4.2Access port register map . . . . .1264
38.5ROM tables . . . . .1266
38.5.1System ROM table registers . . . . .1268
38.5.2System ROM table register map . . . . .1272
38.5.3MCU ROM table registers . . . . .1273

39 Device electronic signature . . . . . 1317

Appendix A OEM key CRC calculation source code . . . . . 1320

List of tables

Table 1.Peripherals versus products . . . . .52
Table 2.STM32U073xx and STM32U083xx memory boundary addresses. . . . .57
Table 3.STM32U031xx memory boundary addresses . . . . .57
Table 4.STM32U0 series peripheral register boundary addresses . . . . .58
Table 5.SRAM size . . . . .60
Table 6.Boot modes. . . . .62
Table 7.Flash memory organization: information block . . . . .65
Table 8.Flash memory organization: main memory. . . . .66
Table 9.Number of wait states according to flash memory clock (HCLK) frequency. . . . .67
Table 10.Page erase overview . . . . .69
Table 11.Mass erase overview . . . . .70
Table 12.Option byte format . . . . .75
Table 13.Organization of option bytes . . . . .75
Table 14.Flash memory read protection status . . . . .78
Table 15.Access status versus protection level and execution modes . . . . .80
Table 17.HDP extension protection. . . . .84
Table 18.FLASH interrupt requests . . . . .85
Table 19.FLASH register map and reset values . . . . .102
Table 20.PVM features . . . . .111
Table 21.Low-power mode summary . . . . .115
Table 22.Functionalities depending on the working mode. . . . .116
Table 23.Low-power run . . . . .119
Table 24.Sleep. . . . .121
Table 25.Low-power sleep. . . . .122
Table 26.Stop 0 mode . . . . .124
Table 27.Stop 1 mode . . . . .125
Table 28.Stop 2 mode . . . . .127
Table 29.Standby mode. . . . .129
Table 30.Shutdown mode . . . . .131
Table 31.PWR register map and reset values. . . . .148
Table 32.Clock source frequency . . . . .162
Table 33.RCC register map and reset values . . . . .210
Table 34.CRS features . . . . .214
Table 35.CRS internal input/output signals . . . . .215
Table 36.CRS interconnection. . . . .216
Table 37.Effect of low-power modes on CRS . . . . .219
Table 38.Interrupt control bits . . . . .219
Table 39.CRS register map and reset values . . . . .224
Table 40.Port bit configuration table . . . . .227
Table 41.GPIO register map and reset values . . . . .241
Table 42.SYSCFG register map and reset values. . . . .262
Table 43.DMA implementation . . . . .266
Table 44.DMA internal input/output signals . . . . .267
Table 45.Programmable data width and endian behavior (when PINC = MINC = 1) . . . . .273
Table 46.DMA interrupt requests. . . . .275
Table 47.DMA register map and reset values . . . . .283
Table 48.DMAMUX instantiation . . . . .287
Table 49.DMAMUX: assignment of multiplexer inputs to resources . . . . .288
Table 50.DMAMUX: assignment of trigger inputs to resources . . . . .288
Table 51.DMAMUX: assignment of synchronization inputs to resources . . . . .289
Table 52.DMAMUX signals . . . . .291
Table 53.DMAMUX interrupts . . . . .295
Table 54.DMAMUX register map and reset values . . . . .300
Table 55.Vector table . . . . .302
Table 56.EXTI signal overview . . . . .306
Table 57.EVG pin overview . . . . .306
Table 58.EXTI event input configurations and register control . . . . .308
Table 59.EXTI line connections . . . . .310
Table 60.Masking functionality . . . . .311
Table 61.EXTI register map sections . . . . .312
Table 62.EXTI controller register map and reset values . . . . .318
Table 63.CRC internal input/output signals . . . . .321
Table 64.CRC register map and reset values . . . . .326
Table 65.ADC main features . . . . .329
Table 66.ADC input/output pins . . . . .331
Table 67.ADC internal input/output signals . . . . .331
Table 68.External triggers . . . . .331
Table 69.Latency between trigger and start of conversion . . . . .337
Table 70.Configuring the trigger polarity . . . . .344
Table 71.tSAR timings depending on resolution . . . . .346
Table 72.Analog watchdog comparison . . . . .355
Table 73.Analog watchdog 1 channel selection . . . . .356
Table 74.Maximum output results vs N and M. Grayed values indicates truncation . . . . .360
Table 75.ADC interrupts . . . . .364
Table 76.ADC register map and reset values . . . . .384
Table 77.DAC features . . . . .388
Table 78.DAC input/output pins . . . . .389
Table 79.DAC internal input/output signals . . . . .389
Table 80.DAC interconnection . . . . .389
Table 81.Sample and refresh timings . . . . .396
Table 82.Channel output modes summary . . . . .397
Table 83.Effect of low-power modes on DAC . . . . .400
Table 84.DAC interrupts . . . . .401
Table 85.DAC register map and reset values . . . . .409
Table 86.VREF buffer modes . . . . .411
Table 87.VREFBUF register map and reset values . . . . .413
Table 88.COMP internal input/output signals . . . . .415
Table 89.COMP1 noninverting input assignment . . . . .416
Table 90.COMP1 inverting input assignment . . . . .416
Table 91.COMP2 noninverting input assignment . . . . .416
Table 92.COMP2 inverting input assignment . . . . .416
Table 93.Comparator behavior in the low-power modes . . . . .419
Table 94.Interrupt control bits . . . . .420
Table 95.COMP register map and reset values . . . . .425
Table 96.Operational amplifier possible connections . . . . .427
Table 97.Operating modes and calibration . . . . .432
Table 98.Effect of low-power modes on the OPAMP . . . . .433
Table 99.OPAMP register map and reset values . . . . .436
Table 100.Example of frame rate calculation . . . . .440
Table 101.Blink frequency . . . . .448
Table 102.Remapping capability . . . . .451
Table 103.LCD interrupt requests . . . . .455
Table 104.LCD register map and reset values . . . . .462
Table 105.TSC implementation . . . . .466
Table 106.Acquisition sequence summary . . . . .469
Table 107.Spread spectrum deviation versus AHB clock frequency . . . . .471
Table 108.I/O state depending on its mode and IODEF bit value . . . . .472
Table 109.Effect of low-power modes on TSC . . . . .474
Table 110.Interrupt control bits . . . . .477
Table 111.TSC register map and reset values . . . . .485
Table 112.RNG internal input/output signals . . . . .488
Table 113.RNG interrupt requests . . . . .496
Table 114.RNG initialization times . . . . .497
Table 115.RNG configurations . . . . .497
Table 116.Configuration selection . . . . .498
Table 117.RNG register map and reset map . . . . .503
Table 118.AES internal input/output signals . . . . .505
Table 119.CTR mode initialization vector definition . . . . .521
Table 120.GCM last block definition . . . . .523
Table 121.Initialization of AES_IVRx registers in GCM mode . . . . .524
Table 122.Initialization of AES_IVRx registers in CCM mode . . . . .531
Table 123.Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . .537
Table 124.AES interrupt requests . . . . .540
Table 125.Processing latency for ECB, CBC and CTR . . . . .540
Table 126.Processing latency for GCM and CCM (in clock cycles) . . . . .540
Table 127.AES register map and reset values . . . . .551
Table 128.Behavior of timer outputs versus BRK/BRK2 inputs . . . . .595
Table 129.Break protection disarming conditions . . . . .597
Table 130.Counting direction versus encoder signals . . . . .603
Table 131.TIM1 internal trigger connection . . . . .620
Table 132.Output control bits for complementary OCx and OCxN channels with break feature . . . . .634
Table 133.TIM1 register map and reset values . . . . .651
Table 134.Counting direction versus encoder signals . . . . .687
Table 135.TIMx internal trigger connection . . . . .705
Table 136.Output control bit for standard OCx channels . . . . .716
Table 137.TIM2/TIM3 register map and reset values . . . . .725
Table 138.TIMx register map and reset values . . . . .740
Table 139.Break protection disarming conditions . . . . .769
Table 140.TIMx Internal trigger connection . . . . .785
Table 141.Output control bits for complementary OCx and OCxN channels with break feature
(TIM15) . . . . .		795
Table 142.TIM15 register map and reset values . . . . .804
Table 143.Output control bits for complementary OCx and OCxN channels with break feature
(TIM16/17) . . . . .		816
Table 144.TIM16 register map and reset values . . . . .825
Table 145.STM32U0 series LPTIM features . . . . .828
Table 146.LPTIM1/2/3 input/output pins . . . . .830
Table 147.LPTIM1/2/3 internal signals . . . . .831
Table 148.LPTIM1/2/3 external trigger connections . . . . .832
Table 149.LPTIM1/2/3 input 1 connections . . . . .832
Table 150.LPTIM1/2/3 input 2 connections . . . . .832
Table 151.LPTIM1/2/3 input capture 1 connections . . . . .832
Table 152.LPTIM1/2/3 input capture 2 connections . . . . .833
Table 153.LPTIM1/3 input capture 2 connections . . . . .833
Table 154.LPTIM1/2/3 input capture 2 connections . . . . .833
Table 155.Prescaler division ratios . . . . .835
Table 156.Encoder counting scenarios . . . . .842
Table 157.Input capture Glitch filter latency (in counter step unit). . . . .846
Table 158.Effect of low-power modes on the LPTIM. . . . .850
Table 159.Interrupt events. . . . .851
Table 160.LPTIM register map and reset values. . . . .878
Table 161.IWDG features . . . . .882
Table 162.IWDG delays versus actions . . . . .884
Table 163.IWDG internal input/output signals . . . . .884
Table 164.Effect of low power modes on IWDG . . . . .889
Table 165.IWDG interrupt request. . . . .891
Table 166.IWDG register map and reset values . . . . .897
Table 167.WWDG features . . . . .898
Table 168.WWDG internal input/output signals. . . . .899
Table 169.WWDG register map and reset values . . . . .904
Table 170.RTC input/output pins . . . . .907
Table 171.RTC internal input/output signals . . . . .907
Table 172.RTC interconnection . . . . .908
Table 173.RTC pin configuration . . . . .908
Table 174.RTC_OUT mapping . . . . .910
Table 175.Effect of low-power modes on RTC . . . . .922
Table 176.RTC pins functionality over modes . . . . .922
Table 177.Interrupt requests . . . . .923
Table 178.RTC register map and reset values . . . . .945
Table 179.TAMP input/output pins . . . . .949
Table 180.TAMP internal input/output signals. . . . .949
Table 181.TAMP interconnection . . . . .950
Table 182.Effect of low-power modes on TAMP . . . . .954
Table 183.TAMP pins functionality over modes . . . . .954
Table 184.Interrupt requests . . . . .955
Table 185.TAMP register map and reset values . . . . .967
Table 186.I2C implementation. . . . .968
Table 187.I2C input/output pins. . . . .970
Table 188.I2C internal input/output signals . . . . .970
Table 189.Comparison of analog and digital filters . . . . .972
Table 190.I 2 C-bus specification data setup and hold times . . . . .974
Table 191.I2C configuration. . . . .978
Table 192.I 2 C-bus specification clock timings . . . . .989
Table 193.Timing settings for f I2CCLK of 8 MHz. . . . .999
Table 194.Timing settings for f I2CCLK of 16 MHz. . . . .999
Table 195.Timing settings for f I2CCLK of 48 MHz. . . . .1000
Table 196.Effect of low-power modes to I2C. . . . .1002
Table 197.I2C interrupt requests . . . . .1002
Table 198.I2C register map and reset values . . . . .1015
Table 199.Instance implementation on STM32U0 series . . . . .1017
Table 200.USART/LPUART features . . . . .1018
Table 201.USART/UART input/output pins . . . . .1020
Table 202.USART internal input/output signals. . . . .1021
Table 203.Noise detection from sampled data . . . . .1033
Table 204.Tolerance of the USART receiver when BRR [3:0] = 0000. . . . .1037
Table 205.Tolerance of the USART receiver when BRR[3:0] is different from 0000. . . . .1037
Table 206.USART frame formats . . . . .1042
Table 207.Effect of low-power modes on the USART . . . . .1065
Table 208.USART interrupt requests. . . . .1066
Table 209.USART register map and reset values . . . . .1104
Table 210.Instance implementation on STM32U0 series . . . . .1107
Table 211.USART/LPUART features . . . . .1108
Table 212.LPUART input/output pins . . . . .1110
Table 213.LPUART internal input/output signals. . . . .1110
Table 214.Error calculation for programmed baud rates at lpuart_ker_ck_pres= 32.768 kHz . . . . .1121
Table 215.Tolerance of the LPUART receiver. . . . .1122
Table 217.Effect of low-power modes on the LPUART . . . . .1134
Table 218.LPUART interrupt requests. . . . .1135
Table 219.LPUART register map and reset values . . . . .1161
Table 220.STM32U0 series SPI implementation. . . . .1164
Table 221.SPI interrupt requests. . . . .1188
Table 222.SPI register map and reset values . . . . .1197
Table 223.STM32U073/83 USB implementation. . . . .1198
Table 224.USB input/output pins. . . . .1200
Table 225.Double-buffering buffer flag definition. . . . .1212
Table 226.Bulk double-buffering memory buffers usage (Device mode). . . . .1212
Table 227.Bulk double-buffering memory buffers usage (Host mode) . . . . .1214
Table 228.Isochronous memory buffers usage . . . . .1215
Table 229.Isochronous memory buffers usage . . . . .1216
Table 230.Resume event detection. . . . .1218
Table 231.Resume event detection for host . . . . .1219
Table 232.Reception status encoding . . . . .1237
Table 233.Endpoint/channel type encoding. . . . .1237
Table 234.Endpoint/channel kind meaning . . . . .1237
Table 235.Transmission status encoding . . . . .1237
Table 236.USB register map and reset values . . . . .1239
Table 237.Definition of allocated buffer memory . . . . .1242
Table 238.USBFSRAM register map and reset values . . . . .1245
Table 239.SW debug port pins . . . . .1247
Table 240.Authentication signal states . . . . .1249
Table 241.Life cycle state and debug states . . . . .1249
Table 242.Packet request . . . . .1250
Table 243.ACK response. . . . .1250
Table 244.Data transfer. . . . .1250
Table 245.Debug port registers. . . . .1251
Table 246.Debug port register map and reset values . . . . .1257
Table 247.MEM-AP registers. . . . .1258
Table 248.Access port register map and reset values. . . . .1264
Table 249.System ROM table . . . . .1266
Table 250.MCU ROM table . . . . .1266
Table 251.Processor ROM table . . . . .1267
Table 252.System ROM table register map and reset values . . . . .1272
Table 253.MCU ROM table register map and reset values . . . . .1277
Table 254.CPU ROM table register map and reset values . . . . .1282
Table 255.DWT register map and reset values . . . . .1289
Table 256.BPU register map and reset values . . . . .1296
Table 257. SCS register map and reset values . . . . .1302
Table 258. Peripheral clock freeze control bits. . . . .1304
Table 259. Peripheral behavior in debug mode . . . . .1304
Table 260. DBGMCU register map and reset values . . . . .1314
Table 261. Document revision history . . . . .1322

List of figures

Figure 1.System architecture . . . . .53
Figure 2.Memory map . . . . .56
Figure 3.Changing read protection (RDP) level . . . . .80
Figure 4.Example of HDP extension protection . . . . .84
Figure 5.Example of disabling core debug access . . . . .85
Figure 6.Power supply overview . . . . .105
Figure 7.Brown-out reset waveform . . . . .110
Figure 8.PVD thresholds . . . . .111
Figure 9.Low-power modes possible transitions . . . . .114
Figure 10.Simplified diagram of the reset circuit . . . . .151
Figure 11.Clock tree . . . . .156
Figure 12.HSE/ LSE clock sources . . . . .157
Figure 13.Frequency measurement with TIM16 in capture mode . . . . .166
Figure 14.CRS block diagram . . . . .215
Figure 15.CRS counter behavior . . . . .217
Figure 16.Basic structure of an I/O port bit . . . . .226
Figure 17.Basic structure of a 5-Volt tolerant I/O port bit . . . . .226
Figure 18.Input floating/pull up/pull down configurations . . . . .231
Figure 19.Output configuration . . . . .232
Figure 20.Alternate function configuration . . . . .233
Figure 21.High impedance-analog configuration . . . . .233
Figure 22.DMA block diagram . . . . .267
Figure 23.DMAMUX block diagram . . . . .290
Figure 24.Synchronization mode of the DMAMUX request line multiplexer channel . . . . .293
Figure 25.Event generation of the DMA request line multiplexer channel . . . . .293
Figure 26.EXTI block diagram . . . . .306
Figure 27.Configurable event trigger logic CPU wake-up . . . . .308
Figure 28.Direct event trigger logic CPU wake-up . . . . .309
Figure 29.EXTI GPIO mux . . . . .310
Figure 30.CRC calculation unit block diagram . . . . .321
Figure 31.ADC block diagram . . . . .330
Figure 32.ADC calibration . . . . .334
Figure 33.Calibration factor forcing . . . . .334
Figure 34.Enabling/disabling the ADC . . . . .335
Figure 35.ADC clock scheme . . . . .336
Figure 36.ADC connectivity . . . . .338
Figure 37.Analog-to-digital conversion time . . . . .343
Figure 38.ADC conversion timings . . . . .343
Figure 39.Stopping an ongoing conversion . . . . .344
Figure 40.Single conversions of a sequence, software trigger . . . . .347
Figure 41.Continuous conversion of a sequence, software trigger . . . . .347
Figure 42.Single conversions of a sequence, hardware trigger . . . . .348
Figure 43.Continuous conversions of a sequence, hardware trigger . . . . .348
Figure 44.Data alignment and resolution (oversampling disabled: OVSE = 0) . . . . .349
Figure 45.Example of overrun (OVR) . . . . .350
Figure 46.Wait mode conversion (continuous mode, software trigger) . . . . .353
Figure 47.Behavior with WAIT = 0, AUTOFF = 1 . . . . .354
Figure 48.Behavior with WAIT = 1, AUTOFF = 1 . . . . .354
Figure 49.Analog watchdog guarded area . . . . .355
Figure 50.ADC_AWDx_OUT signal generation . . . . .357
Figure 51.ADC_AWDx_OUT signal generation (AWDx flag not cleared by software) . . . . .357
Figure 52.ADC_AWDx_OUT signal generation (on a single channel) . . . . .358
Figure 53.Analog watchdog threshold update . . . . .358
Figure 54.20-bit to 16-bit result truncation . . . . .359
Figure 55.Numerical example with 5-bit shift and rounding . . . . .359
Figure 56.Triggered oversampling mode (TOVS bit = 1) . . . . .361
Figure 57.Temperature sensor and VREFINT channel block diagram . . . . .362
Figure 58.DAC block diagram . . . . .388
Figure 59.Data registers in single DAC channel mode . . . . .391
Figure 60.Timing diagram for conversion with trigger disabled TEN = 0 . . . . .391
Figure 61.DAC LFSR register calculation algorithm . . . . .393
Figure 62.DAC conversion (SW trigger enabled) with LFSR wave generation . . . . .393
Figure 63.DAC triangle wave generation . . . . .394
Figure 64.DAC conversion (SW trigger enabled) with triangle wave generation . . . . .394
Figure 65.DAC sample and hold mode phase diagram . . . . .397
Figure 66.Comparator block diagram . . . . .415
Figure 67.Window mode . . . . .418
Figure 68.Comparator hysteresis . . . . .418
Figure 69.Comparator output blanking . . . . .419
Figure 70.Standalone mode: external gain setting mode . . . . .428
Figure 71.Follower configuration . . . . .429
Figure 72.PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used . . . . .430
Figure 73.PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for filtering . . . . .431
Figure 74.LCD controller block diagram . . . . .439
Figure 75.1/3 bias, 1/4 duty . . . . .441
Figure 76.Static duty case 1 . . . . .442
Figure 77.Static duty case 2 . . . . .443
Figure 78.1/2 duty, 1/2 bias . . . . .444
Figure 79.1/3 duty, 1/3 bias . . . . .445
Figure 80.1/4 duty, 1/3 bias . . . . .446
Figure 81.1/8 duty, 1/4 bias . . . . .447
Figure 82.LCD voltage control . . . . .449
Figure 83.Deadtime . . . . .450
Figure 84.Flowchart example . . . . .454
Figure 85.TSC block diagram . . . . .467
Figure 86.Surface charge transfer analog I/O group structure . . . . .468
Figure 87.Sampling capacitor voltage variation . . . . .469
Figure 88.Charge transfer acquisition sequence . . . . .470
Figure 89.Spread spectrum variation principle . . . . .471
Figure 90.Surface charge transfer with comparator analog I/O group structure . . . . .475
Figure 91.Sensor voltage variation for both normal and comparator mode . . . . .476
Figure 92.RNG block diagram . . . . .488
Figure 93.NIST SP800-90B entropy source model . . . . .489
Figure 94.RNG initialization overview . . . . .492
Figure 95.AES block diagram . . . . .505
Figure 96.ECB encryption and decryption principle . . . . .507
Figure 97.CBC encryption and decryption principle . . . . .508
Figure 98.CTR encryption and decryption principle . . . . .509
Figure 99.GCM encryption and authentication principle . . . . .510
Figure 100. GMAC authentication principle . . . . .510
Figure 101. CCM encryption and authentication principle . . . . .511
Figure 102. Example of suspend mode management . . . . .515
Figure 103. ECB encryption . . . . .516
Figure 104. ECB decryption . . . . .516
Figure 105. CBC encryption . . . . .517
Figure 106. CBC decryption . . . . .517
Figure 107. ECB/CBC encryption (Mode 1) . . . . .518
Figure 108. ECB/CBC decryption (Mode 3) . . . . .519
Figure 109. Message construction in CTR mode . . . . .520
Figure 110. CTR encryption . . . . .521
Figure 111. CTR decryption . . . . .521
Figure 112. Message construction in GCM . . . . .523
Figure 113. GCM authenticated encryption . . . . .524
Figure 114. Message construction in GMAC mode . . . . .528
Figure 115. GMAC authentication mode . . . . .528
Figure 116. Message construction in CCM mode . . . . .529
Figure 117. CCM mode authenticated encryption . . . . .531
Figure 118. 128-bit block construction with respect to data swap . . . . .536
Figure 119. DMA transfer of a 128-bit data block during input phase . . . . .538
Figure 120. DMA transfer of a 128-bit data block during output phase . . . . .538
Figure 121. Advanced-control timer block diagram . . . . .555
Figure 122. Counter timing diagram with prescaler division change from 1 to 2 . . . . .557
Figure 123. Counter timing diagram with prescaler division change from 1 to 4 . . . . .557
Figure 124. Counter timing diagram, internal clock divided by 1 . . . . .559
Figure 125. Counter timing diagram, internal clock divided by 2 . . . . .559
Figure 126. Counter timing diagram, internal clock divided by 4 . . . . .560
Figure 127. Counter timing diagram, internal clock divided by N . . . . .560
Figure 128. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .561
Figure 129. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .561
Figure 130. Counter timing diagram, internal clock divided by 1 . . . . .563
Figure 131. Counter timing diagram, internal clock divided by 2 . . . . .563
Figure 132. Counter timing diagram, internal clock divided by 4 . . . . .564
Figure 133. Counter timing diagram, internal clock divided by N . . . . .564
Figure 134. Counter timing diagram, update event when repetition counter is not used . . . . .565
Figure 135. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .566
Figure 136. Counter timing diagram, internal clock divided by 2 . . . . .567
Figure 137. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .567
Figure 138. Counter timing diagram, internal clock divided by N . . . . .568
Figure 139. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .568
Figure 140. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .569
Figure 141. Update rate examples depending on mode and TIMx_RCR register settings . . . . .570
Figure 142. External trigger input block . . . . .571
Figure 143. TIM1 ETR input circuitry . . . . .571
Figure 144. Control circuit in normal mode, internal clock divided by 1 . . . . .572
Figure 145. TI2 external clock connection example . . . . .573
Figure 146. Control circuit in external clock mode 1 . . . . .574
Figure 147. External trigger input block . . . . .574
Figure 148. Control circuit in external clock mode 2 . . . . .575
Figure 149. Capture/compare channel (example: channel 1 input stage) . . . . .576
Figure 150. Capture/compare channel 1 main circuit . . . . .576
Figure 151. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .577
Figure 152. Output stage of capture/compare channel (channel 4) . . . . .577
Figure 153. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .578
Figure 154. PWM input mode timing . . . . .580
Figure 155. Output compare mode, toggle on OC1 . . . . .582
Figure 156. Edge-aligned PWM waveforms (ARR=8) . . . . .583
Figure 157. Center-aligned PWM waveforms (ARR=8) . . . . .584
Figure 158. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .586
Figure 159. Combined PWM mode on channel 1 and 3 . . . . .587
Figure 160. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .588
Figure 161. Complementary output with dead-time insertion . . . . .589
Figure 162. Dead-time waveforms with delay greater than the negative pulse . . . . .589
Figure 163. Dead-time waveforms with delay greater than the positive pulse . . . . .590
Figure 164. Break and Break2 circuitry overview . . . . .592
Figure 165. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .594
Figure 166. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . .595
Figure 167. PWM output state following BRK assertion (OSSI=0) . . . . .596
Figure 168. Output redirection (BRK2 request not represented) . . . . .597
Figure 169. Clearing TIMx OCxREF . . . . .598
Figure 170. 6-step generation, COM example (OSSR=1) . . . . .599
Figure 171. Example of one pulse mode . . . . .600
Figure 172. Retriggerable one pulse mode . . . . .602
Figure 173. Example of counter operation in encoder interface mode . . . . .603
Figure 174. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .604
Figure 175. Measuring time interval between edges on 3 signals . . . . .605
Figure 176. Example of Hall sensor interface . . . . .607
Figure 177. Control circuit in reset mode . . . . .608
Figure 178. Control circuit in Gated mode . . . . .609
Figure 179. Control circuit in trigger mode . . . . .610
Figure 180. Control circuit in external clock mode 2 + trigger mode . . . . .611
Figure 181. General-purpose timer block diagram . . . . .655
Figure 182. Counter timing diagram with prescaler division change from 1 to 2 . . . . .657
Figure 183. Counter timing diagram with prescaler division change from 1 to 4 . . . . .657
Figure 184. Counter timing diagram, internal clock divided by 1 . . . . .658
Figure 185. Counter timing diagram, internal clock divided by 2 . . . . .659
Figure 186. Counter timing diagram, internal clock divided by 4 . . . . .659
Figure 187. Counter timing diagram, internal clock divided by N . . . . .660
Figure 188. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .660
Figure 189. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) . . . . .661
Figure 190. Counter timing diagram, internal clock divided by 1 . . . . .662
Figure 191. Counter timing diagram, internal clock divided by 2 . . . . .662
Figure 192. Counter timing diagram, internal clock divided by 4 . . . . .663
Figure 193. Counter timing diagram, internal clock divided by N . . . . .663
Figure 194. Counter timing diagram, Update event . . . . .664
Figure 195. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .665
Figure 196. Counter timing diagram, internal clock divided by 2 . . . . .666
Figure 197. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .666
Figure 198. Counter timing diagram, internal clock divided by N . . . . .667
Figure 199. Counter timing diagram, Update event with ARPE=1 (counter underflow) . . . . .667
Figure 200. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .668
Figure 201. Control circuit in normal mode, internal clock divided by 1 . . . . .669
Figure 202. TI2 external clock connection example . . . . .669
Figure 203. Control circuit in external clock mode 1 . . . . .670
Figure 204. External trigger input block . . . . .671
Figure 205. Control circuit in external clock mode 2 . . . . .672
Figure 206. Capture/Compare channel (example: channel 1 input stage) . . . . .672
Figure 207. Capture/Compare channel 1 main circuit . . . . .673
Figure 208. Output stage of Capture/Compare channel (channel 1) . . . . .673
Figure 209. PWM input mode timing . . . . .675
Figure 210. Output compare mode, toggle on OC1 . . . . .677
Figure 211. Edge-aligned PWM waveforms (ARR=8) . . . . .678
Figure 212. Center-aligned PWM waveforms (ARR=8) . . . . .680
Figure 213. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .681
Figure 214. Combined PWM mode on channels 1 and 3 . . . . .682
Figure 215. Clearing TIMx_OCxREF . . . . .683
Figure 216. Example of one-pulse mode . . . . .684
Figure 217. Retriggerable one-pulse mode . . . . .686
Figure 218. Example of counter operation in encoder interface mode . . . . .687
Figure 219. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .688
Figure 220. Control circuit in reset mode . . . . .689
Figure 221. Control circuit in gated mode . . . . .690
Figure 222. Control circuit in trigger mode . . . . .691
Figure 223. Control circuit in external clock mode 2 + trigger mode . . . . .692
Figure 224. Master/Slave timer example . . . . .693
Figure 225. Master/slave connection example with 1 channel only timers . . . . .693
Figure 226. Gating TIM2 with OC1REF of TIM3 . . . . .694
Figure 227. Gating TIM2 with Enable of TIM3 . . . . .695
Figure 228. Triggering TIM2 with update of TIM3 . . . . .696
Figure 229. Triggering TIM2 with Enable of TIM3 . . . . .696
Figure 230. Triggering TIM3 and TIM2 with TIM3 TI1 input . . . . .697
Figure 231. Basic timer block diagram . . . . .728
Figure 232. Counter timing diagram with prescaler division change from 1 to 2 . . . . .730
Figure 233. Counter timing diagram with prescaler division change from 1 to 4 . . . . .730
Figure 234. Counter timing diagram, internal clock divided by 1 . . . . .731
Figure 235. Counter timing diagram, internal clock divided by 2 . . . . .732
Figure 236. Counter timing diagram, internal clock divided by 4 . . . . .732
Figure 237. Counter timing diagram, internal clock divided by N . . . . .733
Figure 238. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) . . . . .733
Figure 239. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .734
Figure 240. Control circuit in normal mode, internal clock divided by 1 . . . . .735
Figure 241. TIM15 block diagram . . . . .743
Figure 242. TIM16 block diagram . . . . .744
Figure 243. Counter timing diagram with prescaler division change from 1 to 2 . . . . .746
Figure 244. Counter timing diagram with prescaler division change from 1 to 4 . . . . .746
Figure 245. Counter timing diagram, internal clock divided by 1 . . . . .748
Figure 246. Counter timing diagram, internal clock divided by 2 . . . . .748
Figure 247. Counter timing diagram, internal clock divided by 4 . . . . .749
Figure 248. Counter timing diagram, internal clock divided by N . . . . .749
Figure 249. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .750
Figure 250. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .750
Figure 251. Update rate examples depending on mode and TIMx_RCR register settings . . . . .752
Figure 252.Control circuit in normal mode, internal clock divided by 1 . . . . .753
Figure 253.TI2 external clock connection example. . . . .753
Figure 254.Control circuit in external clock mode 1 . . . . .754
Figure 255.Capture/compare channel (example: channel 1 input stage) . . . . .755
Figure 256.Capture/compare channel 1 main circuit . . . . .755
Figure 257.Output stage of capture/compare channel (channel 1). . . . .756
Figure 258.Output stage of capture/compare channel (channel 2 for TIM15) . . . . .756
Figure 259.PWM input mode timing . . . . .758
Figure 260.Output compare mode, toggle on OC1 . . . . .760
Figure 261.Edge-aligned PWM waveforms (ARR=8) . . . . .761
Figure 262.Combined PWM mode on channel 1 and 2 . . . . .762
Figure 263.Complementary output with dead-time insertion. . . . .763
Figure 264.Dead-time waveforms with delay greater than the negative pulse. . . . .763
Figure 265.Dead-time waveforms with delay greater than the positive pulse. . . . .764
Figure 266.Break circuitry overview . . . . .766
Figure 267.Output behavior in response to a break . . . . .768
Figure 268.Output redirection . . . . .770
Figure 269.6-step generation, COM example (OSSR=1) . . . . .771
Figure 270.Example of one pulse mode . . . . .772
Figure 271.Retriggerable one pulse mode . . . . .774
Figure 272.Measuring time interval between edges on 2 signals . . . . .775
Figure 273.Control circuit in reset mode . . . . .776
Figure 274.Control circuit in gated mode . . . . .777
Figure 275.Control circuit in trigger mode . . . . .778
Figure 276.LPTIM2 block diagram (1) . . . . .829
Figure 277.LPTIM1/3 block diagram (1) . . . . .830
Figure 278.Glitch filter timing diagram . . . . .834
Figure 279.LPTIM output waveform, single-counting mode configuration
when repetition register content is different than zero (with PRELOAD = 1) . . . . .		836
Figure 280.LPTIM output waveform, single-counting mode configuration
and Set-once mode activated (WAVE bit is set). . . . .		837
Figure 281.LPTIM output waveform, Continuous counting mode configuration . . . . .837
Figure 282.Waveform generation . . . . .839
Figure 283.Encoder mode counting sequence . . . . .843
Figure 284.Continuous counting mode when repetition register LPTIM_RCR
different from zero (with PRELOAD = 1). . . . .		844
Figure 285.Capture/compare input stage (channel 1) . . . . .845
Figure 286.Capture/compare output stage (channel 1) . . . . .845
Figure 287.Edge-aligned PWM mode (PRELOAD = 1) . . . . .847
Figure 288.Edge-aligned PWM waveforms (ARR=8 and CCxP = 0) . . . . .848
Figure 289.PWM mode with immediate update versus preloaded update . . . . .849
Figure 290.IRTIM internal hardware connections . . . . .881
Figure 291.Independent watchdog block diagram . . . . .883
Figure 292.Reset timing due to timeout . . . . .885
Figure 293.Reset timing due to refresh in the not allowed area . . . . .886
Figure 294.Changing PR, RL, and performing a refresh (1) . . . . .887
Figure 295.Window comparator update (1) . . . . .888
Figure 296.Independent watchdog interrupt timing diagram. . . . .890
Figure 297.Early wake-up comparator update (1) . . . . .891
Figure 298.Watchdog block diagram . . . . .899
Figure 299.Window watchdog timing diagram . . . . .901
Figure 300.RTC block diagram . . . . .906
Figure 301. TAMP block diagram . . . . .948
Figure 302. Tamper sampling with precharge pulse . . . . .953
Figure 303. Low level detection with precharge and filtering . . . . .954
Figure 304. Block diagram . . . . .969
Figure 305. I 2 C-bus protocol . . . . .971
Figure 306. Setup and hold timings . . . . .973
Figure 307. I2C initialization flow . . . . .975
Figure 308. Data reception . . . . .976
Figure 309. Data transmission . . . . .977
Figure 310. Target initialization flow . . . . .980
Figure 311. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . .982
Figure 312. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . .983
Figure 313. Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . .984
Figure 314. Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . .985
Figure 315. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . .986
Figure 316. Transfer bus diagrams for I2C target receiver
(mandatory events only) . . . . .		986
Figure 317. Controller clock generation . . . . .988
Figure 318. Controller initialization flow . . . . .990
Figure 319. 10-bit address read access with HEAD10R = 0 . . . . .990
Figure 320. 10-bit address read access with HEAD10R = 1 . . . . .991
Figure 321. Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes. . . . .992
Figure 322. Transfer sequence flow for I2C controller transmitter, N > 255 bytes. . . . .993
Figure 323. Transfer bus diagrams for I2C controller transmitter
(mandatory events only) . . . . .		994
Figure 324. Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes . . . . .996
Figure 325. Transfer sequence flow for I2C controller receiver, N > 255 bytes. . . . .997
Figure 326. Transfer bus diagrams for I2C controller receiver
(mandatory events only) . . . . .		998
Figure 327. USART block diagram . . . . .1019
Figure 328. Word length programming . . . . .1023
Figure 329. Configurable stop bits . . . . .1025
Figure 330. TC/TXE behavior when transmitting . . . . .1027
Figure 331. Start bit detection when oversampling by 16 or 8. . . . .1028
Figure 332. usart_ker_ck clock divider block diagram. . . . .1031
Figure 333. Data sampling when oversampling by 16. . . . .1032
Figure 334. Data sampling when oversampling by 8. . . . .1033
Figure 335. Mute mode using Idle line detection . . . . .1040
Figure 336. Mute mode using address mark detection . . . . .1041
Figure 337. Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . .1044
Figure 338. Break detection in LIN mode vs. Framing error detection. . . . .1045
Figure 339. USART example of synchronous master transmission. . . . .1046
Figure 340. USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . .		1046
Figure 341. USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . .		1047
Figure 342. USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . .		1048
Figure 343. ISO 7816-3 asynchronous protocol . . . . .1050
Figure 344. Parity error detection using the 1.5 stop bits . . . . .1052
Figure 345. IrDA SIR ENDEC block diagram. . . . .1056
Figure 346. IrDA data modulation (3/16) - normal mode . . . . .1056
Figure 347. Transmission using DMA . . . . .1058
Figure 348. Reception using DMA . . . . .1059
Figure 349. Hardware flow control between two USARTs . . . . .1059
Figure 350. RS232 RTS flow control . . . . .1060
Figure 351. RS232 CTS flow control . . . . .1061
Figure 352. Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . .1064
Figure 353. Wake-up event not verified (wake-up event = address match, FIFO disabled) . . . . .1064
Figure 354. LPUART block diagram . . . . .1109
Figure 355. LPUART word length programming . . . . .1112
Figure 356. Configurable stop bits . . . . .1114
Figure 357. TC/TXE behavior when transmitting . . . . .1116
Figure 358. lpuart_ker_ck clock divider block diagram . . . . .1120
Figure 359. Mute mode using Idle line detection . . . . .1124
Figure 360. Mute mode using address mark detection . . . . .1125
Figure 361. Transmission using DMA . . . . .1127
Figure 362. Reception using DMA . . . . .1128
Figure 363. Hardware flow control between two LPUARTs . . . . .1129
Figure 364. RS232 RTS flow control . . . . .1129
Figure 365. RS232 CTS flow control . . . . .1130
Figure 366. Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . .1133
Figure 367. Wake-up event not verified (wake-up event = address match, FIFO disabled) . . . . .1133
Figure 368. SPI block diagram . . . . .1164
Figure 369. Full-duplex single master/ single slave application . . . . .1165
Figure 370. Half-duplex single master/ single slave application . . . . .1166
Figure 371. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) . . . . .1167
Figure 372. Master and three independent slaves . . . . .1168
Figure 373. Multimaster application . . . . .1169
Figure 374. Hardware/software slave select management . . . . .1170
Figure 375. Data clock timing diagram . . . . .1171
Figure 376. Data alignment when data length is not equal to 8-bit or 16-bit . . . . .1172
Figure 377. Packing data in FIFO for transmission and reception . . . . .1176
Figure 378. Master full-duplex communication . . . . .1179
Figure 379. Slave full-duplex communication . . . . .1180
Figure 380. Master full-duplex communication with CRC . . . . .1181
Figure 381. Master full-duplex communication in packed mode . . . . .1182
Figure 382. NSSP pulse generation in Motorola SPI master mode . . . . .1185
Figure 383. TI mode transfer . . . . .1186
Figure 384. USB peripheral block diagram . . . . .1199
Figure 385. Packet buffer areas with examples of buffer description table locations . . . . .1206
Figure 386. Block diagram of debug support infrastructure . . . . .1246
Figure 387. CoreSight topology . . . . .1267