5. Reset and clock control (RCC)
5.1 Reset
There are three types of reset, defined as system reset, power reset and RTC domain reset.
5.1.1 Power reset
A power reset is generated when one of the following events occurs:
- • power-on reset (POR)
- • exit from Standby mode
- • exit from Shutdown mode
A power reset set all registers to their reset values except the registers of the RTC domain.
When exiting Standby mode, all registers in the \( V_{CORE} \) domain are set to their reset value. Registers outside the \( V_{CORE} \) domain (RTC, WKUP, IWDG, and Standby/Shutdown mode control) are not impacted.
When exiting Shutdown mode, a power reset is generated, resetting all registers except those in the RTC domain.
5.1.2 System reset
A system reset sets all registers to their reset value unless otherwise specified in the register descriptions.
System reset is generated when one of the following events occurs:
- • low level on NRST (external reset)
- • window watchdog event (WWDG reset)
- • independent watchdog event (IWDG reset)
- • software reset (SW reset) (see Software reset )
- • low-power mode security reset (see Low-power mode security reset )
- • option byte loader reset (see Option byte loader reset )
- • power-on reset (POR) or brown-out reset (BOR)
The reset source can be identified by checking the reset flags in the RCC_CSR register (see Section 5.4.23: Control/status register (RCC_CSR) ).
NRST pin (external reset)
Through specific option bits, the PF2-NRST pin is configurable for operating as:
- • Reset input/output (default at device delivery)
Valid reset signal on the pin is propagated to the internal logic, and each internal reset source is led to a pulse generator the output of which drives this pin. The GPIO functionality (PF2) is not available. The pulse generator guarantees a minimum reset pulse duration of 20 µs for each internal reset source to be output on the NRST pin. An internal reset holder option can be used, if enabled in the option bytes, to ensure that the pin is pulled low until its voltage meets \( V_{IL} \) threshold. This function allows the detection of internal reset sources by external components when the line faces a
significant capacitive load. The BOOT0 pin is sampled on any NRST rising edge, caused by internal or external resets.
- • Reset input
In this mode, any valid reset signal on the NRST pin is propagated to device internal logic, but resets generated internally by the device are not visible on the pin. The GPIO functionality (PF2) is not available. The BOOT0 pin is sampled on POR and any subsequent NRST rising edge, caused by external resets. Other internal resets do not trigger new BOOT0 sampling.
- • GPIO
In this mode, the pin can be used as PF2 standard GPIO. The reset function of the pin is not available. Reset is only possible from device internal reset sources and it is not propagated to the pin. The BOOT0 pin is sampled on POR NRST rising edge only. Subsequent internal resets or transitions on the PF2 GPIO do not trigger new BOOT0 sampling. Also refer to Section 7.3.17: Reset pin (PF2-NRST) in GPIO mode for additional considerations for this mode.
Caution: Upon power-on reset or wake-up from Standby or Shutdown mode, the NRST pin is configured as Reset input/output and driven low by the system until it is reconfigured to the expected mode when the option bytes are loaded, in the fourth clock cycle after the end of \( t_{rstempo} \) .
Figure 10. Simplified diagram of the reset circuit
Software reset
The SYSRESETREQ bit in Cortex®-M0+ Application interrupt and reset control register must be set to force a software reset on the device (refer to the programming manual PM0223).
Low-power mode security reset
To prevent that critical applications mistakenly enter a low-power mode, three low-power mode security resets are available. If enabled in option bytes, the resets are generated in the following conditions:
- • Entering Standby mode
This type of reset is enabled by resetting nRST_STDBY bit in user option bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode.
- • Entering Stop mode
This type of reset is enabled by resetting nRST_STOP bit in user option bytes. In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering Stop mode.
- • Entering Shutdown mode
This type of reset is enabled by resetting nRST_SHDW bit in user option bytes. In this case, whenever a Shutdown mode entry sequence is successfully executed, the device is reset instead of entering Shutdown mode.
For further information on the user option bytes, refer to Section 3.4.1: FLASH option byte description .
Option byte loader reset
The option byte loader reset is generated when the OBL_LAUNCH bit (bit 27) is set in the FLASH_CR register. This bit is used to launch the option byte loading by software.
5.1.3 RTC domain reset
The RTC domain has three specific resets.
A RTC domain reset is generated when one of the following events occurs:
- • Software reset , triggered by setting the BDRST bit in the RTC domain control register (RCC_BDCR) .
- • V DD or V BAT power on , if both supplies have previously been powered off.
- • Exit from Shutdown , forced when the BDRST bit in the FLASH option register (FLASH_OPTR) is set.
A RTC domain reset only affects the LSE oscillator, the RTC, the backup registers and the RCC RTC domain control register.
5.2 Clocks
The device provides the following clock sources producing primary clocks:
- • HSI16 RC - a high-speed fully-integrated RC oscillator producing HSI16 clock (about 16 MHz)
- • HSI48 RC - a high-speed fully-integrated RC oscillator producing HSI48 clock for USB and RNG (about 48 MHz)
- • MSI - (multispeed internal) RC oscillator clock
- • HSE OSC - a high-speed oscillator with external crystal/ceramic resonator or external clock source, producing HSE clock (4 to 48 MHz)
- • LSI RC - a low-speed fully-integrated RC oscillator producing LSI clock (about 32 kHz)
- • LSE OSC - a low-speed oscillator with external crystal/ceramic resonator or external clock source, producing LSE clock (accurate 32.768 kHz or external clock up to 1 MHz)
Each oscillator can be switched on or off independently when it is not used, to optimize power consumption. Check sub-sections of this section for more functional details. For electrical characteristics of the internal and external clock sources, refer to the device datasheet.
The device produces secondary clocks by dividing or/and multiplying the primary clocks:
- • PLLPClk, PLLQCLK and PLLRCLK - clocks output from the PLL block
- • SYSCCLK - a clock obtained through selecting one of LSE, LSI, HSE, MSI, and PLLRCLK clocks
- • HCLK - a clock derived from SYSCCLK through division by a factor programmable from 1 to 512
- • HCLK8 - a clock derived from HCLK through division by eight
- • PCLK - a clock derived from HCLK through division by a factor programmable from 1 to 16
- • LPTIMx_IN - clock from LPTIMx_INx pins, selectable for the LPTIM peripheral
More secondary clocks are generated by fixed division of HSE, HSI16 and HCLK clocks.
The MSI in Range 6 is used as system clock source after startup from reset, delivering a 4 MHz frequency.
The HCLK clock and PCLK clock are used for clocking the AHB and the APB domains, respectively. Their maximum allowed frequency is 64 MHz.
The peripherals are clocked with the clocks from the bus they are attached to (HCLK for AHB, PCLK for APB) except:
- •
TIMx
, with these clock sources to select from:
- – TIMPCLK (selectable for all timers) running at PCLK frequency
- – PLLQCLK selectable for high-speed TIM1 and TIM15 timers
- •
LPTIMx
, with these clock sources to select from:
- – LSI
- – LSE
- – HSI16
- – PCLK (APB clock)
- – LPTIMx_IN selected from LPTIMx_INx pins
The functionality in Stop mode (including wake-up) is supported only when the clock is LSI or LSE.
- •
ADC
, with these clock sources to select from:
- – SYSCLK (system clock)
- – HSI16
- – PLLPCLK
- •
USARTx / LPUARTx
, with these clock sources to select from:
- – SYSCLK (system clock)
- – HSI16
- – LSE
- – PCLK (APB clock)
The wake-up from Stop mode is supported only when the clock is HSI16 or LSE.
- •
I2C1/I2C3
, with these clock sources to select from:
- – SYSCLK (system clock)
- – HSI16
- – PCLK (APB clock)
The wake-up from Stop mode is supported only when the clock is HSI16.
- •
RNG
, with these clock sources to select from:
- – SYSCLK (system clock)
- – HSI16 clock divided by 8
- – PLLQCLK
The RNG clock can additionally be divided by 2, 4 or 8, using a dedicated prescaler.
- •
RTC
, with these clock sources to select from:
- – LSE
- – LSI
- – HSE clock divided by 32
The functionality in Stop mode (including wake-up) is supported only when the clock is LSI or LSE.
- • IWDG , always clocked with LSI clock.
- •
USB
, with these clocks to select from:
- – MSI
- – HSI48
- – PLLQCLK
- •
SysTick
(Cortex
®
core system timer), with these clock sources to select from:
- – HCLK (AHB clock)
- – HCLK clock divided by 8
The selection is done through SysTick control and status register.
HCLK is used as Cortex ® -M0+ free-running clock (FCLK). For more details, refer to the programming manual PM0223.
Figure 11. Clock tree
The diagram illustrates the clock tree architecture for the STM32U083xx series of microcontrollers. It shows the flow of clock signals from various sources to different system components.
- Clock Sources:
- LSI RC 32 kHz: Configurable divider (/1 or /128) to produce LSI . This clock is used for the IWDG and RTC wakeup.
- LSE OSC 32.768 kHz: Connected to OSC32_OUT and OSC32_IN pins. It provides the LSE clock for the RTC.
- HSE OSC 4-48 MHz: Connected to OSC_OUT and OSC_IN pins. It provides the HSE clock.
- CRS (Clock Recovery System): Receives a signal from the USB and provides the HSI48 clock.
- HSI16 RC 16 MHz: Internal RC clock source.
- MSI RC 100 kHz - 48 MHz: Internal RC clock source with programmable frequency.
- PLL: Phase-Locked Loop that takes HSE, HSI16, or MSI as input. It includes a VCO with feedback dividers (/R, /Q, /P) and input dividers (/M, /N). It generates PLLCLK , PLLQCLK , and PLLPCLK .
- Clock Distribution:
- SYSCLK: System clock selected from LSI, LSE, HSE, HSI48, HSI16, MSI, or PLL. It is distributed to the AHB bus, core, memory, and DMA.
- HCLK: AHB clock derived from SYSCLK via an AHB prescaler (/1, 2, ..., 512). It is also used for the FCLK (Cortex free-running clock).
- HCLK8: Derived from HCLK via a /8 divider for the Cortex system timer.
- PCLK: APB clock derived from HCLK via an APB prescaler (/1, 2, 4, 8, 16). It is used for APB peripherals (USART1, LPUART1, LPUART2, USART2, LPUART3, I2C1, I2C3, LPTIM1/2/3).
- TIMPCLK: Derived from HSI48, MSI, or PLLQCLK via a /2 divider for TIM2/3/6/7/16.
- Async clock to ADC: Derived from SYSCLK, HSI16, or PLLPCLK.
- USB/RNG clock: Derived from HSI48, MSI, or PLLQCLK.
- Other Features:
- MCO and MCO2: Configurable pins that output selected clocks with dividers (/1...1024).
- LSCO: Low Speed Clock output pin.
- Clock detector: Block that monitors the HSE clock.
BOLD: clock origin
MSV71415V5
1. Only applies to STM32U073xx and STM32U083xx devices.
5.2.1 HSE clock
The high speed external clock signal (HSE) can be generated from two possible clock sources:
- • HSE external crystal/ceramic resonator
- • HSE user external clock
The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.
Figure 12. HSE/ LSE clock sources
| Clock source | Hardware configuration |
|---|---|
| External clock | The diagram shows a microcontroller block with two pins labeled OSC_IN and OSC_OUT. An external clock source is connected to the OSC_IN pin. The OSC_OUT pin is connected to a GPIO pin, which is configured as OSC_EN as AF. |
| Crystal/Ceramic resonators | The diagram shows a microcontroller block with two pins labeled OSC_IN and OSC_OUT. A crystal/ceramic resonator is connected between these two pins. Two load capacitors, labeled C L1 and C L2 , are connected from the OSC_IN and OSC_OUT pins respectively to ground. The capacitors are labeled as 'Load capacitors'. |
External crystal/ceramic resonator (HSE crystal)
The 4 to 48 MHz external oscillator has the advantage of producing a very accurate rate on the main clock.
The associated hardware configuration is shown in Figure 12 . Refer to the electrical characteristics section of the datasheet for more details.
The HSERDY flag in the Clock control register (RCC_CR) indicates if the HSE oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt enable register (RCC_CIER) .
The HSE Crystal can be switched on and off using the HSEON bit in the Clock control register (RCC_CR) .
External source (HSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to 48 MHz. This mode is selected by setting the HSEBYP and HSEON bits in the Clock control register (RCC_CR) . The external clock signal (square, sinus or triangle) with ~40-60 % duty cycle depending on the frequency (refer to the datasheet ) must drive the OSC_IN pin (see Figure 12 ).
The OSC_OUT pin can be used as a GPIO or it can be configured as OSC_EN alternate function, to provide an enable signal to external clock synthesizer. It allows stopping the external clock source when the device enters low-power modes, as the OSC_EN output is high in Run mode and low when the device is in low-power mode
Note: For details on pin availability, refer to the pinout section in the corresponding device datasheet.
To minimize the consumption, it is recommended to use the square signal.
5.2.2 HSI16 clock
The HSI16 clock signal is generated from an internal 16 MHz RC oscillator.
The HSI16 RC oscillator has the advantage of providing a clock source at low cost (no external components). It also has a faster startup time than the HSE crystal oscillator. However, even after calibration, it is less accurate than an oscillator using a frequency reference such as quartz crystal or ceramic resonator.
The HSI16 can be selected as system clock after wake-up from Stop modes (Stop 0 or Stop 1). Refer to Section 5.3: Low-power modes . It can also be used as a backup clock source (auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 5.2.10: Clock security system (CSS) .
Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process variations. To compensate for this variation, each device is factory calibrated to 1 % accuracy at \( T_A=25^\circ\text{C} \) .
After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Internal clock sources calibration register (RCC_ICSCR) .
Voltage or temperature variations in the application may affect the HSI16 frequency of the RC oscillator. It can be trimmed using the HSITRIM[6:0] bits in the Internal clock sources calibration register (RCC_ICSCR) .
For more details on how to measure the HSI16 frequency variation, refer to Section 5.2.17: Internal/external clock measurement with TIM16 .
The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI16 RC is stable or not. At startup, the HSI16 RC output clock is not released until this bit is set by hardware.
The HSI16 RC can be switched on and off using the HSION bit in the Clock control register (RCC_CR) .
The HSI16 signal can also be used as a backup source (auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 5.2.10: Clock security system (CSS) on page 162 .
5.2.3 HSI48 clock
The HSI48 clock signal is generated from an internal 48 MHz RC oscillator. It can be used as clock source for the USB and RNG peripherals.
The internal 48MHz RC oscillator provides a high-precision clock to the USB peripheral thanks to the clock recovery system (CRS). CRS uses the USB SOF signal, LSE clock or an external signal as timing reference to precisely adjust the HSI48 RC oscillator frequency.
HSI48 RC oscillator is disabled as soon as the system enters in Stop or Standby mode. When the CRS is not used, the HSI48 RC oscillator runs on its free-run frequency which is subject to manufacturing process variations. The devices are factory-calibrated for ~3 % accuracy at \( T_A = 25^\circ\text{C} \) .
Refer to CRS section for more details on how to configure and use CRS.
The HSI48RDY flag in the RCC_CR register indicates if HSI48 is stable or not. At startup, the HSI48 clock is not released until this flag is set by hardware.
The HSI48 RC oscillator is enabled/disabled through the HSI48ON bit of the RCC_CR register. It is automatically enabled (by hardware setting the HSI48ON bit) when selected as clock source for the USB peripheral, as long as the USB peripheral is enabled.
Furthermore, it is possible to output the HSI48 clock through the MCO and MCO2 multiplexers and use it as a clock source for other application components.
5.2.4 MSI clock
The MSI clock signal is generated from an internal RC oscillator. Its frequency range can be adjusted by software by using the MSIRANGE[3:0] bits in the Clock control register (RCC_CR) . Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz, 1 MHz, 2 MHz, 4 MHz (default value), 8 MHz, 16 MHz, 24 MHz, 32 MHz and 48 MHz.
The MSI clock is used as system clock after restart from Reset, wake-up from Standby and Shutdown low-power modes. After restart from Reset, the MSI frequency is set to its default value 4 MHz. Refer to Section 5.3: Low-power modes .
The MSI clock can be selected as system clock after a wake-up from Stop mode (Stop 0, Stop 1 or Stop 2). Refer to Section 5.3: Low-power modes . It can also be used as a backup clock source (auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 5.2.10: Clock security system (CSS) .
The MSI RC oscillator has the advantage of providing a low-cost (no external components) low-power clock source. In addition, when used in PLL-mode with the LSE, it provides a very accurate clock source which can be used by the USB FS device, and feed the main PLL to run the system at the maximum speed 56 MHz.
The MSIRDY flag in the Clock control register (RCC_CR) indicates whether the MSI RC is stable or not. At startup, the MSI RC output clock is not released until this bit is set by hardware. The MSI RC can be switched on and off by using the MSION bit in the Clock control register (RCC_CR) .
Hardware auto calibration with LSE (PLL-mode)
When a 32.768 kHz external oscillator is present in the application, it is possible to configure the MSI in a PLL-mode by setting the MSIPLLEN bit in the Clock control register (RCC_CR) . When configured in PLL-mode, the MSI automatically calibrates itself thanks to the LSE. This mode is available for all MSI frequency ranges. At 48 MHz, the MSI in PLL-mode can be used for the USB FS device, saving the need of an external high-speed crystal.
Software calibration
The MSI RC oscillator frequency can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1 % accuracy at an ambient temperature, TA, of 25 °C. After reset, the factory calibration value is loaded in the MSICAL[7:0] bits in the Internal clock sources calibration register (RCC_ICSCR) . If the application is subject to voltage or temperature variations, this may affect the RC oscillator speed. You can trim the MSI frequency in the application by using the MSITRIM[7:0] bits in the RCC_ICSCR register. For more details on how to measure the MSI frequency variation please refer to Section 5.2.17: Internal/external clock measurement with TIM16 .
Note: Hardware auto calibration with LSE must not be used in conjunction with software calibration.
5.2.5 PLL
The internal PLL multiplies the frequency of HSI16- or HSE-based clock fetched on its input, to produce three independent clock outputs. The allowed input frequency range is from 2.66 to 16 MHz. The dedicated divider PLLM with division factor programmable from one to eight allows setting a frequency within the valid PLL input range. Refer to Figure 11: Clock tree and PLL configuration register (RCC_PLLCFGR) .
The PLL configuration (selection of the input clock and multiplication factor) must be done before enabling the PLL. Once the PLL is enabled, these parameters cannot be changed.
To modify the PLL configuration, proceed as follows:
- 1. Disable the PLL by setting PLLON to 0 in Clock control register (RCC_CR) .
- 2. Wait until PLLRDY is cleared. The PLL is now fully stopped.
- 3. Change the desired parameter.
- 4. Enable the PLL again by setting PLLON to 1.
- 5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, and PLLREN in PLL configuration register (RCC_PLLCFGR) .
An interrupt can be generated when the PLL is ready, if enabled in the Clock interrupt enable register (RCC_CIER) .
The enable bit of each PLL output clock (PLLPEN, PLLQEN, and PLLREN) can be modified at any time without stopping the PLL. PLLREN cannot be cleared if PLLRCLK is used as system clock.
OSC32_OUT can be configured as OSC32_EN alternate function to control the external clock source. The OSC32_EN output is high in Run mode and low when the device is in low-power mode.
5.2.6 LSE clock
The LSE crystal is a 32.768 kHz crystal or ceramic resonator. It has the advantage of providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in RTC domain control register (RCC_BDCR) . The crystal oscillator driving strength can be changed at runtime using the LSEDRV[1:0] bits in the RTC domain control register (RCC_BDCR) to obtain the best compromise between robustness and short start-up time on one side and low-power-consumption on the other side. The LSE drive can be decreased to the lower drive capability (LSEDRV=00) when the LSE is ON. However, once LSEDRV is selected, the drive capability can not be increased if LSEON=1.
The LSERDY flag in the RTC domain control register (RCC_BDCR) indicates whether the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt enable register (RCC_CIER) .
By default, the distribution of the LSE clock by the RTC block is gated to achieve the lowest power consumption. The LSESYSEN bit must be set in the RCC_BDCR register to release the clock distribution to the LCD, SYSCLK, LSCO, and MCO.
External source (LSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. This mode is selected by setting the LSEBYP and LSEON bits in the AHB peripheral clock enable in Sleep mode register (RCC_AHBSMENR) . The external clock signal (square, sinus or triangle) with ~50 % duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin can be used as GPIO. See Figure 12 .
5.2.7 LSI clock
The LSI RC acts as a low-power clock source that can be kept running in Stop and Standby mode for the independent watchdog (IWDG) and RTC. The clock frequency is 32 kHz. For more details, refer to the electrical characteristics section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the Control/status register (RCC_CSR) .
The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the LSI oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt enable register (RCC_CIER) .
5.2.8 System clock (SYSCLK) selection
One of the following clocks can be selected as system clock (SYSCLK):
- • LSI
- • LSE
- • MSI
- • HSI
- • HSE
- • PLLRCLK
The system clock maximum frequency is 56 MHz. Upon system reset, the MSI oscillator (in the 4 MHz range) is selected as system clock. When a clock source is used directly or through the PLL as a system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch occurs when the clock source becomes ready. Status bits in the Internal clock sources calibration register (RCC_ICSCR) indicate which clock(s) is (are) ready and which clock is currently used as a system clock.
5.2.9 Clock source frequency versus voltage scaling
The following table gives the different clock source frequencies depending on the product voltage range.
Table 32. Clock source frequency
| Clock | Maximum clock frequency (MHz) | |
|---|---|---|
| Range 1 | Range 2 | |
| HSI16 | 16 | 16 |
| HSE | 48 | 19 |
| HSI48 | 48 | N/A |
| MSI | 48 | 16 |
| PLLPCLK | 122 (1) | 40 (2) |
| PLLQCLK | 56 (1) | 19 (2) |
| PLLRCLK | 56 (1) | 19 (2) |
| SYSCLK | 56 (1) | 19 (2) |
| HCLK | 56 (1) | 19 (2) |
| PCLK | 56 (1) | 19 (2) |
1. Maximum VCO frequency is 344 MHz.
2. Maximum VCO frequency is 128 MHz.
5.2.10 Clock security system (CSS)
Clock security system can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
If a failure is detected on the HSE clock:
- • the HSE oscillator is automatically disabled
- • a clock failure event is sent to the break input of TIM1, TIM15, and TIM16 timers
- • CSSI (clock security system interrupt) is generated
The CSSI is linked to the Cortex®-M0+ NMI (non-maskable interrupt) exception vector. It makes the software aware of a HSE clock failure to allow it to perform rescue operations.
Note: If the CSS is enabled and the HSE clock fails, the CSSI occurs and an NMI is automatically generated. The NMI is executed infinitely unless the CSS interrupt pending bit is cleared. It is therefore necessary that the NMI ISR clears the CSSI by setting the CSSC bit in the Clock interrupt clear register (RCC_CICR) .
If the HSE oscillator is used directly or indirectly as the system clock (indirectly meaning that it is used as PLL input clock, and the PLL clock is used as system clock), a detected failure causes a switch of the system clock to the MSI or the HSI16 oscillator depending on the STOPWUCK configuration in the Clock configuration register (RCC_CFGR) , and the disabling of the HSE oscillator. If the HSE clock (divided or not) is the clock entry of the PLL used as system clock when the failure occurs, the PLL is disabled too.
5.2.11 Clock security system for LSE clock (LSECSS)
A clock security system on LSE can be activated by setting the LSECSSON bit in RTC domain control register (RCC_BDCR) . This bit can be cleared only by a hardware reset or RTC software reset, or after LSE clock failure detection. LSECSSON must be written after LSE and LSI are enabled (LSEON and LSION enabled) and ready (LSERDY and LSIRDY flags set by hardware), and after selecting the RTC clock by RTCSEL.
The LSECSS works in all modes except VBAT. It keeps working also under system reset (excluding power-on reset). If a failure is detected on the LSE oscillator, the LSE clock is no longer supplied to the RTC but its registers are not impacted.
Note: If the LSECSS is enabled and the LSE clock fails, the LSECSSI occurs and an NMI is automatically generated. The NMI is executed infinitely unless the LSECSS interrupt pending bit is cleared. It is therefore necessary that the NMI ISR clears the LSECSSI by setting the LSECSSC bit in the Clock interrupt clear register (RCC_CICR) .
If LSE is used as system clock, and a failure of LSE clock is detected, the system clock switches automatically to LSI. In low-power modes, an LSE clock failure generates a wake-up. The interrupt flag must then be cleared within the RCC registers.
The software must then disable the LSECSSON bit, stop the defective 32 kHz oscillator (by clearing LSEON), and change the RTC clock source (no clock, LSI or HSE, with RTCSEL), or take any appropriate action to secure the application.
Caution: When the LSECSSD bit is set, the LSE oscillator is held under reset and cannot be restarted. To clear the LSECSSD bit, reset the RTC domain using the BDRST bit.
The frequency of the LSE oscillator must exceed 30 kHz to avoid false positive detections.
5.2.12 ADC clock
The ADC clock is derived from the system clock, or from the PLLPCLK output. It can reach 122 MHz and can be divided by the following prescalers values: 1,2,4,6,8,10,12,16,32,64,128 or 256 by configuring the ADC1_CCR register. It is asynchronous to the AHB clock. Alternatively, the ADC clock can be derived from the AHB
clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). This programmable factor is configured using the CKMODE bitfields in the ADC1_CCR.
If the programmed factor is 1, the AHB prescaler must be set to 1.
5.2.13 RTC clock
The RTCCLK clock source can be either the HSE/32, LSE or LSI clock. It is selected by programming the RTCSEL[1:0] bits in the RTC domain control register (RCC_BDCR) . This selection cannot be modified without resetting the RTC domain. The system must always be configured so as to get a PCLK frequency greater then or equal to the RTCCLK frequency for a proper operation of the RTC.
The LSE clock is in the RTC domain, whereas the HSE and LSI clocks are not. Consequently:
- • If LSE is selected as RTC clock:
- – The RTC continues to work even if the \( V_{DD} \) supply is switched off, provided the \( V_{BAT} \) supply is maintained.
- • If LSI is selected as the RTC clock:
- – The RTC state is not guaranteed if the \( V_{DD} \) supply is powered off.
- • If the HSE clock divided by a prescaler is used as the RTC clock:
- – The RTC state is not guaranteed if the \( V_{DD} \) supply is powered off or if the internal voltage regulator is powered off (removing power from the \( V_{CORE} \) domain).
When the RTC clock is LSE or LSI, the RTC remains clocked and functional under system reset.
5.2.14 Timer clock
The timer clock TIMPCLK is derived from PCLK: it is equal to the PCLK frequency if PPRE[2:0] = 0XX, otherwise it is PCLK frequency \( \times 2 \)
For TIM1 and TIM15, PLLQCLK clock can also be selected, if:
- • PCLK is derived from PLLRCLK, and
- • PLLQCLK frequency is an integer multiplication by 2 or more of the PCLK frequency, without exceeding 56 MHz.
5.2.15 Watchdog clock
If the Independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG.
5.2.16 Clock-out capability
MCO and MCO2
The MCO and MCO2 pins output, independently of each other, the clock selected from:
- • LSI
- • LSE
- • SYSCLK
- • HSI16
- • HSI48
- • HSE
- • MSI
- • PLLRCLK
- • RTCCLK
- • RTC WAKEUP
The multiplexers for MCO and MCO2, respectively, are controlled by the MCOSEL[3:0] and MCO2SEL[3:0] bitfields of the Clock configuration register (RCC_CFGR) . Their outputs are further divided by a factor set through the MCOPRE[3:0] and MCO2PRE[3:0] bitfields of the Clock configuration register (RCC_CFGR) .
LSCO
The LSCO pin allows outputting on of low-speed clocks:
- • LSI
- • LSE
The selection is controlled by the LSCOSEL bit and enabled with the LSCOEN bit of the RTC domain control register (RCC_BDCR) . The configuration registers of the corresponding GPIO port must be programmed in alternate function mode.
The low-speed clock output (LSCO) remains available in Stop 0, Stop 1, Stop 2, Standby, and Shutdown modes.
5.2.17 Internal/external clock measurement with TIM16
It is possible to indirectly measure the frequency of all on-board clock sources with the TIM16 channel 1 input capture, as represented in Figure 13 .
TIM16
By setting the TI1SEL[3:0] field of the TIM16_TISEL register, the clock selected for the input capture channel1 of TIM16 can be one of:
- • GPIO (refer to the alternate function mapping in the device datasheets).
- • LSI clock
- • LSE clock
- • RTC wake-up interrupt signal
- • MCO2 (microcontroller clock output 2)
The second-last option requires to enable the RTC interrupt.
The last option is controlled through the MCO2SEL[3:0] bitfield of the Clock configuration register (RCC_CFGR) . All clock sources can be selected for the MCO2 pin.
Figure 13. Frequency measurement with TIM16 in capture mode
![Diagram showing the connection of various clock sources to the TIM16 timer's TI1 input via a multiplexer. The multiplexer is controlled by the TI1SEL[3:0] bitfield. The inputs to the multiplexer are: GPIO, LSI, LSE, RTC wakeup interrupt, and MCO2. The output of the multiplexer is connected to the TI1 input of the TIM16 block. A small label MSv42175V3 is present in the bottom right corner of the diagram area.](/RM0503-STM32U0/0d9149a10167a487a93c349f5d848b7d_img.jpg)
Calibration of the HSI16 or MSI oscillator
For TIM16, the primary purpose of connecting the LSE to the channel 1 input capture is to precisely measure the HSI16 or MSI selected as system clock. Counting clock pulses between consecutive edges of the LSE clock (the time reference) allows measuring the HSI16 or MSI clock period. Such measurement can determine the HSI16 or MSI oscillator frequency with nearly the same accuracy as the accuracy of the 32.768 kHz quartz crystal used with the LSE oscillator (typically a few tens of ppm). The HSI16 or MSI oscillators can then be trimmed to compensate for deviations from target frequency, due to manufacturing, process, temperature and/or voltage variation.
The HSI16 or MSI oscillators have dedicated user-accessible calibration bits for this purpose.
The basic concept consists in providing a relative measurement (for example, the HSI/LSE ratio): the measurement accuracy is therefore closely related to the ratio between the two clock sources. Increasing the ratio allows improving the measurement accuracy.
Generated by the HSE oscillator, the HSE clock (divided by 32) used as time reference is the second best method for reaching a good HSI16 or MSI frequency measurement accuracy. It is recommended in absence of the LSE clock.
In order to further improve the precision of the HSI16 or MSI oscillator calibration, it is advised to employ one or a combination of the following measures to increase the frequency measurement accuracy:
- • average the results of multiple consecutive measurements
- • use the input capture prescaler of the timer (one capture every up to eight periods)
- • use LSE clock for the RTC and the RTC wake-up interrupt signal as time reference
The last point significantly increases the reference period for HSI16 or MSI clock pulse counting, which improves the accuracy of a single measurement. For operation, the RTC wake-up interrupt must be enabled.
Calibration of the HSI48 oscillator
The HSI48 oscillator is factory-calibrated.
Measurement of the LSI oscillator frequency
The measurement of the LSI oscillator frequency uses the same principle as that for calibrating the HSI16 oscillator. TIM16 channel1 input capture must be used for LSI clock, and HSE selected as system clock source. The number of HSE clock pulses between consecutive edges of the LSI signal, counted by TIM16, is then representative of the LSI clock period.
5.2.18 Peripheral clock enable registers
The clocks to each peripheral can be enabled individually by the corresponding enable bit of the RCC_AHBENR register or by one of the RCC_APBENRx registers. The clocks to the I/O ports can be enabled individually through the RCC_IOPENR register.
When the clock to a peripheral or I/O port is not active, the read and write accesses to the corresponding registers are not effective.
Caution: The enable bit has a synchronization mechanism to create a glitch-free clock for the peripheral or I/O port. After the enable bit is set, there is a 2-clock-cycle delay before the clock be active, which the software must take into account.
5.3 Low-power modes
- • AHB and APB peripheral clocks, including DMA clock, can be disabled by software.
- • Sleep and Low-power Sleep modes stops the CPU clock. The memory interface clocks (flash memory and SRAM interfaces) can be stopped by software during sleep mode. The AHB to APB bridge clocks are disabled by hardware during Sleep mode when all the clocks of the peripherals connected to them are disabled.
- • Stop modes (Stop 0 and Stop 1) stop all the clocks in the \( V_{CORE} \) domain and disable the PLL as well as the HSI16, HSI48, MSI and HSE oscillators.
The USART1, USART2, LPUART1, LPUART2, LPUSART3, I2C1, and I2C3 peripherals can enable the HSI16 oscillator even when the MCU is in Stop mode (if HSI16 is selected as clock source for one of those peripherals).
The USART1, USART2, LPUART1, LPUART2, LPUSART3, I2C1, and I2C3 peripherals can also operate with the clock from the LSE oscillator when the system is in Stop mode, if LSE is selected as clock source for that peripheral and the LSE oscillator is enabled (LSEON set). In that case, the LSE oscillator remains active when the device enters Stop mode (these peripherals do not have the capability to turn on the LSE oscillator).
- • Standby and Shutdown modes stop all clocks in the \( V_{CORE} \) domain and disable the PLL, as well as the HSI16, HSI48, and HSE oscillators.
The CPU deepsleep mode can be overridden for debugging, by setting the DBG_STOP or DBG_STANDBY bits in the DBG_CR register.
When exiting the Stop 0 or Stop 1 modes, STOPWUCK allows the selection of either HSI or MSI as the wake-up clock.
When exiting the Standby and Shutdown modes, the MSI (in the 4 MHz range) becomes automatically the system clock. At wake-up from Standby and Shutdown mode, the user trim is lost.
If a flash memory programming operation is ongoing, Stop, Standby, and Shutdown entry is delayed until the flash memory interface access is finished. If an access to the APB domain
is ongoing, the Stop, Standby, and Shutdown entry is delayed until the APB access is finished.
5.4 RCC registers
Unless otherwise specified, the RCC registers support word, half-word, and byte access, without any wait state.
5.4.1 Clock control register (RCC_CR)
This register supports only word and half-word access.
Address offset: 0x00
Power-on reset value: 0x0000 0083
Other types of reset: same as power-on reset, except HSEBYP bit that keeps its previous value.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | Res. | Res. | Res. | Res. | PLL RDY | PLLON | Res. | Res. | Res. | Res. | CSS ON | HSE BYP | HSE RDY | HSE ON |
| r | rw | rs | rw | r | rw | ||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | HSI ASFS | HSI RDY | HSI KER ON | HSION | MSIRANGE[3:0] | MSI RGSEL | MSI PLLEN | MSI RDY | MSION | |||
| r | r | rw | rw | rw | rw | rw | rw | rs | rw | r | rw | ||||
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 PLLRDY : PLL clock ready flag
Set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON : PLL enable
Set and cleared by software to enable the PLL.
Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be reset if the PLL clock is used as the system clock.
0: PLL OFF
1: PLL ON
Bits 23:20 Reserved, must be kept at reset value.
Bit 19 CSSON : Clock security system enable
Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset.
0: Clock security system OFF (clock detector OFF)
1: Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not).
Bit 18 HSEBYP : HSE crystal oscillator bypass
Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled.
0: HSE crystal oscillator not bypassed
1: HSE crystal oscillator bypassed with external clock
Bit 17 HSERDY: HSE clock ready flagSet by hardware to indicate that the HSE oscillator is stable.
0: HSE oscillator not ready
1: HSE oscillator ready
Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles.
Bit 16 HSEON: HSE clock enableSet and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop, Standby, or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 HSIAFS: HSI16 automatic start from StopSet and cleared by software. When the system wake-up clock is MSI, this bit is used to wake up the HSI16 in parallel of the system wake-up.
0: HSI16 oscillator is not enabled by hardware when exiting Stop mode with MSI as wake-up clock.
1: HSI16 oscillator is enabled by hardware when exiting Stop mode with MSI as wake-up clock.
Bit 10 HSIRDY: HSI16 clock ready flagSet by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION.
0: HSI16 oscillator not ready
1: HSI16 oscillator ready
Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI16 clock cycles.
Bit 9 HSIKERON: HSI16 always enable for peripheral kernels.Set and cleared by software to force HSI16 ON even in Stop modes. The HSI16 can only feed USART1, USART2, CEC and I2C1 peripherals configured with HSI16 as kernel clock. Keeping the HSI16 ON in Stop mode allows avoiding to slow down the communication speed because of the HSI16 startup time. This bit has no effect on HSION value.
0: No effect on HSI16 oscillator.
1: HSI16 oscillator is forced ON even in Stop mode.
Bit 8 HSION: HSI16 clock enableSet and cleared by software.
Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby, or Shutdown mode.
Forced by hardware to keep the HSI16 oscillator ON when it is used directly or indirectly as system clock (also when leaving Stop, Standby, or Shutdown modes, or in case of failure of the HSE oscillator used for system clock).
0: HSI16 oscillator OFF
1: HSI16 oscillator ON
Bits 7:4 MSIRANGE[3:0]: MSI clock rangesThese bits are configured by software to choose the frequency range of MSI when MSIRGSEL is set. 12 12 frequency ranges are available:
0000: range 0 around 100 kHz
0001: range 1 around 200 kHz
0010: range 2 around 400 kHz
0011: range 3 around 800 kHz
0100: range 4 around 1M Hz
0101: range 5 around 2 MHz
0110: range 6 around 4 MHz (reset value)
0111: range 7 around 8 MHz
1000: range 8 around 16 MHz
1001: range 9 around 24 MHz
1010: range 10 around 32 MHz
1011: range 11 around 48 MHz
others: not allowed (hardware write protection)
Note: Warning: MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready (MSIRDY=1). MSIRANGE must NOT be modified when MSI is ON and NOT ready (MSION=1 and MSIRDY=0)
Bit 3 MSIRGSEL: MSI clock range selectionSet by software to select the MSI clock range with MSIRANGE[3:0]. Write 0 has no effect. After a standby or a reset MSIRGSEL is at 0 and the MSI range value is provided by MSISRANGE in CSR register.
0: MSI range is provided by MSISRANGE[3:0] in RCC_CSR register
1: MSI range is provided by MSIRANGE[3:0] in the RCC_CR register
Bit 2 MSIPPLEN: MSI clock PLL enableSet and cleared by software to enable/ disable the PLL part of the MSI clock source. MSIPPLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware). There is a hardware protection to avoid enabling MSIPPLEN if LSE is not ready.
This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the Clock Security System on LSE detects a LSE failure (refer to RCC_CSR register).
0: MSI PLL OFF
1: MSI PLL ON
Bit 1 MSIRDY: MSI clock ready flagThis bit is set by hardware to indicate that the MSI oscillator is stable.
0: MSI oscillator not ready
1: MSI oscillator ready
Note: Once the MSION bit is cleared, MSIRDY goes low after 6 MSI clock cycles.
Bit 0 MSION: MSI clock enableThis bit is set and cleared by software.
Cleared by hardware to stop the MSI oscillator when entering Stop, Standby or Shutdown mode.
Set by hardware to force the MSI oscillator ON when exiting Standby or Shutdown mode.
Set by hardware to force the MSI oscillator ON when STOPWUCK=0 when exiting from Stop modes, or in case of a failure of the HSE oscillator
Set by hardware when used directly or indirectly as system clock.
0: MSI oscillator OFF
1: MSI oscillator ON
5.4.2 Internal clock sources calibration register (RCC_ICSCR)
Address offset: 0x04
Reset value: 0x40XX 00XX
'X' is factory-programmed.
Access: no wait state, word, half-word and byte access
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | HSITRIM[6:0] | HSICAL[7:0] | |||||||||||||
| rw | rw | rw | rw | rw | rw | rw | r | r | r | r | r | r | r | r | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MSITRIM[7:0] | MSICAL[7:0] | ||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | r | r | r | r | r | r | r | r |
Bit 31 Reserved, must be kept at reset value.
Bits 30:24 HSITRIM[6:0] : HSI16 clock trimming
These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI16.
The default value is 64 when added to the HSICAL value, trim the HSI16 to 16 MHz \( \pm 1 \) %.
Bits 23:16 HSICAL[7:0] : HSI16 clock calibration
These bits are initialized at startup with the factory-programmed HSI16 calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value.
Bits 15:8 MSITRIM[7:0] : MSI clock trimming
These bits provide an additional user-programmable trimming value that is added to the MSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the MSI.
Bits 7:0 MSICAL[7:0] : MSI clock calibration
These bits are initialized at startup with the factory-programmed MSI calibration trim value. When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim value.
5.4.3 Clock configuration register (RCC_CFGR)
One or two wait states are inserted if this register is accessed during clock source switch, and between zero and 15 wait states are inserted if during an update of APB or AHB prescaler values.
Address offset: 0x08
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MCOPRE[3:0] | MCOSEL[3:0] | MCO2PRE[3:0] | MCO2SEL[3:0] | ||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| STOP WUCK | PPRE[2:0] | HPRE[3:0] | Res. | Res. | SWS[2:0] | SW[2:0] | |||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | r | r | r | rw | rw | rw | ||
Bits 31:28 MCOPRE[3:0] : Microcontroller clock output prescaler
This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows:
0000: 1
0001: 2
0010: 4
...
0111: 128
1000: 256
1001: 512
1010: 1024
Others: reserved
It is highly recommended to set this field before the MCO output is enabled.
Bits 27:24 MCOSEL[3:0] : Microcontroller clock output clock selector
This bitfield is controlled by software. It sets the clock selector for MCO output as follows:
0000: no clock, MCO output disabled
0001: SYSCLK
0010: MSI
0011: HSI16
0100: HSE
0101: PLLRCLK
0110: LSI
0111: LSE
1000: HSI48
1001: RTCCLK
1010: RTC WAKEUP
Others: Reserved
Note: This clock output may have some truncated cycles at startup or during MCO clock source switching.
Bits 23:20 MCO2PRE[3:0] : Microcontroller clock output 2 prescaler
This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows:
0000: 1
0001: 2
0010: 4
...
0111: 128
1000: 256
1001: 512
1010: 1024
Others: reserved
It is highly recommended to set this field before the MCO2 output is enabled.
Bits 19:16 MCO2SEL[3:0] : Microcontroller clock output 2 clock selector
This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows:
0000: no clock, MCO2 output disabled
0001: SYSCLK
0010: MSI
0011: HSI16
0100: HSE
0101: PLLRCLK
0110: LSI
0111: LSE
1000: HSI48
1001: RTCCLK
1010: RTC WAKEUP
Others: Reserved
Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching.
Bit 15 STOPWUCK : Wake-up from Stop and CSS backup clock selection
Set and cleared by software to select the system clock used when exiting Stop mode.
The selected clock is also used as emergency clock for the Clock Security System on HSE.
Warning: STOPWUCK must not be modified when the Clock Security System is enabled by HSECSSON in RCC_CR register and the system clock is HSE (SWS="10") or a switch on HSE is requested (SW="10").
0: MSI oscillator selected as wake-up from stop clock and CSS backup clock.
1: HSI16 oscillator selected as wake-up from stop clock and CSS backup clock
Bits 14:12 PPRE[2:0] : APB prescaler
This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows:
0xx: 1
100: 2
101: 4
110: 8
111: 16
Bits 11:8 HPRE[3:0] : AHB prescalerThis bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows:
0xxx: 1
1000: 2
1001: 4
1010: 8
1011: 16
1100: 64
1101: 128
1110: 256
1111: 512
Caution: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to Section 4.1.6: Dynamic voltage scaling management ). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value has been taken into account.
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:3 SWS[2:0] : System clock switch statusThis bitfield is controlled by hardware to indicate the clock source used as system clock:
000: MSI
001: HSI16
010: HSE
011: PLLRCLK
100: LSI
101: LSE
Others: Reserved
This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows:
000: MSI
001: HSI16
010: HSE
011: PLLRCLK
100: LSI
101: LSE
Others: Reserved
The setting is forced by hardware to 000 (MSI selected) when the MCU exits Stop, Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected.
5.4.4 PLL configuration register (RCC_PLLCFGR)
Address offset: 0x0C
Reset value: 0x0000 1000
This register configures the PLL clock outputs according to the formulas:
- • \( f_{VCO} = f_{PLLIN} \times (N / M) \)
- • \( f_{PLLP} = f_{VCO} / P \)
- • \( f_{PLLQ} = f_{VCO} / Q \)
- • \( f_{PLLR} = f_{VCO} / R \)
where \( f_{PLLIN} \) is the PLL input clock frequency, \( f_{VCO} \) is the PLL VCO frequency, and P, Q and R are \( f_{VCO} \) division factors and \( f_{PLLP} \) , \( f_{PLLQ} \) and \( f_{PLLR} \) the clock frequencies of the PLLPCLK, PLLQCLK and PLLRCLK PLL clock outputs, respectively.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PLLR[2:0] | PLL REN | PLLQ[2:0] | PLL QEN | Res. | Res. | PLLP[4:0] | PLL PEN | ||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | ||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | PLLN[6:0] | Res. | PLL M[2:0] | Res. | Res. | PLL SRC[1:0] | |||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | ||||
Bits 31:29 PLLR[2:0] : PLL VCO division factor R for PLLRCLK clock output
This bitfield is controlled by software. It sets the PLL VCO division factor R as follows:
000: Reserved
001: 2
010: 3
011: 4
100: 5
101: 6
110: 7
111: 8
The bitfield can be written only when the PLL is disabled.
The PLLRCLK clock can be selected as system clock.
Caution: The software must set this bitfield so as not to exceed 56 MHz on this clock.
Bit 28 PLLREN : PLLRCLK clock output enable
This bit is controlled by software to enable/disable the PLLRCLK clock output of the PLL:
0: Disable
1: Enable
This bit cannot be written when PLLRCLK output of the PLL is selected for system clock.
Disabling the PLLRCLK clock output, when not used, allows saving power.
Bits 27:25 PLLQ[2:0] : PLL VCO division factor Q for PLLQCLK clock output
This bitfield is controlled by software. It sets the PLL VCO division factor Q as follows:
000: Reserved
001: 2
010: 3
011: 4
100: 5
101: 6
110: 7
111: 8
The bitfield can be written only when the PLL is disabled.
Caution: The software must set this bitfield so as not to exceed 56 MHz on this clock.
Bit 24 PLLQEN : PLLQCLK clock output enable
This bit is controlled by software to enable/disable the PLLQCLK clock output of the PLL:
0: Disable
1: Enable
Disabling the PLLQCLK clock output, when not used, allows saving power.
Bits 23:22 Reserved, must be kept at reset value.
Bits 21:17 PLLP[4:0] : PLL VCO division factor P for PLLPCLK clock output
This bitfield is controlled by software. It sets the PLL VCO division factor P as follows:
00000: Reserved
00001: 2
...
11111: 32
The bitfield can be written only when the PLL is disabled.
Caution: The software must set this bitfield so as not to exceed 122 MHz on this clock.
Bit 16 PLLPEN : PLLPCLK clock output enable
This bit is controlled by software to enable/disable the PLLPCLK clock output of the PLL:
0: Disable
1: Enable
Disabling the PLLPCLK clock output, when not used, allows saving power.
Bit 15 Reserved, must be kept at reset value.
Bits 14:8 PLLN[6:0] : PLL frequency multiplication factor N
This bit is controlled by software to set the division factor of the \( f_{VCO} \) feedback divider (that determines the PLL multiplication ratio) as follows:
0000000: Invalid
0000001: Reserved
...
0000011: Reserved
0000100: 4
0000101: 5
...
1111110: 126
1111111: 127
The bitfield can be written only when the PLL is disabled.
Caution: The software must set these bits so that the VCO output frequency is between 96 and 344 MHz.
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 PLL[2:0] : Division factor M of the PLL input clock divider
This bit is controlled by software to divide the PLL input clock before the actual phase-locked loop, as follows:
- 000: 1
- 001: 2
- 010: 3
- 011: 4
- 100: 5
- 101: 6
- 110: 7
- 111: 8
The bitfield can be written only when the PLL is disabled.
Caution: The software must set these bits so that the PLL input frequency after the /M divider is between 2.66 and 16 MHz.
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 PLL[1:0] : PLL input clock source
This bit is controlled by software to select PLL clock source, as follows:
- 00: No clock
- 01: MSI
- 10: HSI16
- 11: HSE
The bitfield can be written only when the PLL is disabled.
When the PLL is not used, selecting 00 allows saving power.
5.4.5 Clock interrupt enable register (RCC_CIER)
Address offset: 0x18
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | HSI48 RDYIE | LSE CSSIE | Res. | Res. | Res. | PLL RDYIE | HSE RDYIE | HSI RDYIE | MSI RDYIE | LSE RDYIE | LSI RDYIE |
| rw | rw | rw | rw | rw | rw | rw | rw |
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 HSI48RDYIE : HSI48 ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the internal HSI48 oscillator.
0: HSI48 ready interrupt disabled
1: HSI48 ready interrupt enabled
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals .
Bit 9 LSECSSIE : LSE clock security system interrupt enable
Set and cleared by software to enable/disable interrupt caused by the clock security system on LSE.
0: Clock security interrupt caused by LSE clock failure disabled
1: Clock security interrupt caused by LSE clock failure enabled
Bits 8:6 Reserved, must be kept at reset value.
Bit 5 PLLRDYIE : PLL ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLL lock:
0: Disable
1: Enable
Bit 4 HSERDYIE : HSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization:
0: Disable
1: Enable
Bit 3 HSIRDYIE : HSI16 ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization:
0: Disable
1: Enable
Bit 2 MSIRDYIE : MSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the MSI oscillator stabilization.
0: MSI ready interrupt disabled
1: MSI ready interrupt enabled
Bit 1 LSERDYIE : LSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization:
0: Disable
1: Enable
Bit 0 LSIRDYIE : LSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization:
0: Disable
1: Enable
5.4.6 Clock interrupt flag register (RCC_CIFR)
Address offset: 0x1C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | HSI48 RDYF | LSE CSSF | CSSF | Res. | Res. | PLL RDYF | HSE RDYF | HSI RDYF | MSI RDYF | LSE RDYF | LSI RDYF |
| r | r | r | r | r | r | r | r | r |
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 HSI48RDYF : HSI48 ready interrupt flag
Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set in a response to setting the HSI48ON (refer to RCC clock recovery RC register (RCC_CRRCR) ).
Cleared by software setting the HSI48RDYC bit.
0: No clock ready interrupt caused by the HSI48 oscillator
1: Clock ready interrupt caused by the HSI48 oscillator
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals.
Bit 9 LSECSSF : LSE clock security system interrupt flag
Set by hardware when a failure is detected in the LSE oscillator.
Cleared by software by setting the LSECSSC bit.
0: No clock security interrupt caused by LSE clock failure
1: Clock security interrupt caused by LSE clock failure
Bit 8 CSSF : HSE clock security system interrupt flag
Set by hardware when a failure is detected in the HSE oscillator.
Cleared by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 PLLRDYF : PLL ready interrupt flag
Set by hardware when the PLL locks and PLLRDYIE is set.
Cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
Bit 4 HSERDYF : HSE ready interrupt flag
Set by hardware when the HSE clock becomes stable and HSERDYIE is set.
Cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the HSE oscillator
1: Clock ready interrupt caused by the HSE oscillator
Bit 3 HSIRDYF : HSI16 ready interrupt flag
Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in a response to setting the HSION (refer to Clock control register (RCC_CR) ). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.
Cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the HSI16 oscillator
1: Clock ready interrupt caused by the HSI16 oscillator
Bit 2 MSIRDYF : MSI ready interrupt flag
Set by hardware when the MSI clock becomes stable and MSIRDYIE is set.
Cleared by software setting the MSIRDYC bit.
0: No clock ready interrupt caused by the MSI oscillator
1: Clock ready interrupt caused by the MSI oscillator
Bit 1 LSERDYF : LSE ready interrupt flag
Set by hardware when the LSE clock becomes stable and LSERDYIE is set.
Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
Bit 0 LSIRDYF : LSI ready interrupt flag
Set by hardware when the LSI clock becomes stable and LSIRDYIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator
5.4.7 Clock interrupt clear register (RCC_CICR)
Address offset: 0x20
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | HSI48 RDYC | LSE CSSC | CSSC | Res. | Res. | PLL RDYC | HSE RDYC | HSI RDYC | MSI RDYC | LSE RDYC | LSI RDYC |
| w | w | w | w | w | w | w | w | w |
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 HSI48RDYC : HSI48 oscillator ready interrupt clear
This bit is set by software to clear the HSI48RDYF flag.
0: No effect
1: Clear the HSI48RDYC flag
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals.
Bit 9 LSECSSC : LSE Clock security system interrupt clear
This bit is set by software to clear the LSECSSF flag.
0: No effect
1: Clear LSECSSF flag
- Bit 8
CSSC
: Clock security system interrupt clear
This bit is set by software to clear the HSECSSF flag.
0: No effect
1: Clear CSSF flag - Bits 7:6 Reserved, must be kept at reset value.
- Bit 5
PLLRDYC
: PLL ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: Clear PLLRDYF flag - Bit 4
HSERDYC
: HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: Clear HSERDYF flag - Bit 3
HSIRDYC
: HSI16 ready interrupt clear
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: Clear HSIRDYF flag - Bit 2
MSIRDYC
: MSI ready interrupt clear
This bit is set by software to clear the MSIRDYF flag.
0: No effect
1: MSIRDYF cleared - Bit 1
LSERDYC
: LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: Clear LSERDYF flag - Bit 0
LSIRDYC
: LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: Clear LSIRDYF flag
5.4.8 AHB peripheral reset register (RCC_AHBRSTR)
Address offset: 0x28
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | TSC RST | Res. | Res. | Res. | Res. | Res. | RNG RST | Res. | AES RST |
| rw | rw | rw | |||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | CRC RST | Res. | Res. | Res. | FLASH RST | Res. | Res. | Res. | Res. | Res. | Res. | DMA2 RST | DMA1 RST |
| rw | rw | rw | rw |
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 TSCRST : Touch sensing controller reset
Set and cleared by software.
0: No effect
1: Reset TSC
Bits 23:19 Reserved, must be kept at reset value.
Bit 18 RNGRST : Random number generator reset
Set and cleared by software.
0: No effect
1: Reset RNG
Bit 17 Reserved, must be kept at reset value.
Bit 16 AESRST : AES hardware accelerator reset
Set and cleared by software.
0: No effect
1: Reset AES
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals.
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CRCRST : CRC reset
Set and cleared by software.
0: No effect
1: Reset CRC
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 FLASHRST : Flash memory interface reset
Set and cleared by software.
0: No effect
1: Reset flash memory interface
This bit can only be set when the flash memory is in power down mode.
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 DMA2RST : DMA2 and DMAMUX reset
Set and cleared by software.
0: No effect
1: Reset DMA2 and DMAMUX
Bit 0 DMA1RST : DMA1 and DMAMUX reset
Set and cleared by software.
0: No effect
1: Reset DMA1 and DMAMUX
5.4.9 I/O port reset register (RCC_IOPRSTR)
Address offset: 0x2C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | GPIOF RST | GPIOE RST | GPIO D RST | GPIO C RST | GPIO B RST | GPIO A RST |
| rw | rw | rw | rw | rw | rw |
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 GPIOFRST : I/O port F reset
This bit is set and cleared by software.
0: no effect
1: Reset I/O port F
Bit 4 GPIOERST : I/O port E reset
This bit is set and cleared by software.
0: no effect
1: Reset I/O port E
Bit 3 GPIO D RST : I/O port D reset
This bit is set and cleared by software.
0: no effect
1: Reset I/O port D
Bit 2 GPIO C RST : I/O port C reset
This bit is set and cleared by software.
0: no effect
1: Reset I/O port C
Bit 1 GPIO B RST : I/O port B reset
This bit is set and cleared by software.
0: no effect
1: Reset I/O port B
Bit 0 GPIO A RST : I/O port A reset
This bit is set and cleared by software.
0: no effect
1: Reset I/O port A
5.4.10 APB peripheral reset register 1 (RCC_APBHRSTR1)
Address offset: 0x38
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LPTIM1 RST | LPTIM2 RST | DAC1 RST | PWR RST | Res. | LPTIM3 RST | I2C4 RST | OPAMP RST | I2C3 RST | I2C2 RST | I2C1 RST | LP UART1 RST | USART 4 RST | USART 3 RST | USART 2 RST | CRS RST |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SPI3 RST | SPI2 RST | USB RST | LP UART3 RST | Res. | Res. | LCD RST | Res. | LP UART2 RST | Res. | TIM7 RST | TIM6 RST | Res. | Res. | TIM3 RST | TIM2 RST |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
Bit 31 LPTIM1RST : Low-power timer 1 reset
Set and cleared by software.
0: No effect
1: Reset LPTIM1
Bit 30 LPTIM2RST : Low-power timer 2 reset
Set and cleared by software.
0: No effect
1: Reset LPTIM2
Bit 29 DAC1RST : DAC1 interface reset
Set and cleared by software.
0: No effect
1: Reset DAC1 interface
Bit 28 PWRRST : Power interface reset
Set and cleared by software.
0: No effect
1: Reset PWR
Bit 27 Reserved, must be kept at reset value.
Bit 26 LPTIM3RST : LPTIM3 reset
Set and cleared by software.
0: No effect
1: Reset LPTIM3
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals.
Bit 25 I2C4RST : I2C4 reset
Set and cleared by software.
0: No effect
1: Reset I2C4
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals.
Bit 24 OPAMP_RST : OPAMP reset
Set and cleared by software.
0: No effect
1: Reset the OPAMP
Bit 23 I2C3RST : I2C3 reset
Set and cleared by software.
0: No effect
1: Reset I2C3
Bit 22 I2C2RST : I2C2 reset
Set and cleared by software.
0: No effect
1: Reset I2C2
Bit 21 I2C1RST : I2C1 reset
Set and cleared by software.
0: No effect
1: Reset I2C1
Bit 20 LPUART1RST : LPUART1 reset
Set and cleared by software.
0: No effect
1: Reset LPUART1
Bit 19 USART4RST : USART4 reset
Set and cleared by software.
0: No effect
1: Reset USART4
Bit 18 USART3RST : USART3 reset
Set and cleared by software.
0: No effect
1: Reset USART3
Bit 17 USART2RST : USART2 reset
Set and cleared by software.
0: No effect
1: Reset USART2
Bit 16 CRSRST : CRS reset
Set and cleared by software.
0: No effect
1: Reset CRS
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals .
Bit 15 SPI3RST : SPI3 reset
Set and cleared by software.
0: No effect
1: Reset SPI3
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals .
Bit 14 SPI2RST : SPI2 reset
Set and cleared by software.
0: No effect
1: Reset SPI2
Bit 13 USBRST : USB reset
Set and cleared by software.
0: No effect
1: Reset USB
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals .
Bit 12 LPUART3RST : LPUART3 reset
Set and cleared by software.
0: No effect
1: Reset LPUART3
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals .
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 LCDRST : LCD reset
Set and cleared by software.
0: No effect
1: Reset LCD
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals .
Bit 8 Reserved, must be kept at reset value.
Bit 7 LPUART2RST : LPUART2 reset
Set and cleared by software.
0: No effect
1: Reset LPUART2
Bit 6 Reserved, must be kept at reset value.
Bit 5 TIM7RST : TIM7 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM7
Bit 4 TIM6RST : TIM6 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM6
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM3RST : TIM3 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM3
Bit 0 TIM2RST : TIM2 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM2
5.4.11 APB peripheral reset register 2 (RCC_APBHRSTR2)
Address offset: 0x40
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ADC RST | Res. | Res. | TIM16 RST | TIM15 RST |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | USART 1 RST | Res. | SPI1 RST | TIM1 RST | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SYS CFG RST |
| rw | rw | rw | rw |
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 ADCRST : ADC reset
Set and cleared by software.
0: No effect
1: Reset ADC
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 TIM16RST : TIM16 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM16 timer
Bit 16 TIM15RST : TIM15 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM15 timer
Bit 15 Reserved, must be kept at reset value.
Bit 14 USART1RST : USART1 reset
Set and cleared by software.
0: No effect
1: Reset USART1
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1RST : SPI1 reset
Set and cleared by software.
0: No effect
1: Reset SPI1
Bit 11
TIM1RST
: TIM1 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM1 timer
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGRST : SYSCFG, COMP and VREFBUF reset
Set and cleared by software.
0: No effect
1: Reset SYSCFG + COMP + VREFBUF
5.4.12 AHB peripheral clock enable register (RCC_AHBENR)
Address offset: 0x48
Reset value: 0x0000 0100
This register individually enables clocks to AHB peripherals. In Sleep and Stop modes, a clock enabled through this register is only supplied to the peripheral if the corresponding bit of the RCC_AHBSMENR register is also set.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | TSC EN | Res. | Res. | Res. | Res. | Res. | RNG EN | Res. | AES EN |
| rw | rw | rw | |||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | CRC EN | Res. | Res. | Res. | FLASH EN | Res. | Res. | Res. | Res. | Res. | Res. | DMA2 EN | DMA1 EN |
| rw | rw | rw | rw |
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 TSCEN : Touch sensing controller clock enable
Set and cleared by software.
0: TSC clock disable
1: TSC clock enable
Bits 23:19 Reserved, must be kept at reset value.
Bit 18 RNGEN : Random number generator clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 17 Reserved, must be kept at reset value.
Bit 16 AESEN : AES hardware accelerator
Set and cleared by software.
0: Disable
1: Enable
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals .
Bits 15:13 Reserved, must be kept at reset value.
Bit 12
CRCEN
: CRC clock enable
Set and cleared by software.
0: Disable
1: Enable
Bits 11:9 Reserved, must be kept at reset value.
Bit 8
FLASHEN
: Flash memory interface clock enable
Set and cleared by software.
0: Disable
1: Enable
This bit can only be cleared when the flash memory is in power down mode.
Bits 7:2 Reserved, must be kept at reset value.
Bit 1
DMA2EN
: DMA2 and DMAMUX clock enable
Set and cleared by software.
0: Disable
1: Enable
DMAMUX is enabled as long as at least one DMA peripheral is enabled.
Bit 0
DMA1EN
: DMA1 and DMAMUX clock enable
Set and cleared by software.
0: Disable
1: Enable
DMAMUX is enabled as long as at least one DMA peripheral is enabled.
5.4.13 I/O port clock enable register (RCC_IOPENR)
Address offset: 0x4C
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | GPIOF EN | GPIOE EN | GPIO D EN | GPIO C EN | GPIO B EN | GPIO A EN |
| rw | rw | rw | rw | rw | rw |
Bits 31:6 Reserved, must be kept at reset value.
Bit 5
GPIOFEN
: I/O port F clock enable
This bit is set and cleared by software.
0: Disable
1: Enable
Bit 4 GPIOEEN : I/O port E clock enable
This bit is set and cleared by software.
0: Disable
1: Enable
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals.
Bit 3 GPIODEN : I/O port D clock enable
This bit is set and cleared by software.
0: Disable
1: Enable
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals.
Bit 2 GPIOCEN : I/O port C clock enable
This bit is set and cleared by software.
0: Disable
1: Enable
Bit 1 GPIOBEN : I/O port B clock enable
This bit is set and cleared by software.
0: Disable
1: Enable
Bit 0 GPIOAEN : I/O port A clock enable
This bit is set and cleared by software.
0: Disable
1: Enable
5.4.14 Debug configuration register (RCC_DBGCFGR)
Address offset: 0x50
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DBG RST | DBG EN |
| rw | rw |
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 DBGIRST : Debug support reset
Set and cleared by software.
0: No effect
1: Reset DBG
Bit 0 DBGEN : Debug support clock enable
Set and cleared by software.
0: Disable
1: Enable
5.4.15 APB peripheral clock enable register 1 (RCC_APBENR1)
Address offset: 0x58
Reset value: 0x0000 0400
This register individually enables clocks to APB peripherals. In Sleep and Stop modes, a clock enabled through this register is only supplied to the peripheral if the corresponding bit of the RCC_APBSMENR1 register is also set.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LPTIM1 EN | LPTIM2 EN | DAC1 EN | PWR EN | Res. | LPTIM3 EN | I2C4 EN | OPAMP EN | I2C3 EN | I2C2 EN | I2C1 EN | LP UART1 EN | USART 4 EN | USART 3 EN | USART 2 EN | CRS EN |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SPI3 EN | SPI2 EN | USB EN | LP UART3 EN | WWDG EN | RTC APB EN | LCD EN | Res. | LP UART2 EN | Res. | TIM7 EN | TIM6 EN | Res. | Res. | TIM3 EN | TIM2 EN |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
Bit 31 LPTIM1EN : LPTIM1 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 30 LPTIM2EN : LPTIM2 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 29 DAC1EN : DAC1 interface clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 28 PWREN : Power interface clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 27 Reserved, must be kept at reset value.
Bit 26 LPTIM3EN : LPTIM3 clock enable
Set and cleared by software.
0: Disable
1: Enable
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals.
Bit 25 I2C4EN : I2C4EN clock enable
Set and cleared by software.
0: Disable
1: Enable
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals.
Bit 24 OPAMPEN : OPAMP clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 23 I2C3EN : I2C3 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 22 I2C2EN : I2C2 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 21 I2C1EN : I2C1 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 20 LPUART1EN : LPUART1 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 19 USART4EN : USART4 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 18 USART3EN : USART3 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 17 USART2EN : USART2 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 16 CRSEN : CRS clock enable
Set and cleared by software.
0: Disable
1: Enable
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals .
Bit 15 SPI3EN : SPI3 clock enable
Set and cleared by software.
0: Disable
1: Enable
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals .
Bit 14 SPI2EN : SPI2 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 13 USBEN : USB clock enable
Set and cleared by software.
0: Disable
1: Enable
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals .
Bit 12 LPUART3EN : LPUART3 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 11 WWDGEN : WWDG clock enable
Set by software to enable the window watchdog clock. Cleared by hardware system reset
0: Disable
1: Enable
This bit can also be set by hardware if the WWDG_SW option bit is 0.
Bit 10 RTCPBEN : RTC APB clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 9 LCDEN : LCD clock enable (1)
Set and cleared by software.
0: Disable
1: Enable
Bit 8 Reserved, must be kept at reset value.
Bit 7 LPUART2EN : LPUART2 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 6 Reserved, must be kept at reset value.
Bit 5 TIM7EN : TIM7 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 4 TIM6EN : TIM6 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM3EN : TIM3 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 0 TIM2EN : TIM2 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
5.4.16 APB peripheral clock enable register 2(RCC_APBENR2)
Address offset: 0x60
Reset value: 0x0000 0000
This register individually enables clocks to APB peripherals. In Sleep and Stop modes, a clock enabled through this register is only supplied to the peripheral if the corresponding bit of the RCC_APBSMENR2 register is also set.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ADC EN | Res. | Res. | TIM16 EN | TIM15 EN |
| rw | rw | rw | |||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | USART1 EN | Res. | SPI1 EN | TIM1 EN | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SYS CFG EN |
| rw | rw | rw | rw |
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 ADCEN : ADC clock enable
Set and cleared by software.
0: Disable
1: Enable
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 TIM16EN : TIM16 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 16 TIM15EN : TIM15 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 15 Reserved, must be kept at reset value.
Bit 14 USART1EN : USART1 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1EN : SPI1 clock enable
Set and cleared by software.
0: Disable
1: Enable
Bit 11 TIM1EN : TIM1 timer clock enable
Set and cleared by software.
0: Disable
1: Enable
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGEN : SYSCFG, COMP and VREFBUF clock enable
Set and cleared by software.
0: Disable
1: Enable
5.4.17 AHB peripheral clock enable in Sleep mode register (RCC_AHBSMENR)
Address offset: 0x68
Reset value: 0x0105 1303
This register can individually program which AHB peripheral clocks are disabled (bit cleared) upon the device entering Sleep mode. When a bit of this register is set (enable), the corresponding peripheral clock is supplied in Sleep mode according to the setting of the RCC_AHBENR register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | TSC SMEN | Res. | Res. | Res. | Res. | Res. | RNG SMEN | Res. | AES SMEN |
| rw | rw | rw | |||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | CRC SMEN | Res. | Res. | SRAM SMEN | FLASH SMEN | Res. | Res. | Res. | Res. | Res. | Res. | DMA2 SMEN | DMA1 SMEN |
| rw | rw | rw | rw | rw |
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 TSCSMEN : TSC clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bits 23:19 Reserved, must be kept at reset value.
Bit 18 RNGSMEN : RNG clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 17 Reserved, must be kept at reset value.
Bit 16 AESSMEN : AES hardware accelerator clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals.
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CRCSMEN : CRC clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 SRAMSMEN : SRAM clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 8 FLASHSMEN : Flash memory interface clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
This bit can be activated only when the flash memory is in power down mode.
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 DMA2SMEN : DMA2 and DMAMUX clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral.
Bit 0 DMA1SMEN : DMA1 and DMAMUX clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral.
5.4.18 I/O port in Sleep mode clock enable register (RCC_IOPSMENR)
Address offset: 0x6C
Reset value: 0x0000 003F
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | GPIOF SMEN | GPIOE SMEN | GPIOD SMEN | GPIOC SMEN | GPIOB SMEN | GPIOA SMEN |
| rw | rw | rw | rw | rw | rw | ||||||||||
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 GPIOFSMEN : I/O port F clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 4 GPIOESMEN : I/O port E clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals .
Bit 3 GPIO DSMEN : I/O port D clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals .
Bit 2 GPIOCSMEN : I/O port C clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 1 GPIOBSMEN : I/O port B clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 0 GPIOASMEN : I/O port A clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
5.4.19 APB peripheral clock enable in Sleep/Stop mode register 1 (RCC_APB SMENR1)
Address offset: 0x78
Reset value: 0xF7FF FEB3
This register can individually program which APB peripheral clocks are disabled (bit cleared) upon the device entering Sleep or Stop mode. When a bit of this register is set (enable), the corresponding peripheral clock is supplied in Sleep or Stop mode according to the setting of the RCC_APBENR1 register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LPTIM1 SMEN | LPTIM2 SMEN | DAC1 SMEN | PWR SMEN | Res. | LPTIM3 SMEN | I2C4 SMEN | OPAMP SMEN | I2C3 SMEN | I2C2 SMEN | I2C1 SMEN | LP UART1 SMEN | USART 4 SMEN | USART 3 SMEN | USART 2 SMEN | CRS SMEN |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SPI3 SMEN | SPI2 SMEN | USB SMEN | LP UART3 SMEN | WWDG SMEN | RTC APB SMEN | LCD SMEN | Res. | LP UART2 SMEN | Res. | TIM7 SMEN | TIM6 SMEN | Res. | Res. | TIM3 SMEN | TIM2 SMEN |
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
Bit 31 LPTIM1SMEN : Low-power timer 1 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 30 LPTIM2SMEN : Low-power timer 2 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 29 DAC1SMEN : DAC1 interface clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 28 PWRSMEN : Power interface clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 27 Reserved, must be kept at reset value.
Bit 26 LPTIM3SMEN : Low-power timer 3 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals .
Bit 25 I2C4SMEN : I2C4 clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals .
Bit 24 OPAMP SMEN : OPAMP clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 23 I2C3SMEN : I2C3 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals .
Bit 22 I2C2SMEN : I2C2 clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 21 I2C1SMEN : I2C1 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 20 LPUART1SMEN : LPUART1 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 19 USART4SMEN : USART4 clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 18 USART3SMEN : USART3 clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 17 USART2SMEN : USART2 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 16 CRSSMEN : CRS clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals .
Bit 15 SPI3SMEN : SPI3 clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals .
Bit 14 SPI2SMEN : SPI2 clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 13 USBSMEN : USB clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals .
Bit 12 LPUART3SMEN : LPUART3 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 11 WWDGSMEN : WWDG clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 10 RTCAPBSMEN : RTC APB clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 9 LCDSMEN : LCD clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals .
Bit 8 Reserved, must be kept at reset value.
Bit 7 LPUART2SMEN : LPUART2 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 6 Reserved, must be kept at reset value.
Bit 5 TIM7SMEN : TIM7 timer clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 4 TIM6SMEN : TIM6 timer clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM3SMEN : TIM3 timer clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 0 TIM2SMEN : TIM2 timer clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
5.4.20 APB peripheral clock enable in Sleep/Stop mode register 2 (RCC_APBSMENR2)
Address offset: 0x80
Reset value: 0x0017 D801
This register can individually program which APB peripheral clocks are disabled (bit cleared) upon the device entering Sleep or Stop mode. When a bit of this register is set (enable), the corresponding peripheral clock is supplied in Sleep or Stop mode according to the setting of the RCC_APBENR2 register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ADC SMEN | Res. | Res. | TIM16 SMEN | TIM15 SMEN |
| rw | rw | rw | |||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | USART 1 SMEN | Res. | SPI1 SMEN | TIM1 SMEN | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SYS CFG SMEN |
| rw | rw | rw | rw |
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 ADC SMEN : ADC clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 TIM16 SMEN : TIM16 timer clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 16 TIM15 SMEN : TIM15 timer clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 15 Reserved, must be kept at reset value.
Bit 14 USART1SMEN : USART1 clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1SMEN : SPI1 clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bit 11 TIM1SMEN : TIM1 timer clock enable during Sleep mode
Set and cleared by software.
0: Disable
1: Enable
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGSMEN : SYSCFG, COMP and VREFBUF clock enable during Sleep and Stop modes
Set and cleared by software.
0: Disable
1: Enable
5.4.21 Peripherals independent clock configuration register (RCC_CCIPR)
Address offset: 0x88
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | ADCSEL[1:0] | CLK48SEL[1:0] | TIM15 SEL | TIM1 SEL | LPTIM3SEL[1:0] | LPTIM2SEL[1:0] | LPTIM1SEL[1:0] | I2C3SEL[1:0] | ||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | ||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | I2C1SEL[1:0] | LPUART1SEL [1:0] | LPUART2SEL [1:0] | LPUART3SEL [1:0] | Res. | Res. | USART2SEL [1:0] | USART1SEL [1:0] | ||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | ||||
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:28 ADCSEL[1:0] : ADCs clock source selection
This bitfield is controlled by software to select the clock source for ADC:
00: System clock
01: PLLPCLK
10: HSI16
11: Reserved
Bits 27:26 CLK48SEL[1:0] : 48 MHz clock source selection
This bitfield is controlled by software to select the 48 MHz clock source used by the USB FS and the RNG:
00: No clock
01: MSI
10: PLLQCLK
11: HSI48 (1)
Bit 25 TIM15SEL : TIM15 clock source selection
This bit is set and cleared by software. It selects TIM15 clock source as follows:
0: TIMPCLK
1: PLLQCLK
Bit 24 TIM1SEL : TIM1 clock source selection
This bit is set and cleared by software. It selects TIM1 clock source as follows:
0: TIMPCLK
1: PLLQCLK
Bits 23:22 LPTIM3SEL[1:0] : LPTIM3 clock source selection
This bitfield is controlled by software to select LPTIM3 clock source as follows:
00: PCLK
01: LSI
10: HSI16
11: LSE
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals .
Bits 21:20 LPTIM2SEL[1:0] : LPTIM2 clock source selection
This bitfield is controlled by software to select LPTIM2 clock source as follows:
00: PCLK
01: LSI
10: HSI16
11: LSE
Bits 19:18 LPTIM1SEL[1:0] : LPTIM1 clock source selection
This bitfield is controlled by software to select LPTIM1 clock source as follows:
00: PCLK
01: LSI
10: HSI16
11: LSE
Bits 17:16 I2C3SEL[1:0] : I2C3 clock source selection
This bitfield is controlled by software to select I2C3 clock source as follows:
00: PCLK
01: SYSCLK
10: HSI16
11: Reserved
Bits 15:14 Reserved, must be kept at reset value.
Bits 13:12 I2C1SEL[1:0] : I2C1 clock source selection
This bitfield is controlled by software to select I2C1 clock source as follows:
00: PCLK
01: SYSCLK
10: HSI16
11: Reserved
Bits 11:10 LPUART1SEL[1:0] : LPUART1 clock source selection
This bitfield is controlled by software to select LPUART1 clock source as follows:
00: PCLK
01: SYSCLK
10: HSI16
11: LSE
Bits 9:8 LPUART2SEL[1:0] : LPUART2 clock source selection
This bitfield is controlled by software to select LPUART2 clock source as follows:
00: PCLK
01: SYSCLK
10: HSI16
11: LSE
Bits 7:6 LPUART3SEL[1:0] : LPUART3 clock source selection
This bitfield is controlled by software to select LPUART3 clock source as follows:
00: PCLK
01: SYSCLK
10: HSI16
11: LSE
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals.
Bits 5:4 Reserved, must be kept at reset value.
Bits 3:2 USART2SEL[1:0] : USART2 clock source selection
This bitfield is controlled by software to select USART2 clock source as follows:
00: PCLK
01: SYSCLK
10: HSI16
11: LSE
Bits 1:0 USART1SEL[1:0] : USART1 clock source selection
This bitfield is controlled by software to select USART1 clock source as follows:
00: PCLK
01: SYSCLK
10: HSI16
11: LSE
5.4.22 RTC domain control register (RCC_BDCR)
Up to three wait states are inserted in case of successive accesses to this register. As this register is outside of the \( V_{CORE} \) domain, it is write-protected upon reset. The DBP bit of the Power control register 1 (PWR_CR1) must be set to allow their modification. Refer to Section 4.1.4: Battery backup domain on page 107 for further information.
The register bits are only reset upon RTC domain reset (see Section 5.1.3: RTC domain reset ), except the LSCOSEL, LSCOEN, and BDRST bits that are only reset upon RTC domain power-on reset. Any internal or external reset has no effect on these bits.
Address offset: 0x90
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | Res. | Res. | Res. | Res. | LSCO SEL | LSCO EN | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BDRST |
| rw | rw | rw | |||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RTCEN | Res. | Res. | Res. | LSE SYS RDY | Res. | RTCSEL[1:0] | LSE SYSEN | LSE CSSD | LSE CSS ON | LSEDRV[1:0] | LSE BYP | LSE RDY | LSEON | ||
| rw | r | rw | rw | r | rw | rw | rw | r | rw | ||||||
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 LSCOSEL : Low-speed clock output selection
Set and cleared by software to select the low-speed output clock:
0: LSI
1: LSE
Bit 24 LSCOEN : Low-speed clock output (LSCO) enable
Set and cleared by software.
0: Disable
1: Enable
Bits 23:17 Reserved, must be kept at reset value.
Bit 16 BDRST : RTC domain software reset
Set and cleared by software to reset the RTC domain:
0: No effect
1: Reset
Bit 15 RTCEN : RTC clock enable
Set and cleared by software. The bit enables clock to RTC and TAMP.
0: Disable
1: Enable
Bits 14:12 Reserved, must be kept at reset value.
Bit 11 LSESYRDY : LSE clock ready for system usage
This flag is set by hardware to indicate that the LSE clock is ready for being used by the system (see LSESYSEN bit). This flag is set when LSE clock is ready (LSEON = 1 and LSERDY = 1) and two LSE clock cycles after that LSESYSEN is set.
Cleared by hardware to indicate that the LSE clock is not ready to be used by the system.
0: LSE clock not ready for system
1: LSE clock ready for system
Bit 10 Reserved, must be kept at reset value.
Bits 9:8 RTCSEL[1:0] : RTC clock source selection
Set by software to select the clock source for the RTC as follows:
00: No clock
01: LSE
10: LSI
11: HSE divided by 32
Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset this bitfield to 00.
Bit 7 LSESYSEN : LSE clock enable for system usage
This bit must be set by software to enable the LSE clock for a system usage.
0: Disabled
1: Enabled, LSE distributed to peripherals including LSCO/MCO/SYSCLK/LCD.
Bit 6 LSECSSD: CSS on LSE failure DetectionSet by hardware to indicate when a failure is detected by the clock security system on the external 32 kHz oscillator (LSE):
0: No failure detected
1: Failure detected
Caution: When the LSECSSD bit is set, the LSE oscillator is held under reset and cannot be restarted. To clear the LSECSSD bit, reset the RTC domain using the BDRST bit.
Bit 5 LSECSSON: CSS on LSE enableSet by software to enable the clock security system on LSE (32 kHz) oscillator as follows:
0: Disable
1: Enable
LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected.
Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD =1). In that case the software must disable the LSECSSON bit.
Bits 4:3 LSEDRV[1:0]: LSE oscillator drive capabilitySet by software to select the LSE oscillator drive capability as follows:
00: low driving capability
01: medium-low driving capability
10: medium-high driving capability
11: high driving capability
Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode.
Bit 2 LSEBYP: LSE oscillator bypassSet and cleared by software to bypass the LSE oscillator.
0: Not bypassed
1: Bypassed
This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0).
Bit 1 LSERDY: LSE oscillator readySet and cleared by hardware to indicate when the external 32 kHz oscillator is ready (stable):
0: Not ready
1: Ready
After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles.
Bit 0 LSEON: LSE oscillator enableSet and cleared by software to enable LSE oscillator:
0: Disable
1: Enable
5.4.23 Control/status register (RCC_CSR)
Up to three wait states are inserted in case of successive accesses to this register. The register is reset upon system reset, except for reset flags that are only reset upon power reset.
Address offset: 0x94
Reset value: 0xXX00 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LPWR RSTF | WWDG RSTF | IWDG RSTF | SFT RSTF | PWR RSTF | PIN RSTF | OBL RSTF | Res. | RMVF | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| r | r | r | r | r | r | r | rw | ||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | Res. | Res. | Res. | MSISRANGE[3:0] | Res. | Res. | Res. | Res. | LSI PRE DIV | LSI RDY | LSION | ||||
| rw | rw | rw | rw | rw | r | rw | |||||||||
Set by hardware when a reset occurs due to illegal Stop, Standby, or Shutdown mode entry.
Cleared by setting the RMVF bit.
0: No illegal mode reset occurred
1: Illegal mode reset occurred
This operates only if nRST_STOP, nRST_STDBY or nRST_SHDW option bits are cleared.
Bit 30 WWDGRSTF: Window watchdog reset flagSet by hardware when a window watchdog reset occurs.
Cleared by setting the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Bit 29 IWDGRSTF: Independent window watchdog reset flagSet by hardware when an independent watchdog reset domain occurs.
Cleared by setting the RMVF bit.
0: No independent watchdog reset occurred
1: Independent watchdog reset occurred
Bit 28 SFTRSTF: Software reset flagSet by hardware when a software reset occurs.
Cleared by setting the RMVF bit.
0: No software reset occurred
1: Software reset occurred
Bit 27 PWRRSTF: BOR or POR/PDR flagSet by hardware when a BOR or POR/PDR occurs.
Cleared by setting the RMVF bit.
0: No BOR or POR occurred
1: BOR or POR occurred
Bit 26 PINRSTF: Pin or system reset flagSet by hardware when a reset from the PF2-NRST pin occurs or when a system reset is triggered by any other source. Cleared by setting the RMVF bit.
0: No system reset occurred
1: System reset from PF2-NRST pin or from other source occurred
Bit 25 OBLRSTF: Option byte loader reset flagSet by hardware when a reset from the Option byte loading occurs.
Cleared by setting the RMVF bit.
0: No reset from Option byte loading occurred
1: Reset from Option byte loading occurred
Bit 24 Reserved, must be kept at reset value.
Bit 23 RMVF : Remove reset flags
Set by software to clear the reset flags.
0: No effect
1: Clear reset flags
Bits 22:12 Reserved, must be kept at reset value.
Bits 11:8 MSISRANGE[3:0] : MSI range after Standby mode
Set by software to choose the MSI frequency at startup. This range is used after exiting Standby mode until MSIRGSEL is set. After a pad or a power-on reset, the range is always 4 MHz. MSISRANGE[3:0] can be written only when MSIRGSEL = 1.
0100: Range 4 around 1 MHz
0100: Range 5 around 2 MHz
0100: Range 6 around 4 MHz
0100: Range 7 around 8 MHz
Others: Reserved
Note: Changing the MSISRANGE[3:0] does not change the current MSI frequency.
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 LSIPREDIV : Internal low-speed oscillator pre-divided by 128
Set and reset by hardware to indicate when the low-speed internal RC oscillator has to be divided by 128. The software has to switch off the LSI before changing this bit.
0: LSI RC oscillator is not divided
1: LSI RC oscillator is divided by 128
Bit 1 LSIRDY : LSI oscillator ready
Set and cleared by hardware to indicate when the LSI oscillator is ready (stable):
0: Not ready
1: Ready
After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC.
Bit 0 LSION : LSI oscillator enable
Set and cleared by software to enable/disable the LSI oscillator:
0: Disable
1: Enable
5.4.24 RCC clock recovery RC register (RCC_CRRCR)
This register applies to STM32U073xx and STM32U083xx devices only. It is reserved otherwise.
Address offset: 0x98
Reset value: 0b0000 0000 0000 0000 1000 1000 0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HSI48CAL[8:0] | Res. | Res. | Res. | Res. | Res. | Res. | HSI48 RDY | HSI48 ON | |||||||
| r | r | r | r | r | r | r | r | r | r | nw | |||||
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:7 HSI48CAL[8:0] : HSI48 clock calibration
These bits are initialized at startup with the factory-programmed HSI48 calibration trim value.
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals.
Bits 6:2 Reserved, must be kept at reset value.
Bit 1 HSI48RDY : HSI48 clock ready flag
The flag is set when the HSI48 clock is ready for use.
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals.
Bit 0 HSI48ON : HSI48 RC oscillator enable
0: Disable
1: Enable
Note: This bit is significant on devices integrating the corresponding peripheral, otherwise it is reserved. Refer to Section 1.5: Availability of peripherals.
5.4.25 RCC register map
The following table gives the RCC register map and the reset values.
Table 33. RCC register map and reset values
| Offset | Register | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 | RCC_CR | Res. | Res. | Res. | Res. | Res. | Res. | PLLRDY | PLLON | Res. | Res. | Res. | Res. | CSSON | HSEBYP | HSERDY | HSEON | Res. | Res. | Res. | Res. | HSIASFS | HSIRDY | HSIKERON | HSION | MSIRANGE[3:0] | MSIRGSEL | MSIPLLEN | MSIRDY | MSION | |||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | ||||||||||||||||
| 0x04 | RCC_ICSCR | Res. | HSITRIM[6:0] | HSICAL[7:0] | MSITRIM[7:0] | MSICAL[7:0] | |||||||||||||||||||||||||||||
| Reset value | 1 | 0 | 0 | 0 | 0 | 0 | 0 | X | X | X | X | X | X | X | X | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | X | X | X | X | X | X | |||||
| 0x08 | RCC_CFGR | MCOPRE[3:0] | MCOSEL[3:0] | MCO2PRE[3:0] | MCO2SEL[3:0] | STOPWUCK | PPRE[2:0] | HPRE[3:0] | Res. | Res. | SWS[2:0] | SW[2:0] | |||||||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||
| 0x0C | RCC_PLLCFGR | PLL[2:0] | PLLREN | PLLQ[2:0] | PLLON | Res. | Res. | PLL[4:0] | PLLPEN | Res. | PLLN[6:0] | Res. | PLL[2:0] | Res. | Res. | PLL[1:0] | |||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||
| 0x10 - 0x14 | Reserved | Res. | |||||||||||||||||||||||||||||||||
| 0x18 | RCC_CIER | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HSI48RDYIE | LSECCSIE | Res. | Res. | Res. | PLLRDYIE | HSERDYIE | HSIRDYIE | MSIRDYIE | LSERDYIE | LSIRDYIE | ||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||||||||||||||||||||||||
Table 33. RCC register map and reset values (continued)
| Offset | Register | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x1C | RCC_CIFR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HSI48RDYF | LSECSSF | CSSF | Res. | Res. | Res. | PLL RDYF | HSERDYF | HSIRDYF | MSIRDYF | LSERDYF | LSIRDYF |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||||||||||||||||||||||
| 0x20 | RCC_CICR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HSI48RDYF | LSECSSC | CSSC | Res. | Res. | Res. | PLL RDYF | HSERDYF | HSIRDYF | MSIRDYF | LSERDYF | LSIRDYF |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||||||||||||||||||||||
| 0x24 | Reserved | Res. | ||||||||||||||||||||||||||||||||
| 0x28 | RCC_AHBRSTR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TSCRST | Res. | Res. | Res. | Res. | Res. | RNGRST | Res. | AESRST | Res. | Res. | Res. | CRCRST | Res. | Res. | Res. | FLASHRST | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DMA2RST | |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | ||||||||||||||||||||||||||||
| 0x2C | RCC_IOPRSTR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | |
| Reset value | 0 | 0 | 0 | 0 | 0 | |||||||||||||||||||||||||||||
| 0x30 - 0x34 | Reserved | Res. | ||||||||||||||||||||||||||||||||
| 0x38 | RCC_APBSTR1 | LPTIM1RST | LPTIM2RST | DAC1RST | PWRST | Res. | LPTIM3RST | I2C4RST | OPAMP1RST | I2C3RST | I2C2RST | I2C1RST | LPUART1RST | USART4RST | USART3RST | USART2RST | CRSRST | SPI3RST | SPI2RST | USB1RST | LPUART3RST | Res. | Res. | LODRST | Res. | LPUART2RST | Res. | TIM7RST | TIM6RST | Res. | Res. | TIM3RST | TIM2RST | |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||||||
| 0x3C | Reserved | Res. | ||||||||||||||||||||||||||||||||
| 0x40 | RCC_APBSTR2 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ADC1RST | Res. | Res. | TIM16RST | TIM15RST | Res. | USART1RST | Res. | SP1RST | TIM1RST | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SYSCFGRST |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||||||||||||||||||||||||
| 0x44 | Reserved | Res. | ||||||||||||||||||||||||||||||||
| 0x48 | RCC_AHBENR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TSCEN | Res. | Res. | Res. | Res. | Res. | RNGEN | Res. | AESSEN | Res. | Res. | Res. | CRCEN | Res. | Res. | Res. | FLASHEN | Res. | Res. | Res. | Res. | Res. | Res. | Res. | DMA2EN | DMA1EN |
| Reset value | 0 | 0 | 0 | 0 | 1 | 0 | ||||||||||||||||||||||||||||
| 0x4C | RCC_IOPENR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | |
| Reset value | 0 | 0 | 0 | 0 | 0 | |||||||||||||||||||||||||||||
| 0x50 | RCC_DBGCFGR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | |
| Reset value | 0 | |||||||||||||||||||||||||||||||||
| 0x54 | Reserved | Res. | ||||||||||||||||||||||||||||||||
Table 33. RCC register map and reset values (continued)
| Offset | Register | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x58 | RCC_APBENR1 | LPTIM1EN | LPTIM2EN | DAC1EN | PWREN | Res. | LPTIM3EN | I2C4EN | OPAMPEN | I2C3EN | I2C2EN | I2C1EN | LPUART1EN | USART4EN | USART3EN | USART2EN | CRSEN | SPI3EN | SPI2EN | USBEN | LPUART3EN | WWDGEN | RTCAPBEN | LCDEN | Res. | LPUART2EN | Res. | TIM7EN | TIM6EN | Res. | Res. | TIM3EN | TIM2EN |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||
| 0x5C | Reserved | Res. | |||||||||||||||||||||||||||||||
| 0x60 | RCC_APBENR2 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ADCEN | Res. | Res. | TIM16EN | TIM15EN | Res. | Res. | USART1EN | Res. | SPI1EN | TIM1EN | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||||||||||||||||||||||
| 0x64 | Reserved | Res. | |||||||||||||||||||||||||||||||
| 0x68 | RCC_AHBSMENR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | TSCSMEN | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | SRAMSMEN | FLASHSMEN | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| Reset value | 1 | 1 | 1 | 1 | |||||||||||||||||||||||||||||
| 0x6C | RCC_IOPSMENR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| Reset value | 1 | ||||||||||||||||||||||||||||||||
| 0x70 - 0x74 | Reserved | Res. | |||||||||||||||||||||||||||||||
| 0x78 | RCC_APBSMENR1 | LPTIM1SMEN | LPTIM2SMEN | DAC1SMEN | PWRSMEN | Res. | LPTIM3SMEN | I2C4SMEN | OPAMPSMEN | I2C3SMEN | I2C2SMEN | I2C1SMEN | LPUART1SMEN | USART4SMEN | USART3SMEN | USART2SMEN | CRSSMEN | SPI3SMEN | SPI2SMEN | USBSMEN | LPUART3SMEN | WWDGSMEN | RTCAPBSMEN | LCDSMEN | Res. | LPUART2SMEN | Res. | TIM7SMEN | TIM6SMEN | Res. | Res. | TIM3SMEN | TIM2SMEN |
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | ||||||
| 0x7C | Reserved | Res. | |||||||||||||||||||||||||||||||
| 0x80 | RCC_APBSMENR2 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ADCSMEN | Res. | Res. | TIM16SMEN | TIM15SMEN | Res. | Res. | USART1SMEN | Res. | SPI1SMEN | TIM1SMEN | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | ||||||||||||||||||||||||||
| 0x84 | Reserved | Res. | |||||||||||||||||||||||||||||||
| 0x88 | RCC_CCIPR | Res. | Res. | ADCSEL[1:0] | CLK48SEL[1:0] | TIM15SEL | TIM1SEL | LPTIM3SEL[1:0] | LPTIM2SEL[1:0] | LPTIM1SEL[1:0] | I2C3SEL[1:0] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||||||||||||||||||||||
| 0x8C | Reserved | Res. | |||||||||||||||||||||||||||||||
Table 33. RCC register map and reset values (continued)
| Offset | Register | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x90 | RCC_BDCR | Res. | Res. | Res. | Res. | Res. | Res. | LSCOSEL | LSCOEN | Res. | Res. | Res. | Res. | Res. | Res. | Res. | BDRST | RTCEN | Res. | Res. | Res. | LSESYSDRDY | Res. | RTC SEL[1:0] | Res. | LSESYSEN | LSECSSD | LSECSSON | LSE DRV[1:0] | Res. | LSEBYP | LSE RDY | LSEON |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||||||||||||||
| 0x94 | RCC_CSR | LPWRSTF | WWDGRSTF | IWDGRSTF | SFTRSTF | PWRSTF | PINRSTF | OBLRSTF | Res. | RMVF | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MSISRANGE [3:0] | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | LSIPREDIV | LSIRDY | LSION |
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||||||||||||||
| 0x98 | RCC_CRRCR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | HSI48CAL[8:0] | Res. | Res. | Res. | Res. | Res. | Res. | HSI48RDY | HSI48ON | |||||||
| Reset value | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||||||||||||||||||
Refer to Section 2.2 on page 55 for the register boundary addresses.