2. Memory and bus architecture

2.1 System architecture

The main system consists of:

• • Two masters:
  • – Cortex ^® -M0+ core
  • – General-purpose DMA
• • Three slaves:
  • – Internal SRAM
  • – Internal flash memory
  • – AHB with AHB-to-APB bridge that connects all the APB peripherals

These are interconnected using a multilayer AHB bus architecture as shown in Figure 1 .

Figure 1. System architecture

System bus (S-bus)

This bus connects the system bus of the Cortex ^® -M0+ core (peripheral bus) to a bus matrix that manages the arbitration between the core and the DMA.

DMA bus

This bus connects the AHB master interface of the DMA to the bus matrix that manages the access of CPU and DMA to SRAM, flash memory and AHB/APB peripherals.

Bus matrix

The bus matrix manages the access arbitration between the core system bus and the DMA master bus. The arbitration uses a Round Robin algorithm. The bus matrix is composed of masters (CPU, DMA) and slaves (flash memory interface, SRAM and AHB-to-APB bridge).

AHB peripherals are connected on system bus through the bus matrix to allow DMA access.

AHB-to-APB bridge (APB)

The AHB-to-APB bridge provides full synchronous connections between the AHB and the APB bus.

Refer to Section 2.2: Memory organization for the address mapping of the peripherals connected to this bridge.

After each device reset, all peripheral clocks are disabled (except for the SRAM and flash memory). Before using a peripheral its clock in the RCC_AHBENR, RCC_APBENRx or RCC_IOPENR register must first be enabled.

Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

2.2 Memory organization

2.2.1 Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word's least significant byte and the highest numbered byte the most significant.

2.2.2 Memory map and register boundary addresses

Figure 2. Memory map

1. STM32U073xx and STM32U083xx: 0x0803 FFFF; STM32U031xx: 0x0800 FFFF.

2. Depends on boot configuration.

All the memory map areas that are not allocated to on-chip memories and peripherals are considered as reserved. For the detailed mapping of available memory and register areas, refer to the following tables.

1. The memory boundary depends on the memory size of the ordered devices.

1. The memory boundary depends on the memory size of the ordered devices.

The following table gives the boundary addresses of the peripherals.

Table 4. STM32U0 series peripheral register boundary addresses

Table 4. STM32U0 series peripheral register boundary addresses (continued)

1. SYSCFG (ITLINE) registers use 0x4001 0000 as reference peripheral base address.

2.3 Embedded SRAM

The following table summarizes the SRAM resources on the devices. Enabling or disabling the parity check does not impact the size of the available SRAM.

The SRAM can be accessed by bytes, half-words (16 bits) or full words (32 bits), at maximum system clock frequency without wait state and thus by both CPU and DMA.

Parity check

The user can enable the parity check using the option bit RAM_PARITY_CHECK in the user option byte (refer to Section 3.4: FLASH option bytes ).

The data bus width is 36 bits because 4 bits are available for parity check (1 bit per byte) in order to increase memory robustness, as required for instance by Class B or SIL norms.

The parity bits are computed and stored when writing into the SRAM. Then, they are automatically checked when reading. If one bit fails, an NMI is generated. In addition, to get the SRAM parity error at the same cycle time that it is occurring, a bus error is generated (triggering a HardFault exception) together with the NMI. This avoids the corrupted data to be used by the application, but with the side effect of having both NMI and HardFault interrupts generated. The same error can also be linked to the BRK_IN Break input of TIM1/15, with the SRAM_PARITY_LOCK control bit in the SYSCFG configuration register 2 (SYSCFG_CFGR2) . The SRAM Parity Error flag (SRAM_PEF) is available in the SYSCFG configuration register 2 (SYSCFG_CFGR2) .

Note: When enabling the SRAM parity check, it is advised to initialize by software the whole SRAM at the beginning of the code, to avoid getting parity errors when reading non-initialized locations.

2.4 Flash memory overview

The flash memory is composed of two distinct physical areas:

• • The main flash memory block. It contains the application program and user data if necessary.
• • The information block. It is composed of three parts:
  • – Option bytes for hardware and memory protection user configuration.
  • – System memory which contains the proprietary bootloader code.
  • – OTP (one-time programmable) area
  Refer to Section 3: Embedded flash memory (FLASH) for more details.

The flash interface implements instruction access and data access based on the AHB protocol. It implements the prefetch buffer that speeds up CPU code execution. It also implements the logic necessary to carry out the flash memory operations (Program/Erase) controlled through the flash registers.

2.5 Boot configuration

In the STM32U0 series, three different boot modes can be selected through the BOOT0 pin, BOOT_LOCK bit in FLASH_SECR register, and boot configuration bits nBOOT1, BOOT_SEL and nBOOT0 in the User option byte, as shown in the following table.

BOOT0 pin is sampled on the NRST (external reset) rising edge. Refer to the description of the NRST (external reset) in Section 5.1.2: System reset for further details about how PF2-

NRST pin mode impacts BOOT0 sampling. The user option bits are loaded during the option byte loading (OBL) process.

The boot mode configuration is then latched on the fourth rising edge of SYSCLK after a reset. It is up to the user to set the boot mode configuration related to the required boot mode.

Table 6. Boot modes

The boot mode configuration is also re-sampled when exiting from Standby and Shutdown modes. Consequently it must be kept in the required Boot mode configuration during Standby and Shutdown modes. After this startup delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, then starts code execution from the boot memory at 0x0000 0004.

Depending on the selected boot mode, main flash memory, system memory or SRAM is accessible as follows:

• • Boot from main flash memory: the main flash memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x0800 0000). In other words, the flash memory contents can be accessed starting from address 0x0000 0000 or 0x0800 0000.
• • Boot from system memory: the system memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space 0x1FFF0000.
• • Boot from the embedded SRAM: the SRAM is aliased in the boot memory space (0x0000 0000), but it is still accessible from its original memory space (0x2000 0000).

Caution: BOOT0 pin shares the same GPIO with serial wire clock (SWCLK) that is used by the debugger to connect with the device, based on the fact that these functionalities can be considered almost completely disjoint. Nevertheless, to ensure system robustness, the STM32U0 series devices provide an hardware mechanism to force BOOT0 low (boot from user flash memory) if a debugger access is detected (and BOOT0 information is taken from the pin), in order to use SWCLK clock for debugger serial communications and at the same time have a safe boot configuration for the device itself. This configuration is kept until next power-on following debugger access.

2.5.1 Physical remap

Once the boot mode is selected, the application software can modify the memory accessible in the code area. This modification is performed by programming the MEM_MODE bits in the SYSCFG configuration register 1 (SYSCFG_CFGR1) .

2.5.2 Embedded bootloader

The embedded bootloader is located in the system memory, programmed by ST during production. It is used to reprogram the flash memory using one of the following serial interfaces:

• • USART, I2C and SPI (applies to all devices)
• • USB (DFU) (applies to STM32U073xx and STM32U083xx)

For further details, refer to the device datasheets and to AN2606.

2.5.3 Forcing boot from main flash memory

The BOOT_LOCK bit allows forcing a unique entry point in the main flash memory for boot, regardless of the other boot mode configuration bits (refer to Section 3.5.6: Forcing boot from main flash memory ).

2.5.4 Empty check

Internal empty check flag (the EMPTY bit of the FLASH access control register (FLASH_ACR) ) is implemented to allow easy programming of virgin devices by the bootloader. This flag is checked when the boot configuration defines the main flash memory as the target boot area and the BOOT_LOCK bit is not set. When the EMPTY flag is set, the device is considered empty and system memory (bootloader) is selected instead of the main flash memory as a boot area, to allow the user to program the device. Refer to AN2606 for more details concerning the bootloader and GPIO configuration in system memory boot mode (some of the GPIOs are reconfigured from the High-Z state).

The EMPTY flag is updated by hardware only during the loading of option bytes: it is set when the full 72-bit content (including ECC) of the address 0x0800 0000 is read as 0xFF FFFF FFFF FFFF FFFF, otherwise it is cleared. It means that, after programming of a virgin device, a power on reset or setting of OBL_LAUNCH bit in FLASH_CR register is required to clear the EMPTY flag (the system reset has no impact on this flag). Software can also modify the EMPTY flag directly in the FLASH_ACR register.

Note: If the device is programmed for the first time but the EMPTY flag is not updated, the device still selects the system memory as a boot area after a system reset.