RM0503-STM32U0
This reference manual targets application developers. It provides complete information on how to use the STM32U0 series microcontroller memory and peripherals.
The STM32U0 series are microcontroller lines with different packages and peripherals.
Refer to the corresponding data briefs for ordering information, mechanical and electrical device characteristics.
For information on the Arm ® Cortex ® -M0+ core, refer to the Cortex ® -M0+ Technical Reference Manual .
The STM32U0 series microcontrollers include ST state-of-the-art patented technology.
Related documents
- • Cortex ® -M0+ Technical Reference Manual, available from: http://infocenter.arm.com
- • STM32U0x1xx and STM32U0x3xx datasheets.
- • STM32U031xx and STM32U073/83xx errata sheets.
Contents
- 1 Documentation conventions . . . . . 51
- 1.1 General information . . . . . 51
- 1.2 List of abbreviations for registers . . . . . 51
- 1.3 Register reset value . . . . . 51
- 1.4 Glossary . . . . . 52
- 1.5 Availability of peripherals . . . . . 52
- 2 Memory and bus architecture . . . . . 53
- 2.1 System architecture . . . . . 53
- 2.2 Memory organization . . . . . 55
- 2.2.1 Introduction . . . . . 55
- 2.2.2 Memory map and register boundary addresses . . . . . 56
- 2.3 Embedded SRAM . . . . . 60
- 2.4 Flash memory overview . . . . . 61
- 2.5 Boot configuration . . . . . 61
- 2.5.1 Physical remap . . . . . 63
- 2.5.2 Embedded bootloader . . . . . 63
- 2.5.3 Forcing boot from main flash memory . . . . . 63
- 2.5.4 Empty check . . . . . 63
- 3 Embedded flash memory (FLASH) . . . . . 64
- 3.1 FLASH introduction . . . . . 64
- 3.2 FLASH main features . . . . . 64
- 3.3 FLASH functional description . . . . . 65
- 3.3.1 Flash memory organization . . . . . 65
- 3.3.2 FLASH error code correction (ECC) . . . . . 66
- 3.3.3 FLASH read access latency . . . . . 66
- 3.3.4 Flash memory acceleration . . . . . 68
- 3.3.5 FLASH program and erase operations . . . . . 68
- 3.3.6 FLASH main memory erase sequences . . . . . 69
- 3.3.7 FLASH main memory programming sequences . . . . . 70
- 3.4 FLASH option bytes . . . . . 75
- 3.4.1 FLASH option byte description . . . . . 75
| 3.4.2 | FLASH option byte programming . . . . . | 76 |
| 3.5 | Flash memory protection . . . . . | 78 |
| 3.5.1 | FLASH read protection (RDP) . . . . . | 78 |
| 3.5.2 | FLASH write protection (WRP) . . . . . | 82 |
| 3.5.3 | Securable memory area (HDP) . . . . . | 83 |
| 3.5.4 | Securable memory area extension (HDP extension) . . . . . | 83 |
| 3.5.5 | Disabling core debug access . . . . . | 85 |
| 3.5.6 | Forcing boot from main flash memory . . . . . | 85 |
| 3.6 | FLASH interrupts . . . . . | 85 |
| 3.7 | FLASH registers . . . . . | 86 |
| 3.7.1 | FLASH access control register (FLASH_ACR) . . . . . | 86 |
| 3.7.2 | FLASH key register (FLASH_KEYR) . . . . . | 87 |
| 3.7.3 | FLASH option key register (FLASH_OPTKEYR) . . . . . | 87 |
| 3.7.4 | FLASH status register (FLASH_SR) . . . . . | 88 |
| 3.7.5 | FLASH control register (FLASH_CR) . . . . . | 90 |
| 3.7.6 | FLASH ECC register (FLASH_ECCR) . . . . . | 92 |
| 3.7.7 | FLASH option register (FLASH_OPTR) . . . . . | 93 |
| 3.7.8 | FLASH WRP area A address register (FLASH_WRP1AR) . . . . . | 95 |
| 3.7.9 | FLASH WRP area B address register (FLASH_WRP1BR) . . . . . | 95 |
| 3.7.10 | FLASH security register (FLASH_SECR) . . . . . | 96 |
| 3.7.11 | FLASH OEM1 key register 1 (FLASH_OEM1KEYR1) . . . . . | 97 |
| 3.7.12 | FLASH OEM1 key register 2 (FLASH_OEM1KEYR2) . . . . . | 97 |
| 3.7.13 | FLASH OEM1 key register 3 (FLASH_OEM1KEYR3) . . . . . | 97 |
| 3.7.14 | FLASH OEM1 key register 4 (FLASH_OEM1KEYR4) . . . . . | 98 |
| 3.7.15 | FLASH OEM2 key register 1 (FLASH_OEM2KEYR1) . . . . . | 98 |
| 3.7.16 | FLASH OEM2 key register 2 (FLASH_OEM2KEYR2) . . . . . | 99 |
| 3.7.17 | FLASH OEM2 key register 3 (FLASH_OEM2KEYR3) . . . . . | 99 |
| 3.7.18 | FLASH OEM2 key register 4 (FLASH_OEM2KEYR4) . . . . . | 99 |
| 3.7.19 | FLASH OEM key status register (FLASH_OEMKEYSR) . . . . . | 100 |
| 3.7.20 | FLASH HDP control register (FLASH_HDPCR) . . . . . | 100 |
| 3.7.21 | FLASH HDP extension register (FLASH_HDPEXTR) . . . . . | 101 |
| 3.7.22 | FLASH register map . . . . . | 102 |
| 4 | Power control (PWR) . . . . . | 104 |
| 4.1 | Power supplies . . . . . | 104 |
| 4.1.1 | Independent analog peripherals supply . . . . . | 105 |
| 4.1.2 | Independent USB transceivers supply . . . . . | 106 |
- 4.1.3 Independent LCD supply . . . . . 106
- 4.1.4 Battery backup domain . . . . . 107
- 4.1.5 Voltage regulator . . . . . 108
- 4.1.6 Dynamic voltage scaling management . . . . . 109
- 4.2 Power supply supervisor . . . . . 110
- 4.2.1 Power-on reset (POR) / power-down reset (PDR) / brown-out reset (BOR) . . . . . 110
- 4.2.2 Programmable voltage detector (PVD) . . . . . 110
- 4.2.3 Peripheral Voltage Monitoring (PVM) . . . . . 111
- 4.3 Low-power modes . . . . . 112
- 4.3.1 Run mode . . . . . 118
- 4.3.2 Low-power run mode (LP run) . . . . . 118
- 4.3.3 Low-power modes . . . . . 119
- 4.3.4 Sleep mode . . . . . 120
- 4.3.5 Low-power sleep mode (LP sleep) . . . . . 121
- 4.3.6 Stop 0 mode . . . . . 122
- 4.3.7 Stop 1 mode . . . . . 124
- 4.3.8 Stop 2 mode . . . . . 125
- 4.3.9 Standby mode . . . . . 127
- 4.3.10 Shutdown mode . . . . . 130
- 4.3.11 Auto-wakeup from low-power mode . . . . . 131
- 4.4 PWR registers . . . . . 132
- 4.4.1 Power control register 1 (PWR_CR1) . . . . . 132
- 4.4.2 Power control register 2 (PWR_CR2) . . . . . 133
- 4.4.3 Power control register 3 (PWR_CR3) . . . . . 134
- 4.4.4 Power control register 4 (PWR_CR4) . . . . . 136
- 4.4.5 Power status register 1 (PWR_SR1) . . . . . 137
- 4.4.6 Power status register 2 (PWR_SR2) . . . . . 138
- 4.4.7 Power status clear register (PWR_SCR) . . . . . 140
- 4.4.8 Power Port A pull-up control register (PWR_PUCRA) . . . . . 141
- 4.4.9 Power Port A pull-down control register (PWR_PDCRA) . . . . . 141
- 4.4.10 Power Port B pull-up control register (PWR_PUCRB) . . . . . 142
- 4.4.11 Power Port B pull-down control register (PWR_PDCRB) . . . . . 143
- 4.4.12 Power Port C pull-up control register (PWR_PUCRC) . . . . . 143
- 4.4.13 Power Port C pull-down control register (PWR_PDCRC) . . . . . 144
- 4.4.14 Power Port D pull-up control register (PWR_PUCRD) . . . . . 144
- 4.4.15 Power Port D pull-down control register (PWR_PDCRD) . . . . . 145
| 4.4.16 | Power Port E pull-up control register (PWR_PUCRE) . . . . . | 145 |
| 4.4.17 | Power Port E pull-down control register (PWR_PDCRE) . . . . . | 146 |
| 4.4.18 | Power Port F pull-up control register (PWR_PUCRF) . . . . . | 147 |
| 4.4.19 | Power Port F pull-down control register (PWR_PDCRF) . . . . . | 147 |
| 4.4.20 | PWR register map and reset value table . . . . . | 148 |
| 5 | Reset and clock control (RCC) . . . . . | 150 |
| 5.1 | Reset . . . . . | 150 |
| 5.1.1 | Power reset . . . . . | 150 |
| 5.1.2 | System reset . . . . . | 150 |
| 5.1.3 | RTC domain reset . . . . . | 152 |
| 5.2 | Clocks . . . . . | 153 |
| 5.2.1 | HSE clock . . . . . | 157 |
| 5.2.2 | HSI16 clock . . . . . | 158 |
| 5.2.3 | HSI48 clock . . . . . | 159 |
| 5.2.4 | MSI clock . . . . . | 159 |
| 5.2.5 | PLL . . . . . | 160 |
| 5.2.6 | LSE clock . . . . . | 161 |
| 5.2.7 | LSI clock . . . . . | 161 |
| 5.2.8 | System clock (SYSCLK) selection . . . . . | 162 |
| 5.2.9 | Clock source frequency versus voltage scaling . . . . . | 162 |
| 5.2.10 | Clock security system (CSS) . . . . . | 162 |
| 5.2.11 | Clock security system for LSE clock (LSECSS) . . . . . | 163 |
| 5.2.12 | ADC clock . . . . . | 163 |
| 5.2.13 | RTC clock . . . . . | 164 |
| 5.2.14 | Timer clock . . . . . | 164 |
| 5.2.15 | Watchdog clock . . . . . | 164 |
| 5.2.16 | Clock-out capability . . . . . | 165 |
| 5.2.17 | Internal/external clock measurement with TIM16 . . . . . | 165 |
| 5.2.18 | Peripheral clock enable registers . . . . . | 167 |
| 5.3 | Low-power modes . . . . . | 167 |
| 5.4 | RCC registers . . . . . | 169 |
| 5.4.1 | Clock control register (RCC_CR) . . . . . | 169 |
| 5.4.2 | Internal clock sources calibration register (RCC_ICSCR) . . . . . | 172 |
| 5.4.3 | Clock configuration register (RCC_CFGR) . . . . . | 173 |
| 5.4.4 | PLL configuration register (RCC_PLLCFGR) . . . . . | 176 |
| 5.4.5 | Clock interrupt enable register (RCC_CIER) . . . . . | 178 |
| 5.4.6 | Clock interrupt flag register (RCC_CIFR) . . . . . | 180 |
| 5.4.7 | Clock interrupt clear register (RCC_CICR) . . . . . | 181 |
| 5.4.8 | AHB peripheral reset register (RCC_AHBRSTR) . . . . . | 182 |
| 5.4.9 | I/O port reset register (RCC_IOPRSTR) . . . . . | 184 |
| 5.4.10 | APB peripheral reset register 1 (RCC_APBSTR1) . . . . . | 185 |
| 5.4.11 | APB peripheral reset register 2 (RCC_APBSTR2) . . . . . | 188 |
| 5.4.12 | AHB peripheral clock enable register (RCC_AHBENR) . . . . . | 189 |
| 5.4.13 | I/O port clock enable register (RCC_IOPENR) . . . . . | 190 |
| 5.4.14 | Debug configuration register (RCC_DBGCFGR) . . . . . | 191 |
| 5.4.15 | APB peripheral clock enable register 1 (RCC_APBENR1) . . . . . | 192 |
| 5.4.16 | APB peripheral clock enable register 2(RCC_APBENR2) . . . . . | 195 |
| 5.4.17 | AHB peripheral clock enable in Sleep mode register (RCC_AHBSMENR) . . . . . | 196 |
| 5.4.18 | I/O port in Sleep mode clock enable register (RCC_IOPSMENR) . . . . . | 197 |
| 5.4.19 | APB peripheral clock enable in Sleep/Stop mode register 1 (RCC_APBSMENR1) . . . . . | 198 |
| 5.4.20 | APB peripheral clock enable in Sleep/Stop mode register 2 (RCC_APBSMENR2) . . . . . | 202 |
| 5.4.21 | Peripherals independent clock configuration register (RCC_CCIPR) . . . . . | 203 |
| 5.4.22 | RTC domain control register (RCC_BDCR) . . . . . | 205 |
| 5.4.23 | Control/status register (RCC_CSR) . . . . . | 207 |
| 5.4.24 | RCC clock recovery RC register (RCC_CRRRCR) . . . . . | 209 |
| 5.4.25 | RCC register map . . . . . | 210 |
| 6 | Clock recovery system (CRS) . . . . . | 214 |
| 6.1 | CRS introduction . . . . . | 214 |
| 6.2 | CRS main features . . . . . | 214 |
| 6.3 | CRS implementation . . . . . | 214 |
| 6.4 | CRS functional description . . . . . | 215 |
| 6.4.1 | CRS block diagram . . . . . | 215 |
| 6.4.2 | CRS internal signals . . . . . | 215 |
| 6.4.3 | Synchronization input . . . . . | 216 |
| 6.4.4 | Frequency error measurement . . . . . | 216 |
| 6.4.5 | Frequency error evaluation and automatic trimming . . . . . | 217 |
| 6.4.6 | CRS initialization and configuration . . . . . | 218 |
| 6.5 | CRS in low-power modes . . . . . | 219 |
| 6.6 | CRS interrupts . . . . . | 219 |
| 6.7 | CRS registers . . . . . | 219 |
| 6.7.1 | CRS control register (CRS_CR) . . . . . | 219 |
| 6.7.2 | CRS configuration register (CRS_CFGR) . . . . . | 220 |
| 6.7.3 | CRS interrupt and status register (CRS_ISR) . . . . . | 221 |
| 6.7.4 | CRS interrupt flag clear register (CRS_ICR) . . . . . | 223 |
| 6.7.5 | CRS register map . . . . . | 224 |
| 7 | General-purpose I/Os (GPIO) . . . . . | 225 |
| 7.1 | Introduction . . . . . | 225 |
| 7.2 | GPIO main features . . . . . | 225 |
| 7.3 | GPIO functional description . . . . . | 225 |
| 7.3.1 | General-purpose I/O (GPIO) . . . . . | 227 |
| 7.3.2 | I/O pin alternate function multiplexer and mapping . . . . . | 228 |
| 7.3.3 | I/O port control registers . . . . . | 229 |
| 7.3.4 | I/O port state in low-power modes . . . . . | 229 |
| 7.3.5 | I/O port data registers . . . . . | 229 |
| 7.3.6 | I/O data bitwise handling . . . . . | 229 |
| 7.3.7 | GPIO locking mechanism . . . . . | 230 |
| 7.3.8 | I/O alternate function input/output . . . . . | 230 |
| 7.3.9 | External interrupt/wake-up lines . . . . . | 230 |
| 7.3.10 | Input configuration . . . . . | 231 |
| 7.3.11 | Output configuration . . . . . | 231 |
| 7.3.12 | Alternate function configuration . . . . . | 232 |
| 7.3.13 | Analog configuration . . . . . | 233 |
| 7.3.14 | Using the HSE or LSE oscillator pins as GPIOs . . . . . | 234 |
| 7.3.15 | Using the GPIO pins in the RTC supply domain . . . . . | 234 |
| 7.3.16 | Using PF3 as GPIO . . . . . | 234 |
| 7.3.17 | Reset pin (PF2-NRST) in GPIO mode . . . . . | 234 |
| 7.4 | GPIO registers . . . . . | 235 |
| 7.4.1 | GPIO port mode register (GPIOx_MODER) (x = A to F) . . . . . | 235 |
| 7.4.2 | GPIO port output type register (GPIOx_OTYPER) (x = A to F) . . . . . | 235 |
| 7.4.3 | GPIO port output speed register (GPIOx_OSPEEDR) (x = A to F) . . . . . | 236 |
| 7.4.4 | GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to F) . . . . . | 236 |
| 7.4.5 | GPIO port input data register (GPIOx_IDR) (x = A to F) . . . . . | 237 |
| 7.4.6 | GPIO port output data register (GPIOx_ODR) (x = A to F) . . . . . | 237 |
| 7.4.7 | GPIO port bit set/reset register (GPIOx_BSRR) (x = A to F) . . . . . | 237 |
| 7.4.8 | GPIO port configuration lock register (GPIOx_LCKR) (x = A to F) . . . . . | 238 |
| 7.4.9 | GPIO alternate function low register (GPIOx_AFRL) (x = A to F) . . . . | 239 |
| 7.4.10 | GPIO alternate function high register (GPIOx_AFRH) (x = A to F) . . . | 240 |
| 7.4.11 | GPIO port bit reset register (GPIOx_BRR) (x = A to F) . . . . . | 241 |
| 7.4.12 | GPIO register map . . . . . | 241 |
Chapters
- 8. System configuration controller (SYSCFG) . . . . . 243
- 1. Documentation conventions
- 2. Memory and bus architecture
- 3. Embedded flash memory (FLASH)
- 4. Power control (PWR)
- 5. Reset and clock control (RCC)
- 6. Clock recovery system (CRS)
- 7. General-purpose I/Os (GPIO)
- 8. System configuration controller (SYSCFG)
- 9. Direct memory access controller (DMA)
- 10. DMA request multiplexer (DMAMUX)
- 11. Nested vectored interrupt controller (NVIC)
- 12. Extended interrupt and event controller (EXTI)
- 13. Cyclic redundancy check calculation unit (CRC)
- 14. Analog-to-digital converter (ADC)
- 15. Digital-to-analog converter (DAC)
- 16. Voltage reference buffer (VREFBUF)
- 17. Comparator (COMP)
- 18. Operational amplifiers (OPAMP)
- 19. Liquid crystal display controller (LCD)
- 20. Touch sensing controller (TSC)
- 21. True random number generator (RNG)
- 22. AES hardware accelerator (AES)
- 23. Advanced-control timer (TIM1)
- 24. General-purpose timers (TIM2/TIM3)
- 25. Basic timers (TIM6/TIM7)
- 26. General-purpose timers (TIM15/TIM16)
- 27. Low-power timer (LPTIM)
- 28. Infrared interface (IRTIM)
- 29. Independent watchdog (IWDG)
- 30. System window watchdog (WWDG)
- 31. Real-time clock (RTC)
- 32. Tamper and backup registers (TAMP)
- 33. Inter-integrated circuit interface (I2C)
- 34. Universal synchronous/asynchronous receiver transmitter (USART/UART)
- 35. Low-power universal asynchronous receiver transmitter (LPUART)
- 36. Serial peripheral interface (SPI)
- 37. Universal serial bus full-speed device interface (USB)
- 38. Debug support (DBG)
- 39. Device electronic signature