46. Revision history

Table 443. Document revision history

Date	Revision	Changes
20-Jan-2022	1	Initial release.
23-Nov-2022	2	Updated document title, Flash programming errors , Section 7.9.15: FLASH boot address 0 register (FLASH_NSBOOTADD0R) , Section 7.9.16: FLASH boot address 1 register (FLASH_NSBOOTADD1R) , Section 7.9.17: FLASH secure boot address 0 register (FLASH_SECBBOOTADD0R) , I/O states in Standby mode , Section 9.1: Introduction , Section 9.2: Main features , Section 9.4.3: Transmit output power , Section 11.7.2: PWR background autonomous mode (BAM) , Section 11.7.6: PWR Stop 0 mode , Section 11.7.7: PWR Stop 1 mode , Section 11.7.9: Power modes output pins , Section 11.10.9: PWR disable Backup domain register (PWR_DBPR) , Section 11.10.10: PWR security configuration register (PWR_SECCFGR) , LSI1 low-power , Section 12.4.17: Clock-out capability , Section 12.8.13: RCC AHB2 peripheral reset register (RCC_AHB2RSTR) , Section 12.8.39: RCC Backup domain control register (RCC_BDCR1) , Section 12.8.51: RCC clock configuration register 2 (RCC_CFGR4) , Section 14.4.5: GPIO port data registers , Section 14.8.1: GPIO port H mode register (GPIOH_MODER) , Section 15.3.3: SYSCFG FPU interrupt mask register (SYSCFG_FPUIMR) , Section 15.3.5: SYSCFG CPU secure lock register (SYSCFG_CSLCKR) , Section 16.3.1: Master to slave interconnection for timers , Section 16.3.5: Triggers to low-power timer , and Section 44.1.1: DESIG package data register (DESIG_PKGR) . Removed former Section 9.4.4: Bluetooth AoA and AoD . Added Section 45: Important security notice . Updated Table 41: Number of wait states according to CPU clock (hclk1) frequency (LPM = 1) , Table 75: Input / output pins , Table 78: 2.4 GHz RADIO supply configuration , Table 83: PWR internal input/output signals , Table 92: Power modes output states versus MCU power modes , Table 94: PWR interrupt requests , Table 104: RCC register map and reset values , Table 119: SYSCFG register map and reset values , and Table 132: Vector table . Updated Figure 32: Operating modes . Minor text edits across the whole document.

Date

Revision

Changes

20-Jan-2022

Initial release.

23-Nov-2022

Updated document title, Flash programming errors , Section 7.9.15: FLASH boot address 0 register (FLASH_NSBOOTADD0R) , Section 7.9.16: FLASH boot address 1 register (FLASH_NSBOOTADD1R) , Section 7.9.17: FLASH secure boot address 0 register (FLASH_SECBBOOTADD0R) , I/O states in Standby mode , Section 9.1: Introduction , Section 9.2: Main features , Section 9.4.3: Transmit output power , Section 11.7.2: PWR background autonomous mode (BAM) , Section 11.7.6: PWR Stop 0 mode , Section 11.7.7: PWR Stop 1 mode , Section 11.7.9: Power modes output pins , Section 11.10.9: PWR disable Backup domain register (PWR_DBPR) , Section 11.10.10: PWR security configuration register (PWR_SECCFGR) , LSI1 low-power , Section 12.4.17: Clock-out capability , Section 12.8.13: RCC AHB2 peripheral reset register (RCC_AHB2RSTR) , Section 12.8.39: RCC Backup domain control register (RCC_BDCR1) , Section 12.8.51: RCC clock configuration register 2 (RCC_CFGR4) , Section 14.4.5: GPIO port data registers , Section 14.8.1: GPIO port H mode register (GPIOH_MODER) , Section 15.3.3: SYSCFG FPU interrupt mask register (SYSCFG_FPUIMR) , Section 15.3.5: SYSCFG CPU secure lock register (SYSCFG_CSLCKR) , Section 16.3.1: Master to slave interconnection for timers , Section 16.3.5: Triggers to low-power timer , and Section 44.1.1: DESIG package data register (DESIG_PKGR) .

Removed former Section 9.4.4: Bluetooth AoA and AoD .

Added Section 45: Important security notice .

Updated Table 41: Number of wait states according to CPU clock (hclk1) frequency (LPM = 1) , Table 75: Input / output pins , Table 78: 2.4 GHz RADIO supply configuration , Table 83: PWR internal input/output signals , Table 92: Power modes output states versus MCU power modes , Table 94: PWR interrupt requests , Table 104: RCC register map and reset values , Table 119: SYSCFG register map and reset values , and Table 132: Vector table .

Updated Figure 32: Operating modes .

Minor text edits across the whole document.

Table 443. Document revision history (continued)

Date	Revision	Changes
20-Oct-2023	3	Document scope extended to STM32WBA54xx and STM32WBA55xx devices. Removed former Section 1.4: Availability of peripherals . Added Section 10: PTA converter (PTACONV) , Section 12.4.19: Audio synchronization , Section 12.8.41: RCC Backup domain control register (RCC_BDCR2) , sections 12.8.44 to 12.8.50 , Section 16.3.14: From timer (TIM1/TIM2/TIM3) to comparators (COMP1/COMP2) , Section 16.3.15: From comparators (COMP1/COMP2) to timers , Section 22: Comparator (COMP) , Section 39.8.5: USART control register 3 [alternate] (USART_CR3) , Section 40.7.5: LPUART control register 3 [alternate] (LPUART_CR3) , Section 44.1.9: DESIG resistor calibration register (DESIG_RCALR) , and Section 44.1.10: DESIG radio gain calibration register (DESIG_RFGAINCALR) . Updated Section 11: Power control (PWR) and its subsections to add SMPS (switch-mode power supply) support, Section 12.4: RCC clocks functional description , Section 12.4.5: LSI clock , Section 12.4.6: System clock (SYSCLK) selection , Section 12.8.18: RCC APB2 peripheral reset register (RCC_APB2RSTR) , Section 12.8.19: RCC APB7 peripheral reset register (RCC_APB7RSTR) , Section 12.8.26: RCC APB2 peripheral clock enable register (RCC_APB2ENR) , Section 12.8.27: RCC APB7 peripheral clock enable register (RCC_APB7ENR) , Section 12.8.34: RCC APB2 peripheral clocks enable in Sleep and Stop modes register (RCC_APB2SMENR) , Section 12.8.35: RCC APB7 peripheral clock enable in Sleep and Stop modes register (RCC_APB7SMENR) , Section 12.8.37: RCC peripherals independent clock configuration register 2 (RCC_CCIPR2) , Section 12.8.39: RCC Backup domain control register (RCC_BDCR1) , Section 14.5.1: GPIO port A mode register (GPIOA_MODER) , Section 23.3.4: Charge transfer acquisition sequence , Section 23.3.4: Charge transfer acquisition sequence , Section 24.7.4: RNG noise source control register (RNG_NSCR) , Section 37.2: TAMP main features , Section 37.3.9: Tamper detection , DBGMCU part number codification register (DBGMCU_PNCR) , and Section 44.1.1: DESIG package data register (DESIG_PKGR) . Updated Table 99: RCC input/output signals connected to package pins or balls , Table 105: RCC security configuration summary , Table 106: Interrupt sources and control , Table 107: RCC register map and reset values , Table 112: GPIO implementation , Table 123: Peripherals interconnect matrix , Table 135: Vector table , Table 138: EXTI line connections , Table 145: ADC features , Table 180: RNG register map and reset map , Table 255: Interconnect to the tim_ti1 input multiplexer , tables 260 to 264 , tables 279 to 282 , tables 284 to 285 , Table 298: Timer break interconnect , Table 300: Interconnect to the ocref_clr input multiplexer , tables 311 to 314 , Table 377: USART interconnection (USART1/2) , Table 384: USART register map and reset values , Table 389: LPUART interconnections (LPUART1) , Table 395: LPUART register map and reset values , tables in Description of SPI interconnections , and Table 442: DESIG register map and reset values . Updated Figure 34: Clock tree , Figure 73: Calibration factor forcing , Figure 359: LPTIM block diagram ⁽¹⁾, Figure 388: I2C initialization flow , and Figure 394: Target initialization flow . Minor text edits across the whole document.

Date

Revision

Changes

20-Oct-2023

Document scope extended to STM32WBA54xx and STM32WBA55xx devices.

Removed former Section 1.4: Availability of peripherals .

Added Section 10: PTA converter (PTACONV) , Section 12.4.19: Audio synchronization , Section 12.8.41: RCC Backup domain control register (RCC_BDCR2) , sections 12.8.44 to 12.8.50 , Section 16.3.14: From timer (TIM1/TIM2/TIM3) to comparators (COMP1/COMP2) , Section 16.3.15: From comparators (COMP1/COMP2) to timers , Section 22: Comparator (COMP) , Section 39.8.5: USART control register 3 [alternate] (USART_CR3) , Section 40.7.5: LPUART control register 3 [alternate] (LPUART_CR3) , Section 44.1.9: DESIG resistor calibration register (DESIG_RCALR) , and Section 44.1.10: DESIG radio gain calibration register (DESIG_RFGAINCALR) .

Updated Section 11: Power control (PWR) and its subsections to add SMPS (switch-mode power supply) support, Section 12.4: RCC clocks functional description , Section 12.4.5: LSI clock , Section 12.4.6: System clock (SYSCLK) selection , Section 12.8.18: RCC APB2 peripheral reset register (RCC_APB2RSTR) , Section 12.8.19: RCC APB7 peripheral reset register (RCC_APB7RSTR) , Section 12.8.26: RCC APB2 peripheral clock enable register (RCC_APB2ENR) , Section 12.8.27: RCC APB7 peripheral clock enable register (RCC_APB7ENR) , Section 12.8.34: RCC APB2 peripheral clocks enable in Sleep and Stop modes register (RCC_APB2SMENR) , Section 12.8.35: RCC APB7 peripheral clock enable in Sleep and Stop modes register (RCC_APB7SMENR) , Section 12.8.37: RCC peripherals independent clock configuration register 2 (RCC_CCIPR2) , Section 12.8.39: RCC Backup domain control register (RCC_BDCR1) , Section 14.5.1: GPIO port A mode register (GPIOA_MODER) , Section 23.3.4: Charge transfer acquisition sequence , Section 23.3.4: Charge transfer acquisition sequence , Section 24.7.4: RNG noise source control register (RNG_NSCR) , Section 37.2: TAMP main features , Section 37.3.9: Tamper detection , DBGMCU part number codification register (DBGMCU_PNCR) , and Section 44.1.1: DESIG package data register (DESIG_PKGR) .

Updated Table 99: RCC input/output signals connected to package pins or balls , Table 105: RCC security configuration summary , Table 106: Interrupt sources and control , Table 107: RCC register map and reset values , Table 112: GPIO implementation , Table 123: Peripherals interconnect matrix , Table 135: Vector table , Table 138: EXTI line connections , Table 145: ADC features , Table 180: RNG register map and reset map , Table 255: Interconnect to the tim_ti1 input multiplexer , tables 260 to 264 , tables 279 to 282 , tables 284 to 285 , Table 298: Timer break interconnect , Table 300: Interconnect to the ocref_clr input multiplexer , tables 311 to 314 , Table 377: USART interconnection (USART1/2) , Table 384: USART register map and reset values , Table 389: LPUART interconnections (LPUART1) , Table 395: LPUART register map and reset values , tables in Description of SPI interconnections , and Table 442: DESIG register map and reset values .

Updated Figure 34: Clock tree , Figure 73: Calibration factor forcing , Figure 359: LPTIM block diagram ⁽¹⁾, Figure 388: I2C initialization flow , and Figure 394: Target initialization flow .

Minor text edits across the whole document.

Table 443. Document revision history (continued)

Date	Revision	Changes
05-Jun-2024	4	Updated Section 8.4: ICACHE functional description , Section 9.2: Main features , Section 11.10.2: PWR control register 2 (PWR_CR2) , Section 15.2.1: I/O compensation cell management , Suspend/resume operations in ECB/CBC modes , Suspend and resume operations in CCM mode , Suspend/resume operations in ECB/CBC modes , Suspend and resume operations in CCM mode , Section 30.5.10: TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)(x = 2, 3) , Section 36.3.6: Clock and prescalers , Section 37.3.2: TAMP pins and internal signals , Section 41.4.5: Standard multislave communication , and DBGMCU identity code register (DBGMCU_IDCODE) . Updated figures 72 to 74 , 77 , and 79 in Section 21: Analog-to-digital converter (ADC4) . Updated Figure 245: General-purpose timer block diagram , Figure 436: IrDA SIR ENDEC block diagram , Figure 438: Transmission using DMA , Figure 439: Reception using DMA , Figure 450: Transmission using DMA , and Figure 451: Reception using DMA . Added Figure 385: Tamper sampling with precharge pulse and Figure 386: Low level detection with precharge and filtering . Added Table 177: RNG initialization times and Table 179: Configuration selection . Removed former Section 24.6.3: Data collection . Removed former Table 384: Error calculation for programmed baud rates at $f_{CK} = 100$ MHz , Table 394: SPI interconnection (SPI8) , and Table 395: SPI interconnection (SPI1 to SPI6) . Added Initialization time , Section 38.7: I2C DMA requests and its subsections, and Section 38.8: I2C debug modes . Updated Table 363: Timing settings for $f_{I2CCLK}$ of 8 MHz , Table 364: Timing settings for $f_{I2CCLK}$ of 16 MHz , Table 375: USART/UART input/output pins , Table 377: USART interconnection (USART1/2) , Table 389: LPUART interconnections (LPUART1) , and Table 396: SPI features . Rearranged sequence of registers in Section 42: Serial audio interface (SAI) . Minor text edits across the whole document.

Date

Revision

Changes

05-Jun-2024

Updated Section 8.4: ICACHE functional description , Section 9.2: Main features , Section 11.10.2: PWR control register 2 (PWR_CR2) , Section 15.2.1: I/O compensation cell management , Suspend/resume operations in ECB/CBC modes , Suspend and resume operations in CCM mode , Suspend/resume operations in ECB/CBC modes , Suspend and resume operations in CCM mode , Section 30.5.10: TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)(x = 2, 3) , Section 36.3.6: Clock and prescalers , Section 37.3.2: TAMP pins and internal signals , Section 41.4.5: Standard multislave communication , and DBGMCU identity code register (DBGMCU_IDCODE) .

Updated figures 72 to 74 , 77 , and 79 in Section 21: Analog-to-digital converter (ADC4) .

Updated Figure 245: General-purpose timer block diagram , Figure 436: IrDA SIR ENDEC block diagram , Figure 438: Transmission using DMA , Figure 439: Reception using DMA , Figure 450: Transmission using DMA , and Figure 451: Reception using DMA .

Added Figure 385: Tamper sampling with precharge pulse and Figure 386: Low level detection with precharge and filtering .

Added Table 177: RNG initialization times and Table 179: Configuration selection .

Removed former Section 24.6.3: Data collection .

Removed former Table 384: Error calculation for programmed baud rates at $f_{CK} = 100$ MHz , Table 394: SPI interconnection (SPI8) , and Table 395: SPI interconnection (SPI1 to SPI6) .

Added Initialization time , Section 38.7: I2C DMA requests and its subsections, and Section 38.8: I2C debug modes .

Updated Table 363: Timing settings for $f_{I2CCLK}$ of 8 MHz , Table 364: Timing settings for $f_{I2CCLK}$ of 16 MHz , Table 375: USART/UART input/output pins , Table 377: USART interconnection (USART1/2) , Table 389: LPUART interconnections (LPUART1) , and Table 396: SPI features .

Rearranged sequence of registers in Section 42: Serial audio interface (SAI) .

Minor text edits across the whole document.

Table 443. Document revision history (continued)

Date	Revision	Changes
27-Sep-2024	5	Document scope extended to STM32WBA50xx devices. Updated Introduction , Section 2.3.2: Memory map and register boundary addresses , Section 2.3.3: Embedded SRAM , Section 12.8.39: RCC Backup domain control register (RCC_BDCR1) , Section 12.8.40: RCC control/status register (RCC_CSR) , Section 17.4.17: GPDMA autonomous mode , Section 34.4.1: IWDG block diagram , Configuring the IWDG when the window option is disabled , Section 34.7.4: IWDG status register (IWDG_SR) , Section 36.6.24: RTC alarm A binary mode register (RTC_ALRABINR) , Section 36.6.24: RTC alarm A binary mode register (RTC_ALRABINR) , Active tamper detection , Section 37.6.5: TAMP active tamper control register 1 (TAMP_ATCR1) , Data frame format , Section 41.4.12: SPI data transmission and reception procedures , and Section 41.4.14: Communication using DMA (direct memory addressing) . Updated Figure 1: System architecture , Figure 34: Clock tree , Figure 377: Window comparator update ⁽¹⁾, and Figure 379: Early wake-up comparator update ⁽¹⁾. Updated Table 5: Memory map and peripheral register boundary addresses and its footnotes, Table 34: SRAM parity access error , Table 75: 2.4 GHz RADIO implementation , Table 123: Peripherals interconnect matrix , Table 346: Active tamper output change period , and Table 348: Active tamper filtered pulse duration . Minor text edits across the whole document.
16-Jan-2025	6	Added Section 1.3: Register reset value . Updated Section 2.1.4: Bus matrix , Section 2.2.1: Default TrustZone security state , Section 5.6.5: GTZC1 TZSC privilege configuration register 1 (GTZC1_TZSC_PRIVCFG1) , Section 5.6.6: GTZC1 TZSC privilege configuration register 2 (GTZC1_TZSC_PRIVCFG2) , Section 5.6.7: GTZC1 TZSC privilege configuration register 3 (GTZC1_TZSC_PRIVCFG3) , Section 7.3.2: Error code correction (ECC) , Section 9.1: Introduction , Section 10.3.3: PTACONV protocols , Section 10.3.4: PTACONV interface with the 2.4 GHz RADIO , Section 11.4.1: External power supplies , Exiting Standby mode , Section 14.4: GPIO functional description , and Section 14.4.13: GPIO analog configuration . Replaced master/slave with controller/target in Section 38: Inter-integrated circuit interface (I2C) . Added Table 1: Bus matrix access arbitration . Updated Table 5: Memory map and peripheral register boundary addresses , Table 81: PTACONV internal input/output signals , Table 257: Interconnect to the tim_ti3 input multiplexer , Table 273: Interrupt requests , and Table 442: DESIG register map and reset values . Updated Figure 24: PTACONV block diagram , Figure 25: 4-wire PTA grant protocol , Figure 26: 4-wire PTA deny protocol , Figure 27: 3-wire time-multiplexed PTA_STATUS , Figure 47: High-impedance analog configuration , Figure 207: tim_o cref_clr input selection multiplexer , Figure 285: O CREF_CLR input selection multiplexer , and Figure 422: Start bit detection when oversampling by 16 or 8 . Minor text edits across the whole document.

Date

Revision

Changes

27-Sep-2024

Document scope extended to STM32WBA50xx devices.

Updated Introduction , Section 2.3.2: Memory map and register boundary addresses , Section 2.3.3: Embedded SRAM , Section 12.8.39: RCC Backup domain control register (RCC_BDCR1) , Section 12.8.40: RCC control/status register (RCC_CSR) , Section 17.4.17: GPDMA autonomous mode , Section 34.4.1: IWDG block diagram , Configuring the IWDG when the window option is disabled , Section 34.7.4: IWDG status register (IWDG_SR) , Section 36.6.24: RTC alarm A binary mode register (RTC_ALRABINR) , Section 36.6.24: RTC alarm A binary mode register (RTC_ALRABINR) , Active tamper detection , Section 37.6.5: TAMP active tamper control register 1 (TAMP_ATCR1) , Data frame format , Section 41.4.12: SPI data transmission and reception procedures , and Section 41.4.14: Communication using DMA (direct memory addressing) .

Updated Figure 1: System architecture , Figure 34: Clock tree , Figure 377: Window comparator update ⁽¹⁾, and Figure 379: Early wake-up comparator update ⁽¹⁾.

Updated Table 5: Memory map and peripheral register boundary addresses and its footnotes, Table 34: SRAM parity access error , Table 75: 2.4 GHz RADIO implementation , Table 123: Peripherals interconnect matrix , Table 346: Active tamper output change period , and Table 348: Active tamper filtered pulse duration .

Minor text edits across the whole document.

16-Jan-2025

Added Section 1.3: Register reset value .

Updated Section 2.1.4: Bus matrix , Section 2.2.1: Default TrustZone security state , Section 5.6.5: GTZC1 TZSC privilege configuration register 1 (GTZC1_TZSC_PRIVCFG1) , Section 5.6.6: GTZC1 TZSC privilege configuration register 2 (GTZC1_TZSC_PRIVCFG2) , Section 5.6.7: GTZC1 TZSC privilege configuration register 3 (GTZC1_TZSC_PRIVCFG3) , Section 7.3.2: Error code correction (ECC) , Section 9.1: Introduction , Section 10.3.3: PTACONV protocols , Section 10.3.4: PTACONV interface with the 2.4 GHz RADIO , Section 11.4.1: External power supplies , Exiting Standby mode , Section 14.4: GPIO functional description , and Section 14.4.13: GPIO analog configuration .

Replaced master/slave with controller/target in Section 38: Inter-integrated circuit interface (I2C) .

Added Table 1: Bus matrix access arbitration .

Updated Table 5: Memory map and peripheral register boundary addresses , Table 81: PTACONV internal input/output signals , Table 257: Interconnect to the tim_ti3 input multiplexer , Table 273: Interrupt requests , and Table 442: DESIG register map and reset values .

Updated Figure 24: PTACONV block diagram , Figure 25: 4-wire PTA grant protocol , Figure 26: 4-wire PTA deny protocol , Figure 27: 3-wire time-multiplexed PTA_STATUS , Figure 47: High-impedance analog configuration , Figure 207: tim_o cref_clr input selection multiplexer , Figure 285: O CREF_CLR input selection multiplexer , and Figure 422: Start bit detection when oversampling by 16 or 8 .

Minor text edits across the whole document.

Table 443. Document revision history (continued)

Date	Revision	Changes
11-Mar-2025	7	Replaced Bluetooth® Low Energy with Bluetooth® LE. Updated document Section 12.8.9: RCC clock interrupt enable register (RCC_CIER) , Section 40.7.8: LPUART interrupt and status register (LPUART_ISR) , Section 41.8.4: SPI configuration register 2 (SPI_CFG2) , Section 42.6.4: SAI slot register (SAI_ASLOTR) , and DBGMCU identity code register (DBGMCU_IDCODE) . Added Section 3.6.2: RSSLIB functions , Section 9.5: Low-power modes , and Section 10.4: Low-power modes . Replaced SS with NSS in Section 41: Serial peripheral interface (SPI) . Updated Table 99: RCC input/output signals connected to package pins or balls , Table 135: Vector table , Table 377: USART interconnection (USART1/2) , Table 389: LPUART interconnections (LPUART1) , and Table 441: DBGMCU register map and reset values . Minor text edits across the whole document.

Date

Revision

Changes

11-Mar-2025

Replaced Bluetooth® Low Energy with Bluetooth® LE.

Updated document Section 12.8.9: RCC clock interrupt enable register (RCC_CIER) , Section 40.7.8: LPUART interrupt and status register (LPUART_ISR) , Section 41.8.4: SPI configuration register 2 (SPI_CFG2) , Section 42.6.4: SAI slot register (SAI_ASLOTR) , and DBGMCU identity code register (DBGMCU_IDCODE) .

Added Section 3.6.2: RSSLIB functions , Section 9.5: Low-power modes , and Section 10.4: Low-power modes .

Replaced SS with NSS in Section 41: Serial peripheral interface (SPI) .

Updated Table 99: RCC input/output signals connected to package pins or balls , Table 135: Vector table , Table 377: USART interconnection (USART1/2) , Table 389: LPUART interconnections (LPUART1) , and Table 441: DBGMCU register map and reset values .

Minor text edits across the whole document.

Index

A

ADC_AWD1TR	676	BPU_CIDR1	1786
ADC_AWD2CR	682	BPU_CIDR2	1786
ADC_AWD2TR	677	BPU_CIDR3	1787
ADC_AWD3CR	682	BPU_COMPxR	1781
ADC_AWD3TR	680	BPU_CTRLR	1781
ADC_CALFACT	683	BPU_DEVARCHR	1782
ADC_CCR	683	BPU_DEVTYPEr	1782
ADC_CFGR1	671	BPU_PIDR0	1783
ADC_CFGR2	674	BPU_PIDR1	1784
ADC_CHSELR	678	BPU_PIDR2	1784
ADC_CR	669	BPU_PIDR3	1785
ADC_DR	681	BPU_PIDR4	1783
ADC_IER	666
ADC_ISR	665	C
ADC_PWRR	681	C1ROM_CIDR3	1751
ADC_SMPR	675	COMP1_CSR	694
AES_CR	765	COMP2_CSR	695
AES_DINR	768	CRC_CR	621
AES_DOUTR	769	CRC_DR	620
AES_ICR	776	CRC_IDR	620
AES_IER	774	CRC_INIT	622
AES_ISR	775	CRC_POL	622
AES_IVR0	771	CTI_APPCLEAR	1804
AES_IVR1	771	CTI_APPPULSER	1805
AES_IVR2	771	CTI_APPSETr	1804
AES_IVR3	772	CTI_CHINSTSR	1807
AES_KEYR0	769	CTI_CHOUTSTSR	1808
AES_KEYR1	770	CTI_CIDR0	1812
AES_KEYR2	770	CTI_CIDR1	1812
AES_KEYR3	770	CTI_CIDR2	1813
AES_KEYR4	772	CTI_CIDR3	1813
AES_KEYR5	772	CTI_CONTROLR	1803
AES_KEYR6	773	CTI_DEVIDR	1809
AES_KEYR7	773	CTI_DEVTYPEr	1809
AES_SR	767	CTI_GATER	1808
AES_SUSPxR	773	CTI_INENRx	1805
APx_BASER	1733	CTI_INTACKR	1803
APx_BDyR	1732	CTI_OUTENRx	1806
APx_CFGR	1733	CTI_PIDR0	1810
APx_CSWR	1731	CTI_PIDR1	1810
APx_DRWR	1732	CTI_PIDR2	1811
APx_IDR	1734	CTI_PIDR3	1811
APx_TAR	1732	CTI_PIDR4	1809
		CTI_TRGISTSR	1806
		CTI_TRGOSTSR	1807

B

BPU_CIDR0

1785

D

DBGMCU_AHB1FZR . . . . .	1824	DWT_DEVARCHR . . . . .	1761
DBGMCU_APB1HFZR . . . . .	1822	DWT_DEVTYPE R . . . . .	1762
DBGMCU_APB1LFZR . . . . .	1821	DWT_EXCCNTR . . . . .	1755
DBGMCU_APB2FZR . . . . .	1822	DWT_FOLDCNTR . . . . .	1756
DBGMCU_APB7FZR . . . . .	1823	DWT_FUNCTR0 . . . . .	1757
DBGMCU_CIDR0 . . . . .	1829	DWT_FUNCTR1 . . . . .	1758
DBGMCU_CIDR1 . . . . .	1829	DWT_FUNCTR2 . . . . .	1759
DBGMCU_CIDR2 . . . . .	1830	DWT_FUNCTR3 . . . . .	1760
DBGMCU_CIDR3 . . . . .	1830	DWT_LSUCNTR . . . . .	1756
DBGMCU_DBG_AUTH_DEVICE . . . . .	1826	DWT_PCSR . . . . .	1756
DBGMCU_DBG_AUTH_HOST . . . . .	1825	DWT_PIDR0 . . . . .	1763
DBGMCU_IDCODE . . . . .	1819	DWT_PIDR1 . . . . .	1763
DBGMCU_IDCODER . . . . .	1816	DWT_PIDR2 . . . . .	1763
DBGMCU_PIDR0 . . . . .	1827	DWT_PIDR3 . . . . .	1764
DBGMCU_PIDR1 . . . . .	1827	DWT_PIDR4 . . . . .	1762
DBGMCU_PIDR2 . . . . .	1828	DWT_SLP CNTR . . . . .	1755
DBGMCU_PIDR3 . . . . .	1828
DBGMCU_PIDR4 . . . . .	1826
DBGMCU_PNCR . . . . .	1826
DBGMCU_SCR . . . . .	1820
DBGMCU_SR . . . . .	1825
DESIG_FLASHSIZER . . . . .	1836
DESIG_PKGR . . . . .	1834
DESIG_RCALR . . . . .	1837
DESIG_RFGAINCALR . . . . .	1837
DESIG_TSCAL1R . . . . .	1835
DESIG_TSCAL2R . . . . .	1836
DESIG_UID64R1 . . . . .	1838
DESIG_UID64R2 . . . . .	1838
DESIG_UIDR1 . . . . .	1834
DESIG_UIDR2 . . . . .	1835
DESIG_UIDR3 . . . . .	1835
DESIG_VREFINTCALR . . . . .	1837
DP_ABORTR . . . . .	1722
DP_BUFFR . . . . .	1727
DP_CTRLSTATR . . . . .	1723
DP_DLCR . . . . .	1724
DP_DLPIDR . . . . .	1726
DP_PIDR . . . . .	1722
DP_EVENSTATR . . . . .	1726
DP_RESENR . . . . .	1726
DP_SELECTR . . . . .	1727
DP_TARGETIDR . . . . .	1725
DWT_CIDR0 . . . . .	1764
DWT_CIDR1 . . . . .	1765
DWT_CIDR2 . . . . .	1765
DWT_CIDR3 . . . . .	1766
DWT_COMPxR . . . . .	1757
DWT_CPICNTR . . . . .	1755
DWT_CTRLR . . . . .	1753
DWT_CYCCNTR . . . . .	1754

E

EXTI_EMR1 . . . . .	614
EXTI_EXTICR1 . . . . .	606
EXTI_EXTICR2 . . . . .	608
EXTI_EXTICR3 . . . . .	609
EXTI_EXTICR4 . . . . .	611
EXTI_FPR1 . . . . .	605
EXTI_FTSR1 . . . . .	603
EXTI_IMR1 . . . . .	613
EXTI_LOCKR . . . . .	613
EXTI_PRIVCFG R1 . . . . .	606
EXTI_RPR1 . . . . .	604
EXTI_RTSR1 . . . . .	602
EXTI_SECCFG R1 . . . . .	605
EXTI_SWIER1 . . . . .	603

F

FLASH_ACR . . . . .	214
FLASH_ECCR . . . . .	223
FLASH_NSBOOTADD0R . . . . .	228
FLASH_NSBOOTADD1R . . . . .	229
FLASH_NSCR1 . . . . .	220
FLASH_NSCR2 . . . . .	225
FLASH_NSKEYR . . . . .	215
FLASH_NSSR . . . . .	217
FLASH_OEM1KEYR1 . . . . .	233
FLASH_OEM1KEYR2 . . . . .	233
FLASH_OEM2KEYR1 . . . . .	234
FLASH_OEM2KEYR2 . . . . .	234
FLASH_OPSR . . . . .	224
FLASH_OPTKEYR . . . . .	216
FLASH_OPTR . . . . .	226
FLASH_PDKEYR . . . . .	217
FLASH_PRIFCFG R . . . . .	235

FLASH_PRIVBBRx	236
FLASH_SECBBRx	234
FLASH_SECBBOOTADD0R	229
FLASH_SECCR1	222
FLASH_SECCR2	226
FLASH_SECHDPCR	235
FLASH_SECKEYR	216
FLASH_SECSR	219
FLASH_SECWMR1	230
FLASH_SECWMR2	231
FLASH_WRPAR	231
FLASH_WRPBR	232

G

GPDMA_CxBR1	584
GPDMA_CxC	575
GPDMA_CxDAR	587
GPDMA_CxFCR	573
GPDMA_CxLBAR	572
GPDMA_CxLLR	588
GPDMA_CxSAR	586
GPDMA_CxSR	574
GPDMA_CxTR1	577
GPDMA_CxTR2	581
GPDMA_MISR	571
GPDMA_PRIVCFGGR	570
GPDMA_RCFGLOCKR	570
GPDMA_SECCFGR	569
GPDMA_SMISR	572
GPIOA_AFRH	474
GPIOA_AFRL	473
GPIOA_BRR	475
GPIOA_BSRR	472
GPIOA_IDR	471
GPIOA_LCKR	472
GPIOA_MODER	468
GPIOA_ODR	471
GPIOA_OSPEEDR	469
GPIOA_OTYPER	469
GPIOA_PUPDR	470
GPIOA_SECCFGR	476
GPIOB_AFRH	482
GPIOB_AFRL	481
GPIOB_BRR	483
GPIOB_BSRR	480
GPIOB_IDR	479
GPIOB_LCKR	480
GPIOB_MODER	476
GPIOB_ODR	480
GPIOB_OSPEEDR	477
GPIOB_OTYPER	477
GPIOB_PUPDR	478
GPIOB_SECCFGR	484
GPIOC_AFRH	489
GPIOC_BRR	489
GPIOC_BSRR	487
GPIOC_IDR	486
GPIOC_LCKR	488
GPIOC_MODER	484
GPIOC_ODR	487
GPIOC_OSPEEDR	485
GPIOC_OTYPER	485
GPIOC_PUPDR	486
GPIOC_SECCFGR	490
GPIOH_AFRL	495
GPIOH_BRR	495
GPIOH_BSRR	493
GPIOH_IDR	492
GPIOH_LCKR	494
GPIOH_MODER	490
GPIOH_ODR	493
GPIOH_OSPEEDR	491
GPIOH_OTYPER	491
GPIOH_PUPDR	492
GPIOH_SECCFGR	496
GTZC1_MPCBB_CFGLOCK	161
GTZC1_MPCBB_CR	160
GTZC1_MPCBB_PRIVCFGGRn	162
GTZC1_MPCBB_SECCFGRn	161
GTZC1_TZIC_FCR1	153
GTZC1_TZIC_FCR2	154
GTZC1_TZIC_FCR3	155
GTZC1_TZIC_FCR4	157
GTZC1_TZIC_IER1	142
GTZC1_TZIC_IER2	143
GTZC1_TZIC_IER3	144
GTZC1_TZIC_IER4	146
GTZC1_TZIC_SR1	147
GTZC1_TZIC_SR2	148
GTZC1_TZIC_SR3	150
GTZC1_TZIC_SR4	151
GTZC1_TZSC_CR	131
GTZC1_TZSC_PRIVCFGGR1	136
GTZC1_TZSC_PRIVCFGGR2	137
GTZC1_TZSC_PRIVCFGGR3	138
GTZC1_TZSC_SECCFGR1	131
GTZC1_TZSC_SECCFGR2	132
GTZC1_TZSC_SECCFGR3	134

H

HASH_CR	847
HASH_CSRx	853

HASH_DIN	848
HASH_HRAx	850
HASH_HRx	851
HASH_IMR	851
HASH_SR	852
HASH_STR	849
HSEM_CR	453
HSEM_ICR	447
HSEM_IER	446
HSEM_ISR	447
HSEM_KEYR	453
HSEM_MISR	448
HSEM_MSISR	451
HSEM_PRIVCFGR	452
HSEM_RLRx	445
HSEM_Rx	443
HSEM_SECCFGR	451
HSEM_SICR	449
HSEM_SIER	449
HSEM_SISR	450

I

I2C_AUTOOCR	1447
I2C_CR1	1434
I2C_CR2	1437
I2C_ICR	1445
I2C_ISR	1442
I2C_OAR1	1439
I2C_OAR2	1439
I2C_PECR	1446
I2C_RXDR	1446
I2C_TIMEOUTR	1441
I2C_TIMINGR	1440
I2C_TXDR	1447
ICACHE_CR	252
ICACHE_CRRx	255
ICACHE_FCR	254
ICACHE_HMONR	255
ICACHE_IER	254
ICACHE_MMONR	255
ICACHE_SR	253
ITM_CIDR0	1776
ITM_CIDR1	1777
ITM_CIDR2	1777
ITM_CIDR3	1778
ITM_DEVARCHR	1773
ITM_DEVTYPE	1773
ITM_PIDR0	1774
ITM_PIDR1	1775
ITM_PIDR2	1775
ITM_PIDR3	1776
ITM_PIDR4	1774
ITM_STIMRx	1770
ITM_TCR	1772
ITM_TER	1771
ITM_TPR	1771
IWDG_EWCR	1273
IWDG_KR	1270
IWDG_PR	1270
IWDG_RLR	1271
IWDG_SR	1271
IWDG_WINR	1273

L

LPTIM_ARR	1251
LPTIM_CCMR1	1254
LPTIM_CCR1	1251
LPTIM_CCR2	1256
LPTIM_CFGR	1247
LPTIM_CFGR2	1252
LPTIM_CNT	1252
LPTIM_CR	1250
LPTIM_RCR	1253
LPTIMx_DIER	1244-1245
LPTIMx_ICR	1241-1242
LPTIMx_ISR	1237, 1239
LPUART_AUTOOCR	1593
LPUART_BRR	1581
LPUART_CR1	1569, 1572
LPUART_CR2	1575
LPUART_CR3	1577, 1579
LPUART_ICR	1590
LPUART_ISR	1582, 1587
LPUART_PRESC	1592
LPUART_RDR	1591
LPUART_RQR	1581
LPUART_TDR	1591

P

PKA_CLRFR	887
PKA_CR	884
PKA_SR	886
PTACONV_ACTCR	270
PTACONV_CR	271
PTACONV_PRICR	270
PWR_CR1	307
PWR_CR2	308
PWR_CR3	309
PWR_DBPR	315
PWR_IORETENRA	322
PWR_IORETENRB	323
PWR_IORETENRC	324

PWR_IORETENRH	325
PWR_IORETRA	322
PWR_IORETRB	323
PWR_IORETRC	324
PWR_IORETRH	325
PWR_PRIVCFGR	317
PWR_RADIOSCR	326
PWR_SECCFGR	316
PWR_SR	318
PWR_SVMCR	310
PWR_SVMSR	319
PWR_VOSR	309
PWR_WUCR1	311
PWR_WUCR2	312
PWR_WUCR3	313
PWR_WUSCR	320
PWR_WUSR	319

R

RAMCFG_M1CR	169
RAMCFG_M1ISR	169
RAMCFG_M2CR	170
RAMCFG_M2ICR	173
RAMCFG_M2IER	171
RAMCFG_M2ISR	172
RAMCFG_M2PEAR	172
RAMCFG_M2WPR1	173
RAMCFG_M2WPR2	174
RAMCFG_MxERKEYR	170
RAMCFG_RAMxIER	175
RCC_AHB1ENR	384
RCC_AHB1RSTR	375
RCC_AHB1SMENR	395
RCC_AHB2ENR	386
RCC_AHB2RSTR	376
RCC_AHB2SMENR	397
RCC_AHB4ENR	388
RCC_AHB4RSTR	378
RCC_AHB4SMENR	400
RCC_AHB5ENR	389
RCC_AHB5RSTR	378
RCC_AHB5SMENR	400
RCC_APB1ENR1	390
RCC_APB1ENR2	391
RCC_APB1RSTR1	379
RCC_APB1RSTR2	380
RCC_APB1SMENR1	401
RCC_APB1SMENR2	403
RCC_APB2ENR	392
RCC_APB2RSTR	381
RCC_APB2SMENR	403
RCC_APB7ENR	394
RCC_APB7RSTR	382
RCC_APB7SMENR	405
RCC_ASARR	424
RCC_ASCAR	425
RCC_ASCNTR	424
RCC_ASCOR	425
RCC_ASCR	422
RCC_ASIER	422
RCC_ASSR	423
RCC_BDCR1	412
RCC_BDCR2	419
RCC_CCIPR1	407
RCC_CCIPR2	410
RCC_CCIPR3	411
RCC_CFGR1	363
RCC_CFGR2	364
RCC_CFGR3	365
RCC_CFGR4	426
RCC_CICR	373
RCC_CIER	370
RCC_CIFR	372
RCC_CR	360
RCC_CSR	417
RCC_ECSCR1	428
RCC_ICSCR3	362
RCC_PLL1CFGR	366
RCC_PLL1DIVR	368
RCC_PLL1FRACR	369
RCC_PRIVCFGR	421
RCC_RADIOENR	427
RCC_SECCFGR	420
RNG_CR	727
RNG_DR	730
RNG_HTCR	732
RNG_NSCR	731
RNG_SR	729
ROM_CIDR0	1748
ROM_CIDR1	1749
ROM_CIDR2	1749
ROM_CIDR3	1750
ROM_MEMTYPER	1745
ROM_PIDR0	1746
ROM_PIDR1	1747
ROM_PIDR2	1747
ROM_PIDR3	1748
ROM_PIDR4	1746
RTC_ALRABINR	1333
RTC_ALRBBINR	1334
RTC_ALRMAR	1324
RTC_ALRMASSR	1326
RTC_ALRMBR	1327

RTC_ALRMBSSR	1328
RTC_CALR	1320
RTC_CR	1312
RTC_DR	1307
RTC_ICSR	1309
RTC_MISR	1330
RTC_PRER	1311
RTC_PRIVCFGR	1316
RTC_SCR	1332
RTC_SECCFGR	1318
RTC_SHIFTR	1321
RTC_SMISR	1331
RTC_SR	1329
RTC_SSR	1308
RTC_TR	1306
RTC_TSDR	1323
RTC_TSSSR	1324
RTC_TSTR	1322
RTC_WPR	1319
RTC_WUTR	1312

S

SAES_CR	819
SAES_DINR	823
SAES_DOUTr	824
SAES_ICR	831
SAES_IER	829
SAES_ISR	830
SAES_IVR0	826
SAES_IVR1	826
SAES_IVR2	826
SAES_IVR3	827
SAES_KEYR0	824
SAES_KEYR1	825
SAES_KEYR2	825
SAES_KEYR3	825
SAES_KEYR4	827
SAES_KEYR5	827
SAES_KEYR6	828
SAES_KEYR7	828
SAES_SR	822
SAES_SUSPxR	828
SAI_ACLRFR	1695
SAI_ACR1	1685
SAI_ACR2	1687
SAI_ADR	1696
SAI_AFRRCR	1689
SAI_AIM	1691
SAI_ASLOTR	1690
SAI_ASr	1693
SAI_BCLRFR	1706

SAI_BCR1	1696
SAI_BCR2	1699
SAI_BDR	1707
SAI_BFRRCR	1701
SAI_BIM	1703
SAI_BSLOTR	1702
SAI_BSR	1704
SAI_PDMCR	1708
SAI_PDMdLY	1709
SPI_AUTOcr	1643
SPI_CFG1	1633
SPI_CFG2	1636
SPI_CR1	1631
SPI_CR2	1633
SPI_CRCPOLY	1644
SPI_IER	1638
SPI_IFCR	1642
SPI_RXCRC	1646
SPI_RXDR	1644
SPI_SR	1639
SPI_TXCRC	1645
SPI_TXDR	1643
SPI_UDRDR	1646
SYSCFG_CCCR	515
SYSCFG_CCCSR	513
SYSCFG_CCVr	514
SYSCFG_CFGR1	506
SYSCFG_CFGR2	511
SYSCFG_CNSLCKr	509
SYSCFG_CSLCKr	510
SYSCFG_FPUIMr	508
SYSCFG_MESr	512
SYSCFG_RSSCMDr	515
SYSCFG_SECCFGR	506
SYSROM_CIDR0	1739
SYSROM_CIDR1	1740
SYSROM_CIDR2	1740
SYSROM_CIDR3	1740
SYSROM_MEMTYPER	1737
SYSROM_PIDR0	1737
SYSROM_PIDR1	1738
SYSROM_PIDR2	1738
SYSROM_PIDR3	1739
SYSROM_PIDR4	1737

T

TAMP_ATCR1	1360
TAMP_ATCR2	1364
TAMP_ATOR	1364
TAMP_ATSEEDr	1363
TAMP_BKPxR	1379

TAMP_COUNT1R	1378	TIM3_CNT	1129
TAMP_CR1	1353	TIMx_AF1	1141, 1205
TAMP_CR2	1355	TIMx_AF2	1142, 1208
TAMP_CR3	1358	TIMx_ARR	1199
TAMP_FLTCR	1359	TIMx_BDTR	1201
TAMP_IER	1369	TIMx_CCER	1128, 1195
TAMP_MISR	1373	TIMx_CCMR1	1120, 1122, 1192-1193
TAMP_PRIVCFGR	1368	TIMx_CCMR2	1124-1125
TAMP_RPFCGR	1378	TIMx_CCR1	1200
TAMP_SCR	1376	TIMx_CNT	1198
TAMP_SECCFGR	1367	TIMx_CR1	1109, 1187
TAMP_SMISR	1374	TIMx_CR2	1110, 1188
TAMP_SR	1371	TIMx_DCR	1143, 1209
TIM1_AF1	1022	TIMx_DIER	1116, 1189
TIM1_AF2	1025	TIMx_DMAR	1144, 1210
TIM1_ARR	1008	TIMx_DTR2	1204
TIM1_BDTR	1012	TIMx_ECR	1139
TIM1_CCER	1003	TIMx_EGR	1119, 1191
TIM1_CCMR1	994, 996	TIMx_OR1	1208
TIM1_CCMR2	999-1000	TIMx_PSC	1130, 1198
TIM1_CCMR3	1018	TIMx_RCR	1199
TIM1_CCR1	1009	TIMx_SMCR	1112
TIM1_CCR2	1009	TIMx_SR	1117, 1190
TIM1_CCR3	1010	TIMx_TISEL	1140, 1205
TIM1_CCR4	1011	TPIU_ACPR	1790
TIM1_CCR5	1016	TPIU_CIDR0	1798
TIM1_CCR6	1017	TPIU_CIDR1	1798
TIM1_CNT	1007	TPIU_CIDR2	1799
TIM1_CR1	980	TPIU_CIDR3	1799
TIM1_CR2	981	TPIU_CLAIMCLR	1793
TIM1_DCR	1027	TPIU_CLAIMSETR	1793
TIM1_DIER	989	TPIU_CSPSR	1790
TIM1_DMAR	1029	TPIU_DEVIDR	1794
TIM1_DTR2	1019	TPIU_DEVTYPE	1795
TIM1_ECR	1020	TPIU_FFCR	1792
TIM1_EGR	993	TPIU_FFSR	1791
TIM1_PSC	1007	TPIU_FSCR	1792
TIM1_RCR	1008	TPIU_PIDR0	1796
TIM1_SMCR	985	TPIU_PIDR1	1796
TIM1_SR	990	TPIU_PIDR2	1797
TIM1_TISEL	1021	TPIU_PIDR3	1797
TIM2_ARR	1131	TPIU_PIDR4	1795
TIM2_CCR1	1133	TPIU_SPPR	1790
TIM2_CCR2	1134	TPIU_SSPSR	1789
TIM2_CCR3	1136	TSC_CR	706
TIM2_CCR4	1138	TSC_ICR	710
TIM2_CNT	1130	TSC_IER	709
TIM3_ARR	1131	TSC_IOASCR	711
TIM3_CCR1	1132	TSC_IOCCR	712
TIM3_CCR2	1133	TSC_IOGCSR	713
TIM3_CCR3	1135	TSC_IOGxCR	713
TIM3_CCR4	1137	TSC_IOHCR	711

TSC_IOSCR .....	712
TSC_ISR .....	710
TZSC_CR .....	141, 159

U

USART_AUTOCR .....	1537
USART_BRR .....	1519
USART_CR1 .....	1501, 1505
USART_CR2 .....	1508
USART_CR3 .....	1512, 1516
USART_GTPR .....	1520
USART_ICR .....	1534
USART_ISR .....	1523, 1529
USART_PRESC .....	1536
USART_RDR .....	1535
USART_RQR .....	1522
USART_RTOR .....	1521
USART_TDR .....	1536

W

WWDG_CFR .....	1281
WWDG_CR .....	1280
WWDG_SR .....	1282

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