22. Comparator (COMP)

Available only on STM32WBA54/55xx devices.

22.1 Introduction

The device embeds two ultra-low-power comparators, COMP1 and COMP2. These comparators can be used for a variety of functions including:

• • Wake-up from low-power mode triggered by an analog signal
• • Analog signal conditioning
• • Cycle-by-cycle current control loop when combined with a PWM output from a timer

22.2 COMP main features

• • Each comparator has configurable plus and minus inputs used for flexible voltage selection:
  • – Multiplexed I/O pins
  • – Internal reference voltage and three submultiple values (1/4, 1/2, 3/4) provided by a scaler (buffered voltage divider)
• • Programmable hysteresis
• • Programmable speed/consumption
• • Outputs that can be redirected to an I/O or to timer inputs for triggering break events for fast PWM shutdowns
• • Comparator outputs with blanking source
• • Comparators that can be combined as a window comparator
• • Interrupt generation capability for each comparator with wake-up from Sleep and Stop modes (through the EXTI controller)

22.3 COMP functional description

22.3.1 COMP block diagram

Figure 100. Comparator block diagrams

22.3.2 COMP pins and internal signals

The I/Os used as comparators inputs must be configured in analog mode in the GPIOs registers.

The comparator output can be connected to the I/Os using the alternate function channel given in “Alternate function mapping” table in the datasheet.

The output can also be internally redirected to a variety of timer input for the following purposes:

• • Emergency shut-down of PWM signals, using BKIN and BKIN2 inputs
• • Cycle-by-cycle current control, using OCREF_CLR inputs
• • Input capture for timing measures

The comparator output can be simultaneously redirected internally and externally.

Table 160. COMP1 noninverting input assignment

Table 161. COMP1 inverting input assignment

Table 162. COMP2 noninverting input assignment

Table 163. COMP2 inverting input assignment

22.3.3 Comparator LOCK mechanism

The comparators can be used for safety purposes, such as over-current or thermal protection. For applications having specific functional safety requirements, the comparator programming must not be altered in case of spurious register access or program counter corruption. For this purpose, the comparator control and status registers can be write-protected (read-only).

Once the programming is completed, the COMPxLOCK bit can be set to 1. This causes the whole COMPx_CSR register to become read-only, including the COMPxLOCK bit.

The write protection can be reset only by an MCU reset.

22.3.4 Window comparator

The purpose of the window comparator is to monitor if the analog voltage is within the range defined by the lower and upper thresholds.

The two embedded comparators can be used to create a window comparator. The monitored analog voltage is connected to the noninverting (plus) inputs of the two comparators. The upper and lower threshold voltages are connected to the inverting (minus) inputs of the comparators.

Two noninverting inputs can be connected internally by enabling the WINMODE bit to save one IO for other purposes.

Figure 101. Window mode

22.3.5 Hysteresis

The comparator includes a programmable hysteresis to avoid spurious output transitions in case of noisy signals. The hysteresis can be disabled if not needed (for instance when exiting a low-power mode), to be able to force the hysteresis value using external components.

Figure 102. Comparator hysteresis

22.3.6 Comparator output-blanking function

The blanking function prevents the current regulation to trip upon short current spikes at the beginning of the PWM period (typically the recovery current in power switches antiparallel diodes). This blanking function consists of a selection of a blanking window that is a timer output compare signal. The selection is done by software (refer to the comparator register description for possible blanking signals).

The complementary of the blanking signal is AND-ed with the comparator output to provide the wanted comparator output (see the example in Figure 103 ).

Figure 103. Comparator output blanking

22.3.7 COMP power and speed modes

COMP1 and COMP2 power consumption versus propagation delay can be adjusted to have the optimum trade-off for a given application.

22.3.8 Scaler function

The scaler block provides the different voltage reference levels to the comparator inputs. This block is based on an amplifier driving a resistor bridge. The amplifier input is connected to the internal voltage reference. The amplifier and the resistor bridge are enabled by setting the INMSEL value in the COMP_CFGRx registers, to connect the corresponding inverting input to the scaler output.

When the divided voltage is not used, the resistor bridge and the amplifier are disabled to reduce power consumption. When the resistor bridge is disconnected, the 1/4 VREF_COMP, 1/2 VREF_COMP, and 3/4 VREF_COMP levels are equal to VREF_COMP.

Figure 104. Scaler

22.4 COMP low-power modes

Table 166. Comparator behavior in the low-power modes

22.5 COMP interrupts

The comparator outputs are internally connected to the extended interrupts and events controller (EXTI). Each comparator has its own EXTI line and can generate either interrupts or events. The same mechanism is used to exit the low-power modes.

Refer to Section 19: Extended interrupts and event controller (EXTI) for more details.

To enable the COMPx interrupt, follow this sequence:

1. 1. Configure and enable the EXTI line corresponding to the COMPx output event in interrupt mode and select the rising, falling or both edges sensitivity.
2. 2. Configure and enable the NVIC IRQ channel mapped to the corresponding EXTI lines.
3. 3. Enable the COMPx.

Table 167. Interrupt control bits

22.6 COMP registers

22.6.1 COMP1 control and status register (COMP1_CSR)

Address offset: 0x00

Reset value: 0x0000 0000

Bit 31 LOCK : COMP1_CSR register lock

This bit is set by software and cleared by reset. It locks the whole content of COMP1_CSR.

0: COMP1_CSR read/write bits can be written by software.

1: COMP1_CSR bits can be read but not written by software.

Bit 30 VALUE : COMP1 output status

This bit is read-only. It reflects the level of the COMP1 output after the polarity selector and blanking (see Figure 103 ).

Bits 29:25 Reserved, must be kept at reset value.

Bits 24:20 BLANKSEL[4:0] : COMP1 blanking source selector

This field is controlled by software (if not locked) and selects the blanking source:

00000: None (no blanking)

xxxx1: tim1_oc5

xxx1x: tim2_oc3

xx1xx: tim3_oc3

Others: Reserved

Bits 19:18 PWRMODE[1:0] : COMP1 power mode selector

Controlled by software (if not locked), selects the power consumption and, as a consequence, the speed of the COMP1.

00: High speed

01: Intermediate speed and power

10: Medium speed and power

11: Ultra-low-power

Bits 17:16 HYST[1:0] : COMP1 hysteresis selector

Controlled by software (if not locked), selects the COMP1 hysteresis.

00: None

01: Low hysteresis

10: Medium hysteresis

11: High hysteresis

Bit 15 POLARITY : COMP1 polarity selector

Controlled by software (if not locked), selects the COMP1 output polarity.

0: Noninverted

1: Inverted

Bit 14 WINOUT : COMP1 output selector

Controlled by software (if not locked), selects the COMP1 output.

0: COMP1_VALUE

1: COMP1_VALUE XOR COMP2_VALUE (required for window mode, see Figure 101 )

Bits 13:12 Reserved, must be kept at reset value.

Bit 11 WINMODE : COMP1 noninverting input selector for window mode

Controlled by software (if not locked), selects the signal for the COMP1_INP input of the COMP1.

0: Signal selected with INPSEL[1:0]

1: COMP2_INP signal of COMP2 (required for window mode, see Figure 101 )

Bits 10:8 INPSEL[2:0] : COMP1 signal selector for noninverting input

Controlled by software (if not locked), selects the signal for the noninverting input COMP1_INP (see Table 160 for the assignment).

Bits 7:4 INMSEL[3:0] : COMP1 signal selector for inverting input INM

Controlled by software (if not locked), selects the signal for the inverting input COMP1_INM (see Table 161 for the assignment).

Bits 3:1 Reserved, must be kept at reset value.

Bit 0 EN : COMP1 enable

Controlled by software (if not locked), enables COMP1.

0: COMP1 disabled

1: COMP1 enabled

22.6.2 COMP2 control and status register (COMP2_CSR)

Address offset: 0x04

Reset value: 0x0000 0000

Bit 31 LOCK : COMP2_CSR register lock

This bit is set by software and cleared by reset. It locks the whole content of COMP2_CSR.

0: COMP2_CSR read/write bits can be written by software.

1: COMP2_CSR bits can be read but not written by software.

Bit 30 VALUE : COMP2 output status

This bit is read-only. It reflects the level of the COMP2 output after the polarity selector and blanking (see Figure 103 ).

Bits 29:25 Reserved, must be kept at reset value.

Bits 24:20 BLANKSEL[4:0] : COMP2 blanking source selector

Controlled by software (if not locked) and selects the blanking source:

00000: None (no blanking)

xxxx1: tim3_oc4

Others: Reserved

Bits 19:18 PWRMODE[1:0] : COMP2 power mode selector

Controlled by software (if not locked), selects the power consumption and, as a consequence, the speed of the COMP2.

00: High speed

01: Intermediate speed and power

10: Medium speed and power

11: Ultra-low-power

Bits 17:16 HYST[1:0] : COMP2 hysteresis selector

Controlled by software (if not locked), selects the COMP2 hysteresis.

00: None

01: Low hysteresis

10: Medium hysteresis

11: High hysteresis

Bit 15 POLARITY : COMP2 polarity selector

Controlled by software (if not locked), selects the COMP2 output polarity.

0: Noninverted

1: Inverted

Bit 14 WINOUT : COMP2 output selector

Controlled by software (if not locked), selects the COMP2 output.

0: COMP2_VALUE

1: COMP1_VALUE XOR COMP2_VALUE (required for window mode, see Figure 101 )

Bits 13:12 Reserved, must be kept at reset value.

Bit 11 WINMODE : COMP2 noninverting input selector for window mode

Controlled by software (if not locked), selects the signal for the COMP2_INP input of the COMP2.

0: Signal selected with INPSEL[1:0]

1: COMP1_INP signal of COMP1 (required for window mode, see Figure 101 )

Bit 10 Reserved, must be kept at reset value.

Bits 9:8 INPSEL[1:0] : COMP2 signal selector for noninverting input

Controlled by software (if not locked), selects the signal for the noninverting input COMP2_INP (see Table 162 for the assignment).

Bits 7:4 INMSEL[3:0] : COMP2 signal selector for inverting input INM

Controlled by software (if not locked), selects the signal for the inverting input COMP2_INM (see Table 163 for the assignment).

Bits 3:1 Reserved, must be kept at reset value.

Bit 0 EN : COMP2 enable

Controlled by software (if not locked), enables COMP2.

0: COMP2 disabled

1: COMP2 enabled

22.6.3 COMP register map

Table 168. COMP register map and reset values

Refer to Section 2.3 for the register boundary addresses.