18. Nested vectored interrupt controller (NVIC)
The NVIC is an Arm Cortex embedded interrupt controller that supports low latency interrupt processing.
18.1 NVIC main features
- • 70 maskable interrupt channels (not including the 16 Cortex-M33 with FPU interrupt lines)
- • 16 programmable priority levels (4 bits of interrupt priority used)
- • Low-latency exception and interrupt handling
- • Power management control
- • Implementation of system control registers
The NVIC and the processor core interface are closely coupled, enabling low-latency interrupt processing and efficient processing of late arriving interrupts.
The NVIC registers are banked across secure and non-secure states.
All interrupts including the core exceptions are managed by the NVIC.
18.2 Interrupt and exception vectors
The grey rows in Table 135 indicate vectors without specific position.
Table 135. Vector table
| Position | Priority | Type of priority | Acronym | Description | Address |
|---|---|---|---|---|---|
| - | - | - | - | Reserved | 0x0000 0000 |
| - | -4 | Fixed | Reset | Reset | 0x0000 0004 |
| -14 | -2 | Fixed | NMI | Non maskable interrupt. - RCC clock security system (HSECSS) - FLASH ECC double error detection - RAMCFG SRAM2 parity error | 0x0000 0008 |
| -13 | -3 | Fixed | Secure HardFault | Secure hard fault when AIRCR.BFHFNMINS = 1 | 0x0000 000C |
| -1 | Fixed | Secure hard fault when AIRCR.BFHFNMINS = 0 | |||
| -1 | Fixed | Non-secure HardFault | Non-secure hard fault. All classes of fault | ||
| -12 | 0 | Settable | MemManage | Memory management | 0x0000 0010 |
| -11 | 1 | Settable | BusFault | Pre-fetch fault, memory access fault | 0x0000 0014 |
| -10 | 2 | Settable | UsageFault | Undefined instruction or illegal state | 0x0000 0018 |
| -9 | 3 | Settable | SecureFault | Secure fault | 0x0000 001C |
Table 135. Vector table (continued)
| Position | Priority | Type of priority | Acronym | Description | Address |
|---|---|---|---|---|---|
| - | - | - | - | Reserved | 0x0000 0020 - 0x0000 0028 |
| -5 | 4 | Settable | SVCall | System service call via SWI instruction | 0x0000 002C |
| -4 | 5 | Settable | Debug monitor | Debug monitor | 0x0000 0030 |
| - | - | - | - | Reserved | 0x0000 0034 |
| -2 | 6 | Settable | PendSV | Pendable request for system service | 0x0000 0038 |
| -1 | 7 | Settable | SysTick | System tick timer | 0x0000 003C |
| 0 | 8 | Settable | WWDG | Window watchdog interrupt | 0x0000 0040 |
| 1 | 9 | Settable | PVD | Power voltage monitor | 0x0000 0044 |
| 2 | 10 | Settable | RTC | RTC non-secure global interrupts | 0x0000 0048 |
| 3 | 11 | Settable | RTC_S (1) | RTC secure global interrupts | 0x0000 004C |
| 4 | 12 | Settable | TAMP | Tamper global interrupts | 0x0000 0050 |
| 5 | 13 | Settable | RAMCFG | RAM configuration global interrupt | 0x0000 0054 |
| 6 | 14 | Settable | FLASH | Flash interface non-secure global interrupt Flash ECC single error correction interrupt | 0x0000 0058 |
| 7 | 15 | Settable | FLASH_S (1) | Flash interface secure global interrupt | 0x0000 005C |
| 8 | 16 | Settable | GTZC_TZIC (1) | GTZC_TZIC global interrupt | 0x0000 0060 |
| 9 | 17 | Settable | RCC | RCC non-secure global interrupt | 0x0000 0064 |
| 10 | 18 | Settable | RCC_S (1) | RCC secure global interrupt | 0x0000 0068 |
| 11 | 19 | Settable | EXTI0 | EXTI line0 interrupt | 0x0000 006C |
| 12 | 20 | Settable | EXTI1 | EXTI line1 interrupt | 0x0000 0070 |
| 13 | 21 | Settable | EXTI2 | EXTI line2 interrupt | 0x0000 0074 |
| 14 | 22 | Settable | EXTI3 | EXTI line3 interrupt | 0x0000 0078 |
| 15 | 23 | Settable | EXTI4 | EXTI line4 interrupt | 0x0000 007C |
| 16 | 24 | Settable | EXTI5 | EXTI line5 interrupt | 0x0000 0080 |
| 17 | 25 | Settable | EXTI6 | EXTI line6 interrupt | 0x0000 0084 |
| 18 | 26 | Settable | EXTI7 | EXTI line7 interrupt | 0x0000 0088 |
| 19 | 27 | Settable | EXTI8 | EXTI line8 interrupt | 0x0000 008C |
| 20 | 28 | Settable | EXTI9 | EXTI line9 interrupt | 0x0000 0090 |
| 21 | 29 | Settable | EXTI10 (1) | EXTI line10 interrupt | 0x0000 0094 |
| 22 | 30 | Settable | EXTI11 (1) | EXTI line11 interrupt | 0x0000 0098 |
| 23 | 31 | Settable | EXTI12 | EXTI line12 interrupt | 0x0000 009C |
| 24 | 32 | Settable | EXTI13 | EXTI line13 interrupt | 0x0000 00A0 |
Table 135. Vector table (continued)
| Position | Priority | Type of priority | Acronym | Description | Address |
|---|---|---|---|---|---|
| 25 | 33 | Settable | EXTI14 | EXTI line14 interrupt | 0x0000 00A4 |
| 26 | 34 | Settable | EXTI15 | EXTI line15 interrupt | 0x0000 00A8 |
| 27 | 35 | Settable | IWDG | Independent watchdog interrupt | 0x0000 00AC |
| 28 | 36 | Settable | SAES (1) | Secure AES interrupt | 0x0000 00B0 |
| 29 | 37 | Settable | GPDMA1_CH0 | GPDMA1 channel 0 global interrupt | 0x0000 00B4 |
| 30 | 38 | Settable | GPDMA1_CH1 | GPDMA1 channel 1 global interrupt | 0x0000 00B8 |
| 31 | 39 | Settable | GPDMA1_CH2 | GPDMA1 channel 2 global interrupt | 0x0000 00BC |
| 32 | 40 | Settable | GPDMA1_CH3 | GPDMA1 channel 3 global interrupt | 0x0000 00C0 |
| 33 | 41 | Settable | GPDMA1_CH4 | GPDMA1 channel 4 global interrupt | 0x0000 00C4 |
| 34 | 42 | Settable | GPDMA1_CH5 | GPDMA1 channel 5 global interrupt | 0x0000 00C8 |
| 35 | 43 | Settable | GPDMA1_CH6 | GPDMA1 channel 6 global interrupt | 0x0000 00CC |
| 36 | 44 | Settable | GPDMA1_CH7 | GPDMA1 channel 7 global interrupt | 0x0000 00D0 |
| 37 | 45 | Settable | TIM1_BRK TIM1_TERR TIM1_ERR | TIM1 break TIM1 transition error TIM1 index error | 0x0000 00D4 |
| 38 | 46 | Settable | TIM1_UP | TIM1 update | 0x0000 00D8 |
| 39 | 47 | Settable | TIM1_TRG_COM TIM1_DIR TIM1_IDX | TIM1 trigger and commutation TIM1 direction change interrupt TIM1 index | 0x0000 00DC |
| 40 | 48 | Settable | TIM1_CC | TIM1 capture compare interrupt | 0x0000 00E0 |
| 41 | 49 | Settable | TIM2 | TIM2 global interrupt | 0x0000 00E4 |
| 42 | 50 | Settable | TIM3 (1) | TIM3 global interrupt | 0x0000 00E8 |
| 43 | 51 | Settable | I2C1_EV (1) | I2C1 event interrupt | 0x0000 00EC |
| 44 | 52 | Settable | I2C1_ER (1) | I2C1 error interrupt | 0x0000 00F0 |
| 45 | 53 | Settable | SPI1 (1) | SPI1 global interrupt | 0x0000 00F4 |
| 46 | 54 | Settable | USART1 | USART1 global interrupt | 0x0000 00F8 |
| 47 | 55 | Settable | USART2 (1) | USART2 global interrupt | 0x0000 00FC |
| 48 | 56 | Settable | LPUART1 | LPUART1 global interrupt | 0x0000 0100 |
| 49 | 57 | Settable | LPTIM1 | LPTIM1 global interrupt | 0x0000 0104 |
| 50 | 58 | Settable | LPTIM2 (1) | LPTIM2 global interrupt | 0x0000 0108 |
| 51 | 59 | Settable | TIM16 | TIM16 global interrupt | 0x0000 010C |
| 52 | 60 | Settable | TIM17 (1) | TIM17 global interrupt | 0x0000 0110 |
| 53 | 61 | Settable | COMP (2) | COMP1/COMP2 interrupt | 0x0000 0114 |
| 54 | 62 | Settable | I2C3_EV | I2C3 event interrupt | 0x0000 0118 |
Table 135. Vector table (continued)
| Position | Priority | Type of priority | Acronym | Description | Address |
|---|---|---|---|---|---|
| 55 | 63 | Settable | I2C3_ER | I2C3 error interrupt | 0x0000 011C |
| 56 | 64 | Settable | SAI1 (2) | SAI1 global interrupt | 0x0000 0120 |
| 57 | 65 | Settable | TSC | TSC global interrupt | 0x0000 0124 |
| 58 | 66 | Settable | AES | AES global interrupt | 0x0000 0128 |
| 59 | 67 | Settable | RNG | RNG global interrupt | 0x0000 012C |
| 60 | 68 | Settable | FPU | Floating point interrupt | 0x0000 0130 |
| 61 | 69 | Settable | HASH | HASH interrupt | 0x0000 0134 |
| 62 | 70 | Settable | PKA | PKA global interrupt | 0x0000 0138 |
| 63 | 71 | Settable | SPI3 | SPI3 global interrupt | 0x0000 013C |
| 64 | 72 | Settable | ICACHE | Instruction cache global interrupt | 0x0000 0140 |
| 65 | 73 | Settable | ADC4 | ADC4 global interrupt | 0x0000 0144 |
| 66 | 74 | Settable | RADIO | 2.4 GHz RADIO global interrupt | 0x0000 0148 |
| 67 | 75 | Settable | WKUP | PWR non-secure global WKUP pin interrupt | 0x0000 014C |
| 68 | 76 | Settable | HSEM | HSEM non-secure interrupt | 0x0000 0150 |
| 69 | 77 | Settable | HSEM_S (1) | HSEM secure interrupt | 0x0000 0154 |
| 70 | 78 | Settable | WKUP_S (1) | PWR secure WKUP pin interrupt | 0x0000 0158 |
| 71 | 79 | Settable | RCC_AUDIO (2) | RCC audio synchronization interrupt | 0x0000 015C |
1. Available only on STM32WBA52/54/55xx devices.
2. Available only on STM32WBA54/55xx devices.