18. Nested vectored interrupt controller (NVIC)

The NVIC is an Arm Cortex embedded interrupt controller that supports low latency interrupt processing.

18.1 NVIC main features

The NVIC and the processor core interface are closely coupled, enabling low-latency interrupt processing and efficient processing of late arriving interrupts.

The NVIC registers are banked across secure and non-secure states.

All interrupts including the core exceptions are managed by the NVIC.

18.2 Interrupt and exception vectors

The grey rows in Table 135 indicate vectors without specific position.

Table 135. Vector table

PositionPriorityType of priorityAcronymDescriptionAddress
----Reserved0x0000 0000
--4FixedResetReset0x0000 0004
-14-2FixedNMINon maskable interrupt.
- RCC clock security system (HSECSS)
- FLASH ECC double error detection
- RAMCFG SRAM2 parity error
0x0000 0008
-13-3FixedSecure HardFaultSecure hard fault when AIRCR.BFHFNMINS = 10x0000 000C
-1FixedSecure hard fault when AIRCR.BFHFNMINS = 0
-1FixedNon-secure HardFaultNon-secure hard fault. All classes of fault
-120SettableMemManageMemory management0x0000 0010
-111SettableBusFaultPre-fetch fault, memory access fault0x0000 0014
-102SettableUsageFaultUndefined instruction or illegal state0x0000 0018
-93SettableSecureFaultSecure fault0x0000 001C

Table 135. Vector table (continued)

PositionPriorityType of priorityAcronymDescriptionAddress
----Reserved0x0000 0020 -
0x0000 0028
-54SettableSVCallSystem service call via SWI instruction0x0000 002C
-45SettableDebug monitorDebug monitor0x0000 0030
----Reserved0x0000 0034
-26SettablePendSVPendable request for system service0x0000 0038
-17SettableSysTickSystem tick timer0x0000 003C
08SettableWWDGWindow watchdog interrupt0x0000 0040
19SettablePVDPower voltage monitor0x0000 0044
210SettableRTCRTC non-secure global interrupts0x0000 0048
311SettableRTC_S (1)RTC secure global interrupts0x0000 004C
412SettableTAMPTamper global interrupts0x0000 0050
513SettableRAMCFGRAM configuration global interrupt0x0000 0054
614SettableFLASHFlash interface non-secure global interrupt
Flash ECC single error correction interrupt
0x0000 0058
715SettableFLASH_S (1)Flash interface secure global interrupt0x0000 005C
816SettableGTZC_TZIC (1)GTZC_TZIC global interrupt0x0000 0060
917SettableRCCRCC non-secure global interrupt0x0000 0064
1018SettableRCC_S (1)RCC secure global interrupt0x0000 0068
1119SettableEXTI0EXTI line0 interrupt0x0000 006C
1220SettableEXTI1EXTI line1 interrupt0x0000 0070
1321SettableEXTI2EXTI line2 interrupt0x0000 0074
1422SettableEXTI3EXTI line3 interrupt0x0000 0078
1523SettableEXTI4EXTI line4 interrupt0x0000 007C
1624SettableEXTI5EXTI line5 interrupt0x0000 0080
1725SettableEXTI6EXTI line6 interrupt0x0000 0084
1826SettableEXTI7EXTI line7 interrupt0x0000 0088
1927SettableEXTI8EXTI line8 interrupt0x0000 008C
2028SettableEXTI9EXTI line9 interrupt0x0000 0090
2129SettableEXTI10 (1)EXTI line10 interrupt0x0000 0094
2230SettableEXTI11 (1)EXTI line11 interrupt0x0000 0098
2331SettableEXTI12EXTI line12 interrupt0x0000 009C
2432SettableEXTI13EXTI line13 interrupt0x0000 00A0

Table 135. Vector table (continued)

PositionPriorityType of priorityAcronymDescriptionAddress
2533SettableEXTI14EXTI line14 interrupt0x0000 00A4
2634SettableEXTI15EXTI line15 interrupt0x0000 00A8
2735SettableIWDGIndependent watchdog interrupt0x0000 00AC
2836SettableSAES (1)Secure AES interrupt0x0000 00B0
2937SettableGPDMA1_CH0GPDMA1 channel 0 global interrupt0x0000 00B4
3038SettableGPDMA1_CH1GPDMA1 channel 1 global interrupt0x0000 00B8
3139SettableGPDMA1_CH2GPDMA1 channel 2 global interrupt0x0000 00BC
3240SettableGPDMA1_CH3GPDMA1 channel 3 global interrupt0x0000 00C0
3341SettableGPDMA1_CH4GPDMA1 channel 4 global interrupt0x0000 00C4
3442SettableGPDMA1_CH5GPDMA1 channel 5 global interrupt0x0000 00C8
3543SettableGPDMA1_CH6GPDMA1 channel 6 global interrupt0x0000 00CC
3644SettableGPDMA1_CH7GPDMA1 channel 7 global interrupt0x0000 00D0
3745SettableTIM1_BRK
TIM1_TERR
TIM1_ERR
TIM1 break
TIM1 transition error
TIM1 index error
0x0000 00D4
3846SettableTIM1_UPTIM1 update0x0000 00D8
3947SettableTIM1_TRG_COM
TIM1_DIR
TIM1_IDX
TIM1 trigger and commutation
TIM1 direction change interrupt
TIM1 index
0x0000 00DC
4048SettableTIM1_CCTIM1 capture compare interrupt0x0000 00E0
4149SettableTIM2TIM2 global interrupt0x0000 00E4
4250SettableTIM3 (1)TIM3 global interrupt0x0000 00E8
4351SettableI2C1_EV (1)I2C1 event interrupt0x0000 00EC
4452SettableI2C1_ER (1)I2C1 error interrupt0x0000 00F0
4553SettableSPI1 (1)SPI1 global interrupt0x0000 00F4
4654SettableUSART1USART1 global interrupt0x0000 00F8
4755SettableUSART2 (1)USART2 global interrupt0x0000 00FC
4856SettableLPUART1LPUART1 global interrupt0x0000 0100
4957SettableLPTIM1LPTIM1 global interrupt0x0000 0104
5058SettableLPTIM2 (1)LPTIM2 global interrupt0x0000 0108
5159SettableTIM16TIM16 global interrupt0x0000 010C
5260SettableTIM17 (1)TIM17 global interrupt0x0000 0110
5361SettableCOMP (2)COMP1/COMP2 interrupt0x0000 0114
5462SettableI2C3_EVI2C3 event interrupt0x0000 0118

Table 135. Vector table (continued)

PositionPriorityType of priorityAcronymDescriptionAddress
5563SettableI2C3_ERI2C3 error interrupt0x0000 011C
5664SettableSAI1 (2)SAI1 global interrupt0x0000 0120
5765SettableTSCTSC global interrupt0x0000 0124
5866SettableAESAES global interrupt0x0000 0128
5967SettableRNGRNG global interrupt0x0000 012C
6068SettableFPUFloating point interrupt0x0000 0130
6169SettableHASHHASH interrupt0x0000 0134
6270SettablePKAPKA global interrupt0x0000 0138
6371SettableSPI3SPI3 global interrupt0x0000 013C
6472SettableICACHEInstruction cache global interrupt0x0000 0140
6573SettableADC4ADC4 global interrupt0x0000 0144
6674SettableRADIO2.4 GHz RADIO global interrupt0x0000 0148
6775SettableWKUPPWR non-secure global WKUP pin interrupt0x0000 014C
6876SettableHSEMHSEM non-secure interrupt0x0000 0150
6977SettableHSEM_S (1)HSEM secure interrupt0x0000 0154
7078SettableWKUP_S (1)PWR secure WKUP pin interrupt0x0000 0158
7179SettableRCC_AUDIO (2)RCC audio synchronization interrupt0x0000 015C

1. Available only on STM32WBA52/54/55xx devices.

2. Available only on STM32WBA54/55xx devices.