16. Peripherals interconnect matrix

16.1 Introduction

Several peripherals have direct connections between them, enabling autonomous communication and/or synchronization between them. This saves CPU resources and, consequently power consumption. In addition, these hardware connections remove software latency and result in more predictable system design.

Depending on peripherals, these interconnections can operate in Run, Sleep, Stop 0, and Stop 1 modes.

16.2 Connection summary

Table 123. Peripherals interconnect matrix ^{(1) (2)}

1. Numbers in this table are links to corresponding subsections of Section 16.3 .

2. The “-” symbol in gray cells means no interconnect.

3. Available only on STM32WBA52/54/55xx devices.

16.3 Interconnection details

16.3.1 Master to slave interconnection for timers

From timer (TIM1/TIM2/TIM3/TIM16/TIM17) to timer (TIM1/TIM2/TIM3).

Purpose

Some timers are linked together internally for timer synchronization or chaining.

When one timer is configured in master mode, it can reset, start, stop or clock the counter of another timer configured in slave mode.

The synchronization modes are detailed in:

• • Section 29.3.30: Timer synchronization for advanced-control timers (TIM1)
• • Section 30.4.23: Timer synchronization and Section 30.4.22: Timers and external trigger synchronization for general-purpose timers (TIM2/TIM3)

Triggering signals

The output from master timer is on signal tim_trgo for TIM1/TIM2/TIM3, and tim_oc for TIM16/TIM17, following a configurable timer event. The input to slave timer is on signals tim_itr.

The possible master/slave connections are given in:

• • Table 259: Internal trigger connection for TIM1
• • Table 283: TIMx internal trigger connection for TIM2/TIM3

Active power mode(s)

Run, Sleep.

16.3.2 Triggers to ADC4

From EXTI and timers (TIM1/TIM2) and (LPTIM1) to ADC4.

Purpose

The timers TIM1/TIM2 can be used to generate the ADC4 trigger event through the timer outputs tim_oc or tim_trgo. Low-power timer LPTIM1 can be used to generate the ADC4 trigger event through output lptim1_ch1. In addition GPIO pin 15 via EXTI channel can be used to generate an ADC4 trigger event.

Triggering signals

The input trigger signal list and the description of the interconnection between ADC4 and timers and EXTI is given in:

• • Table 150: ADC interconnection
• • Section 21.4.16: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) .
• • Section 21.4.21: Example timing diagrams (single/continuous modes hardware/software triggers)

Active power mode(s)

Run, Sleep, and for LPTIM and EXTI also in Stop 0 and Stop 1.

16.3.3 ADC4 analog watchdog as trigger to timer

From ADC4 to TIM1/TIM3.

Purpose

The internal analog watchdog output signals from ADC4 are connected to timers. ADC4 can provide trigger event through watchdog signals to timer (TIM1/TIM3) in order to reset, start, stop or enable the counting.

Settings description of the ADC analog watchdog and timer trigger are provided in:

• • Section 29.3.6: External trigger input for TIM1/TIM3
• • Table 260: Interconnect to the tim_etr input multiplexer for TIM1
• • Table 284: Interconnect to the tim_etr input multiplexer for TIM3

Triggering signals

The output from ADC4 is on signals adc_awd (three watchdogs on ADC4) and the input to timer on signal tim_etr.

Active power mode(s)

Run, Sleep, and an ADC4 conversion in autonomous mode in Stop 0 and Stop 1 can generate a wakeup interrupt and desired trigger action to timers.

16.3.4 Internal clock source to timer

From HSE32, HSI16, LSE, LSI and MCO to timer (TIM1/TIM2/TIM3/TIM16/TIM17) and low power timer (LPTIM1/LPTIM2).

Purpose

A timer input or clock can receive different clock sources and can be used, for example, to calibrate internal oscillators and a reference clock.

External clocks (HSE32, LSE), internal clocks (HSI16, LSI), microcontroller output clock (MCO) can be used as input to timer.

• • HSI16 is assigned to timer (TIM1) as external trigger input signal (tim_etr4). HSI16 can be selected as counter clock provided by an external clock source in mode2: external trigger input. Inputs assignment and clock selection description are detailed in Section 29.3.7: Clock selection .
• • HSI16 and LSE are assigned to timer TIM2/TIM3 as external input signals (tim_etr4/tim_etr11). HSI/LSE can be selected as counter clock provided by an external clock source in mode2: external trigger input. Inputs assignment and clock selection description are detailed in Section 30.4.5: Clock selection .
• • HSE32, HSI16, LSE, and LSI are assigned to general purpose timers TIM16/TIM17 as input multiplexer input signal (tim_ti1_in3/tim_ti1_in5/tim_ti1_in6/tim_ti1_in9). HSI16/LSE/LSI can be selected as counter clock provided by an external clock source in mode1: input multiplexer input. Inputs assignment and clock selection description are detailed in Section 31.3.6: Clock selection .
• • MCO is connected as external input to general-purpose timers TIM16/TIM17, making possible the calibration of the HSI16 system clock with LSE or LSI with HSE system clock. This feature is detailed in Section 31.3.6: Clock selection .
• • LSE and LSI can be selected as input capture 2 (lptim_ic2_mux1/lptim_ic2_mux2) to LPTIM1. This feature is detailed in Section 32.4.18: Input capture mode .
• • HSI16/256 can be selected as input capture 2 (lptim_ic2_mux1) to LPTIM2. This feature is detailed in Section 32.4.18: Input capture mode .

Triggering signals

The input to timer is on signals tim_etr or tim_ti1_in and for low power timer on signals lptim_ic2_mux.

The possible connections are given in:

• • Table 260: Interconnect to the tim_etr input multiplexer for TIM1
• • Table 284: Interconnect to the tim_etr input multiplexer for TIM2/TIM3
• • Table 279: Interconnect to the tim_ti1 input multiplexer for TIM16/TIM17
• • Table 313: LPTIM1/2 input 2 connections for LPTIM1/LPTIM2

Active power mode(s)

Run, Sleep.

16.3.5 Triggers to low-power timer

From RTC wake-up, RTC alarm, TAMP, GPDMA1 and LPTIM_ETR to low power timer (LPTIM1/LPTIM2).

Purpose

Low-power timer counters may be started after the detection of an active edge on a trigger input (lptim_ext_trig0 to 5). This feature is detailed in Section 32.4.7: Trigger multiplexer .

Triggering signals

The input to low power timer on signals lptim_ext_trig.

The possible connections are given in Table 311: LPTIM1/2 external trigger connections .

Active power mode(s)

Run, Sleep, Stop 0, Stop 1.

16.3.6 Internal analog signals to analog peripheral

From internal analog source to analog peripheral (ADC4).

Purpose

The internal reference voltage ( \( V_{REFINT} \) ), the internal temperature sensor ( \( V_{SENSE} \) ) and digital core voltage ( \( V_{CORE} \) ) monitoring signals are connected to analog peripheral (ADC4), as described in:

• • Section 21.4.9: Channel selection (CHSEL, SCANDIR, CHSELRMOD)
• • Section 21.4.27: Temperature sensor and internal reference voltage

Input signals

The input to analog peripheral on signals Vin.

The possible connections are given in Table 150: ADC interconnection .

Active power mode(s)

Run, Sleep, Stop 0, Stop 1.

16.3.7 System errors as break signals to timers

From system errors to timers (TIM1/TIM16/TIM17).

Purpose

HSE32 clock security, CPU lockup, SRAM2 parity error, FLASH ECC double error detection and PVD can generate system errors in the form of timer break toward timers (TIM1/TIM16/TIM17).

The purpose of the break function is to protect power switches driven by PWM signals generated by the timers. This feature is detailed in:

• • Section 29.3.18: Using the break function for TIM1
• • Section 31.3.13: Using the break function for TIM16/TIM17

Break signals

The input to timer on signals tim_sys_brk.

The possible connections are given in:

• • Table 263: System break interconnect for TIM1
• • Table 299: System break interconnect for TIM16/TIM17

Active power mode(s)

Run, Sleep.

16.3.8 Triggers to GPDMA1

From GPIO pin EXTI, RTC, TAMP, timers (TIM2), low-power timer (LPTIM1/LPTIM2), COMP1/COMP2, GPDMA1, ADC4 to GPDMA1.

Purpose

A GPDMA trigger can be assigned to a GPDMA channel x. A programmed GPDMA transfer can be triggered by a rising/falling edge of a selected input trigger event. The trigger mode can also be programmed to condition the linked-list item transfer.

More details are given in:

• • Section 17.3.5: GPDMA triggers
• • Section 17.4.12: GPDMA triggered transfer

Triggering signals

Trigger mapping is specified in Table 129: Programmed GPDMA1 trigger .

Active power mode(s)

Run, Sleep, and for peripherals supporting autonomous mode also in Stop 0 and Stop 1.

16.3.9 Internal tamper sources

From LSE clock security, RTC, Debug, ADC4, AES/SAES, PKA, TRNG and IWDG to TAMP

Purpose

In order to detect any abnormal activity or tentative to corrupt the device, tampers are introduced and alert the system of such undesired events. Different actions can be taken in consequence. More details are given in Section 37: Tamper and backup registers (TAMP) .

Resources

List of tamper sources can be found in Table 344: TAMP interconnection .

Active power mode(s)

These interconnections are active in all power modes if the tamper source is active.

16.3.10 Triggers to communication peripherals

From LP timers (LPTIM1/LPTIM2), comparators (COMP1/COMP2), GPDMA1 transfer complete, EXTI GPIOs, RTC alarm and RTC wakeup to I2C1, I2C3, USART1, USART2, LPUART1, SPI1 and SPI3.

Purpose

LP timer (LPTIM1) output channels (lptim1_ch1 and lptim2_ch1), comparator (COMP1, COMP2) output channels (comp1_out and comp2_out), EXTI GPIOs, RTC alarm and RTC wakeup, can be used as trigger to start a communication on the selected I2C, USART, LPUART and SPI peripheral.

A GPDMA1 transfer complete can trigger both the GPDMA1 regular or linked-list new transfers and communication on selected communication peripheral.

These features are detailed in:

• • Section 38.4.16: Autonomous mode I2C
• • Section 39.5.22: USART autonomous mode USART
• • Section 40.4.15: LPUART autonomous mode LPUART
• • Section 41.4.15: Autonomous mode SPI

Triggering signals

The outputs from triggers are directly connected to peripheral trigger inputs.

The selection of input triggers is detailed in:

• • Table 357: I2C1 interconnection and Table 358: I2C3 interconnection
• • Table 377: USART interconnection (USART1/2)
• • Table 389: LPUART interconnections (LPUART1)
• • Table 399: SPI interconnection (SPI1) and Table 400: SPI interconnection (SPI3)

Active power mode

These interconnections remain active in Run, Sleep and Stop modes if both source and communication line are autonomous under the mode. Refer to:

• • Section 39.6: USART in low-power modes
• • Section 38.5: I2C in low-power modes
• • Section 41.6: SPI in low-power modes

16.3.11 Output from tamper

From TAMP to RTC.

Purpose

The RTC can timestamp a tamper event in order to retrieve history in time of such detection. The RTC can also control RTC_OUT and send tamp status tamp_evt outside the MCU. More details are given in Section 36.3.3: GPIOs controlled by the RTC and TAMP .

Active power mode

This interconnection remain active in all power modes.

16.3.12 Timers generating IRTIM signal

From timer (TIM16/TIM17) to IRTIM.

Purpose

Timers (TIM16/TIM17) output channels timx_oc1 are used to generate the waveform of infrared signal output. The functionality is detailed in Section 33: Infrared interface (IRTIM) .

Active power mode(s)

Run, Sleep.

16.3.13 From encryption keys to AES/SAES

From TAMP backup registers, system Flash memory to and in between SAES and AES.

Purpose

The encryption mechanism requires a hardware key that must be stored in a protected non-volatile memory. Different approaches are implemented in order to load them in a non-readable way. Tamper backup registers or system Flash can be used to store respectively BHK or RHUK, and to implement a dedicated bus to pass it to the SAES. Refer to Section 26.4.14: SAES operation with wrapped keys for more details.

The AES encryption mechanism (faster than the SAES) can benefit from the sharing key of the SAES. Refer to Section 26.4.15: SAES operation with shared keys for more details.

Active power mode

AES and SAES are operational in Run and Sleep modes.

16.3.14 From timer (TIM1/TIM2/TIM3) to comparators (COMP1/COMP2)

Purpose

Advanced-control timer (TIM1) and general-purpose timer (TIM2/TIM3) can be used as blanking window input to COMP1/COMP2.

The blanking function is described in Section 22.3.6: Comparator output-blanking function .

The blanking sources are given in the following registers:

• • COMP1 control and status register (COMP1_CSR) BLANKING
• • COMP2 control and status register (COMP2_CSR) BLANKING

Triggering signals

Timer output signals TIMx_OCx are the inputs to blanking source of COMP1/COMP2.

Active power mode(s)

Run, Sleep.

16.3.15 From comparators (COMP1/COMP2) to timers

From RTC wakeup, RTC alarm and TAMP to timers (TIM1/TIM2/TIM3/TIM16/TIM17) and low power timers (LPTIM1/LPTIM2).

Purpose

Comparators (COMP1/COMP2) output values can be connected to timers TIM1/TIM2/TIM3/TIM16/TIM17 input captures or TIMx_ETR signals.

Comparators (COMP1/COMP2) output values can also generate break input signals for timer TIM1 on input pins TIMx_BKIN or TIMx_BKIN2 through GPIO alternate function selection using open drain connection of I/Os.

Comparators (COMP1/COMP2) output values can be connected to low-power timers LPTIM1/LPTIM2 input, input capture and external trigger signals.

The possible connections are given in:

• • Section 29.3.2: TIM1 pins and internal signals
• • Section 30.4.2: TIM2/TIM3 pins and internal signals
• • Section 31.3.2: TIM16/TIM17 pins and internal signals
• • Section 32.4.2: LPTIM pins and internal signals

Active power mode(s)

Run, Sleep.