15. System configuration controller (SYSCFG)

15.1 SYSCFG main features

The devices feature a set of configuration registers. The main purposes of the system configuration controller are the following:

• • Managing robustness feature
• • Configuring FPU interrupts
• • Enabling/disabling the I ² C fast-mode plus high-drive mode on some I/Os and voltage booster for I/Os analog switches
• • Managing the I/O compensation cell
• • Provides memory erase status
• • Communication channel with the RSS

15.2 SYSCFG functional description

15.2.1 I/O compensation cell management

The I/O compensation cell generates an 8-bit value for the I/O buffer (4 bits for N-MOS and 4 bits for P-MOS), which depends on PVT operating conditions such as process, voltage, and temperature. These bits are used to control the current slew-rate and output impedance in the I/O buffer. A compensation cell is embedded for the I/Os (supplied by V _DD ).

By default the compensation cells are disabled, and a fixed code is applied to all the I/Os.

When enabled, the compensation cell tracks the PVT, and the 8-bit code PCV1 and NCV1 for I/Os supplied by V _DD is available in SYSCFG_CCVR once the RDY1 is set. If the CS1 bit is cleared, the I/O receives the code from SYSCFG_CCVR, resulting from the compensation cell.

To optimize the trimming, the code can be adjusted through SYSCFG_CCCR. A set of bits is available, namely PCC1/NCC1 for the V _DD power rail. It can be selected through CS1 bit in SYSCFG_CCCSR (see Figure 48).

Figure 48. I/O compensation cell block diagram

To reduce the power consumption, it is recommended to copy the code from SYSCFG_CCVR to SYSCFG_CCCR. After the result is ready, set the CS bit and disable the compensation cell.

Table 119. Effect of low-power modes on I/O compensation

15.2.2 SYSCFG TrustZone ^® security and privilege

SYSCFG TrustZone security

When the TrustZone security is activated, the SYSCFG is able to secure registers from being modified by non-secure accesses.

The TrustZone security is activated by the TZEN user option bit in the FLASH_OPTR.

A non-secure read/write access to a secured register is RAZ/WI and generates an illegal access event. An illegal access interrupt is generated if the SYSCFG illegal access event is enabled in the GTZC.

As soon as at least one function is configured to be secured, the SYSCFG reset and clock control bits in the RCC are also secured.

Privileged/unprivileged mode

The SYSCFG registers can be read and written by privileged and unprivileged accesses, except the SYSCFG registers for CPU configuration: SYSCFG_CSLCKR, SYSCFG_FPUIMR and SYSCFG_CNSLCKR registers, and the FPUSEC bit in the SYSCFG_SECCFGR.

An unprivileged access to a privileged register is RAZ/WI.

Table 120 shows the register security overview.

Table 120. TrustZone security and privilege register accesses

Table 120. TrustZone security and privilege register accesses (continued)

1. TrustZone security is activated by the TZEN user option bit in the FLASH_OPTR.

2. Refer to register description for register access.

15.3 SYSCFG registers

15.3.1 SYSCFG secure configuration register (SYSCFG_SECCFGR)

Address offset: 0x000

Reset value: 0x0000 0000

When the system is secure (TZEN = 1), this register provides write access security and can be written only when the access is secure. It can be globally write-protected, or each bit of this register can be individually write-protected. A non-secure write access is WI and generates an illegal access event. There are no read restrictions.

When the system is not secure (TZEN = 0), this register is RAZ/WI.

This register can be read and written by privileged and unprivileged access, except for FPUSEC that can be written only with privileged access.

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 FPUSEC : FPU security

0: SYSCFG_FPUIMR register can be read and written by secure and non-secure access.

1: SYSCFG_FPUIMR register can be read and written by secure access only.

Bit 2 Reserved, must be kept at reset value.

Bit 1 CLASSBSEC : Class B security

0: SYSCFG_CFGR2 register can be read and written by secure and non-secure access.

1: SYSCFG_CFGR2 register can be read and written by secure access only.

Bit 0 SYSCFGSEC : SYSCFG clock control, memory erase status and compensation cell registers security

0: SYSCFG configuration clock in RCC registers, SYSCFG_MESR and SYSCFG_CCCSR, SYSCFG_CCVR and SYSCFG_CCCR can be read and written by secure and non-secure access.

1: SYSCFG configuration clock in RCC registers, SYSCFG_MESR and SYSCFG_CCCSR, SYSCFG_CCVR and SYSCFG_CCCR can be read and written by secure access only.

15.3.2 SYSCFG configuration register 1 (SYSCFG_CFGR1)

Address offset: 0x004

Reset value: 0x0000 0000

When the system is secure (TZEN = 1), this register can be a mix of secure and non-secure bits depending on ADC security configuration bit in GTZC peripheral and the GPIO port pin

security configuration in the GPIO peripheral. A non-secure read/write access on secured bits is RAZ/WI.

When the system is not secure (TZEN = 0), there is no access restriction.

This register can be read and written by privileged and unprivileged access.

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 PB3_FMP: Fast-mode Plus drive capability activation on PB3

This bit can be read and written only with secure access if PB3 is secure in GPIOB. This bit enables the Fast-mode Plus drive mode for PB3 when PB3 is not used by I2C peripheral. This can be used to drive a LED for instance.

Access can be protected by GPIOB SEC3.

0: PB3 pin operates in standard mode when not used by I2C peripheral

1: Fast-mode Plus mode is enabled on PAB3 pin and the GPIO speed control is bypassed.

Bit 18 PA15_FMP: Fast-mode Plus drive capability activation on PA15

This bit can be read and written only with secure access if PA15 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA15 when PA15 is not used by I2C peripheral. This can be used to drive a LED for instance.

Access can be protected by GPIOA SEC15.

0: PA15 pin operates in standard mode when not used by I2C peripheral

1: Fast-mode Plus mode is enabled on PA15 pin and the GPIO speed control is bypassed.

Bit 17 PA7_FMP: Fast-mode Plus drive capability activation on PA7

This bit can be read and written only with secure access if PA7 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA7 when PA7 is not used by I2C peripheral. This can be used to drive a LED for instance.

Access can be protected by GPIOA SEC7.

0: PA7 pin operates in standard mode when not used by I2C peripheral

1: Fast-mode Plus mode is enabled on PA7 pin and the GPIO speed control is bypassed.

Bit 16 PA6_FMP: Fast-mode Plus drive capability activation on PA6

This bit can be read and written only with secure access if PA6 is secure in GPIOA. This bit enables the Fast-mode Plus drive mode for PA6 when PA6 is not used by I2C peripheral. This can be used to drive a LED for instance.

Access can be protected by GPIOA SEC6.

0: PA6 pin operates in standard mode when not used by I2C peripheral

1: Fast-mode Plus mode is enabled on PA6 pin and the GPIO speed control is bypassed.

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 ANASWVDD : GPIO analog switch control voltage selection

Access can be protected by GTZC_TZSC ADC4SEC.

0: I/O analog switches are supplied by \( V_{DDA} \) or booster when booster is ON.

1: I/O analog switches are supplied by \( V_{DD} \) .

Note: Refer to Table 121 for setting.

Bit 8 BOOSTEN : I/O analog switch voltage booster enable

Access can be protected by GTZC_TZSC ADC4SEC.

0: I/O analog switches are supplied by \( V_{DDA} \) voltage.

1: I/O analog switches are supplied by a dedicated voltage booster (supplied by \( V_{DD} \) ).

Note: Refer to Table 121 for setting.

Bits 7:0 Reserved, must be kept at reset value.

Table 121 describes when the BOOSTEN and the ANASWVDD must be set or reset, depending on the voltage settings.

Table 121. BOOSTEN and ANASWVDD set/reset

15.3.3 SYSCFG FPU interrupt mask register (SYSCFG_FPUIMR)

Address offset: 0x008

Reset value: 0x0000 001F

When the system is secure (TZEN = 1), this register can be protected against non-secure access by setting the FPUSEC bit in the SYSCFG_SECCFGR register: a non-secure read/write access is RAZ/WI and generates an illegal access event.

When the system is not secure (TZEN = 0), there is no access restriction.

This register can be read and written by privileged access only. Unprivileged access is RAZ/WI.

Bits 31:6 Reserved, must be kept at reset value.

Bits 5:0 FPU_IE[5:0] : Floating point unit interrupts enable bits
FPU_IE[5]: Inexact interrupt enable (interrupt disable at reset)
FPU_IE[4]: Input abnormal interrupt enable
FPU_IE[3]: Overflow interrupt enable
FPU_IE[2]: Underflow interrupt enable
FPU_IE[1]: Divide-by-zero interrupt enable
FPU_IE[0]: Invalid operation Interrupt enable

15.3.4 SYSCFG CPU non-secure lock register (SYSCFG_CNSLCKR)

Address offset: 0x00C

Reset value: 0x0000 0000

This register is used to lock the configuration of non-secure MPU and VTOR_NS registers. This register can be read and written by privileged access only. Unprivileged access is RAZ/WI.

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 LOCKNSMPU : Non-secure MPU registers lock

This bit is set by software and cleared only by a system reset. When set, this bit disables write access to non-secure MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers.

0: Non-secure MPU registers write enabled

1: Non-secure MPU registers write disabled

Bit 0 LOCKNSVTOR : VTOR_NS register lock

This bit is set by software and cleared only by a system reset.

0: VTOR_NS register write enabled

1: VTOR_NS register write disabled

15.3.5 SYSCFG CPU secure lock register (SYSCFG_CSLCKR)

Address offset: 0x010

Reset value: 0x0000 0000

This register is used to lock the configuration of PRIS and BFHFNMINs bits in the AIRCR register, SAU, secure MPU and VTOR_S registers.

When the system is secure (TZEN = 1), this register can be written only when the access is secure. A non-secure read/write access is RAZ/WI and generates an illegal access event.

When the system is not secure (TZEN = 0), this register is RAZ/WI.

This register can be read and written by privileged access only. Unprivileged access is RAZ/WI.

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 LOCKSAU : SAU registers lock

This bit is set by software and cleared only by a system reset. When set, it disables write access to SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers.

0: SAU registers write enabled

1: SAU registers write disabled

Bit 1 LOCKSMU : Secure MPU registers lock

This bit is set by software and cleared only by a system reset. When set, it disables write access to secure MPU_CTRL, MPU_RNR and MPU_RBAR registers.

0: Secure MPU registers writes enabled

1: Secure MPU registers writes disabled

Bit 0 LOCKSVT AIRCR : VTOR_S register and AIRCR register bits lock

This bit is set by software and cleared only by a system reset. When set, it disables write access to VTOR_S register, PRIS and BFHFNMINs bits in the AIRCR register.

0: VTOR_S register PRIS and BFHFNMINs bits in the AIRCR register write enabled

1: VTOR_S register PRIS and BFHFNMINs bits in the AIRCR register write disabled

15.3.6 SYSCFG configuration register 2 (SYSCFG_CFGR2)

Address offset: 0x014

Reset value: 0x0000 0000

When the system is secure (TZEN = 1), this register can be protected against non-secure access by setting the CLASSBSEC bit in the SYSCFG_SECCFGR register. When CLASSBSEC bit is set, only secure access is allowed: non-secure read/write access is RAZ/WI and generates an illegal access event.

When the system is not secure (TZEN = 0), there is no access restriction.

This register can be read and written by privileged and unprivileged access.

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 ECCL: ECC lock

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the Flash ECC double error signal connection to TIM1/16/17 break input.

0: ECC double error disconnected from TIM1/16/17 break input

1: ECC double error connected to TIM1/16/17 break input

Bit 2 PVDL: PVD lock enable bit

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection to TIM1/16/17 break input, as well as the PVDE and PVDLS[2:0] in the PWR register.

0: PVD interrupt disconnected from TIM1/16/17 break input. PVDE and PVDLS[2:0] bits can be programmed by the application.

1: PVD interrupt connected to TIM1/16/17 break input. PVDE and PVDLS[2:0] bits are read only.

Bit 1 SPL: SRAM2 parity lock bit

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/16/17 break inputs.

0: SRAM2 parity error disconnected from TIM1/16/17 break inputs

1: SRAM2 parity error connected to TIM1/16/17 break inputs

Bit 0 CLL: Cortex-M33 LOCKUP (hardfault) output enable

This bit is set by software and cleared only by a system reset. It can be used to enable and lock the connection of Cortex-M33 LOCKUP (hardfault) output to TIM1/16/17 break input.

0: Cortex-M33 LOCKUP output disconnected from TIM1/16/17 break inputs

1: Cortex-M33 LOCKUP output connected to TIM1/16/17 break inputs

15.3.7 SYSCFG memory erase status register (SYSCFG_MESR)

Address offset: 0x018

Power-on reset value: 0x0000 0000

System reset value: 0x0000 000X (bit MCLR not affected by system reset)

When the system is secure (TZEN = 1), this register can be protected against non-secure access by setting the SYSCFGSEC bit in the SYSCFG_SECCFGR register. When SYSCFGSEC bit is set, only secure access is allowed: non-secure read/write access is RAZ/WI and generates an illegal access event.

When the system is not secure (TZEN = 0), there is no access restriction.

This register can be read and written by privileged and unprivileged access.

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 IPMEE : ICACHE and PKA SRAM erase status

This bit is set by hardware when ICACHE and PKA SRAM erase is completed after potential tamper detection (refer to Section 37: Tamper and backup registers (TAMP) for more details).

This bit is cleared by software by writing 1 to it.

0: ICACHE and PKA SRAM erase ongoing if not yet cleared by software

1: ICACHE and PKA SRAM erase done

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 MCLR : Device memories erase status

This bit is set by hardware when SRAM2, ICACHE, PKA SRAM erase is completed after power-on reset or tamper detection (refer to Section 37: Tamper and backup registers (TAMP) for more details). This bit is not reset by system reset and is cleared by software by writing 1 to it.

0: Memory erase ongoing if not yet cleared by software

1: Memory erase done

15.3.8 SYSCFG compensation cell control/status register (SYSCFG_CCCSR)

Address offset: 0x01C

Reset value: 0x0000 0002

When the system is secure (TZEN = 1), this register can be protected against non-secure access by setting the SYSCFGSEC bit in the SYSCFG_SECCFGR register. When SYSCFGSEC bit is set, only secure access is allowed: non-secure read/write access is RAZ/WI and generates an illegal access event.

When the system is not secure (TZEN = 0), there is no access restriction.

This register can be read and written by privileged and unprivileged access.

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 RDY1 : \( V_{DD} \) I/Os compensation cell ready flag

This bit provides the compensation cell status of the I/Os supplied by \( V_{DD} \) .
0: \( V_{DD} \) I/Os compensation cell not ready
1: \( V_{DD} \) I/Os compensation cell ready

Note: The HSI16 clock is required for the compensation cell to work properly. The compensation cell ready bit (RDY1) is not set if the HSI16 clock is not enabled (HSION).

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 CS1 : \( V_{DD} \) I/Os code selection

This bit selects the code to be applied for the compensation cell of the I/Os supplied by \( V_{DD} \) .
0: \( V_{DD} \) I/Os code from the cell (available in the SYSCFG_CCVR)
1: \( V_{DD} \) I/Os code from the SYSCFG compensation cell code register (SYSCFG_CCCR)

Bit 0 EN1 : \( V_{DD} \) I/Os compensation cell enable

This bit enables the compensation cell of the I/Os supplied by \( V_{DD} \) .
0: \( V_{DD} \) I/Os compensation cell disabled
1: \( V_{DD} \) I/Os compensation cell enabled

15.3.9 SYSCFG compensation cell value register (SYSCFG_CCVR)

Address offset: 0x020

Reset value: 0x0000 0000

When the system is secure (TZEN = 1), this register can be protected against non-secure access by setting the SYSCFGSEC bit in the SYSCFG_SECCFGR register. When SYSCFGSEC bit is set, only secure access is allowed: non-secure read/write access is RAZ/WI and generates an illegal access event.

When the system is not secure (TZEN = 0), there is no access restriction.

This register can be read and written by privileged and unprivileged access.

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 PCV1[3:0] : PMOS compensation value of the I/Os supplied by \( V_{DD} \)

This value is provided by the cell and can be used by the CPU to compute an I/Os compensation cell code for PMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the SYSCFG_CCCSR is reset.

Bits 3:0 NCV1[3:0] : NMOS compensation value of the I/Os supplied by \( V_{DD} \)

This value is provided by the cell and can be used by the CPU to compute an I/Os compensation cell code for NMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the SYSCFG_CCCSR is reset.

15.3.10 SYSCFG compensation cell code register (SYSCFG_CCCR)

Address offset: 0x024

Reset value: 0x0000 0078

When the system is secure (TZEN = 1), this register can be protected against non-secure access by setting the SYSCFGSEC bit in the SYSCFG_SECCFGR register. When SYSCFGSEC bit is set, only secure access is allowed: non-secure read/write access is RAZ/WI and generates an illegal access event.

When the system is not secure (TZEN = 0), there is no access restriction.

This register can be read and written by privileged and unprivileged access.

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 PCC1[3:0] : PMOS compensation code of the I/Os supplied by \( V_{DD} \)

These bits are written by software to define an I/Os compensation cell code for PMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the SYSCFG_CCCSR is set.

Bits 3:0 NCC1[3:0] : NMOS compensation code of the I/Os supplied by \( V_{DD} \)

These bits are written by software to define an I/Os compensation cell code for NMOS transistors. This code is applied to the I/Os compensation cell when the CS1 bit of the SYSCFG_CCCSR is set.

15.3.11 SYSCFG RSS command register (SYSCFG_RSSCMDR)

When the system is secure (TZEN = 1), this register can be read and written only when the access is secure. Otherwise it is RAZ/WI.

When the system is not secure (TZEN = 0), this register is RAZ/WI.

This register can be read and written by privileged and unprivileged access.

Address offset: 0x02C

Power-on reset value: 0x0000 0000

System reset: not affected

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 RSSCMD[15:0] : RSS commands

This field defines a command to be executed by the RSS.

15.3.12 SYSCFG register map

Table 122. SYSCFG register map and reset values