12. Reset and clock control (RCC)

12.1 Introduction

The reset and clock control (RCC) manages the different resets, and generates all clocks for the bus and peripherals.

12.2 RCC pins and internal signals

Table 99 lists the RCC inputs and output signals connected to package pins or balls.

Table 99. RCC input/output signals connected to package pins or balls

12.3 RCC reset functional description

The following types of reset exist:

• • power reset
• • system reset
• • Backup domain reset
• • individual peripheral reset

12.3.1 Power reset

A power reset is generated when one of the following events occurs:

• • a brownout reset (BOR)
• • when exiting Standby modes

A BOR sets all registers to their reset values. Five BOR threshold levels can be selected by user option bytes. The Backup domain is always reset on the \( V_{BOR0} \) threshold, as is the power-on reset.

When exiting Standby mode, all registers in the Core domain are set to their reset value. Registers outside the Core domain (RTC, TAMP, WKUP, IWDG, and Standby modes control) are not impacted.

12.3.2 System reset

A system reset sets all registers to their reset values except the reset flags in RCC control/status register (RCC_CSR) and the registers in the Backup domain.

A system reset is generated when one of the following events occurs:

• • a low level on the NRST pin (external reset)
• • a window watchdog event (WWDG reset)
• • an independent watchdog event (IWDG reset)
• • a software reset (SW reset), see Software reset
• • a low-power mode security reset, see Low-power mode security reset
• • an option byte loader reset, see Option byte loader reset
• • a brownout reset

The reset source can be identified by checking the reset flags in RCC control/status register (RCC_CSR) .

The device internal reset sources (BOR, WWDG, IWDG, ...) act on the NRST pin and this pin is always kept low during the delay phase. The internal reset signal is output on the NRST pin. The pulse generator guarantees a minimum reset pulse duration of \( t_{O(NRST)} \) , see datasheet, for each internal reset source. In case of an external reset, the reset pulse is generated while the NRST pin is asserted low.

In case of an internal reset, the internal pull-up \( R_{PU} \) is deactivated to save the power consumption through the pull-up resistor.

Figure 33. Simplified diagram of the reset circuit

Software reset

The SYSRESETREQ bit in CPU1 Cortex ^® -M33 application interrupt and reset control register must be set to force a software reset on the device.

Low-power mode security reset

To avoid that critical applications mistakenly enter a low-power mode, low-power mode security resets are available. If enabled in option bytes, a reset is generated in any of the following conditions:

• • Entering Stop mode: this type of reset is enabled by resetting nRST_STOP bit in user option bytes. In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering Stop mode.
• • Entering Standby mode: this type of reset is enabled by resetting nRST_STDBY bit in user option bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode.

For further information on the user option bytes, refer to Section 7.4.1: Option bytes description .

Option byte loader reset

The option byte loader reset is generated when the OBL_LAUNCH bit is set in the FLASH_CR register. This bit is used to launch by software the option byte loading.

12.3.3 Backup domain reset

The Backup domain has two specific resets.

A Backup domain reset is generated when one of the following events occurs:

• • a software reset, triggered by setting the BDRST bit in the RCC Backup domain control register (RCC_BDCR1)
• • a V _DD supply BOR0 power-on reset

A Backup domain reset affects only the LSE and LSI oscillators, the RTC, TAMP and the backup registers, and the RCC_BDCRx registers.

12.3.4 Individual peripheral reset

Individual peripherals can be reset by software with their reset register bit in the RCC.

12.3.5 CPU reset

The CPU reset vector is selected via the boot option bytes.

12.4 RCC clocks functional description

The following clock sources can be used to drive the system clock (SYSCLK):

• • HSI16: high-speed internal 16 MHz RC oscillator clock
• • HSE32: high-speed external crystal or clock, 32 MHz
• • PLL1 clocks

The HSI16 is used as system clock source after startup from reset, configured at 16 MHz.

There are additional clock sources:

• • LSI:
  • – LSI1: 32 kHz low-speed low-power internal RC that drives the independent watchdog and optionally the RTC used for auto wake-up from Stop and Standby modes
  • – LSI2: 32 kHz low-speed low drift internal RC that drives optionally the RTC or 2.4 GHz RADIO sleep timer used for auto wake-up from Stop and Standby modes ^(a) .
• • LSE: 32.768 kHz low-speed external crystal or clock that optionally drives the real-time clock (rtc_ck)

Each clock source can be switched on or off independently when it is not used, to optimize power consumption.

The AHB1, AHB2, the APB1, APB2, and APB7 frequencies are derived from the SYSCLK and are provided with several prescalers to configure them. The maximum frequency of these AHB and APB domains is 100 MHz.

The AHB5 frequency is also derived from the SYSCLK and is provided with a prescaler, which enables to configure it. The maximum frequency of this AHB domain is 32 MHz.

Most peripheral kernel clocks are derived from their bus clock (hclk1, hclk5, pclk1, pclk2 or pclk7). In addition, some peripherals receive an independent kernel clock. For these peripherals the kernel clock can be selected by software between several sources, thanks to RCC_CCIPRx registers (x = 1, 2, 3):

• • RNG
• • ADC4
• • U(S)ARTx (x = 1, 2)
• • LPUART1
• • I2Cx (x = 1, 3)
• • SPIx (x = 1, 3)
• • SAI1
• • LPTIMx (x = 1, 2)
• • RTC and TAMP (selected in RCC_BDCR1)
• • IWDG (always LSI)
• • 2.4 GHz RADIO (always HSE32)
• • 2.4 GHz RADIO sleep timer (selected in RCC_BDCR1)

The RCC feeds the CPU system timer (SysTick) clock with the AHB clock (hclk1) divided by 8, or LSE or LSI. The SysTick can work either with this clock or directly with the CPU bus clock (hclk1), configurable in the CPU SysTick control and status register.

FCLK acts as CPU free-running clock.

a. Available only on STM32WBA54/55xx devices.

Figure 34. Clock tree

12.4.1 HSE32 clock with trimming

The HSE32 32 MHz external oscillator has the advantage of producing a very accurate rate on the main clock. The HSE32 furthermore provides on-chip trimming capability in RCC_ECSCR1. The HSE32 must be used for any 2.4 GHz RADIO transmission and reception.

The high-speed external clock signal (HSE32) can be generated from the following clock sources:

• • HSE32 external crystal
• • HSE32 external clock

The clock source must be placed as close as possible to the oscillator pins to minimize output distortion and startup stabilization time.

HSE32 is controlled from the CPU and from the 2.4 GHz RADIO. It can be switched on and off using the HSEON bit in the RCC clock control register (RCC_CR) . HSE32 must be enabled with the HSEON bit when used for the CPU.

The HSERDY flag in the RCC clock control register (RCC_CR) indicates if the HSE32 oscillator is stable and forwarded or not for use by the CPU. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the RCC PLL1 dividers register (RCC_PLL1DIVR) . See data sheet for HSE32 stabilization ready time.

When waking up from a sleep timer event the 2.4 GHz RADIO enables HSE32 autonomously for its own purpose with STRADIOCLKON, independently of the HSEON bit. To use the 2.4 GHz RADIO outside a sleep timer event, software must enable HSE32 with HSEON.

External crystal (HSE32 crystal)

The associated hardware configuration is shown in Figure 35 . Refer to the electrical characteristics section of the datasheet for more details.

Frequency trimming

When using HSE32 with external crystal, the load capacitors are provided by the integrated capacitor banks, these can be trimmed. The HSE32 load capacitor trimming allows a compensation of device manufacturing process variations, used crystal, and PCB design. The HSE32 frequency can be tuned in the application via the RCC_ECSCR1 register.

The HSE32 frequency can be measured by outputting the HSE32 clock on the MCO when in Run or Sleep mode.

External clock (HSE32 external)

The associated hardware configuration is shown in Figure 35 . Refer to the electrical characteristics section of the datasheet for more details.

Figure 35. HSE 32 clock sources

12.4.2 HSI16 clock

The HSI16 clock signal is generated from an internal 16 MHz RC oscillator.

The HSI16 RC oscillator has the advantage of providing a clock source at low cost. It also has a faster startup time than the HSE32 crystal oscillator. However, even with calibration, the frequency is less accurate than an external crystal oscillator.

The HSI16 clock is used as system clock after reset and wake-up from Stop and Standby modes. It can also be used as a backup clock source (auxiliary clock) for the CPU if the HSE32 crystal oscillator fails. Refer to Section 12.4.8 .

The HSIRDY flag in the RCC clock control register (RCC_CR) indicates if the HSI16 RC is stable or not. At startup, the HSI16 RC output clock is not released until this bit is set by hardware.

The HSI16 RC can be switched on and off using the HSION bit in the RCC clock control register (RCC_CR) .

Calibration

The RC oscillator frequencies may vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1 % accuracy at \( T_A = 25^\circ\text{C} \) .

After reset, the factory calibration value is loaded in the HSICAL bits in the RCC internal clock sources calibration register 3 (RCC_ICSCR3) .

If the application is subject to voltage or temperature variations this may affect the RC oscillator speed. The HSI16 frequency can be trimmed in the application using the HSITRIM in the RCC internal clock sources calibration register 3 (RCC_ICSCR3) .

For more details on how to measure the HSI16 frequency variation, refer to Section 12.4.18 .

12.4.3 PLL1

The RCC features one PLL1 that is generally used to provide clocks to the CPU and to some peripherals. The PLL1 must be enabled only in range 1. Before entering range 2 the PLL must be disabled.

The PLL1 integrated into the RCC offers the following features:

• • input frequency range: 4 to 16 MHz
• • VCO frequency range: 128 to 544 MHz
• • capability to work either in integer or fractional mode
• • 13-bit sigma-delta ( \( \Sigma\Delta \) ) modulator, allowing to fine-tune the VCO frequency by steps of 11 to 0.3 ppm
• • the \( \Sigma\Delta \) modulator can be updated on-the-fly, without generating frequency overshoots on PLL1 outputs
• • three outputs with postdividers

The PLL1 is controlled via the registers RCC_PLL1DIVR, RCC_PLL1FRACR, RCC_PLL1CFGR and RCC_CR.

The frequency of the reference clock provided to the PLL1 (ref_ck) must range between 4 and 16 MHz. The user application must program properly the PLL1M dividers in the RCC PLL1 configuration register (RCC_PLL1CFGR) to match this condition. In addition, PLL1RGE must be set according to the reference input frequency to guarantee an optimal performance of the PLL1.

To reduce the power consumption, it is recommended to configure the VCO output to the lowest possible frequency.

PLL1N loop divider must be programmed to achieve the expected frequency at VCO output. In addition, the VCO output range (128 to 544 MHz) must be respected.

The PLL1 operates in integer mode when PLL1FRACEN is 0 and the PLL is enabled with PLL1ON. At any time fractional mode can be enabled by setting PLL1FRACN to the required value and subsequently setting PLLFRACEN from 0 to 1. The \( \Sigma\Delta \) modulator is designed to minimize the jitter impact while allowing very small step frequency adjustments. To update the fractional value, first set PLL1FRACEN to 0 before updating the PLL1FRACN value, and subsequently set PLL1FRACEN to 1. The old PLL1FRACN value is used until the new value is activated by setting PLL1FRACEN from 0 to 1. PLL1FRACN can be updated by software only when PLL1FRACEN is 0.

The PLL1 can be enabled by setting PLL1ON to 1 in the RCC clock control register (RCC_CR) . The PLL1RDY bit indicates that the PLL1 is ready (meaning locked).

Note: Before enabling the PLL1, make sure that the reference frequency (ref_ck) provided to the PLL1 is stable.

The hardware prevents writing PLL1ON to 0 if the PLL1 is currently used to deliver the system clock.

The following PLL1 parameters cannot be changed once the PLL1 is enabled: PLL1M, PLL1SRC, PLL1N, PLL1RGE, PLL1P, PLL1Q, and PLL1R.

To ensure an optimal behavior of the PLL1 when one of the postdividers (PLL1P, PLL1Q, or PLL1R) is not used, the application must set the enable bit (PLL1PEN, PLL1QEN, or PLL1REN), and, preferably, also the corresponding postdivider field (PLL1P, PLL1Q, or PLL1R) to 0.

If the above rules are not respected, the PLL1 output frequency is not guaranteed.

Output frequency computation

When the PLL1 is operated in integer mode, the VCO frequency ( \( F_{VCO} \) ) is given by

When the PLL1 is operated in fractional mode, it is possible to change the value of the PLL1FRACN on-the-fly without disturbing the PLL1 output. This feature can be used either to generate a specific frequency from any crystal value with a good accuracy, or to fine-tune the frequency on-the-fly.

For PLL1, the VCO frequency is given by the following formula:

For both integer and fractional mode, the PLL1 output frequency is given by

The PLL1 is disabled by hardware when:

• • the system enters Stop or Standby mode
• • an HSE32 failure occurs, and PLL1 clocked by HSE32 is used as system clock.

The fractional information used by the PLL is reset when disabling the PLL.

PLL1 initialization phase

Here below the recommended PLL1 initialization sequence in integer and fractional mode (PLL1 is supposed to be disabled at the start of the sequence):

1. 1. Initialize the PLL1 registers according to the required frequency.
   • – For integer mode, set PLL1FRACEN to 0.
   • – For fractional mode, set PLL1FRACN to the required initial value and then set PLL1FRACEN to 1.
2. 2. Once the PLL1ON bit is set to 1, the application must wait till PLL1RDY bit goes to 1. As long as PLL1RDY = 0, the PLL1FRACEN bit must not be altered.
3. 3. When the PLL1RDY bit goes to 1, the PLL1 is ready to be used.
4. 4. If the application intends to tune the PLL1 frequency on-the-fly.
   1. a) PLL1FRACEN must be set to 0. This allows to update the PLL1FRACN value while keeping the PLL running.
   2. b) A new value can be uploaded into PLL1FRACN.
   3. c) PLL1FRACEN must be set to 1 to activate the new programmed value in PLL1FRACN and to have it taken into account by the PLL.

Note: When the PLL1RDY goes to 1, it means that the difference between the PLL1 output frequency and the target value is lower than \( \pm 2\% \) .

12.4.4 LSE clock

The LSE crystal is a 32.768 kHz low-speed external crystal or ceramic resonator. It has the advantage of providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar, the 2.4 GHz RADIO sleep timer or other timing functions.

The LSE crystal is switched on and off using the LSEON bit in RCC Backup domain control register (RCC_BDCR1) . If the LSE is used by other peripherals or functions than RTC and TAMP, the LSESYSEN bit must be also be set in the RCC Backup domain control register (RCC_BDCR1) (refer to LSE when used by peripherals other than RTC/TAMP and RCC functions ).

The crystal oscillator driving strength can be changed at runtime using the LSEDRV[1:0] bits to obtain the best compromise between robustness and short start-up time on one side and low-power-consumption on the other side. The LSE drive can be decreased to a lower drive capability when the LSE is ON. However, once LSEDRV is selected, the drive capability cannot be increased if LSEON = 1.

The LSERDY flag in the RCC Backup domain control register (RCC_BDCR1) indicates whether the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the RCC clock interrupt enable register (RCC_CIER) .

In addition, glitches on LSE can be filtered by setting LSEGON. LSEGON must be written when the LSE is disabled (LSEON = 0 and LSERDY = 0).

The LSE oscillator can be trimmed using the LSETRIM trimming bits in RCC Backup domain control register (RCC_BDCR1) . After BOR0 reset and OBL_LAUNCH when SBF is cleared the factory trimmed values are loaded in the LSETRIM bits, which can subsequently be modified by the application software.

External source (LSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. This mode is selected by setting the LSEBYP and LSEON bits in the RCC Backup domain control register (RCC_BDCR1) . The external clock signal (square, sinus, or triangle) with ~50 % duty cycle, must drive the OSC32_IN pin while the OSC32_OUT pin can be used as GPIO (see Figure 36 ).

Figure 36. LSE 32 clock sources

Clock source	Hardware configuration
External clock	Diagram showing the external clock configuration. The OSC_IN pin is connected to an external source, and the OSC_OUT pin is connected to a GPIO pin.
Crystal/ceramic resonators	Diagram showing the crystal/ceramic resonator configuration. The OSC_IN pin is connected to one side of a crystal and a load capacitor (CL1) to ground. The OSC_OUT pin is connected to the other side of the crystal and another load capacitor (CL2) to ground. The load capacitors are labeled 'Load capacitors'.

LSE when used by peripherals other than RTC/TAMP and RCC functions

By default, when enabled by LSEON, the LSE is sent only to RTC and TAMP (assuming that RTCSEL = 01).

If the LSE is needed for other peripherals (such as peripheral clock or trigger source), or if the LSE is used by an RCC function (such as LSCO or MCO), the lsesys clock must be enabled with LSESYSEN according to the sequence below:

1. 1. Wait till LSE clock is ready and LSEON bit is set and LSERDY bit goes to 1 in RCC Backup domain control register (RCC_BDCR1) .
2. 2. Set the LSESYSEN bit in RCC_BDCR1.
3. 3. Wait till LSESYS clock is ready (LSESYSRDY = 1 in RCC_BDCR1).

The LSE power consumption is increased when LSESYSEN = 1.

12.4.5 LSI clock

The low-power clock LSI can be kept running in Stop and Standby modes for the IWDG, RTC, TAMP, and 2.4 GHz RADIO sleep timer. The LSI clock can be generated from two sources:

• • LSI1 RC low-power oscillator
• • LSI2 RC low-drift oscillator ^(a)

a. Available only on STM32WBA54/55xx devices.

Selection between LSI1 or LSI2 is done by the LSI2ON bit. Whenever LSI2 is enabled (LSI2ON =1) and LSI2 is ready (LSY2RDY = 1) the LSI clock is generated by LSI2. Else LSI1 is selected as LSI clock source.

Table 100. LSI clock selection

When the IWDG is started the LSI clock is forced on and cannot be disabled. When both the LSI1 and LSI2 are disabled LSI1 is forced on. When LSI selects LSI2 RC source, the LSI1 RC source can be disabled.

LSI1 low-power

Caution: The LSI1 must not be used for the 2.4 GHz RADIO sleep timer.

The LSI1 RC can be switched on and off using the LSI1ON bit in the RCC Backup domain control register (RCC_BDCR1) .

The LSI1RDY flag in the RCC Backup domain control register (RCC_BDCR1) indicates if the LSI1 oscillator is stable or not. At startup, the clock is not released until this bit goes to 1 by hardware. An interrupt can be generated if enabled in the RCC clock interrupt enable register (RCC_CIER) . After LSI1 ready, there is an additional delay of up to seven clock cycles before clocking the peripheral.

The clock frequency is either ~32 kHz or ~250 Hz, depending on the LSI1PREDIV bit in RCC Backup domain control register (RCC_BDCR1) . Setting this bit results in a lower consumption (refer to the electrical characteristics section of the datasheet for more details).

Note: When the IWDG is enabled or when the RTC or TAMP is clocked by the LSI, the LSI1PREDIV cannot be changed anymore.

LSI2 low-drift ^(a)

The LSI2 RC can be switched on and off using the LSI2ON bit in the RCC Backup domain control register (RCC_BDCR1) .

The LSI2RDY flag in the RCC Backup domain control register (RCC_BDCR1) indicates if the LSI2 oscillator is stable or not. At startup, the clock is not released until this bit goes to 1 by hardware. An interrupt can be generated if enabled in the RCC clock interrupt enable register (RCC_CIER) . After LSI2 ready, there is an additional delay of up to six clock cycles before clocking the peripheral.

a. Available only on STM32WBA54/55xx devices,

The LSI2 makes possible trimming using the LSI2CFG and LSI2MODE in RCC Backup domain control register (RCC_BDCR2) :

• • use LSI2CFG to select the temperature at which the frequency temperature sensitivity is the lowest
• • use LSI2MODE to configure the power consumption versus the accuracy. For best performance nominal power consumption and highest accuracy must be selected.

12.4.6 System clock (SYSCLK) selection

Different clock sources can be used to drive the system clock (SYSCLK):

• • HSI16 oscillator
• • HSE32 oscillator
• • PLL1

The system clock maximum frequency is 100 MHz. After a system reset, the HSI16 oscillator at 16 MHz, is selected as system clock. When a clock source is used directly or through the PLL1 as a system clock, it is not possible to stop it.

A switch from one clock source to another occurs only if the target clock source is ready (for example, clock stable after startup delay or PLL1 locked). If a clock source that is not yet ready is selected, the switch occurs when the clock source becomes ready. Status bits in the RCC clock configuration register 1 (RCC_CFGR1) indicate which clocks are ready, and which one is currently used as a system clock.

Table 101 gives the different bus frequencies depending on the product voltage range.

Table 101. SYSCLK and bus maximum frequency

Note: After reset voltage scaling range 2 is used with SYSCLK at 16 MHz, hclk5 at 8 MHz, and one wait state on FLASH, SRAM1 and SRAM2.

System clock frequency change and hclk5

When increasing the SYSCLK frequency above 32 MHz, the hclk5 division ratio in HPRE5 must be adapted to keep the hclk5 frequency \( \leq 32 \) MHz.

Warning: The AHB5 clock frequency must never exceed 32 MHz. When this is not respected, device operation cannot be guaranteed.

For this purpose HPRE5 must be written by software with the divider value corresponding to the \( f_{PLL1RCLK} \) frequency, before switching the system clock to the PLL1 source in SW. The written HPRE5 value is used by the hardware to divide the SYSCLK, at the same time as the SYSCLK clock switch to the PLL1 source.

1. 1. Lock PLL1 with pll1rclk at required frequency
2. 2. Optional: select PLL1RCLKPRE to divide
3. 3. Set HPRE5 value to be used with \( f_{PLL1RCLK} \) frequency
4. 4. Switch SYSCLK source to pll1rclk in SW
5. 5. Wait for SYSCLK switch to be completed in SWS ( \( hclk5 = f_{PLL1RCLK} / HPRE5 \) )

When decreasing the SYSCLK frequency from a frequency above 32 MHz from PLL1 source to the HSE32 or HSE16 source, the hclk5 is set to not divided by hardware.

1. 6. Switch SYSCLK source away from PLL1
2. 7. Wait for SYSCLK switch to be completed in SWS (SYSCLK = HSI16 or HSE32, \( hclk5 = SYSCLK / HDIV5 \) )

The HPRE5 value written by software takes effect only when the SYSCLK has been switched to PLL1 in SWS.

When SW = PLL1 and SWS = not PLL1, writes to HPRE5 are ignored.

Note: The HPRE5 divider is not used when SYSCLK source is HSE32, HSE32 divided by 2 or HSI16 (SWS = not PLL1).

In range 2 the hclk5 frequency must be kept \( \leq 8 \) MHz. Before entering in range 2 HDIV5 must select divide by 2.

When going from range 1 to range 2:

1. 1. Set HDIV5 to divide by 2
2. 2. Switch SYSCLK source to HSE32 divided by 2 or HSI16
3. 3. Wait for SYSCLK switch to be completed in SWS
4. 4. Select range 2 in VOS in PWR_VOSR.
5. 5. Optionally, wait until the ACTVOS in PWR_SVMSR = VOS in PWR_VOSR and ACTVOSRDY flag is set in PWR_SVMSR.

When going from range 2 to range 1:

1. 1. Select range 1 in VOS in PWR_VOSR
2. 2. Wait until VOSRDY flag is set in PWR_VOSR
3. 3. Optionally clear HDIV5 to no longer divide by 2

Note: When entering in Stop 1 mode hardware set hclk5 frequency to divider by 2 in HDIV5.

Note: The HDIV5 divider is not used when SYSCLK source is PLL1 (SWS = PLL1).

Note: When 2.4 GHz RADIO is active, the device must be in range 1 and hclk5 must be \( \geq 16 \) MHz and HDIV5 must be cleared.

12.4.7 Clock source frequency versus voltage scaling

Table 102. Clock source maximum frequency

12.4.8 HSE32 clock security system (HSECSS)

The HSECSS can be activated by software with the HSECSSON. In this case, the clock detector is enabled after the HSE32 oscillator wake-up time and disabled when this oscillator is stopped.

Thanks to the HSECSS it is possible to detect the absence of a clock. See device datasheet for more information.

If a failure is detected on the HSE32 clock, the HSE32 oscillator is automatically disabled. A clock failure event is sent to some timers break input and an interrupt is generated to inform the software about the failure (clock security system interrupt HSECSSI). This allows the MCU to perform rescue operations. The HSECSSI is linked to the CPU1 Cortex ^® -M33 NMI (non-maskable interrupt) exception vector.

Once the HSECSS is enabled and if the HSE32 clock fails, the HSECSSI occurs and an NMI is automatically generated. The NMI is executed indefinitely unless the HSECSSI pending bit is cleared. As a consequence, in the NMI ISR, the user must clear the HSECSSI by setting the HSECSSC bit in the RCC clock interrupt clear register (RCC_CICR) .

If the HSE32 oscillator is used directly or indirectly as the system clock (indirectly means: it is used as PLL1 input clock and the PLL1 clock is used as system clock), a detected failure causes a switch of the system clock to the HSI16 oscillator and the disabling of the HSE32 oscillator. If the HSE32 clock (divided or not) is the clock entry of the PLL1 used as system clock when the failure occurs, the PLL1 is disabled too.

12.4.9 LSE clock security system on (LSECSS)

A clock security system on LSE can be activated by software writing the LSECSSON bit in the RCC Backup domain control register (RCC_BDCR1) . This bit can be disabled only by a hardware reset or RTC software reset, or after a failure detection on LSE. LSECSSON must be written after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after the RTC clock has been selected by RTCSEL.

The LSECSS is working in all modes, also under system reset (excluding power-on reset and BDRST).

The clock security system on LSE detects when the LSE disappears or in case of over frequency. In addition, the glitches on LSE can be filtered by setting LSEGON. LSEGON must be written when LSE is disabled (LSEON = 0 and LSERDY = 0).

If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied and no hardware action is made to register settings.

In case of an LSECSS detection event (LSECSSD = 1 in the RCC_BDCR1), the software must disable the LSECSSON bit, stop the defective 32 kHz oscillator (disabling LSEON), change the low-power clock source (no clock or LSI or HSE32), or take any required action to secure the application.

The LSECSS detection event is connected to the internal tamper 3 of the TAMP peripheral. The internal tamper 3 must be enabled (ITAMP3E = 1 in TAMP_CR1 register) and the associated interrupt enabled (ITAMP3IE in TAMP_IER) to enable wake up from the low-power modes.

An LSECSS detection event erases also the TAMP backup registers and backup SRAM unless ITAMP3POM = 1 in TAMP_CR3, see Section 37: Tamper and backup registers (TAMP) for more details.

Refer to the datasheet for LSECSS electrical characteristics.

12.4.10 ADC kernel clock

The ADC kernel clock source is selected thanks to ADCSEL in the RCC peripherals independent clock configuration register 3 (RCC_CCIPR3) .

If the application requires that the ADC is precisely triggered by a (LP)TIM without any uncertainty, the hclk must be selected as ADC kernel clock source. The other clock sources are asynchronous to (LP)TIM therefore an uncertainty of the trigger instant is added by the resynchronization between the two clock domains.

12.4.11 RTC and TAMP kernel clock

The RTC kernel clock source is used by RTC and TAMP and can be either the HSE32 / 32, LSE or LSI clock. It is selected by programming the RTCSEL bits in the RCC Backup domain control register (RCC_BDCR1) . This selection cannot be modified without resetting the Backup domain. For a proper RTC operation, the RTC bus clock pclk must always be configured so as to get a greater or equal frequency compared to the RTC kernel clock.

The TAMP does not require any kernel clock if only the backup registers are used, with tamper in edge detection mode. All other tamper detection modes require a kernel clock (refer to Section 37: Tamper and backup registers (TAMP) for more details).

The LSE and the LSI clocks are in the Backup domain, whereas the HSE32 clock is not. Consequently:

• • If LSE or LSI is selected as RTC or TAMP clock, these peripherals continue to work in Stop and Standby modes, provided the V _DD supply is maintained.
• • If the HSE32 clock is used as the RTC or TAMP clock, these peripherals work only in Run and Sleep modes. They stop working in Stop and Standby modes. Depending on the TAMP configuration, they can remain functional if used in a mode that does not need a kernel clock.

When the RTC and TAMP clock is LSE or LSI, the RTC and TAMP remain clocked and functional under system reset.

If the LSE is needed only for the RTC or TAMP, LSESYSEN must be kept at reset value to get the lowest consumption.

12.4.12 2.4 GHz RADIO bus clocks

The 2.4 GHz RADIO bus clock can be enabled by software with RADIOEN and RADIOSMEN bits, and by hardware on a sleep timer wake-up event by STRADIOCLKON. Before accessing the 2.4 GHz RADIO sleep timer registers the bus clock must be ready, indicated by RADIOCLKRDY register bit.

Table 103. 2.4 GHz RADIO bus clock control

1. When 2.4 GHz RADIO state is ACTIVE or STRADIOCLKON is 1, the device does not enter Stop 1 or Standby modes.

2. When 2.4 GHz RADIO state is SLEEP, the device does not enter Standby mode.

When exiting from low-power mode and the 2.4 GHz RADIO bus clock has been stopped, the RADIOCLKRDY must be rechecked before accessing the 2.4 GHz RADIO registers.

The 2.4 GHz RADIO bus clock is kept active only in low-power modes, when STRADIOCLKON is set and/or RADIOEN and RADIOSMEN are set and the 2.4 GHz RADIO is active.

12.4.13 2.4 GHz RADIO kernel clocks

The 2.4 GHz RADIO has different kernel clocks

• • The baseband kernel clock
• • The sleep timer low power clock

The 2.4 GHz RADIO baseband kernel clock is enabled by register bit BBCLKEN. This clock has the HSE32 as clock source. For this purpose, the HSE32 oscillator is enabled by hardware on a 2.4 GHz RADIO sleep timer wake-up event setting the STRADIOCLKON register bit or by software setting HSEON register bit. When the 2.4 GHz RADIO no longer needs the HSE32 and bus clocks, software must clear the BBCLKEN, STRADIOCLKON and if HSE32 is not used by any other function the HSEON bits.

Figure 37. Radio control

When in range 2 the 2.4 GHz RADIO baseband kernel clock is divided by 4 by hardware. The 2.4 GHz RADIO baseband kernel clock need to be enabled to access the 2.4 GHz RADIO RXTX RAM or sequence RAM.

Also the 2.4 GHz RADIO bus clock (hclk5) is enabled by hardware via the STRADIOCLKON, independent from RADIOEN and RADIOSMEN bits. When the 2.4 GHz RADIO no longer needs its bus clock, software must clear the STRADIOCLKON bit. The STRADIOCLKON bit also keeps the 2.4 GHz RADIO bus clock and baseband kernel clock active when entering low power modes.

Outside any scheduled radio activity, when in Run mode, software can enable the 2.4 GHz RADIO bus clock by the RADIOEN and RADIOSMEN register bits. In this case, the RADIOSMEN allows to keep the 2.4 GHz RADIO bus clock and baseband kernel clock active when entering low power modes.

The 2.4 GHz RADIO sleep timer kernel clock source can be either the HSE32 / 1000, LSE or LSI clock. LSI must be used only when its source is LSI2. It is selected by programming the RADIOSTSEL bits in the RCC Backup domain control register (RCC_BDCR1) .

12.4.14 Timer kernel clock

The timer (TIM) kernel clock frequency is derived from the bus clock pclk. The frequency is automatically defined by hardware:

• • if the APB prescaler equals 1, the timer clock frequencies are set to the APB domain frequency (kernel clock frequency = pclk frequency)
• • otherwise, they are set to twice ( \( \times 2 \) ) the APB domain frequency (kernel clock frequency = \( 2 \times \) pclk frequency)

12.4.15 Independent watchdog kernel clock

The independent watchdog uses the LSI as kernel clock.

If the independent watchdog (IWDG) is started by either user option or software and the LSI clock is disabled (LSI1ON and LSI2ON are cleared to 0), the LSI1 oscillator is forced on. After the LSI oscillator ready delay, the LSI clock is provided to the IWDG.

12.4.16 SysTick calibration value register

The Cortex-M33 with TrustZone security extension embeds two SysTick timers.

When TrustZone is activated, the following SysTick timers are available:

• • SysTick, secure instance

• • SysTick, non-secure instance

When TrustZone is disabled, only one SysTick timer is available.

The Cortex-M33 SysTick timer calibration value (STCALIB) is 0x3E8. It gives a reference time base of 1 ms based on a SysTick clock frequency of 1 MHz. To match the 1 ms time base for an application running at a given frequency, the SysTick reload value must be programmed as follows in the Cortex-M33 SYST_RVR register:

• • When SysTick clock source is CPU clock hclk1
  reload value = ( \( f_{HCLK1} \times STCALIB \) ) - 1
• • When SysTick clock source is external clock (hclk1 divided by 8)
  reload value = ( \( (f_{HCLK1}/8) \times STCALIB \) ) - 1

Example: SysTick clock source is CPU clock hclk1 of 100 MHz, to match a 1 ms time base:

SysTick reload value = (100 x STCALIB) - 1 = 0x1869F

Note: When using debug Stop mode (DBG_STOP), before the CPU enters SleepDeep, it is good practice to disable the SysTick by software.

12.4.17 Clock-out capability

• MCO

The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin. One of the following clock signals can be selected as MCO clock.

• – active in Run, Sleep and Stop modes
  • - LSI
  • - LSE
  • - HSI16 (in Stop modes only when an autonomous peripheral kernel clock request is active)
  • - HSE32 (in Stop modes only when the 2.4 GHz RADIO kernel clock request is active)
  • - SYSCLKpre (in Stop modes when an autonomous peripheral, other than 2.4 GHz RADIO, kernel clock request is active)
  • - hclk5 (when enabled by RCC_AHB5CR.RADIOEN, and in Stop modes when the 2.4 GHz RADIO kernel clock request is active)
• – active only in Run and Sleep modes
  • - pll1pclk
  • - pll1qclk
  • - pll1rclk

The selection is controlled by the MCOSEL bits in the RCC clock configuration register 1 (RCC_CFGR1) . The selected clock can be divided with the MCOPRE field in the RCC clock configuration register 1 (RCC_CFGR1) . The MCO clock output requires the corresponding GPIO pin alternate function to select MCO.

• LSCO

Slow clock output (LSCO) allows one of the low-speed clocks to be output onto the external LSCO pin:

• – LSI
• – LSE

This output remains available in all Run, Sleep, Stop and Standby modes. The selection is controlled by the LSCOSEL bit and enabled with the LSCOEN in the RCC Backup domain control register (RCC_BDCR1) .

12.4.18 Internal/external clock measurement

The HSI16 and LSI frequency can indirectly be measured by mean of the TIM16 or TIM17 channel 1 input capture and LPTIM1 or LPTIM2 channel 2 input capture.

HSI16 calibration using LSE

The primary purpose of connecting the LSE to the channel 1 input capture of TIM16 and TIM17 and to the channel 2 input capture of LPTIM1, is to be able to precisely measure the HSI16 frequency. When using TIM16 or TIM17 for this purpose the HSI16 must be used as system clock source.

The number of HSI16 clock counts between two edges of the LSE signal provides a measure of the internal clock period. Taking advantage of the high precision of LSE crystal (typically a few hundred ppm), the internal clock frequency can be determined with the similar resolution depending on the measurement time. The HSI16 can be trimmed to compensate the process, temperature and/or voltage related frequency deviations.

The basic concept consists in providing a relative measurement (such as the HSI16/LSE ratio). The precision is therefore closely related to the ratio between the two clock sources, the higher the ratio, the better the measurement.

The HSI16 oscillator has dedicated user-accessible calibration bits (HSITRIM) for this purpose.

HSI16 calibration using HSE32

The HSE32 must be used as system clock and the timer input capture must be connected to HSI16/256. TIM16 and 17 channel 1 input capture, as well and the LPTIM2 input capture 2, are connected to the divided oscillator only when TIMICSEL is different from 0b0xx in the RCC peripherals independent clock configuration register 1 (RCC_CCIPR1) .

LSI calibration using HSE32

The calibration of the LSI follows the same principle as the HSI16 calibration, but changing the reference clock. The LSI clock must be connected to the channel 1 input capture of the TIM16 or TIM17, or to the channel 2 input capture of the LPTIM1. Then defining the HSE32 as system clock source. The number of HSE32 clock counts between edges of the LSI signal, provides a measure of the internal low-speed clock period.

The basic concept consists in providing a relative measurement (such as the HSE32/LSI ratio). The precision is therefore closely related to the ratio between the two clock sources, the higher the ratio, the better the measurement.

12.4.19 Audio synchronization

The audio synchronization system provides capture compare information between the Bluetooth® LE radio packet timing and audio clock.

• • 20-bit programmable free-running up-counter
• • Auto-reload
• • Clock prescaler
• • Compare
• • Input capture
• • Capture period
• • Interrupt:
  • – Input capture
  • – Compare
  • – Compare error

Before enabling the audio synchronization counter the auto-reload, clock prescaler, and capture prescaler must be provided.

• • The clock prescaler is used to provide a lower speed clock to the counter.
• • The auto-reload is used to define the audio synchronization counter period.
• • The capture prescaler is used to define the capture period. The capture period is a multiple of the audio synchronization counter period.

A capture value of the counter and the capture prescaler value are updated on the first audio synchronization trigger event in the capture period. Any subsequent audio trigger synchronization event during this capture period is discarded. When enabled, an associated capture event interrupt can be generated.

After enabling the audio synchronization counter in CEN, the capture prescaler starts counting the capture period only after having received a first synchronization from a Bluetooth® LE radio packet.

A capture error flag is set when no audio trigger synchronization event occurs during the capture period. When enabled, an associated capture error interrupt event can be generated.

The compare can be used to generate an interrupt when the counter reaches the compare value.

Figure 38. Audio synchronization counter block diagram

How to use the audio synchronization counter

In the example below the following parameters have been used:

• • auto-reload = R (counter period)
• • capture prescaler = TP (capture period)
• • compare = C

Figure 39. Audio synchronization timing example

The capture value is updated only the first audiosync_itr event in the capture period. In the first capture period counter value N and capture prescaler value 0 are captured. The capture period counting is only started after the very first audiosync_itr event after enabling the audio synchronization counter with ENC. The other audiosync_itr events during this capture period are discarded. In the next capture period counter value M and capture prescaler value 0 are captured.

The counter drift (in ppm) is calculated by software: \( Drift = 10^6 \times (N - M) / (R \times TP) \)

The trigger event may be delayed due to missing receive packets at the 2.4 GHz radio. This delay has to be compensated for in the calculation.

Error handling

When no audiosync_itr event has been received during the capture period, a capture error interrupt is generated when enabled.

Audio synchronization associated functionality

The audiosync_ker_ck is gated with the audio synchronization counter enable bit CEN.

The audiosync_itr must be connected to NVIC71.

12.4.20 Peripherals clock gating and autonomous mode

Peripherals clock gating in Run mode

Each peripheral clock can be enabled by the corresponding EN bit in the RCC_AHBxENR and RCC_APBxENR registers.

When the peripheral clock is not active, read or write accesses to the peripheral registers are not supported.

The enable bit has a synchronization mechanism to create a glitch-free clock for the peripheral. After the enable bit is set, the clock is active after two cycles of the peripheral bus clock.

Caution: Just after enabling the peripheral clock, the software must wait for these two clock cycles before accessing the peripheral registers.

Peripherals clock gating in Sleep and Stop modes

When a peripheral is enabled in RCC_AHBxENR or RCC_APBxENR registers, its bus and kernel clocks can be automatically gated off when the device is in Sleep and Stop modes, by clearing the peripheral SMEN bit in the RCC_AHBxSMENR or RCC_APBxSMENR registers. Both peripheralEN and peripheralSMEN bit of the peripheral must be set to keep the peripheral bus and kernel clocks on in Sleep and Stop modes. In Stop modes, the peripheral bus and kernel clocks are further more active only upon the peripheral clock requests. Except for the 2.4 GHz RADIO, which requests its bus clock independently from the setting in the RADIOEN and RADIOSMEN register bits.

For the 2.4 GHz RADIO the bus clock runs only in Sleep and Stop modes when the STRADIOCLKON is set, or when the 2.4 GHz RADIO is active and RADIOEN and RADIOSMEN are set.

Caution: All peripherals on the same bus, with the SMEN bit set, get a clock when an autonomous peripheral on the same bus requests its clock. Peripherals that are not supposed to be clocked in Stop mode must have their SMEN bit cleared.

Caution: The SMEN bit must be set to allow the generation of an interrupt capable to wake up the device from Sleep and Stop mode. This is not necessary when the peripheral wake-up interrupt is generated though the EXTI (GPIO, COMP and PVD).

Peripherals clock gating and autonomous mode in Stop 0/1 modes

Some peripherals support autonomous mode (refer to Table 104: Autonomous peripherals ). They are able to generate a kernel clock request and a AHB/APB bus clock request when they need, in order to operate and update their status register even in Stop mode. Depending upon the configuration, either a DMA request or an interrupt can be associated to the peripheral event.

When the system enters low-power mode (Stop and Standby) and an autonomous peripheral bus clock request is active or upon an autonomous peripheral bus clock request during Stop mode, Stop 0 mode is entered and the HSI16 oscillator is kept active or woken up and selected as SYSCLK and the bus clocks for all peripherals, with their clock enabled in peripheralEN and peripheralSMEN, are activated.

Note: As soon as the CPU enters Sleepdeep, the system enter Stop mode and the autonomous mode operation peripheral bus clock and SYSCLK is switched to HSI16 at 16 MHz. If autonomous peripheral operation with higher bus clock frequencies is needed, the CPU must enter Sleep and keep the system in Run with the configured Run mode SYSCLK clock frequency.

If the autonomous peripheral is configured with DMA requests enabled, a data transfer is performed thanks to the peripheral bus clock. The bus clocks as well as the oscillator (HSI16) are automatically switched off as soon as the transfer is finished, and no other peripheral requests its bus clock.

If the autonomous peripheral is configured with interrupt enabled, the interrupt wakes up the device into Run mode.

The autonomous peripherals are autonomous in Stop 0 with the GPDMA1 and SRAM1, SRAM2 and are autonomous in Stop 1 mode on their kernel clock.

Table 104 shows the list of peripherals with autonomous mode capability.

Table 104. Autonomous peripherals

1. Enabled when both peripheralEN and peripheralSMEN bits of the peripheral are set.

2. Enabled when the 2.4 GHz RADIO bit STRADIOCLKON and BBCLKEN bits are set and the 2.4 GHz RADIO is active. Available only in Stop 0 range 1.

For peripherals the autonomous mode is enabled in Stop 0 and Stop 1 modes if both peripheralEN and peripheralSMEN bits of the peripheral are set.

For the 2.4 GHz RADIO sleep timer it is operational down to standby with retention mode. Waking up from the sleep timer puts the system in Stop 0 mode and enables the 2.4 GHz RADIO bus clock. The 2.4 GHz RADIO active mode is enabled by software when in addition BBCLKEN bit is set, and allows autonomous operation in Stop 0 range 1 mode.

If an autonomous peripheral requests its kernel clock in Stop mode, the internal oscillator (HSI16) is woken up if it was off and the kernel clock is propagated only to the peripheral requesting it and the peripheralEN and peripheralSMEN bits are set. When the peripheral releases its kernel clock request, the HSI16 is switched off if no other peripheral requests it. Only the 2.4 GHz RADIO uses HSE32 as kernel clock which is woken-up if it was off by a 2.4 GHz RADIO each time it is woke-up by the sleep timer.

If an autonomous peripheral requests its bus clock in Stop mode and the peripheral peripheralEN and peripheralSMEN bits are set, the internal oscillator (HSI16) is woken up if it was off and the system clock is propagated to all peripherals on the associated AHB bus configured with both peripheralEN and peripheralSMEN bits set.

Caution: The bus clock propagates to all peripherals (autonomous and non-autonomous) on the same AHB bus with both peripheralEN and peripheralSMEN bits set.

HSI16 can be forced to remain ON in Stop mode, by configuring HSIKERON in the RCC_CR. In this case, the oscillator is propagated only to the peripheral kernel clocks of the enabled autonomous peripherals which select this oscillator as kernel clock. This allows the peripheral baudrates or conversion rates increase, as there is no need to wait for the oscillator wake-up time when the peripheral requests its kernel clock.

The LSE or LSI selected as peripheral kernel clock remains always ON in Stop modes.

12.5 RCC security and privilege functional description

12.5.1 RCC TrustZone® security protection modes

TrustZone security is activated by the TZEN user option bit in the FLASH_OPTR. The RCC is able to secure RCC configuration and status bits from being modified by non-secure accesses.

This is configured through the RCC Backup domain control register (RCC_BDCR1) to prevent non-secure access to read or modify the following features:

• • HSE32, HSECSS, HSI16, LSI, LSE, LSECSS, LSCO, configuration and status bits
• • PLL1, AHB and APB prescalers configuration and status bits
• • system clock (SYSCLK) source clock selection and status bits
• • MCO clock output configuration bits
• • Remove reset flag RMVF configuration

If SPRIV is set in the RCC privilege configuration register (RCC_PRIVCFGR) , the RCC_SECCFGR register can be written only by secure and privileged access. If SPRIV is cleared in RCC_PRIVCFGR, RCC_SECCFGR can be written only by secure access, privileged or unprivileged.

RCC_SECCFGR can be read by secure, non-secure, privileged and unprivileged access.

When a peripheral is configured as secure, its related clock, reset, clock source selection and clock enable during low-power modes control bits, are also secure, see Table 105 .

A peripheral is secure when:

• • For securable peripherals by GTZC-TZSC (TrustZone security controller), by the SEC security bit in the secure configuration registers corresponding to this peripheral.
• • For TrustZone-aware peripherals, a security feature of this peripheral is enabled through its dedicated bits.

Table 105 summarizes the RCC secured bits following the security configuration bit in the RCC_SECCFGR register.

When one security configuration bit is set, some configuration and status bits are secured. The RCC registers may contain secure and non-secure bits:

• • Secured bits: read and write operations are allowed only by a secure access. Non-secure read returns 0 and write accesses are ignored. No illegal access event is generated.
• • Non-secure bits: no restriction. Read and write operations are allowed by both secure and non-secure accesses.
• • A non-secure write access to RCC_SECCFGR is ignored and generates an illegal access event. An illegal access interrupt is generated if the RCC illegal access interrupt is enabled in the GTZC TZIC registers. RCC_SECCFGR can be read by secure or non-secure access.

When the TrustZone security is disabled (TZEN = 0), all registers are non-secure. RCC_SECCFGR write accesses are ignored.

Table 105. RCC security configuration summary

Table 105. RCC security configuration summary (continued)

12.5.2 RCC privilege protection modes

By default, after reset, all RCC registers can be read or written with both privileged and unprivileged access except RCC privilege configuration register (RCC_PRIVCFGR) that can be written only with privileged access. RCC_PRIVCFGR can be read by secure and non secure, privileged and unprivileged access.

The SPRIV bit in RCC_PRIVCFGR can be written only with secure privileged access. This bit configures the privileged access of all RCC secure functions (as defined by RCC Backup domain control register (RCC_BDCR1) or by the GTZC-TZSC for securable peripherals, or by the peripheral itself in case of TrustZone-aware peripherals).

When the SPRIV bit is set in RCC_PRIVCFGR:

• • Writing the RCC secure bits is possible only with privileged access, including RCC_SECCFGR.
• • The RCC secure bits can be read only with privileged access except RCC_SECCFGR and RCC_PRIVCFGR that can be read by privileged or unprivileged access.
• • An unprivileged access to a privileged RCC bit or register is discarded: the bits are read as zero and the write to these bits is ignored (RAZ/WI).

The NSPRIV bit in RCC_PRIVCFGGR can be written with privileged access only, secure or non-secure. This bit configures the privileged access of all RCC non-secure functions (as defined by RCC_SECCFGR, or by the GTZC-TZSC for securable peripherals, or by the peripheral itself in case of TrustZone-aware peripherals).

When the NSPRIV bit is set in RCC_PRIVCFGGR:

• • Writing the RCC non-secure bits is possible only with privileged access.
• • The RCC non-secure bits can be read only with privileged access except RCC_PRIVCFGGR that can be read by privileged or unprivileged access.
• • An unprivileged access to a privileged RCC bit or register is discarded: the bits are read as zero and the write to these bits is ignored (RAZ/WI).

12.6 RCC low-power modes

• • AHB and APB peripheral clocks, including DMA clock, can be disabled by software.
• • Sleep mode stops the CPU hclk1 clock. The memory interface clocks (flash memory, cache and all SRAM interfaces) can be stopped by software during Sleep mode. The AHB to APB bridge clocks are disabled by hardware during Sleep mode when all the clocks of the peripherals connected to them are disabled.
• • Stop modes stop all the clocks in the Core domain and disable the PLL1, HSI16 and HSE32 oscillators. However, HSI16 can be switched on if the peripheral requests it for kernel clock operation purpose, or to generate a wake-up interrupt (see Section 12.4.20 for more details). LSI and LSE can also remain active in Stop modes.
• • Standby mode stop all the clocks in the Core domain and disable the PLL1, HSI16, HSE32 oscillators. LSI and LSE can remain active in Standby modes.

Stopping the system clock in Stop and Standby modes can be overridden for debugging by setting the DBG_STOP, and/or DBG_STANDBY. For more details, refer to Section 43.12.4: Low-power mode emulation .

Note: When using debug Stop mode (DBG_STOP) a SysTick event wakes up the device. It is good practice to disable the SysTick, before the CPU enters SleepDeep.

When entering and exiting Stop modes, the system clock is HSI16, whose user trim is kept.

When leaving the Standby modes, the system clock is HSI16. The user trim is lost.

If a flash memory programming operation is ongoing, Stop and Standby mode entry is delayed until the flash memory interface access is finished. If an access to the APB domain is ongoing, Stop and Standby modes entry is delayed until the APB access is finished. If an autonomous peripheral bus clock request is active, Stop 0 mode is entered. If an other low-power mode (Stop 1 and Standby) is selected in LPMS, entry to the selected low-power mode is delayed until the autonomous peripheral bus clock request is released.

12.7 RCC interrupts

Table 106 summarizes the interrupt sources and the way to control them.

Table 106. Interrupt sources and control

1. The RCC secure interrupt vector is used only when TrustZone is enabled.

2. The LSECSS failure event (LSECSSD) is connected to TAMP internal tamper 3. To get the interrupt associated to this event, the internal tamper 3 must be enabled and the internal tamper 3 interrupt must be enabled. The ITAMP3F, ITAMP3E, ITAMP3IE and CITAMP3F bits are in the TAMP peripheral.

1. 3. It is not possible to mask this interrupt when the security system feature is enabled (HSECSSON = 1).

12.8 RCC registers

12.8.1 RCC clock control register (RCC_CR)

Address offset: 0x000

Reset value: 0x0000 0500

Access: no wait state; word, half-word and byte access

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 PLL1RDY : PLL1 clock ready flag

Set by hardware to indicate that the PLL1 is locked.

Access can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: PLL1 unlocked

1: PLL1 locked (PLL1RDY remains set when PLL1 is selected as sysclk and PLL1 is disabled by HSECSS failure).

Bit 24 PLL1ON : PLL1 enable

Set and cleared by software to enable the main PLL.

Cleared by hardware when entering Stop or Standby modes and when PLL1 on HSE32 is selected as sysclk, on a HSECSS failure.

This bit cannot be reset if the PLL1 clock is used as the system clock.

Access can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: PLL1 off

1: PLL1 on

Bits 23:21 Reserved, must be kept at reset value.

Set and cleared by software to control the division factor of the HSE32 clock for SYSCLK. Access can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
0: HSE32 not divided, SYSCLK = HSE32
1: HSE32 divided, SYSCLK = HSE32/2

Set by software to enable the HSE32 clock security system. When HSECSSON is set, the clock detector is enabled by hardware when the HSE32 oscillator is ready and disabled by hardware if a HSE32 clock failure is detected. This bit is set only and is cleared by reset. Access can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
0: HSE32 clock security system off (clock detector off)
1: HSE32 clock security system on (clock detector on if the HSE32 oscillator is stable, off if not).

Set by hardware to indicate that the HSE32 oscillator is stable. This bit is set both when HSE32 is enabled by software by setting HSEON and when requested as kernel clock by the 2.4 GHz RADIO. Access can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
0: HSE32 oscillator not ready
1: HSE32 oscillator ready to be used by the CPU (HSERDY remains set when HSE32 is disabled by HSECSS failure).

Set and cleared by software. Cleared by hardware to stop the HSE32 clock for the CPU when entering Stop and Standby modes and on a HSECSS failure. When the HSE32 is used as 2.4 GHz RADIO kernel clock, enabled by RADIOEN and RADIOSMEN and the 2.4 GHz RADIO is active, HSEON is not cleared when entering low power mode. In this case, only Stop 0 mode is entered as low power mode. This bit cannot be reset if the HSE32 oscillator is used directly or indirectly as the system clock. Access can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
0: HSE32 oscillator not requested by the CPU.
1: HSE32 oscillator ON

Bits 15:11 Reserved, must be kept at reset value.

Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION.

Access can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: HSI16 oscillator not ready

1: HSI16 oscillator ready

Note: Once the HSION bit is cleared, HSI16RDY goes low after six HSI16 clock cycles.

Set and cleared by software to force HSI16 oscillator on even in Stop modes.

Keeping the HSI16 oscillator on in Stop modes allows the communication speed not to be reduced by the HSI16 oscillator startup time. This bit has no effect on register bit HSION value.

Cleared by hardware when entering Standby modes.

Refer to Peripherals clock gating and autonomous mode for more details.

Access can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect on HSI16 oscillator

1: HSI16 oscillator forced on even in Stop mode

Set and cleared by software.

Cleared by hardware when entering Stop and Standby modes.

Set by hardware to force the HSI16 oscillator on when exiting Stop and Standby modes.

Set by hardware to force the HSI16 oscillator on in case of clock security failure of the HSE32 crystal oscillator.

This bit is set by hardware if the HSI16 is used directly or indirectly as system clock.

Access can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: HSI16 oscillator off

1: HSI16 oscillator on

Bits 7:0 Reserved, must be kept at reset value.

12.8.2 RCC internal clock sources calibration register 3 (RCC_ICSCR3)

Address offset: 0x010

Reset value: 0x0010 0XXX

X is factory-programmed.

Access: no wait state; word, half-word and byte access

Access to this register can be protected by RCC HSISEC and RCC SPRIV or RCC NSPRIV.

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:16 HSITRIM[4:0] : HSI16 clock trimming

These bits provide an additional user-programmable trimming value that is added to the HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI16.

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:0 HSICAL[11:0] : HSI16 clock calibration

These bits are initialized at startup with the factory-programmed HSI16 calibration value. When HSITRIM[4:0] is written, HSICAL[11:0] is updated with the sum of HSITRIM[4:0] and the initial factory trim value.

12.8.3 RCC clock configuration register 1 (RCC_CFGR1)

Address offset: 0x01C

Reset value: 0x0000 0000

Access: 0 ≤ wait state ≤ 2; word, half-word and byte access

One or two wait states are inserted only if the access occurs during clock source switch.

Access to this register can be protected by RCC SYSCLKSEC and RCC SPRIV or RCC NSPRIV.

Bit 31 Reserved, must be kept at reset value.

Bits 30:28 MCOPRE[2:0] : microcontroller clock output prescaler

Set and cleared by software.

It is highly recommended to change this prescaler before MCO output is enabled.

000: MCO divided by 1

001: MCO divided by 2

010: MCO divided by 4

011: MCO divided by 8

100: MCO divided by 16

others: not allowed

Bits 27:24 MCOSSEL[3:0] : microcontroller clock output

Set and cleared by software.

0000: MCO output disabled, no clock on MCO

0001: sysclkpre system clock after PLL1RCLKPRE division selected

0010: reserved

0011: HSI16 clock selected

0100: HSE32 clock selected

0101: pll1rclk clock selected

0110: LSI clock selected

0111: LSE clock selected

1000: pll1pclk clock selected

1001: pll1qclk clock selected

1010: hclk5 clock selected

others: reserved

Note: This clock output may have some truncated cycles at startup or during MCO clock source switching.

Bits 23:4 Reserved, must be kept at reset value.

Bits 3:2 SWS[1:0] : system clock switch status

Set and cleared by hardware to indicate which clock source is used as system clock.

00: HSI16 oscillator used as system clock

01: reserved

10: HSE32 or HSE32/2, as defined by HSEPRE, used as system clock

11: pll1rclk used as system clock

Bits 1:0 SW[1:0] : system clock switch

Set and cleared by software to select system clock source (SYSCLK).

Cleared by hardware when entering Stop and Standby modes

When selecting HSE32 directly or indirectly as system clock and HSE32 oscillator clock security fails, cleared by hardware.

00: HSI16 selected as system clock

01: reserved

10: HSE32 or HSE32/2, as defined by HSEPRE, selected as system clock

11: pll1rclk selected as system clock

12.8.4 RCC clock configuration register 2 (RCC_CFGR2)

Address offset: 0x020

Reset value: 0x0000 0000

Access: word, half-word and byte access

From 0 to 15 wait states are inserted if the access occurs when the APB or AHB prescalers values update is on going.

Access to this register can be protected by RCC PRESCSEC and RCC SPRIV or RCC NSPRIV.

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:8 PPRE2[2:0] : APB2 prescaler

Set and cleared by software to control the division factor of the APB2 clock (pclk2).

0xx: pclk2 = hclk1 not divided

100: pclk2 = hclk1 divided by 2

101: pclk2 = hclk1 divided by 4

110: pclk2 = hclk1 divided by 8

111: pclk2 = hclk1 divided by 16

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 PPRE1[2:0] : APB1 prescaler

Set and cleared by software to control the division factor of the APB1 clock (pclk1).

0xx: pclk1 = hclk1 not divided

100: pclk1 = hclk1 divided by 2

101: pclk1 = hclk1 divided by 4

110: pclk1 = hclk1 divided by 8

111: pclk1 = hclk1 divided by 16

Bit 3 Reserved, must be kept at reset value.

Bits 2:0 HPRE[2:0] : AHB1, AHB2 and AHB4 prescaler

Set and cleared by software to control the division factor of the AHB1, AHB2 and AHB4 clock (hclk1).

Caution: The software must limit the incremental frequency step by setting these bits correctly to ensure that the hclk1 maximum incremental frequency step does not exceed the maximum allowed incremental frequency step (for more details, refer to Table 101 ). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account.

0xx: hclk1 = SYSCLK not divided

100: hclk1 = SYSCLK divided by 2

101: hclk1 = SYSCLK divided by 4

110: hclk1 = SYSCLK divided by 8

111: hclk1 = SYSCLK divided by 16

12.8.5 RCC clock configuration register 3 (RCC_CFGR3)

Address offset: 0x024

Reset value: 0x0000 0000

Access: word, half-word and byte access

From 0 to 15 wait states are inserted if the access occurs when the APB or AHB prescalers values update is on going.

Access to this register can be protected by RCC PRECSEC and RCC SPRIV or RCC NSPRIV.

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:4 PPRE7[2:0] : APB7 prescaler

Set and cleared by software to control the division factor of the APB7 clock (pclck7).

0xx: hclk1 not divided

100: hclk1 divided by 2

101: hclk1 divided by 4

110: hclk1 divided by 8

111: hclk1 divided by 16

Bits 3:0 Reserved, must be kept at reset value.

12.8.6 RCC PLL1 configuration register (RCC_PLL1CFGR)

Address offset: 0x028

Reset value: 0x0000 0000

Access: no wait state; word, half-word and byte access.

Access to this register can be protected by RCC PLL1SEC and RCC SPRIV or RCC NSPRIV.

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 PLL1RCLKPRERDY : pll1rclkpre not divided ready.

Set by hardware after PLL1RCLKPRE has been set from divided to not divide, to indicate that the pll1rclk not divided is available on sysclkpre.

0: pll1rclk divided

1: pll1rclk not divided ready

Bit 21 PLL1RCLKPRESTEP : pll1rclk clock for SYSCLK prescaler division step selection
Set and cleared by software to control the division step of the pll1rclk clock for SYSCLK.

0: pll1rclk 2-step division
1: pll1rclk 3-step division

Bit 20 PLL1RCLKPRE : pll1rclk clock for SYSCLK prescaler division enable
Set and cleared by software to control the division of the pll1rclk clock for SYSCLK.

0: pll1rclk not divided, sysclkpre = pll1rclk
1: pll1rclk divided, sysclkpre = pll1rclk divided

Bit 19 Reserved, must be kept at reset value.

Bit 18 PLL1REN : PLL1 DIVR divider output enable
Set and cleared by software to enable the pll1rclk output of the PLL1. This bit cannot be cleared when pll1rclk is used as system clock as indicated in SWS.

To save power, PLL1REN and PLL1R bits must be set to 0 when the pll1rclk is not used.
0: pll1rclk output disabled
1: pll1rclk output enabled

Bit 17 PLL1QEN : PLL1 DIVQ divider output enable
Set and reset by software to enable the pll1qclk output of the PLL1.

To save power, PLL1QEN and PLL1Q bits must be set to 0 when the pll1qclk is not used.
0: pll1qclk output disabled
1: pll1qclk output enabled

Bit 16 PLL1PEN : PLL1 DIVP divider output enable
Set and reset by software to enable the pll1pclk output of the PLL1.

To save power, PLL1PEN and PLL1P bits must be set to 0 when the pll1pclk is not used.
0: pll1pclk output disabled
1: pll1pclk output enabled

Bits 15:11 Reserved, must be kept at reset value.

Bits 10:8 PLL1M[2:0] : Prescaler for PLL1
Set and cleared by software to configure the prescaler of the PLL1. The VCO1 input frequency is PLL1 input clock frequency/PLL1M.

This field can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).
000: division by 1 (bypass)
001: division by 2
010: division by 3
...
111: division by 8

Bits 7:5 Reserved, must be kept at reset value.

Bit 4 PLL1FRACEN : PLL1 fractional latch enable
Set and reset by software to latch the content of PLL1FRACN into the \( \Sigma\Delta \) modulator. In order to latch the PLL1FRACN value into the \( \Sigma\Delta \) modulator, PLL1FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL1FRACN into the modulator (see PLL1 initialization phase for details).

Bits 3:2 PLL1RGE[1:0] : PLL1 input frequency range
Set and reset by software to select the proper reference frequency range used for PLL1. This field can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).
00-01-10: PLL1 input (ref_ck) clock range frequency between 4 and 8 MHz
11: PLL1 input (ref_ck) clock range frequency between 8 and 16 MHz

Bits 1:0 PLL1SRC[1:0] : PLL1 entry clock source

Set and cleared by software to select PLL1 clock source. This field can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).

Cleared by hardware when entering Stop or Standby modes.

00: no clock sent to PLL1

01: reserved

10: HS116 clock selected as PLL1 clock entry

11: HSE32 clock after HSEPRE divider selected as PLL1 clock entry

Note: In order to save power, when no PLL1 clock is used, the value of PLL1SRC must be 0.

12.8.7 RCC PLL1 dividers register (RCC_PLL1DIVR)

Address offset: 0x034

Reset value: 0x0101 0280

Access: no wait state; word, half-word and byte access.

Access to this register can be protected by RCC PLL1SEC and RCC SPRIV or RCC NSPRIV.

Bit 31 Reserved, must be kept at reset value.

Bits 30:24 PLL1R[6:0] : PLL1 DIVR division factor

Set and reset by software to control the frequency of the pll1rclk clock. Division factors are forbidden if \( VCO\ frequency / (2 \times (TRUNC(division\ factor / 2)) > pll1rclk\ maximum\ frequency \) .

These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).

0000000: pll1rclk = VCO output frequency

0000001: pll1rclk = VCO output frequency / 2 (default after reset)

0000010: pll1rclk = VCO output frequency / 3

0000011: pll1rclk = VCO output frequency / 4

...

1111111: pll1rclk = VCO output frequency / 128

Bit 23 Reserved, must be kept at reset value.

Bits 22:16 PLL1Q[6:0] : PLL1 DIVQ division factor

Set and reset by software to control the frequency of the pll1qclk clock. Division factors are forbidden if \( VCO\ frequency / (2 \times (TRUNC(division\ factor / 2)) > pll1qclk\ maximum\ frequency \) .

These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).

0000000: pll1qclk = VCO output frequency

0000001: pll1qclk = VCO output frequency / 2 (default after reset)

0000010: pll1qclk = VCO output frequency / 3

0000011: pll1qclk = VCO output frequency / 4

...

1111111: pll1qclk = VCO output frequency / 128

Bits 15:9 PLL1P[6:0] : PLL1 DIVP division factor

Set and reset by software to control the frequency of the pll1pclk clock. Division factors are forbidden if \( VCO\ frequency / (2 \times (TRUNC(division\ factor / 2)) > pll1pclk\ maximum\ frequency \) .

These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).

0000000: pll1pclk = VCO output frequency

0000001: pll1pclk = VCO output frequency / 2 (default after reset)

0000010: pll1pclk = VCO output frequency

0000011: pll1pclk = VCO output frequency / 4

...

1111111: pll1pclk = VCO output frequency / 128

Bits 8:0 PLL1N[8:0] : Multiplication factor for PLL1 VCO

Set and reset by software to control the multiplication factor of the VCO.

These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).

0x003: multiplication factor for PLL1 VCO = 4

0x004: multiplication factor for PLL1 VCO = 5

0x005: multiplication factor for PLL1 VCO = 6

...

0x080: multiplication factor for PLL1 VCO = 129 (default after reset)

...

0x1FF: multiplication factor for PLL1 VCO = 512

others: reserved

VCO output frequency = \( F_{ref\_ck} \times \) multiplication factor for PLL1 VCO, when fractional value 0 has been loaded into PLL1FRACN, with:

• – multiplication factor for PLL1 VCO between 4 and 512
• – input frequency \( F_{ref\_ck} \) between 4 and 16 MHz

12.8.8 RCC PLL1 fractional divider register (RCC_PLL1FRACR)

Address offset: 0x038

Reset value: 0x0000 0000

Access: no wait state; word, half-word and byte access.

Access to this register can be protected by RCC PLL1SEC and RCC SPRIV or RCC NSPRIV.

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:3 PLL1FRACN[12:0] : Fractional part of the multiplication factor for PLL1 VCO

Set and reset by software to control the fractional part of the multiplication factor of the VCO.

These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.

VCO output frequency = \( F_{ref\_ck} \times [\text{multiplication factor for PLL1 VCO} + (\text{PLL1FRACN} / 2^{13})] \) , with:

• – Multiplication factor for PLL1 VCO must be between 4 and 512
• – PLL1FRACN can be between 0 and \( 2^{13} - 1 \)
• – The input frequency \( F_{ref\_ck} \) must be between 4 and 16 MHz

To change the used fractional value on-the-fly even if the PLL1 is enabled, the application must proceed as follows:

• – Set the bit PLL1FRACEN to 0
• – Write the new fractional value into PLL1FRACN
• – Set the bit PLL1FRACEN to 1

Bits 2:0 Reserved, must be kept at reset value.

12.8.9 RCC clock interrupt enable register (RCC_CIER)

Address offset: 0x050

Reset value: 0x0000 0000

Access: no wait state; word, half-word and byte access

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 LSI2RDYIE : LSI2 ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the LSI2 oscillator stabilization.

Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LSI2 ready interrupt disabled

1: LSI2 ready interrupt enabled

If the LSI2 is ready (LSI2RDY in RCC_BDCR1 is 1) before enabling LSI2RDYIE, the LSI2RDYF in RCC_CIFR is not set, and no interrupt is generated.

Note that this bit is reserved on STM32WBA50/52xx devices.

Bits 15:7 Reserved, must be kept at reset value.

Set and cleared by software to enable/disable interrupt caused by PLL1 lock.

Access can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: PLL1 lock interrupt disabled

1: PLL1 lock interrupt enabled

If the PLL1 is ready (PLL1RDY in RCC_CR is 1) before enabling PLL1RDYIE, the PLL1RDYF in RCC_CIFR is not set, and no interrupt is generated.

Set and cleared by software to enable/disable interrupt caused by the HSE32 oscillator stabilization.

Access can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: HSE32 ready interrupt disabled

1: HSE32 ready interrupt enabled

If the HSE is ready (HSERDY in RCC_CR is 1) before enabling HSERDYIE, the HSERDYF in RCC_CIFR is not set and no interrupt is generated.

Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization.

Access can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: HSI16 ready interrupt disabled

1: HSI16 ready interrupt enabled

If the HSI16 is ready (HSIRDY in RCC_CR is 1) before enabling HSIRDYIE, the HSIRDYF in RCC_CIFR is not set, and no interrupt is generated.

Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization.

Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LSE ready interrupt disabled

1: LSE ready interrupt enabled

If the LSE is ready (LSERDY in RCC_BDCR1 is 1) before enabling LSERDYIE, the LSERDYF in RCC_CIFR is not set, and no interrupt is generated.

Bit 0 LSI1RDYIE : LSI1 ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the LSI1 oscillator stabilization.

Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LSI1 ready interrupt disabled

1: LSI1 ready interrupt enabled

If the LSI1 is ready (LSI1RDY in RCC_BDCR1 is 1) before enabling LSI1RDYIE, the LSI1RDYF in RCC_CIFR is not set, and no interrupt is generated.

12.8.10 RCC clock interrupt flag register (RCC_CIFR)

Address offset: 0x054

Reset value: 0x0000 0000

Access: no wait state, word; half-word and byte access

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 LSI2RDYF : LSI2 ready interrupt flag

Set by hardware when the LSI2 clock becomes stable and LSI2RDYIE is set.

Cleared by software setting the LSI2RDYC bit.

Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: no clock ready interrupt caused by the LSI2 oscillator

1: clock ready interrupt caused by the LSI2 oscillator

Note that this bit is reserved on STM32WBA50/52xx devices.

Bits 15:11 Reserved, must be kept at reset value.

Bit 10 HSECSSF : HSE32 clock security system interrupt flag

Set by hardware when a clock security failure is detected in the HSE32 oscillator.

Cleared by software setting the HSECSSC bit.

Access can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: no clock security interrupt caused by HSE32 clock failure

1: clock security interrupt caused by HSE32 clock failure

Bits 9:7 Reserved, must be kept at reset value.

Set by hardware when the PLL1 locks and PLL1RDYIE is set.

Cleared by software setting the PLL1RDYC bit.

Access can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: no clock ready interrupt caused by PLL1 lock

1: clock ready interrupt caused by PLL1 lock

Bit 5 Reserved, must be kept at reset value.

Set by hardware when the HSE32 clock becomes stable and HSERDYIE is set.

Cleared by software setting the HSERDYC bit.

Access can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: no clock ready interrupt caused by the HSE32 oscillator

1: clock ready interrupt caused by the HSE32 oscillator

Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see RCC_CR). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.

Access can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

Cleared by software setting the HSIRDYC bit.

0: no clock ready interrupt caused by the HSI16 oscillator

1: clock ready interrupt caused by the HSI16 oscillator

Bit 2 Reserved, must be kept at reset value.

Set by hardware when the LSE clock becomes stable and LSERDYIE is set.

Cleared by software setting the LSERDYC bit.

Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: no clock ready interrupt caused by the LSE oscillator

1: clock ready interrupt caused by the LSE oscillator

Set by hardware when the LSI1 clock becomes stable and LSI1RDYIE is set.

Cleared by software setting the LSI1RDYC bit.

Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: no clock ready interrupt caused by the LSI1 oscillator

1: clock ready interrupt caused by the LSI1 oscillator

12.8.11 RCC clock interrupt clear register (RCC_CICR)

Address offset: 0x058

Reset value: 0x0000 0000

Access: no wait state; word, half-word and byte access

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 LSI2RDYC : LSI2 ready interrupt clear

Writing this bit to 1 clears the LSI2RDYF flag. Writing 0 has no effect.

Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

Note that this bit is reserved on STM32WBA50/52xx devices.

Bits 15:11 Reserved, must be kept at reset value.

Bit 10 HSECSSC : High speed external clock security system interrupt clear

Writing this bit to 1 clears the HSECSSF flag. Writing 0 has no effect.

Access can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

Bits 9:7 Reserved, must be kept at reset value.

Bit 6 PLL1RDYC : PLL1 ready interrupt clear

Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect.

Access can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

Bit 5 Reserved, must be kept at reset value.

Bit 4 HSERDYC : HSE32 ready interrupt clear

Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect.

Access can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

Bit 3 HSIRDYC : HSI16 ready interrupt clear

Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect.

Access can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

Bit 2 Reserved, must be kept at reset value.

Bit 1 LSERDYC : LSE ready interrupt clear

Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect.

Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

Bit 0 LSI1RDYC : LSI1 ready interrupt clear

Writing this bit to 1 clears the LSI1RDYF flag. Writing 0 has no effect.

Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

12.8.12 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)

Address offset: 0x060

Reset value: 0x0000 0000

Access: no wait state; word, half-word and byte access

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 TSCRST : TSC reset

Set and cleared by software.

Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset TSC

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 CCRCRST : CRC reset

Set and cleared by software.

Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset CRC

Bits 11:1 Reserved, must be kept at reset value.

Bit 0 GPDMA1RST : GPDMA1 reset

Set and cleared by software.

Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset GPDMA1

12.8.13 RCC AHB2 peripheral reset register (RCC_AHB2RSTR)

Address offset: 0x064

Reset value: 0x0000 0000

Access: no wait state; word, half-word and byte access

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 PKARST : PKA reset

Set and cleared by software.

Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset PKA

Bit 20 HSEMRST : HSEM reset

Set and cleared by software.

Can only be accessed secure when one or more features in the HSEM is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset HSEM

Set and cleared by software.

Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset SAES

Note that this bit is reserved on STM32WBA50xx devices.

Set and cleared by software.

Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset RNG

Set and cleared by software.

Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset HASH

Set and cleared by software.

Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset AES

Bits 15:8 Reserved, must be kept at reset value.

Set and cleared by software.

Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset IO port H

Bits 6:3 Reserved, must be kept at reset value.

Set and cleared by software.

Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset IO port C

Bit 1 GPIOBRST : IO port B reset

Set and cleared by software.

Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset IO port B

Bit 0 GPIOARST : IO port A reset

Set and cleared by software.

Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset IO port A

12.8.14 RCC AHB4 peripheral reset register (RCC_AHB4RSTR)

Address offset: 0x06C

Reset value: 0x0000 0000

Access: no wait state,; word, half-word and byte access

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 ADC4RST : ADC4 reset

Set and cleared by software.

Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset ADC4 interface

Bits 4:0 Reserved, must be kept at reset value.

12.8.15 RCC AHB5 peripheral reset register (RCC_AHB5RSTR)

Address offset: 0x070

Reset value: 0x0000 0000

Access: no wait state,; word, half-word and byte access

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 PTACONVRST: PTACONV reset

Set and cleared by software.

Access can be secured by GTZC_TZSC PTACONVSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset PTACONV

Bit 1 is reserved on STM32WBA50/52xx devices.

Bit 0 RADIORST: 2.4 GHz RADIO reset

Set and cleared by software.

Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset 2.4 GHz RADIO

12.8.16 RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1)

Address offset: 0x074

Reset value: 0x0000 0000

Access: no wait state, word; half-word and byte access

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 I2C1RST : I2C1 reset

Set and cleared by software.

Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset I2C1

Bit 21 is reserved on STM32WBA50xx devices.

Bits 20:18 Reserved, must be kept at reset value.

Bit 17 USART2RST : USART2 reset

Set and cleared by software.

Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset USART2

Bit 17 is reserved on STM32WBA50xx devices.

Bits 16:2 Reserved, must be kept at reset value.

Bit 1 TIM3RST : TIM3 reset

Set and cleared by software.

Access can be secured by GTZC_TZSC TIM3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset TIM3

Bit 1 is reserved on STM32WBA50xx devices.

Bit 0 TIM2RST : TIM2 reset

Set and cleared by software.

Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset TIM2

12.8.17 RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2)

Address offset: 0x078

Reset value: 0x0000 0000

Access: no wait state; word, half-word and byte access

This register is reserved on STM32WBA50xx devices.

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 LPTIM2RST : LPTIM2 reset

Set and cleared by software.

Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset LPTIM2

Bits 4:0 Reserved, must be kept at reset value.

12.8.18 RCC APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x07C

Reset value: 0x0000 0000

Access: no wait state; word, half-word and byte access

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 SAI1RST : SAI1 reset

Set and cleared by software.

Access can be secured by GTZC_TZSC SAI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset SAI1

Note that this bit is reserved on STM32WBA50/52xx devices.

Bits 20:19 Reserved, must be kept at reset value.

Bit 18 TIM17RST : TIM17 reset

Set and cleared by software.

Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset TIM17

Note that this bit is reserved on STM32WBA50xx devices.

Bit 17 TIM16RST : TIM16 reset

Set and cleared by software.

Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset TIM16

Bits 16:15 Reserved, must be kept at reset value.

Bit 14 USART1RST : USART1 reset

Set and cleared by software.

Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset USART1

Bit 13 Reserved, must be kept at reset value.

Bit 12 SPI1RST : SPI1 reset

Set and cleared by software.

Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset SPI1

Note that this bit is reserved on STM32WBA50xx devices.

Bit 11 TIM1RST : TIM1 reset

Set and cleared by software.

Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset TIM1

Bits 10:0 Reserved, must be kept at reset value.

12.8.19 RCC APB7 peripheral reset register (RCC_APB7RSTR)

Address offset: 0x080

Reset value: 0x0000 0000

Access: no wait state; word, half-word and byte access

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 COMPRST : COMP reset

Set and cleared by software.

Access can be secured by GTZC_TZSC COMPSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset COMP

Note that this bit is reserved on STM32WBA50/52xx devices.

Bits 14:12 Reserved, must be kept at reset value.

Bit 11 LPTIM1RST : LPTIM1 reset

Set and cleared by software.

Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset LPTIM1

Bits 10:8 Reserved, must be kept at reset value.

Bit 7 I2C3RST : I2C3 reset

Set and cleared by software.

Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset I2C3

Bit 6 LPUART1RST : LPUART1 reset

Set and cleared by software.

Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset LPUART1

Bit 5 SPI3RST : SPI3 reset

Set and cleared by software.

Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset SPI3

Bits 4:2 Reserved, must be kept at reset value.

Bit 1 SYSCFGRST : SYSCFG reset

Set and cleared by software.

Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: No effect

1: Reset SYSCFG

Bit 0 Reserved, must be kept at reset value.

12.8.20 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)

Address offset: 0x088

Reset value: 0x8000 0100

Access: no wait state; word, half-word and byte access

Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported.

Bit 31 SRAM1EN : SRAM1 bus clock enable

Set and reset by software.

Access can be secured by GTZC_MPCBB1 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: SRAM1 bus clock disabled

1: SRAM1 bus clock enabled

Bits 30:25 Reserved, must be kept at reset value.

Bit 24 GTZC1EN : GTZC1 bus clock enable

Set and reset by software.

Can only be accessed secure when device is secure (TZEN = 1). When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: GTZC1 bus clock disabled

1: GTZC1 bus clock enabled

Note that this bit is reserved on STM32WBA50xx devices.

Bits 23:18 Reserved, must be kept at reset value.

Bit 17 RAMCFGEN : RAMCFG bus clock enable

Set and cleared by software.

Access can be secured by GTZC_TZSC RAMCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: RAMCFG bus clock disabled

1: RAMCFG bus clock enabled

Bit 16 TSCEN : Touch sensing controller bus clock enable

Set and cleared by software.

Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: TSC bus clock disabled

1: TSC bus clock enabled

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 CRCCEN : CRC bus clock enable

Set and cleared by software.

Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: CRC bus clock disabled

1: CRC bus clock enabled

Bits 11:9 Reserved, must be kept at reset value.

Bit 8 FLASHEN : FLASH bus clock enable

Set and cleared by software. This bit can be disabled only when the flash memory is in power down mode.

Can only be accessed secured when the flash security state is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: FLASH bus clock disabled

1: FLASH bus clock enabled

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 GPDMA1EN : GPDMA1 bus clock enable

Set and cleared by software.

Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: GPDMA1 bus clock disabled

1: GPDMA1 bus clock enabled

12.8.21 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)

Address offset: 0x08C

Reset value: 0x4000 0000

Access: no wait state, word, half-word and byte access

Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported.

Bit 31 Reserved, must be kept at reset value.

Bit 30 SRAM2EN : SRAM2 bus clock enable

Set and cleared by software.

Access can be secured by GTZC_MPCBB2 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: SRAM2 bus clock disabled

1: SRAM2 bus clock enabled

Bits 29:22 Reserved, must be kept at reset value.

Bit 21 PKAEN : PKA bus clock enable

Set and cleared by software.

Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: PKA bus clock disabled

1: PKA bus clock enabled

Set and cleared by software.

Can only be accessed secure when one or more features in the HSEM is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: HSEM bus clock disabled

1: HSEM bus clock enabled

Set and cleared by software.

Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: SAES bus clock disabled

1: SAES bus clock enabled

Note that this bit is reserved on STM32WBA50xx devices.

Set and cleared by software.

Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: RNG bus and kernel clocks disabled

1: RNG bus and kernel clocks enabled

Set and cleared by software.

Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: HASH bus clock disabled

1: HASH bus clock enabled

Set and cleared by software.

Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: AES bus clock disabled

1: AES bus clock enabled

Bits 15:8 Reserved, must be kept at reset value.

Set and cleared by software.

Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: IO port H bus clock disabled

1: IO port H bus clock enabled

Bits 6:3 Reserved, must be kept at reset value.

Bit 2 GPIOCEN : IO port C bus clock enable

Set and cleared by software.

Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: IO port C bus clock disabled

1: IO port C bus clock enabled

Bit 1 GPIOBEN : IO port B bus clock enable

Set and cleared by software.

Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: IO port B bus clock disabled

1: IO port B bus clock enabled

Bit 0 GPIOAEN : IO port A bus clock enable

Set and cleared by software.

Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: IO port A bus clock disabled

1: IO port A bus clock enabled

12.8.22 RCC AHB4 peripheral clock enable register (RCC_AHB4ENR)

Address offset: 0x094

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported.

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 ADC4EN : ADC4 bus and kernel clocks enable

Set and cleared by software.

Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: ADC4 bus and kernel clocks disabled

1: ADC4 bus and kernel clocks enabled

Bits 4:3 Reserved, must be kept at reset value.

Bit 2 PWREN : PWR bus clock enable

Set and cleared by software.

Can only be accessed secure when one or more features in the PWR is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: PWR bus clock disabled

1: PWR bus clock enabled

Bits 1:0 Reserved, must be kept at reset value.

12.8.23 RCC AHB5 peripheral clock enable register (RCC_AHB5ENR)

Address offset: 0x098

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported.

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 PTACONVEN : PTACONV bus clock enable

Set and cleared by software.

Access can be secured by GTZC_TZSC PTACONVSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: PTACONV bus clock disabled

1: PTACONV bus clock enabled

Note that this bit is reserved on STM32WBA50/52xx devices.

Bit 0 RADIOEN : 2.4 GHz RADIO bus clock enable

Set and cleared by software.

Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: 2.4 GHz RADIO bus clock disabled (The 2.4 GHz RADIO bus clock may still be enabled by STRADIOCLKON)

1: 2.4 GHz RADIO bus clock enabled

Note: Before accessing the 2.4 GHz RADIO sleep timer registers, check the RADIOCLKRDY bit. When RADIOSMEN and STRADIOCLKON are both cleared, RADIOCLKRDY bit must be re-checked when exiting low-power modes (Sleep and Stop).

12.8.24 RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1)

Address offset: 0x09C

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported.

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 I2C1EN : I2C1 bus and kernel clocks enable

Set and cleared by software.

Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: I2C1 bus and kernel clocks disabled

1: I2C1 bus and kernel clocks enabled

Note that this bit is reserved on STM32WBA50xx devices.

Bits 20:18 Reserved, must be kept at reset value.

Bit 17 USART2EN : USART2 bus and kernel clocks enable

Set and cleared by software.

Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV..

0: USART2 bus and kernel clocks disabled

1: USART2 bus and kernel clocks enabled

Note that this bit is reserved on STM32WBA50xx devices.

Bits 16:12 Reserved, must be kept at reset value.

Bit 11 WWDGEN : WWDG bus clock enable

Set by software to enable the window watchdog bus clock. Reset by hardware system reset.

This bit can also be set by hardware if the WWDG_SW option bit is reset.

Access can be secured by GTZC_TZSC WWDGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: WWDG bus clock disabled

1: WWDG bus clock enabled

Bits 10:2 Reserved, must be kept at reset value.

Bit 1 TIM3EN : TIM3 bus and kernel clocks enable

Set and cleared by software.

Access can be secured by GTZC_TZSC TIM3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: TIM3 bus and kernel clocks disabled

1: TIM3 bus and kernel clocks enabled

Note that this bit is reserved on STM32WBA50xx devices.

Bit 0 TIM2EN : TIM2 bus and kernel clocks enable

Set and cleared by software.

Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: TIM2 bus and kernel clocks disabled

1: TIM2 bus and kernel clocks enabled

12.8.25 RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2)

Address offset: 0x0A0

Reset value: 0x0000 0000

Access: no wait state; word, half-word and byte access

This register is reserved on STM32WBA50xx devices.

Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported.

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 LPTIM2EN : LPTIM2 bus and kernel clocks enable

Set and cleared by software.

Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LPTIM2 bus and kernel clocks disabled

1: LPTIM2 bus and kernel clocks enabled

Bits 4:0 Reserved, must be kept at reset value.

12.8.26 RCC APB2 peripheral clock enable register (RCC_APB2ENR)

Address offset: 0x0A4

Reset value: 0x0000 0000

Access: word, half-word and byte access

Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported.

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 SAI1EN : SAI1 bus and kernel clocks enable

Set and cleared by software.

Access can be secured by GTZC_TZSC SAI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: SAI1 bus and kernel clocks disabled

1: SAI1 bus and kernel clocks enabled

Note that this bit is reserved on STM32WBA50/52xx devices.

Bits 20:19 Reserved, must be kept at reset value.

Set and cleared by software.

Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: TIM17 bus and kernel clocks disabled

1: TIM17 bus and kernel clocks enabled

Note that this bit is reserved on STM32WBA50xx devices.

Set and cleared by software.

Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: TIM16 bus and kernel clocks disabled

1: TIM16 bus and kernel clocks enabled

Bits 16:15 Reserved, must be kept at reset value.

Set and cleared by software.

Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: USART1 bus and kernel clocks disabled

1: USART1 bus and kernel clocks enabled

Bit 13 Reserved, must be kept at reset value.

Set and cleared by software.

Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: SPI1 bus and kernel clocks disabled

1: SPI1 bus and kernel clocks enabled

Note that this bit is reserved on STM32WBA50xx devices.

Set and cleared by software.

Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: TIM1 bus and kernel clocks disabled

1: TIM1 bus and kernel clocks enabled

Bits 10:0 Reserved, must be kept at reset value.

12.8.27 RCC APB7 peripheral clock enable register (RCC_APB7ENR)

Address offset: 0x0A8

Reset value: 0x0000 0000

Access: no wait state; word, half-word and byte access

Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported.

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 RTCAPBEN : RTC and TAMP bus clock enable

Set and cleared by software.

Can only be accessed secure when one or more features in the RTC or TAMP is/are secure.

When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: RTC bus clock disabled

1: RTC bus clock enabled

Bits 20:16 Reserved, must be kept at reset value.

Bit 15 COMPEN : COMP bus clock enable

Set and cleared by software.

Access can be secured by GTZC_TZSC COMPSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: COMP bus clock disabled

1: COMP bus clock enabled

Note that this bit is reserved on STM32WBA50/52xx devices.

Bits 14:12 Reserved, must be kept at reset value.

Bit 11 LPTIM1EN : LPTIM1 bus and kernel clocks enable

Set and cleared by software.

Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LPTIM1 bus and kernel clocks disabled

1: LPTIM1 bus and kernel clocks enabled

Bits 10:8 Reserved, must be kept at reset value.

Bit 7 I2C3EN : I2C3 bus and kernel clocks enable

Set and cleared by software.

Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: I2C3 bus and kernel clocks disabled

1: I2C3 bus and kernel clocks enabled

Bit 6 LPUART1EN : LPUART1 bus and kernel clocks enable

Set and cleared by software.

Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LPUART1 bus and kernel clocks disabled

1: LPUART1 bus and kernel clocks enabled

Bit 5 SPI3EN : SPI3 bus and kernel clocks enable

Set and cleared by software.

Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: SPI3 bus and kernel clocks disabled

1: SPI3 bus and kernel clocks enabled

Bits 4:2 Reserved, must be kept at reset value.

Bit 1 SYSCFGEN : SYSCFG bus clock enable

Set and cleared by software.

Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: SYSCFG bus clock disabled

1: SYSCFG bus clock enabled

Bit 0 Reserved, must be kept at reset value.

12.8.28 RCC AHB1 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB1SMENR)

Address offset: 0x0B0

Reset value: 0xFFFF FFFF

Access: no wait state, word, half-word and byte access

This register configures the clock gating only when the corresponding RCC_AHB1ENR.peripheralEN bit is set.

Bit 31 SRAM1SMEN : SRAM1 bus clock enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_MPCBB1 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: SRAM1 bus clock disabled by the clock gating during Sleep and Stop modes

1: SRAM1 bus clock enabled by the clock gating during Sleep and Stop modes

Bit 30 Reserved, must be kept at reset value.

Bit 29 ICACHESMEN : ICACHE bus clock enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC ICACHE_REGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: ICACHE bus clock disabled by the clock gating during Sleep and Stop modes

1: ICACHE bus clock enabled by the clock gating during Sleep and Stop modes

Bits 28:25 Reserved, must be kept at reset value.

Bit 24 GTZC1SMEN : GTZC1 bus clock enable during Sleep and Stop modes

Set and cleared by software.

Can only be accessed secure when one device is secure (TZEN = 1). When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: GTZC1 bus clock disabled by the clock gating during Sleep and Stop modes

1: GTZC1 bus clock enabled by the clock gating during Sleep and Stop modes

Note that this bit is reserved on STM32WBA50xx devices.

Bits 23:18 Reserved, must be kept at reset value.

Bit 17 RAMCFGSMEN : RAMCFG bus clock enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC RAMCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: RAMCFG bus clock disabled by the clock gating during Sleep and Stop modes

1: RAMCFG bus clock enabled by the clock gating during Sleep and Stop modes

Bit 16 TSCSMEN : TSC bus clock enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV..

0: TSC bus clock disabled by the clock gating during Sleep and Stop modes

1: TSC bus clock enabled by the clock gating during Sleep and Stop modes

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 CRCSMEN : CRC bus clock enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: CRC bus clock disabled by the clock gating during Sleep and Stop modes

1: CRC bus clock enabled by the clock gating during Sleep and Stop modes

Bits 11:9 Reserved, must be kept at reset value.

Bit 8 FLASHSMEN : FLASH bus clock enable during Sleep and Stop modes

Set and cleared by software.

Can only be accessed secured when the flash security state is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: FLASH bus clock disabled by the clock gating during Sleep and Stop modes

1: FLASH bus clock enabled by the clock gating during Sleep and Stop modes

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 GPDMA1SMEN : GPDMA1 bus clock enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: GPDMA1 bus clock disabled by the clock gating during Sleep and Stop modes

1: GPDMA1 bus clock enabled by the clock gating during Sleep and Stop modes

Note: This bit must be set to allow the peripheral to wake up from Stop modes.

12.8.29 RCC AHB2 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB2SMENR)

Address offset: 0x0B4

Reset value: 0xFFFF FFFF

Access: no wait state; word, half-word and byte access

This register configures the clock gating only when the corresponding RCC_AHB2ENR.peripheralEN bit is set.

Bit 31 Reserved, must be kept at reset value.

Bit 30 SRAM2SMEN : SRAM2 bus clock enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_MPCBB2 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: SRAM2 bus clock disabled by the clock gating during Sleep and Stop modes

1: SRAM2 bus clock enabled by the clock gating during Sleep and Stop modes

Bits 29:22 Reserved, must be kept at reset value.

Bit 21 PKASMEN : PKA bus clock enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: PKA bus clock disabled by the clock gating during Sleep and Stop modes

1: PKA bus clock enabled by the clock gating during Sleep and Stop modes

Bit 20 Reserved, must be kept at reset value.

Bit 19 SAESSMEN : SAES accelerator bus clock enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: SAES bus clock disabled by the clock gating during Sleep and Stop modes

1: SAES bus clock enabled by the clock gating during Sleep and Stop modes

Note that this bit is reserved on STM32WBA50xx devices.

Bit 18 RNGSMEN : Random number generator (RNG) bus and kernel clocks enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: RNG bus and kernel clocks disabled by the clock gating during Sleep and Stop modes

1: RNG bus and kernel clocks enabled by the clock gating during Sleep and Stop modes

Bit 17 HASHSMEN : HASH bus clock enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: HASH bus clock disabled by the clock gating during Sleep and Stop modes

1: HASH bus clock enabled by the clock gating during Sleep and Stop modes

Bit 16 AESSMEN : AES bus clock enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: AES bus clock disabled by the clock gating during Sleep and Stop modes

1: AES bus clock enabled by the clock gating during Sleep and Stop modes

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 GPIOHSMEN : IO port H bus clock enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: IO port H bus clock disabled by the clock gating during Sleep and Stop modes

1: IO port H bus clock enabled by the clock gating during Sleep and Stop modes

Bits 6:3 Reserved, must be kept at reset value.

Bit 2 GPIOCSMEN : IO port C bus clock enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: IO port C bus clock disabled by the clock gating during Sleep and Stop modes

1: IO port C bus clock enabled by the clock gating during Sleep and Stop modes

Bit 1 GPIOBSMEN : IO port B bus clock enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: IO port B bus clock disabled by the clock gating during Sleep and Stop modes

1: IO port B bus clock enabled by the clock gating during Sleep and Stop modes

Bit 0 GPIOASMEN : IO port A bus clock enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: IO port A bus clock disabled by the clock gating during Sleep and Stop modes

1: IO port A bus clock enabled by the clock gating during Sleep and Stop modes

12.8.30 RCC AHB4 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB4SMENR)

Address offset: 0x0BC

Reset value: 0xFFFF FFFF

Access: no wait state; word, half-word and byte access

This register configures the clock gating only when the corresponding RCC_AHB4ENR.peripheralEN bit is set.

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 ADC4SMEN : ADC4 bus and kernel clocks enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: ADC4 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes

1: ADC4 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes

Note: This bit must be set to allow the peripheral to wake up from Stop modes.

Bits 4:3 Reserved, must be kept at reset value.

Bit 2 PWRSMEN : PWR bus clock enable during Sleep and Stop modes

Set and cleared by software.

Can only be accessed secure when one or more features in the PWR is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: PWR bus clock disabled by the clock gating during Sleep and Stop modes

1: PWR bus clock enabled by the clock gating during Sleep and Stop modes

Bits 1:0 Reserved, must be kept at reset value.

12.8.31 RCC AHB5 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB5SMENR)

Address offset: 0x0C0

Reset value: 0xFFFF FFFF

Access: no wait state; word, half-word and byte access

This register configures the clock gating only when the corresponding RCC_AHB5ENR.peripheralEN bit is set.

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 PTACONVSMEN : PTACONV bus clock enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC PTACONVSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: PTACONV bus clock disabled by the clock gating during Sleep and Stop modes

1: PTACONV bus clock enabled by the clock gating during Sleep and Stop modes

Note that this bit is reserved on STM32WBA50/52xx devices.

Bit 0 RADIOSMEN : 2.4 GHz RADIO bus clock enable during Sleep and Stop modes when the 2.4 GHz RADIO is active.

Set and cleared by software.

Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: 2.4 GHz RADIO bus clock disabled by the clock gating during Sleep and Stop modes (The 2.4 GHz RADIO bus clock may still be enabled by STRADIOCLKON)

1: 2.4 GHz RADIO bus clock enabled by the clock gating during Sleep and Stop modes when the 2.4 GHz RADIO is active

12.8.32 RCC APB1 peripheral clocks enable in Sleep and Stop modes register 1 (RCC_APB1SMENR1)

Address offset: 0x0C4

Reset value: 0xFFFF FFFF

Access: no wait state; word, half-word and byte access

This register configures the clock gating only when the corresponding RCC_APB1ENR1.peripheralEN bit is set.

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 I2C1SMEN : I2C1 bus and kernel clocks enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: I2C1 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes

1: I2C1 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes

Note that this bit is reserved on STM32WBA50xx devices.

Note: This bit must be set to allow the peripheral to wake up from Stop modes.

Bits 20:18 Reserved, must be kept at reset value.

Bit 17 USART2SMEN : USART2 bus and kernel clocks enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: USART2 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes

1: USART2 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes

Note that this bit is reserved on STM32WBA50xx devices.

Note: This bit must be set to allow the peripheral to wake up from Stop modes.

Bits 16:12 Reserved, must be kept at reset value.

Bit 11 WWDGSMEN : Window watchdog bus clock enable during Sleep and Stop modes

Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated.

Access can be secured by GTZC_TZSC WWDGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: WWDG bus clock disabled by the clock gating during Sleep mode

1: WWDG bus clock enabled by the clock gating during Sleep mode

Bits 10:2 Reserved, must be kept at reset value.

Bit 1 TIM3SMEN : TIM3 bus and kernel clocks enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC TIM3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: TIM3 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes

1: TIM3 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes

Note that this bit is reserved on STM32WBA50xx devices.

Bit 0 TIM2SMEN : TIM2 bus and kernel clocks enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: TIM2 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes

1: TIM2 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes

12.8.33 RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2 (RCC_APB1SMENR2)

Address offset: 0x0C8

Reset value: 0xFFFF FFFF

Access: no wait state; word, half-word and byte access

This register configures the clock gating only when the corresponding RCC_APB1ENR2.peripheralEN bit is set.

This register is reserved on STM32WBA50xx devices.

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 LPTIM2SMEN : LPTIM2 bus and kernel clocks enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LPTIM2 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes

1: LPTIM2 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes

Note: This bit must be set to allow the peripheral to wake up from Stop modes.

Bits 4:0 Reserved, must be kept at reset value.

12.8.34 RCC APB2 peripheral clocks enable in Sleep and Stop modes register (RCC_APB2SMENR)

Address offset: 0x0CC

Reset value: 0xFFFF FFFF

Access: word, half-word and byte access

This register configures the clock gating only when the corresponding RCC_APB2ENR.peripheralEN bit is set.

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 SAI1SMEN : SAI1 bus and kernel clocks enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC SAI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: SAI1 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes

1: SAI1 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes

Note that this bit is reserved on STM32WBA50/52xx devices.

Bits 20:19 Reserved, must be kept at reset value.

Bit 18 TIM17SMEN : TIM17 bus and kernel clocks enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: TIM17 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes

1: TIM17 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes

Note that this bit is reserved on STM32WBA50xx devices.

Bit 17 TIM16SMEN : TIM16 bus and kernel clocks enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: TIM16 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes

1: TIM16 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes

Bits 16:15 Reserved, must be kept at reset value.

Bit 14 USART1SMEN : USART1 bus and kernel clocks enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: USART1 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes

1: USART1 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes

Note: This bit must be set to allow the peripheral to wake up from Stop modes.

Bit 13 Reserved, must be kept at reset value.

Bit 12 SPI1SMEN : SPI1 bus and kernel clocks enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: SPI1 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes

1: SPI1 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes

Note that this bit is reserved on STM32WBA50xx devices.

Note: This bit must be set to allow the peripheral to wake up from Stop modes.

Bit 11 TIM1SMEN : TIM1 bus and kernel clocks enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: TIM1 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes

1: TIM1 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes

Bits 10:0 Reserved, must be kept at reset value.

12.8.35 RCC APB7 peripheral clock enable in Sleep and Stop modes register (RCC_APB7SMENR)

Address offset: 0x0D0

Reset value: 0xFFFF FFFF

Access: no wait state; word, half-word and byte access

This register configures the clock gating only when the corresponding RCC_APB7ENR.peripheralEN bit is set.

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 RTCAPBSMEN : RTC and TAMP APB clock enable during Sleep and Stop modes

Set and cleared by software.

Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: RTC and TAMP APB clock disabled by the clock gating during Sleep and Stop modes

1: RTC and TAMP APB clock enabled by the clock gating during Sleep and Stop modes

Note: This bit must be set to allow the peripheral to wake up from Stop modes.

Bits 20:16 Reserved, must be kept at reset value.

Bit 15 COMPSMEN : COMP bus clock enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC COMPSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: COMP bus clock disabled by the clock gating during Sleep and Stop modes

1: COMP bus clock enabled by the clock gating during Sleep and Stop modes

Note that this bit is reserved on STM32WBA50/52xx devices.

Bits 14:12 Reserved, must be kept at reset value.

Bit 11 LPTIM1SMEN : LPTIM1 bus and kernel clocks enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LPTIM1 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes

1: LPTIM1 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes

Note: This bit must be set to allow the peripheral to wake up from Stop modes.

Bits 10:8 Reserved, must be kept at reset value.

Bit 7 I2C3SMEN : I2C3 bus and kernel clocks enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: I2C3 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes

1: I2C3 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes

Note: This bit must be set to allow the peripheral to wake up from Stop modes.

Bit 6 LPUART1SMEN : LPUART1 bus and kernel clocks enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LPUART1 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes

1: LPUART1 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes

Note: This bit must be set to allow the peripheral to wake up from Stop modes.

Bit 5 SPI3SMEN : SPI3 bus and kernel clocks enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: SPI3 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes

1: SPI3 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes

Note: This bit must be set to allow the peripheral to wake up from Stop modes.

Bits 4:2 Reserved, must be kept at reset value.

Bit 1 SYSCFGSMEN : SYSCFG bus clock enable during Sleep and Stop modes

Set and cleared by software.

Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: SYSCFG bus clock disabled by the clock gating during Sleep and Stop modes

1: SYSCFG bus clock enabled by the clock gating during Sleep and Stop modes

Bit 0 Reserved, must be kept at reset value.

12.8.36 RCC peripherals independent clock configuration register 1 (RCC_CCIPR1)

Address offset: 0x0E0

Reset value: 0x0000 0000

Access: no wait states; word, half-word and byte access

Bit 31 TIMICSEL : Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture

When the TIMICSEL bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected to HSI16/256.

When TIMICSEL is cleared, the HSI16, clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture.

Access can be secured by GTZC_TZSC TIM16SEC, TIM17SEC, or LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: HSI16 divider disabled

1: HSI16/256 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture

Note: The clock division must be disabled (TIMICSEL configured to 0) before selecting or changing a clock sources division.

Bits 30:24 Reserved, must be kept at reset value.

Bits 23:22 SYSTICKSEL[1:0] : SysTick clock source selection

These bits are used to select the SysTick clock source.

Access can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

00: hclk1 divided by 8 selected

01: LSI selected

10: LSE selected

11: reserved

Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one hclk1 cycle is introduced, due to the LSE or LSI sampling with hclk1 in the SysTick circuitry.

Bits 21:20 SPI1SEL[1:0] : SPI1 kernel clock source selection

These bits are used to select the SPI1 kernel clock source.

Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

00: pclk2 selected

01: SYSCLK selected

10: HSI16 selected

11: reserved

Note that these bits are reserved on STM32WBA50xx devices.

Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16.

Bits 19:18 LPTIM2SEL[1:0] : Low-power timer 2 kernel clock source selection

These bits are used to select the LPTIM2 kernel clock source.

Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

00: pclk1 selected

01: LSI selected

10: HSI16 selected

11: LSE selected

Note that these bits are reserved on STM32WBA50xx devices.

Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI16 if HSIKERON = 1.

Bits 17:12 Reserved, must be kept at reset value.

Bits 11:10 I2C1SEL[1:0] : I2C1 kernel clock source selection

These bits are used to select the I2C1 kernel clock source.

Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

00: pclk1 selected

01: SYSCLK selected

10: HSI16 selected

11: reserved

Note that these bits are reserved on STM32WBA50xx devices.

Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16.

Bits 9:4 Reserved, must be kept at reset value.

Bits 3:2 USART2SEL[1:0] : USART2 kernel clock source selection

These bits are used to select the USART2 kernel clock source.

Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

00: pclk1 selected

01: SYSCLK selected

10: HSI16 selected

11: LSE selected

Note that these bits are reserved on STM32WBA50xx devices.

Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE.

Bits 1:0 USART1SEL[1:0] : USART1 kernel clock source selection

This bits are used to select the USART1 kernel clock source.

Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

00: pclk2 selected

01: SYSCLK selected

10: HSI16 selected

11: LSE selected

Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE.

12.8.37 RCC peripherals independent clock configuration register 2 (RCC_CCIPR2)

Address offset: 0x0E4

Reset value: 0x0000 0000

Access: no wait state; word, half-word and byte access

Bit 31 Reserved, must be kept at reset value.

Bit 30 ASSEL : Audio synchronization kernel clock source selection

This bit allows to select the audio synchronization kernel clock source.

Access can be secured by GTZC_TZSC SAI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: pll1pclk selected

1: pll1qclk selected

Note: This bit is reserved on STM32WBA50/52xx devices.

Bits 29:14 Reserved, must be kept at reset value.

Bits 13:12 RNGSEL[1:0] : RNGSEL kernel clock source selection

These bits allow to select the RNG kernel clock source.

Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

00: LSE selected

01: LSI selected

10: HSI16 selected

11: pll1qclk divide by 2 selected

Bits 11:8 Reserved, must be kept at reset value.

Bits 7:5 SAI1SEL[2:0] : SAI1 kernel clock source selection

These bits are used to select the SAI1 kernel clock source.

Access can be secured by GTZC_TZSC SAI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

000: pll1pclk selected

001: pll1qclk selected

010: SYSCLK selected

011: input pin AUDIOCLK selected

100: HSI16 clock selected

others: reserved

Note that these bits are reserved on STM32WBA50/52xx devices.

Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible.

Bits 4:0 Reserved, must be kept at reset value.

12.8.38 RCC peripherals independent clock configuration register 3 (RCC_CCIPR3)

Address offset: 0x0E8

Reset value: 0x0000 0000

Access: no wait state; word, half-word and byte access

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:12 ADCSEL[2:0] : ADC4 kernel clock source selection

These bits are used to select the ADC4 kernel clock source.

Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

000: hclk1 clock selected

001: SYSCLK selected

010: pll1pclk selected

011: HSE32 clock selected

100: HSI16 clock selected

others: reserved

Note: The ADC4 is functional in Stop modes only when the kernel clock is HSI16.

Bits 11:10 LPTIM1SEL[1:0] : LPTIM1 kernel clock source selection

These bits are used to select the LPTIM1 kernel clock source.

Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

00: pclk7 selected.

01: LSI selected

10: HSI16 selected

11: LSE selected

Note: The LPTIM1 is functional in Stop modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1.

Bits 9:8 Reserved, must be kept at reset value.

Bits 7:6 I2C3SEL[1:0] : I2C3 kernel clock source selection

These bits are used to select the I2C3 kernel clock source.

Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

00: pclk7 selected

01: SYSCLK selected

10: HSI16 selected

11: reserved

Note: The I2C3 is functional in Stop modes only when the kernel clock is HSI16.

Bit 5 Reserved, must be kept at reset value.

Bits 4:3 SPI3SEL[1:0] : SPI3 kernel clock source selection

These bits are used to select the SPI3 kernel clock source.

Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

00: pclk7 selected

01: SYSCLK selected

10: HSI16 selected

11: reserved

Note: The SPI3 is functional in Stop modes only when the kernel clock is HSI16.

Bit 2 Reserved, must be kept at reset value.

Bits 1:0 LPUART1SEL[1:0] : LPUART1 kernel clock source selection

These bits are used to select the LPUART1 kernel clock source.

Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

00: pclk7 selected

01: SYSCLK selected

10: HSI16 selected

11: LSE selected

Note: The LPUART1 is functional in Stop modes only when the kernel clock is HSI16 or LSE.

12.8.39 RCC Backup domain control register (RCC_BDCR1)

Address offset: 0x0F0

Backup domain reset value: 0b0000 0000 0000 0000 0XX0 0000 0000 1000

Where X (LSETRIM) is loaded with factory-programmed value at BOR0 reset and OBL_LAUNCH when SBF is cleared.

Fields LSCOSEL, LSCOEN, LSETRIM, RADIOSTSEL, LSI1ON, LSI1PREDIV, and BDRST are reset only by Backup domain power-on reset (BOR0), and not by a BDRST reset.

Reset value not affected by exit Standby mode, nor by system reset or BORx (x = 1 to 4).

Access: 0 ≤ wait state ≤ 3; word, half-word and byte access

Wait states are inserted in case of successive accesses to this register.

Note: The LSETRIM bits are outside the Core domain: as a result, after reset, they are write-protected and the DBP bit in the PWR disable Backup domain register (PWR_DBPR) must be set before they can be modified (see Section 11: Power control (PWR) for further information).

Bit 31 Reserved, must be kept at reset value.

Bit 30 LSI2RDY : LSI2 oscillator ready

Set and cleared by hardware to indicate when the LSI2 oscillator is stable. After the LSI2ON bit is cleared, LSI2RDY goes low after three internal low-speed oscillator clock cycles.

Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LSI2 oscillator not ready

1: LSI2 oscillator ready

Note that this bit is reserved on STM32WBA50/52xx devices.

Bit 29 LSI2ON : LSI2 oscillator enable

Set and cleared by software.

Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LSI2 oscillator off

1: LSI2 oscillator on

Note that this bit is reserved on STM32WBA50/52xx devices.

Set and cleared by software to enable the LSI1 division. This bit can be written only when the LSI1 is disabled (LSI1ON = 0 and LSI1RDY = 0). The LSI1PREDIV cannot be changed if the LSI1 is used by the IWDG or by the RTC.

Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LSI1 not divided

1: LSI1 divided by 128

Set and cleared by hardware to indicate when the LSI1 oscillator is stable. After the LSI1ON bit is cleared, LSI1RDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI1 is used by IWDG or RTC, even if LSI1ON = 0.

Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LSI1 oscillator not ready

1: LSI1 oscillator ready

Set and cleared by software.

Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LSI1 oscillator off

1: LSI1 oscillator on

Set and cleared by software.

Access can be secured by RCC LSISEC and/or RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LSI clock selected

1: LSE clock selected

Set and cleared by software.

Access can be secured by RCC LSISEC and/or RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LSCO disabled

1: LSCO enabled

Bits 23:20 Reserved, must be kept at reset value.

Bits 19:18 RADIOSTSEL[1:0] : 2.4 GHz RADIO sleep timer kernel clock enable and selection

Set and cleared by software.

Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

00: no clock selected, 2.4 GHz RADIO sleep timer kernel clock disabled

01: LSE oscillator clock selected

10: LSI oscillator clock selected

11: HSE32 oscillator clock divided by 1000 selected

Bit 17 Reserved, must be kept at reset value.

Bit 16 BDRST : Backup domain software reset

Set and cleared by software.

A Backup domain reset is generated only when the domain protection is disabled.

Can only be accessed secure when one or more features in the RTC or TAMP are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: Reset not activated

1: Reset the entire Backup domain when the protection is disabled

Bit 15 Reserved, must be kept at reset value.

Bits 14:13 LSETRIM[1:0] : LSE trimming

These bits are initialized at startup and after OBL_LAUNCH with SBF cleared with the factory-programmed LSE calibration value.

Set and cleared by software. These bits must be modified only once after a BOR reset or an OBL_LAUNCH and before enabling LSE with LSEON (when both LSEON = 0 and LSERDY = 0).

Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

00: current source resistance \( 5/4 \times R \)

01: current source resistance \( R \)

10: current source resistance \( 3/4 \times R \)

11: current source resistance \( 2/3 \times R \)

Note: OBL_LAUNCH of this field occurs only when SBF is cleared and must then only be started by software when LSE oscillator is disabled, LSEON = 0 and LSERDY = 0.

Bit 12 LSEGFON : LSE clock glitch filter enable

Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0).

Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LSE glitch filter disabled

1: LSE glitch filter enabled

Set and cleared by hardware to indicate when the LSE system clock is stable. When the LSESYSEN bit is set, the LSESYRDY flag is set after two LSE clock cycles.

The LSE clock must be already enabled and stable (LSEON and LSERDY are set).

When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles.

Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LSESYS clock not ready

1: LSESYS clock ready

Set by software to enable and select the clock source for the RTC.

Can only be accessed secure when one or more features in the RTC or TAMP is/are secure.

When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

00: no clock selected, RTC and TAMP kernel clock disabled

01: LSE oscillator clock selected, and enabled

10: LSI oscillator clock selected, and enabled

11: HSE32 oscillator clock divided by 32 selected, and enabled

Set by software to enable the LSE system clock generated by RCC. The Lsesys clock is used for peripherals (USART, LPUART, LPTIM, RNG, 2.4 GHz RADIO) and functions (LSCO, MCO, TIM triggers, LPTIM trigger) excluding the RTC, TAMP and LSECSS.

Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LSESYS clock disabled

1: LSESYS clock enabled

Set by hardware to indicate when a failure is detected by the LSECCS on the external 32 kHz oscillator.

Reset when LSCSSON bit is cleared.

Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: no failure detected on LSE

1: failure detected on LSE

Set by software to enable the LSECSS. LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware) and after the RTCSEL bit is selected.

Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case, the software must disable the LSECSSON bit.

Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LSECSS disabled off

1: LSECSS enabled on

Set by software to modulate the drive capability of the LSE oscillator. LSEDRV must be programmed to a different value than 0 before enabling the LSE oscillator in 'Xtal' mode.

Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

00: reserved

01: 'Xtal mode' medium-low driving capability

10: 'Xtal mode' medium-high driving capability

11: 'Xtal mode' higher driving capability

Note: The oscillator is in 'Xtal mode' when it is not in bypass mode.

Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0).

Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LSE oscillator 'Xtal' mode

1: LSE oscillator bypassed

Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles.

Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LSE oscillator not ready

1: LSE oscillator ready

Set and cleared by software.

Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0: LSE oscillator off

1: LSE oscillator on

12.8.40 RCC control/status register (RCC_CSR)

Address offset: 0x0F4

Reset value: 0x0C00 0000

Reset flags are only reset by BOR0 power reset.

Access: 0 ≤ wait state ≤ 3; word, half-word and byte access

Access can be protected by RCC SPRIV or RCC NSPRIV.

Wait states are inserted in case of successive accesses to this register.

Bit 31 LPWRRSTF : Low-power reset flag

Set by hardware when a reset occurs due to illegal Stop and Standby modes entry.

Cleared by writing to the RMVF bit.

0: no illegal mode reset occurred

1: illegal mode reset occurred

Bit 30 WWDGRSTF : Window watchdog reset flag

Set by hardware when a window watchdog reset occurs.

Cleared by writing to the RMVF bit.

0: no window watchdog reset occurred

1: window watchdog reset occurred

Bit 29 IWDGRSTF : Independent watchdog reset flag

Set by hardware when an independent watchdog reset domain occurs.

Cleared by writing to the RMVF bit.

0: no independent watchdog reset occurred

1: independent watchdog reset occurred

Bit 28 SFTRSTF : Software reset flag

Set by hardware when a software reset occurs.

Cleared by writing to the RMVF bit.

0: no software reset occurred

1: software reset occurred

Bit 27 BORRSTF : BOR flag

Set by hardware when a BOR occurs.

Cleared by writing to the RMVF bit.

0: no BOR occurred

1: BOR occurred

Bit 26 PINRSTF : NRST pin reset flag

Set by hardware when a reset from the NRST pin occurs.

Cleared by writing to the RMVF bit.

0: No reset from NRST pin occurred

1: Reset from NRST pin occurred

Bit 25 OBLRSTF : Option byte loader reset flag

Set by hardware when a reset from the option byte loading occurs.

Cleared by writing to the RMVF bit.

0: No reset from option byte loading occurred

1: Reset from option byte loading occurred

Bit 24 Reserved, must be kept at reset value.

Bit 23 RMVF : Remove reset flag

Set by software to clear the reset flags.

Access can be secured by RCC RMVFSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt.

0: No effect

1: Clear the reset flags (once set by software bit is cleared automatically by hardware)

Bits 22:0 Reserved, must be kept at reset value.

12.8.41 RCC Backup domain control register (RCC_BDCR2)

Address offset: 0x0F8

Backup domain reset value: 0x0000 0000

Reset value is not effected by exit Standby mode, nor by system reset or BORx (x = 1 to 4).

Access: 0 ≤ wait state ≤ 3; word, half-word and byte access

Wait states are inserted in case of successive accesses to this register.

This register is reserved on STM32WBA50/52xx devices.

Note: The bits of this register are outside the Core domain. As a result, after reset, they are write-protected and the DBP bit in the PWR disable Backup domain register (PWR_DBPR) must be set before they can be modified (see Section 11: Power control (PWR) for further information).

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:4 LSI2CFG[3:0] : LSI2 oscillator configuration

Set and cleared by software to control the temperature at which the frequency temperature sensitivity is close to zero.

Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0x0: LSI2 frequency temperature sensitivity is close to zero at +80 °C

0x1: LSI2 frequency temperature sensitivity is close to zero at +50 °C

0x2: LSI2 frequency temperature sensitivity is close to zero at +20 °C

others reserved

Bit 3 Reserved, must be kept at reset value.

Bits 2:0 LSI2MODE[2:0] : LSI2 oscillator operating mode configuration

Set and cleared by software to select operating mode of power consumption versus accuracy.

Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0b000: nominal-power, high accuracy

0b001: low-power, medium accuracy

0b010: ultra-low-power, low accuracy

others reserved

12.8.42 RCC secure configuration register (RCC_SECCFGR)

Address offset: 0x110

Reset value: 0x0000 0000

Access: no wait state; word, half-word and byte access

When the system is secure (TZEN = 1), this register can be written only by a secure privileged access if RCC SPRIV = 1 and by a secure privileged or unprivileged access if RCC SPRIV = 0. A non-secure write access generates an illegal access event and data are not written. This register can be read by secure or non-secure, privileged or unprivileged access.

When the system is not secure (TZEN = 0), this register is read as 0 writes are ignored.

This register is reserved on STM32WBA50xx devices.

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 RMVFSEC : Remove reset flag security

Set and reset by software.

0: Non secure

1: Secure

Bits 11:8 Reserved, must be kept at reset value.

Bit 7 PLL1SEC : PLL1 clock configuration and status bits security

Set and reset by software.

0: Non secure

1: Secure

Bit 6 PRESCSEC : AHBx/APBx prescaler configuration bits security

Set and reset by software.

0: Non secure

1: Secure

1. Bit 5 SYSCCLKSEC : SYSCCLK selection, clock output on MCO configuration security
   Set and reset by software.
   0: Non secure
   1: Secure
2. Bit 4 LSESEC : LSE clock configuration and status bits security
   Set and reset by software.
   0: Non secure
   1: Secure
3. Bit 3 LSISEC : LSI clock configuration and status bits security
   Set and reset by software.
   0: Non secure
   1: Secure
4. Bit 2 Reserved, must be kept at reset value.
5. Bit 1 HSESEC : HSE32 clock configuration bits, status bits and HSECSS security
   Set and reset by software.
   0: Non secure
   1: Secure
6. Bit 0 HSISEC : HSI16 clock configuration and status bits security
   Set and reset by software.
   0: Non secure
   1: Secure

12.8.43 RCC privilege configuration register (RCC_PRIVCFGR)

Address offset: 0x114

Reset value: 0x0000 0000

Access: no wait state; word, half-word and byte access

This register can be written only by a privileged access. It can be read by privileged or unprivileged access.

This register is reserved on STM32WBA50xx devices.

Bits 31:2 Reserved, must be kept at reset value.

1. Bit 1 NSPRIV : RCC non-secure functions privilege configuration
   Set and reset by software.
   This bit can be written only by privileged access, secure or non-secure.
   0: Read and write to RCC non-secure functions can be done by privileged or unprivileged access.
   1: Read and write to RCC non-secure functions can be done by privileged access only.

Bit 0 SPRIV : RCC secure functions privilege configuration

Set and reset by software.

This bit can be written only by a secure privileged access.

0: Read and write to RCC secure functions can be done by privileged or unprivileged access.

1: Read and write to RCC secure functions can be done by privileged access only.

12.8.44 RCC audio synchronization control register (RCC_ASCR)

Address offset: 0x1C0

Reset value: 0x0000 4000

Access to this register can be protected by GTZC_TZSC SAI1SEC and RCC SPRIV or RCC NSPRIV.

This register is reserved on STM32WBA50/52xx devices.

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 CPS[6:0] : Capture prescaler

This field is set and cleared by software.

Capture period in number of counter periods. Capture period = counter period * (TPS + 1).

Bit 15 Reserved, must be kept at reset value.

Bits 14:8 PSC[6:0] : Clock prescaler

This field is set and cleared by software.

Counter clock frequency = \( f_{\text{audiosync\_ker\_ck}} / (\text{PSC} + 1) \) .

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 CEN : Counter enable

This bit is set and cleared by software.

Clearing this bit resets the audio synchronization counter and capture prescaler and all associated registers ASCR, ASIER, ASSR, ASCNTR, ASARR, ASCAR, and ASCOR.

0: Audio synchronization counter and kernel clock disabled

1: Audio synchronization counter and kernel clock enabled

12.8.45 RCC audio synchronization interrupt enable register (RCC_ASIER)

Address offset: 0x1C4

Reset value: 0x0000 0000

Access to this register can be protected by GTZC_TZSC SAI1SEC and RCC SPRIV or RCC NSPRIV.

This register is reserved on STM32WBA50/52xx devices.

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 CAEIE : Capture error interrupt enable

This bit is set and cleared by software.

0: Capture error interrupt disabled and flag masked

1: Capture error interrupt and flag enabled

Bit 1 COIE : Comparator interrupt enable

This bit is set and cleared by software.

0: Compare interrupt disabled and flag masked

1: Compare interrupt and flag enabled

Bit 0 CAIE : Capture trigger interrupt enable

This bit is set and cleared by software.

0: Capture trigger interrupt disabled and flag masked

1: Capture trigger interrupt and flag enabled

12.8.46 RCC audio synchronization status register (RCC_ASSR)

Address offset: 0x1C8

Reset value: 0x0000 0000

Access to this register can be protected by GTZC_TZSC_SAI1SEC and RCC_SPRIV or RCC_NSPRIV.

This register is reserved on STM32WBA50/52xx devices.

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 CAEF : Capture error interrupt flag

This bit is set by hardware, only when CAEIE is enabled. This bit is cleared by software by writing it to 0 or masked when CAEIE is 0.

0: No capture error has been detected

1: A capture error has been detected

Bit 1 COF : Comparer interrupt flag

This field is set by hardware, only when COIE is enabled. This bit is cleared by software by writing it to 0 or masked when COIE is 0.

0: No counter compare occurred

1: A counter compare has occurred

Bit 0 CAF : Capture trigger interrupt flag

This field is set by hardware, only when CAIE is enabled. This bit is cleared by software by writing it to 0 or masked when CAIE is 0.

0: No capture update occurred

1: A capture update has occurred

12.8.47 RCC auto-reload register (RCC_ASCNTR)

Address offset: 0x1CC

Reset value: 0x0000 0000

Access to this register can be protected by GTZC_TZSC SAI1SEC and RCC SPRIV or RCC NSPRIV.

This register is reserved on STM32WBA50/52xx devices.

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 CNT[19:0] : Counter value

This field is set by hardware.

CNT[19:0] is the counter value at the time this register is read.

12.8.48 RCC auto-reload register (RCC_ASARR)

Address offset: 0x1D0

Reset value: 0x0008 0000

Access to this register can be protected by GTZC_TZSC SAI1SEC and RCC SPRIV or RCC NSPRIV.

This register is reserved on STM32WBA50/52xx devices.

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 AR[19:0] : Auto-reload value

This field is set by software. This is the counter auto-reload value at which to restart the audio synchronization counter from value 0. It defines the counter period.

12.8.49 RCC capture register (RCC_ASCAR)

Address offset: 0x1D4

Reset value: 0x0000 0000

Access to this register can be protected by GTZC_TZSC SAI1SEC and RCC SPRIV or RCC NSPRIV.

This register is reserved on STM32WBA50/52xx devices.

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:0 CA[26:0] : Capture value

This field is set by hardware.

CA[26:20] is the capture period counter value loaded on the trigger event.

CA[19:0] is the audio synchronization counter value loaded on the trigger event.

12.8.50 RCC compare register (RCC_ASCOR)

Address offset: 0x1D8

Reset value: 0x0000 0000

Access to this register can be protected by GTZC_TZSC SAI1SEC and RCC SPRIV or RCC NSPRIV.

This register is reserved on STM32WBA50/52xx devices.

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 CO[19:0] : Compare value

This field is set by software. This is the value to compare with the audio synchronization counter to generate a compare interrupt event.

12.8.51 RCC clock configuration register 2 (RCC_CFGR4)

Address offset: 0x200

Reset value: 0x0000 0010

Access: word, half-word and byte access

1 or 2 wait states are inserted only if the access occurs during clock source switch.

Access to this register can be protected by RCC PRECSEC and RCC SPRIV or RCC NSPRIV.