6. RAMs configuration controller (RAMCFG)

6.1 Introduction

The RAMCFG configures the features of the internal SRAMs (SRAM1 and SRAM2).

6.2 RAMCFG main features

The internal SRAMs support some of the features listed hereafter, configured in RAMCFG:

• • Parity error detection with failing address indication
• • Write protection (1-Kbyte granularity)
• • Programmable wait states
• • SRAM software erase

6.3 RAMCFG functional description

6.3.1 Internal SRAMs features

Two main SRAMs (SRAM1 and SRAM2) are embedded in the devices, together with 2.4 GHz RADIO RXTXRAM and Sequence SRAM, each with specific features:

• • SRAM power/retention control
  • – SRAM1 and/or SRAM2 powered down in Stop modes to reduce consumption
  • – SRAM1, SRAM2 and/or 2.4 GHz RADIO SRAMs retained in Standby mode.

  Refer to Section 11: Power control (PWR) for more details.

• • SRAM erase on RDP regression:
  • – SRAM1 and SRAM2 are erased by hardware in case of Readout protection (RDP) level regression to Level 0.5 or Level 0.

Refer to Section 7: Embedded flash memory (FLASH) for more details.

• • SRAM erase on reset:
  • – SRAM2 is erased when a system reset occurs if the SRAM2_RST option bit is selected in the flash memory user option bytes.
  • – SRAM1 is erased when a system reset occurs if the SRAM1_RST option bit is selected in the flash memory user option bytes.

Refer to Section 7: Embedded flash memory (FLASH) for more details.

• • Tamper protection
  • – SRAM2 is protected by the tamper detection circuit, and is erased by hardware in case of tamper detection
  • – SRAM2 is also erased by hardware in case of a V _DD BOR0 (Backup domain supply power-on)

Refer to Section 37: Tamper and backup registers (TAMP) for more details.

• • Parity and write protection:
  • – SRAM2 features parity and write protection

Refer to Section 6.3.2 and Section 6.3.3 for more details.

• • Wait states and software reset:
  • – SRAM1 and SRAM2 feature programmable wait state configuration.
  • – SRAM1 and SRAM2 feature software erase.

Refer to Section 6.3.4 and Section 6.3.5 for more details.

Table 33. SRAMs features

1. 2.4 GHz RADIO SRAMs are always retained in Stop modes.

6.3.2 Internal SRAM parity

Parity is supported by SRAM2 when enabled with the SRAM2_PE user option bit, and when, furthermore, either PEIE or PENMI is enabled. Refer to Section 7: Embedded flash memory (FLASH) for more details.

Four parity bits are added per 32 bits of SRAM (1 bit per byte) to increase memory robustness.

The parity bits are computed and stored when writing into the SRAM2, then they are automatically checked when reading. If one byte parity fails, an NMI or IRQ can be generated. The same error can also be linked to the break input (BRK_IN) of TIM1, TIM16, and TIM17, with the SYSCFG_CFGR2.SPL control bit.

Note: When enabling SRAM2 parity, initialize by software the whole RAM at the beginning of the code, to avoid getting parity errors when reading noninitialized addresses.

When a parity error is detected, the PED and CPED bits are set in RAMCFG SRAM2 interrupt status register (RAMCFG_M2ISR) and RAMCFG SRAM2 interrupt clear register (RAMCFG_M2ICR) . An interrupt or NMI can be generated if enabled by the PEIE or PENMI bits in the RAMCFG SRAM2 interrupt enable register (RAMCFG_M2IER) . When the ALE bit is set in RAMCFG SRAM2 control register (RAMCFG_M2CR) , the failing parity SRAM offset word address is stored in the RAMCFG SRAM2 parity error address register (RAMCFG_M2PEAR) , together with the failing byte(s) parity error flag and the AHB bus master ID.

When the PED and CPED bits are already set any subsequent parity failing access SRAM offset word address is no longer updated. A new parity error SRAM offset word address is only latched when PED and CPED are 0.

Unaligned word and half word accesses can generate a parity error on bytes not belonging to the accessed data (see Table 34 ).

Table 34. SRAM parity access error

Table 35. SRAM parity error bus master ID

6.3.3 Internal SRAM write protection

The SRAM2 is made of 64 1-Kbyte write protect pages, each can be write-protected by setting its corresponding PxWP (x = 0 to 63) bit in the RAMCFG SRAM2 write protection register 1 (RAMCFG_M2WPR1) and RAMCFG SRAM2 write protection register 2 (RAMCFG_M2WPR2) .

When writing to a write-protected page, the write is ignored and a bus error is generated.

Any SRAM erase operation erases the write-protected pages as well.

6.3.4 Internal SRAM read access latency

To read correctly data, the number of wait states (WS) must be correctly programmed in the WSC[2:0] field of the RAM control register, depending upon the voltage scaling range for SRAM1 and SRAM2, and upon AHB hclk1 clock frequency (see Table 36 ).

Table 36. Number of wait states versus hclk frequency and voltage range scaling

After reset, the SRAM1 and SRAM2 hclk1 frequency is 16 MHz, 1 wait state (WSC) is configured in RAMCFG_MxCR.

Before entering Stop 1 mode, the software must set SRAM1 and SRAM2 wait states to at least 1 in RAMCFG_MxCR, to comply with the SYSCLK 16 MHz and range 2 configuration when exiting the mode.

6.3.5 Internal SRAM erase

SRAM erase can be requested by executing this software sequence:

1. 1. Write 0xCA in the RAMCFG SRAMx erase key register (RAMCFG_MxERKEYR) .
2. 2. Write 0x53 in the RAMCFG SRAMx erase key register (RAMCFG_MxERKEYR) .
3. 3. Write 1 in the SRAMER bit of the RAMCFG SRAM1 control register (RAMCFG_M1CR) .

SRAM erase can also start because of a tamper (see Section 37: Tamper and backup registers (TAMP) ), or upon a reset condition (see Section 7.4: FLASH option bytes ).

SRAMBUSY flag is set in the related SRAM interrupt status register as long as the erase is ongoing.

The total duration of each SRAM erase is N x AHB clock cycles, where N is the size of the SRAM in 32-bit words.

If the SRAM is read while an erase is ongoing, default zero data is read on the AHB bus.

If the SRAM is written while an erase is ongoing, wait states are inserted on the AHB bus until the end of the erase operation.

An SRAM erase operation also erases write-protected pages.

6.4 RAMCFG low-power modes

Table 37. Effect of low-power modes on RAMCFG

6.5 RAMCFG interrupts

Table 38. RAMCFG interrupt requests

1. Stop 0 mode only.

6.6 RAMCFG registers

In the registers described below, x refers to SRAM index.

Access to all RAMCFG registers can be protected by GTZC_TZSC RAMCFGSEC and GTZC_TZSC RAMCFGSPRIV.

6.6.1 RAMCFG SRAM1 control register (RAMCFG_M1CR)

Address offset: 0x000

Reset value: 0x0001 0000

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:16 WSC[2:0] : SRAM1 wait state configuration

This field is used to program the number of wait states inserted on the AHB when reading the SRAM1, depending on its access time.

000: Zero wait states

001: One wait state

...

111: Seven wait states

Note: Before entering Stop 1 mode, software must set SRAM1 wait states to at least 1.

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 SRAMER : SRAM1 erase

This bit can be set by software only after writing the unlock sequence in the ERASEKEY field of the RAMCFG_M1ERKEYR register. Setting this bit starts the SRAM1 erase. This bit is automatically cleared by hardware at the end of the erase operation.

0: No erase operation ongoing

1: Erase operation ongoing

Bits 7:0 Reserved, must be kept at reset value.

6.6.2 RAMCFG SRAM1 interrupt status register (RAMCFG_M1ISR)

Address offset: 0x008

Reset value: 0x0000 0000

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 SRAMBUSY : SRAM busy with erase operation.

0: No memory erase operation ongoing

1: Memory erase operation ongoing

Note: Depending on the SRAM, the erase operation can be performed due to software request, system reset if the enabled by user option, tamper detection or RDP regression. Refer to Table 33.

Bits 7:0 Reserved, must be kept at reset value.

6.6.3 RAMCFG SRAMx erase key register (RAMCFG_MxERKEYR)

Address offset: \( 0x028 + 0x040 * (x - 1) \) , ( \( x = 1 \) to \( 2 \) )

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 ERASEKEY[7:0] : Erase write protection key

The following steps are required to unlock the write protection of the SRAMER bit in the RAMCFG_MxCR register.

1. a) Write 0xCA into ERASEKEY[7:0]
2. b) Write 0x53 into ERASEKEY[7:0]

Note: Writing a wrong key reactivates the write protection.

6.6.4 RAMCFG SRAM2 control register (RAMCFG_M2CR)

Address offset: 0x040

Reset value: 0x0001 0000

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:16 WSC[2:0] : SRAM2 wait state configuration

This field is used to program the number of wait states inserted on the AHB when reading the SRAM2, depending on its access time.

000: 0 wait state

001: 1 wait state

...

111: 7 wait states

Note: Before entering Stop 1 mode software must set SRAM2 wait states to at least 1.

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 SRAMER : SRAM2 erase

This bit can be set by software only after writing the unlock sequence in the ERASEKEY field of the RAMCFG_M2ERKEYR register. Setting this bit starts the SRAM2 erase. This bit is automatically cleared by hardware at the end of the erase operation.

0: No erase operation ongoing

1: Erase operation ongoing

Bits 7:5 Reserved, must be kept at reset value.

Bit 4 ALE : SRAM2 parity fail address latch enable

0: Failing address not stored in the SRAM2 parity error address register RAMCFG_M2PEAR

1: Failing address stored in the SRAM2 parity error address register RAMCFG_M2PEAR

Bits 3:0 Reserved, must be kept at reset value.

6.6.5 RAMCFG SRAM2 interrupt enable register (RAMCFG_M2IER)

Address offset: 0x044

Reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 PENMI : Parity error NMI.

This bit is set by software and cleared only by a global RAMCFG reset

0: NMI not generated in case of parity error

1: NMI generated in case of parity error

Note: When PENMI bit is set, the RAMCFG maskable interrupt is not generated for a parity error whatever PEIE bit value.

Bit 2 Reserved, must be kept at reset value.

Bit 1 PEIE : Parity error interrupt enable

0: Parity error interrupt disabled

1: Parity error interrupt enabled

Bit 0 Reserved, must be kept at reset value.

6.6.6 RAMCFG SRAM2 interrupt status register (RAMCFG_M2ISR)

Address offset: 0x048

Reset value: 0x0000 0000

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 SRAMBUSY : SRAM2 busy with erase operation.

0: No memory erase operation ongoing

1: Memory erase operation ongoing

Note: Depending on the SRAM2, the erase operation can be performed due to software request, system reset if the enabled by user option, tamper detection or RDP regression. Refer to Table 33.

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 PED : Parity error detected

0: No parity error detected

1: Parity error detected

Bit 0 Reserved, must be kept at reset value.

6.6.7 RAMCFG SRAM2 parity error address register (RAMCFG_M2PEAR)

Address offset: 0x050

Reset value: 0x0000 0000

Bits 31:28 BYTE[3:0] : Byte parity error flag.

When ALE bit is set in RAMCFG_M2CR register, this field is updated when PED and CPED are zero and a new parity error is detected, with:

1xxx: parity error detected on fourth byte in word aligned address

x1xx: parity error detected on third byte in word aligned address

xx1x: parity error detected on second byte in word aligned address

xxx1: parity error detected on first byte in word aligned address

Bits 27:24 ID[3:0] : Parity error AHB bus master ID.

When ALE bit is set in RAMCFG_M2CR register, this field is updated when PED and CPED are zero and a new parity error is detected, with:

010: parity error detected on CPU access
011: parity error detected on Debugger access
110: parity error detected on DMA master port 0 access
111: parity error detected on DMA master port 1 access
Others: reserved

Bits 23:16 Reserved, must be kept at reset value.

Bits 15:0 PEA[15:0] : Parity error SRAM word aligned address offset.PEA[1:0] read 0b00.

When ALE bit is set in RAMCFG_M2CR register, this field is updated when PED and CPED are zero and a new parity error is detected, with the SRAM word aligned address offset corresponding to the parity error.

6.6.8 RAMCFG SRAM2 interrupt clear register (RAMCFG_M2ICR)

Address offset: 0x054
Reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 CPED : Clear parity error detect bit

Writing 1 to this bit clears the PED bit in RAMCFG_M2ISR.

Reading this bit returns the value of the RAMCFG_M2ISR PED bit.

Bit 0 Reserved, must be kept at reset value.

6.6.9 RAMCFG SRAM2 write protection register 1 (RAMCFG_M2WPR1)

Address offset: 0x058
Reset value: 0x0000 0000

Bits 31:0 PyWP : SRAM2 1-Kbyte write protect page y write protection (y = 31 to 0)

These bits are set by software and cleared only by a system reset.

0: Write protection of SRAM2 1-Kbyte write protect page y is disabled.

1: Write protection of SRAM2 1-Kbyte write protect page y is enabled.

6.6.10 RAMCFG SRAM2 write protection register 2 (RAMCFG_M2WPR2)

Address offset: 0x05C

Reset value: 0x0000 0000

Bits 31:0 PyWP : SRAM2 1-Kbyte write protect page y write protection (y = 63 to 32)

These bits are set by software and cleared only by a system reset.

0: Write protection of SRAM2 1-Kbyte write protect page y is disabled.

1: Write protection of SRAM2 1-Kbyte write protect page y is enabled.

6.6.11 RAMCFG register map

Table 39. RAMCFG register map and reset values