RM0493-STM32WBA5

Introduction

This document is addressed to application developers. It provides complete information on how to use the STM32WBA50/52/54/55xx (hereinafter referred to as STM32WBA5xxx) microcontrollers.

These MCUs include ST state-of-the-art patented technology, and feature 2.4 GHz wireless radio, embedded memories, and peripherals. They are based on a single core (Arm ^®Cortex ^®-M33), with the following memory configurations:

• For STM32WBA52/54/55xx devices
- – 1-Mbyte flash + 128-Kbyte SRAM (STM32WBA52/54/55xGx)
- – 512-Kbyte flash + 96-Kbyte SRAM (STM32WBA52/54/55xEx)
• For STM32WBA50xx devices
- – 1-Mbyte flash + 64-Kbyte SRAM (STM32WBA50xGx)

Related documents (available from STMicroelectronics web site www.st.com ):

• STM32WBA5xxx datasheets
• STM32WBA5xxx erratas

1 Documentation conventions . . . . . 70
- 1.1 General information . . . . . 70
- 1.2 List of abbreviations for registers . . . . . 70
- 1.3 Register reset value . . . . . 70
- 1.4 Glossary . . . . . 71
2 Memory and bus architecture . . . . . 72
- 2.1 System architecture . . . . . 72
  - 2.1.1 CPU C-bus . . . . . 73
  - 2.1.2 CPU S-bus . . . . . 73
  - 2.1.3 GPDMA1-bus . . . . . 73
  - 2.1.4 Bus matrix . . . . . 74
  - 2.1.5 AHB/APB bridges . . . . . 74
- 2.2 TrustZone ^®security architecture . . . . . 74
  - 2.2.1 Default TrustZone security state . . . . . 76
  - 2.2.2 TrustZone peripheral classification . . . . . 76
- 2.3 Memory organization . . . . . 79
  - 2.3.1 Introduction . . . . . 79
  - 2.3.2 Memory map and register boundary addresses . . . . . 80
  - 2.3.3 Embedded SRAM . . . . . 85
  - 2.3.4 Flash memory overview . . . . . 85
3 System security . . . . . 86
- 3.1 Key security features . . . . . 86
- 3.2 Secure firmware install ^(a). . . . . 87
- 3.3 Secure boot ^(a). . . . . 87
  - 3.3.1 Unique boot entry and BOOT_LOCK . . . . . 88
  - 3.3.2 Immutable root of trust in system flash memory . . . . . 88
- 3.4 Secure firmware update . . . . . 88
- 3.5 Resource isolation using TrustZone ^(a). . . . . 88
  - 3.5.1 TrustZone security architecture . . . . . 89
  - 3.5.2 Armv8-M security extension of Cortex-M33 . . . . . 89
  - 3.5.3 Memory and peripheral allocation using IDAU/SAU . . . . . 90

3.5.4	Memory and peripheral allocation using GTZC .....	92
3.5.5	Managing security in TrustZone-aware peripherals .....	94
3.5.6	Activating TrustZone security .....	101
3.5.7	Deactivating TrustZone security .....	101
3.6	Isolation of other resources .....	102
3.6.1	Temporal isolation using secure hide protection (HDP) .....	102
3.6.2	RSSLIB functions .....	102
3.6.3	Resource isolation using Cortex privileged mode .....	103
3.7	Secure execution .....	107
3.7.1	Memory protection unit (MPU) .....	107
3.7.2	Embedded flash memory write protection .....	107
3.7.3	Tamper detection and response .....	108
3.8	Secure storage .....	110
3.8.1	Hardware secret key management .....	111
3.9	Unique ID .....	112
3.10	Crypto engines .....	112
3.10.1	Crypto engines features .....	112
3.10.2	Secure AES coprocessor (SAES) .....	113
3.11	Product life cycle .....	113
3.11.1	Life-cycle management with readout protection (RDP) .....	115
3.11.2	Recommended option byte settings .....	118
3.12	Access controlled debug .....	118
3.12.1	Debug protection with readout protection (RDP) .....	118
3.13	Software intellectual property protection and collaborative development .....	119
3.13.1	Software intellectual property protection with RDP .....	119
3.13.2	Other software intellectual property protections .....	120
4	Boot modes .....	121
5	Global TrustZone® controller (GTZC) .....	124
5.1	Introduction .....	124
5.2	GTZC main features .....	124
5.3	GTZC implementation .....	126
5.4	GTZC functional description .....	127
5.4.1	GTZC block diagram .....	127
5.4.2	Illegal access definition .....	128

5.4.3	TrustZone security controller (TZSC) . . . . .	129
5.4.4	Memory protection controller - block based (MPCBB) . . . . .	129
5.4.5	TrustZone illegal access controller (TZIC) . . . . .	129
5.4.6	Power-on/reset state . . . . .	130
5.5	GTZC interrupts . . . . .	130
5.6	GTZC1 TZSC registers . . . . .	131
5.6.1	GTZC1 TZSC control register (GTZC1_TZSC_CR) . . . . .	131
5.6.2	GTZC1 TZSC secure configuration register 1 (GTZC1_TZSC_SECCFGR1) . . . . .	131
5.6.3	GTZC1 TZSC secure configuration register 2 (GTZC1_TZSC_SECCFGR2) . . . . .	132
5.6.4	GTZC1 TZSC secure configuration register 3 (GTZC1_TZSC_SECCFGR3) . . . . .	134
5.6.5	GTZC1 TZSC privilege configuration register 1 (GTZC1_TZSC_PRIVCFGR1) . . . . .	136
5.6.6	GTZC1 TZSC privilege configuration register 2 (GTZC1_TZSC_PRIVCFGR2) . . . . .	137
5.6.7	GTZC1 TZSC privilege configuration register 3 (GTZC1_TZSC_PRIVCFGR3) . . . . .	138
5.6.8	GTZC1 TZSC register map . . . . .	141
5.7	GTZC1 TZIC registers . . . . .	142
5.7.1	GTZC1 TZIC interrupt enable register 1 (GTZC1_TZIC_IER1) . . . . .	142
5.7.2	GTZC1 TZIC interrupt enable register 2 (GTZC1_TZIC_IER2) . . . . .	143
5.7.3	GTZC1 TZIC interrupt enable register 3 (GTZC1_TZIC_IER3) . . . . .	144
5.7.4	GTZC1 TZIC interrupt enable register 4 (GTZC1_TZIC_IER4) . . . . .	146
5.7.5	GTZC1 TZIC status register 1 (GTZC1_TZIC_SR1) . . . . .	147
5.7.6	GTZC1 TZIC status register 2 (GTZC1_TZIC_SR2) . . . . .	148
5.7.7	GTZC1 TZIC status register 3 (GTZC1_TZIC_SR3) . . . . .	150
5.7.8	GTZC1 TZIC status register 4 (GTZC1_TZIC_SR4) . . . . .	151
5.7.9	GTZC1 TZIC flag clear register 1 (GTZC1_TZIC_FCR1) . . . . .	153
5.7.10	GTZC1 TZIC flag clear register 2 (GTZC1_TZIC_FCR2) . . . . .	154
5.7.11	GTZC1 TZIC flag clear register 3 (GTZC1_TZIC_FCR3) . . . . .	155
5.7.12	GTZC1 TZIC flag clear register 4 (GTZC1_TZIC_FCR4) . . . . .	157
5.7.13	GTZC1 TZIC register map . . . . .	159
5.8	GTZC1 MPCBB registers . . . . .	160
5.8.1	GTZC1 MPCBB control register (GTZC1_MPCBB_CR) . . . . .	160
5.8.2	GTZC1 MPCBB configuration lock register (GTZC1_MPCBB_CFGLOCK) . . . . .	161

5.8.3	GTZC1 MPCBB security configuration for super-block n register (GTZC1_MPCBB_SECCFGGRn) .....	161
5.8.4	GTZC1 MPCBB privileged configuration for super-block n register (GTZC1_MPCBB_PRIVCFGGRn) .....	162
5.8.5	GTZC1 MPCBB1 and MPCBB2 register map .....	163
5.8.6	GTZC1 MPCBB6 register map .....	164
6	RAMs configuration controller (RAMCFG) .....	165
6.1	Introduction .....	165
6.2	RAMCFG main features .....	165
6.3	RAMCFG functional description .....	165
6.3.1	Internal SRAMs features .....	165
6.3.2	Internal SRAM parity .....	166
6.3.3	Internal SRAM write protection .....	167
6.3.4	Internal SRAM read access latency .....	167
6.3.5	Internal SRAM erase .....	168
6.4	RAMCFG low-power modes .....	168
6.5	RAMCFG interrupts .....	168
6.6	RAMCFG registers .....	169
6.6.1	RAMCFG SRAM1 control register (RAMCFG_M1CR) .....	169
6.6.2	RAMCFG SRAM1 interrupt status register (RAMCFG_M1ISR) .....	169
6.6.3	RAMCFG SRAMx erase key register (RAMCFG_MxERKEYR) .....	170
6.6.4	RAMCFG SRAM2 control register (RAMCFG_M2CR) .....	170
6.6.5	RAMCFG SRAM2 interrupt enable register (RAMCFG_M2IER) .....	171
6.6.6	RAMCFG SRAM2 interrupt status register (RAMCFG_M2ISR) .....	172
6.6.7	RAMCFG SRAM2 parity error address register (RAMCFG_M2PEAR) .....	172
6.6.8	RAMCFG SRAM2 interrupt clear register (RAMCFG_M2ICR) .....	173
6.6.9	RAMCFG SRAM2 write protection register 1 (RAMCFG_M2WPR1) .....	173
6.6.10	RAMCFG SRAM2 write protection register 2 (RAMCFG_M2WPR2) .....	174
6.6.11	RAMCFG register map .....	175
7	Embedded flash memory (FLASH) .....	176
7.1	Introduction .....	176
7.2	FLASH main features .....	176
7.3	FLASH functional description .....	177

7.3.1	Flash memory organization . . . . .	177
7.3.2	Error code correction (ECC) . . . . .	178
7.3.3	Read access latency . . . . .	179
7.3.4	Flash power-down mode . . . . .	181
7.3.5	Flash memory program and erase operations . . . . .	181
7.3.6	Flash memory erase sequences . . . . .	183
7.3.7	Flash memory programming sequences . . . . .	184
7.3.8	Flash memory programming erase suspend . . . . .	187
7.3.9	Flash memory endurance . . . . .	188
7.3.10	Flash memory errors flags . . . . .	189
7.3.11	Power-down during programming or erase operations . . . . .	190
7.3.12	Reset during programming or erase operations . . . . .	190
7.4	FLASH option bytes . . . . .	192
7.4.1	Option bytes description . . . . .	192
7.4.2	Option bytes programming . . . . .	192
7.5	FLASH TrustZone security and privilege protections . . . . .	194
7.5.1	Trustzone security protection . . . . .	194
7.5.2	Watermark-based secure flash memory area protection . . . . .	195
7.5.3	Secure hide protection (HDP) . . . . .	196
7.5.4	Block-based secure flash memory area protection . . . . .	197
7.5.5	Flash security attribute state . . . . .	197
7.5.6	Block-based privileged flash memory area protection . . . . .	198
7.5.7	Flash memory registers privileged and unprivileged modes . . . . .	198
7.6	Flash memory protection . . . . .	198
7.6.1	Write protection (WRP) . . . . .	199
7.6.2	Readout protection (RDP) . . . . .	200
7.7	Summary of flash memory and registers access control . . . . .	209
7.8	FLASH interrupts . . . . .	212
7.9	FLASH registers . . . . .	214
7.9.1	FLASH access control register (FLASH_ACR) . . . . .	214
7.9.2	FLASH key register (FLASH_NSKEYR) . . . . .	215
7.9.3	FLASH secure key register (FLASH_SECKEYR) . . . . .	216
7.9.4	FLASH option key register (FLASH_OPTKEYR) . . . . .	216
7.9.5	FLASH power-down key register (FLASH_PDKEYR) . . . . .	217
7.9.6	FLASH status register (FLASH_NSSR) . . . . .	217
7.9.7	FLASH secure status register (FLASH_SECSR) . . . . .	219

7.9.8	FLASH control register (FLASH_NSCR1) . . . . .	220
7.9.9	FLASH secure control register (FLASH_SECCR1) . . . . .	222
7.9.10	FLASH ECC register (FLASH_ECCR) . . . . .	223
7.9.11	FLASH operation status register (FLASH_OPSR) . . . . .	224
7.9.12	FLASH control 2 register (FLASH_NSCR2) . . . . .	225
7.9.13	FLASH secure control 2 register (FLASH_SECCR2) . . . . .	226
7.9.14	FLASH option register (FLASH_OPTR) . . . . .	226
7.9.15	FLASH boot address 0 register (FLASH_NSBOOTADD0R) . . . . .	228
7.9.16	FLASH boot address 1 register (FLASH_NSBOOTADD1R) . . . . .	229
7.9.17	FLASH secure boot address 0 register (FLASH_SECBOOTADD0R) . . . . .	229
7.9.18	FLASH secure watermark register 1 (FLASH_SECWMR1) . . . . .	230
7.9.19	FLASH secure watermark register 2 (FLASH_SECWMR2) . . . . .	231
7.9.20	FLASH WRP area A address register (FLASH_WRPAR) . . . . .	231
7.9.21	FLASH WRP area B address register (FLASH_WRPBR) . . . . .	232
7.9.22	FLASH OEM1 key register 1 (FLASH_OEM1KEYR1) . . . . .	233
7.9.23	FLASH OEM1 key register 2 (FLASH_OEM1KEYR2) . . . . .	233
7.9.24	FLASH OEM2 key register 1 (FLASH_OEM2KEYR1) . . . . .	234
7.9.25	FLASH OEM2 key register 2 (FLASH_OEM2KEYR2) . . . . .	234
7.9.26	FLASH secure block based register x (FLASH_SECBBRx) . . . . .	234
7.9.27	FLASH secure HDP control register (FLASH_SECHDPCR) . . . . .	235
7.9.28	FLASH privilege configuration register (FLASH_PRIFCFGGR) . . . . .	235
7.9.29	FLASH privilege block based register x (FLASH_PRIVBBRx) . . . . .	236
7.9.30	FLASH register map . . . . .	237
8	Instruction cache (ICACHE) . . . . .	241
8.1	ICACHE introduction . . . . .	241
8.2	ICACHE main features . . . . .	241
8.3	ICACHE implementation . . . . .	242
8.4	ICACHE functional description . . . . .	242
8.4.1	ICACHE block diagram . . . . .	243
8.4.2	ICACHE reset and clocks . . . . .	243
8.4.3	ICACHE TAG memory . . . . .	244
8.4.4	Direct-mapped ICACHE (1-way cache) . . . . .	245
8.4.5	ICACHE enable . . . . .	246
8.4.6	Cacheable and noncacheable traffic . . . . .	246
8.4.7	Address remapping . . . . .	247
8.4.8	Cacheable accesses . . . . .	249

- 8.4.9 Dual-master cache . . . . . 250
- 8.4.10 ICACHE security . . . . . 250
- 8.4.11 ICACHE maintenance . . . . . 250
- 8.4.12 ICACHE performance monitoring . . . . . 251
- 8.4.13 ICACHE boot . . . . . 251
8.5 ICACHE low-power modes . . . . . 251
8.6 ICACHE error management and interrupts . . . . . 252
8.7 ICACHE registers . . . . . 252
- 8.7.1 ICACHE control register (ICACHE_CR) . . . . . 252
- 8.7.2 ICACHE status register (ICACHE_SR) . . . . . 253
- 8.7.3 ICACHE interrupt enable register (ICACHE_IER) . . . . . 254
- 8.7.4 ICACHE flag clear register (ICACHE_FCR) . . . . . 254
- 8.7.5 ICACHE hit monitor register (ICACHE_HMONR) . . . . . 255
- 8.7.6 ICACHE miss monitor register (ICACHE_MMONR) . . . . . 255
- 8.7.7 ICACHE region x configuration register (ICACHE_CRRx) . . . . . 255
- 8.7.8 ICACHE register map . . . . . 257

9 Radio system . . . . . 258
- 9.1 Introduction . . . . . 258
- 9.2 Main features . . . . . 258
- 9.3 2.4 GHz RADIO implementation . . . . . 259
- 9.4 Functional description . . . . . 259
  - 9.4.1 Block diagram . . . . . 259
  - 9.4.2 Pins and internal signals . . . . . 259
  - 9.4.3 Transmit output power . . . . . 260
  - 9.4.4 Bluetooth® LE AoA and AoD . . . . . 261
  - 9.4.5 RXTX data SRAM access . . . . . 261
- 9.5 Low-power modes . . . . . 262

10 PTA converter (PTACONV) . . . . . 263
- 10.1 PTACONV introduction . . . . . 263
- 10.2 PTACONV main features . . . . . 263
- 10.3 PTACONV functional description . . . . . 263
  - 10.3.1 PTACONV block diagram . . . . . 264
  - 10.3.2 PTACONV pins and internal signals . . . . . 264
  - 10.3.3 PTACONV protocols . . . . . 265

10.3.4	PTACONV interface with the 2.4 GHz RADIO . . . . .	268
10.4	Low-power modes . . . . .	268
10.5	PTACONV registers . . . . .	270
10.5.1	PTACONV active control register (PTACONV_ACTCR) . . . . .	270
10.5.2	PTACONV priority control register (PTACONV_PRICR) . . . . .	270
10.5.3	PTACONV control register (PTACONV_CR) . . . . .	271
10.5.4	PTACONV register map . . . . .	272
11	Power control (PWR) . . . . .	273
11.1	Introduction . . . . .	273
11.2	PWR main features . . . . .	273
11.3	PWR pins and internal signals . . . . .	274
11.4	PWR power supplies and supply domains . . . . .	276
11.4.1	External power supplies . . . . .	277
11.4.2	Application RADIO power supply schemes . . . . .	278
11.4.3	Power-up and power-down power sequences . . . . .	279
11.4.4	Independent analog peripherals supply . . . . .	279
11.4.5	Radio peripherals supply . . . . .	279
11.4.6	Backup domain . . . . .	279
11.4.7	Internal regulators . . . . .	280
11.5	PWR system supply voltage regulation . . . . .	280
11.5.1	SMPS and LDO embedded regulators . . . . .	280
11.5.2	LDO and SMPS versus reset, voltage scaling, and low-power modes . . . . .	280
11.5.3	LDO and SMPS step-down converter fast startup . . . . .	281
11.5.4	Dynamic voltage scaling management . . . . .	281
11.5.5	2.4 GHz RADIO PA regulator . . . . .	282
11.6	PWR power supply supervision . . . . .	282
11.6.1	Brownout reset (BOR) . . . . .	282
11.6.2	Programmable voltage detector (PVD) . . . . .	283
11.7	PWR power management . . . . .	285
11.7.1	PWR power modes . . . . .	285
11.7.2	PWR background autonomous mode (BAM) . . . . .	291
11.7.3	PWR Run mode . . . . .	293
11.7.4	PWR low-power modes . . . . .	293
11.7.5	PWR Sleep mode . . . . .	294
11.7.6	PWR Stop 0 mode . . . . .	295

11.7.7	PWR Stop 1 mode . . . . .	299
11.7.8	PWR Standby mode . . . . .	300
11.7.9	Power modes output pins . . . . .	303
11.8	PWR security and privileged protection . . . . .	303
11.8.1	PWR security protection . . . . .	303
11.8.2	PWR privileged protection . . . . .	305
11.9	PWR interrupts . . . . .	306
11.10	PWR registers . . . . .	307
11.10.1	PWR control register 1 (PWR_CR1) . . . . .	307
11.10.2	PWR control register 2 (PWR_CR2) . . . . .	308
11.10.3	PWR control register 3 (PWR_CR3) . . . . .	309
11.10.4	PWR voltage scaling register (PWR_VOSR) . . . . .	309
11.10.5	PWR supply voltage monitoring control register (PWR_SVMCR) . . . . .	310
11.10.6	PWR wake-up control register 1 (PWR_WUCR1) . . . . .	311
11.10.7	PWR wake-up control register 2 (PWR_WUCR2) . . . . .	312
11.10.8	PWR wake-up control register 3 (PWR_WUCR3) . . . . .	313
11.10.9	PWR disable Backup domain register (PWR_DBPR) . . . . .	315
11.10.10	PWR security configuration register (PWR_SECCFGR) . . . . .	316
11.10.11	PWR privilege control register (PWR_PRIVCFGR) . . . . .	317
11.10.12	PWR status register (PWR_SR) . . . . .	318
11.10.13	PWR supply voltage monitoring status register (PWR_SVMSR) . . . . .	319
11.10.14	PWR wake-up status register (PWR_WUSR) . . . . .	319
11.10.15	PWR wake-up status clear register (PWR_WUSCR) . . . . .	320
11.10.16	PWR port A Standby IO retention enable register (PWR_IORETENRA) . . . . .	322
11.10.17	PWR port A Standby IO retention status register (PWR_IORETRA) . . . . .	322
11.10.18	PWR port B Standby IO retention enable register (PWR_IORETENRB) . . . . .	323
11.10.19	PWR port B Standby IO retention status register (PWR_IORETRB) . . . . .	323
11.10.20	PWR port C Standby IO retention enable register (PWR_IORETENRC) . . . . .	324
11.10.21	PWR port C Standby IO retention status register (PWR_IORETRC) . . . . .	324
11.10.22	PWR port H Standby IO retention enable register (PWR_IORETENRH) . . . . .	325
11.10.23	PWR port H Standby IO retention status register (PWR_IORETRH) . . . . .	325
11.10.24	PWR 2.4 GHz RADIO status and control register (PWR_RADIOSCR) . . . . .	326
11.10.25	PWR register map . . . . .	328

12	Reset and clock control (RCC) . . . . .	331
12.1	Introduction . . . . .	331
12.2	RCC pins and internal signals . . . . .	331
12.3	RCC reset functional description . . . . .	331
12.3.1	Power reset . . . . .	331
12.3.2	System reset . . . . .	332
12.3.3	Backup domain reset . . . . .	333
12.3.4	Individual peripheral reset . . . . .	333
12.3.5	CPU reset . . . . .	333
12.4	RCC clocks functional description . . . . .	333
12.4.1	HSE32 clock with trimming . . . . .	335
12.4.2	HSI16 clock . . . . .	337
12.4.3	PLL1 . . . . .	338
12.4.4	LSE clock . . . . .	339
12.4.5	LSI clock . . . . .	341
12.4.6	System clock (SYSCLK) selection . . . . .	343
12.4.7	Clock source frequency versus voltage scaling . . . . .	344
12.4.8	HSE32 clock security system (HSECSS) . . . . .	345
12.4.9	LSE clock security system on (LSECSS) . . . . .	345
12.4.10	ADC kernel clock . . . . .	346
12.4.11	RTC and TAMP kernel clock . . . . .	346
12.4.12	2.4 GHz RADIO bus clocks . . . . .	346
12.4.13	2.4 GHz RADIO kernel clocks . . . . .	347
12.4.14	Timer kernel clock . . . . .	348
12.4.15	Independent watchdog kernel clock . . . . .	348
12.4.16	SysTick calibration value register . . . . .	348
12.4.17	Clock-out capability . . . . .	349
12.4.18	Internal/external clock measurement . . . . .	350
12.4.19	Audio synchronization . . . . .	351
12.4.20	Peripherals clock gating and autonomous mode . . . . .	353
12.5	RCC security and privilege functional description . . . . .	355
12.5.1	RCC TrustZone® security protection modes . . . . .	355
12.5.2	RCC privilege protection modes . . . . .	357
12.6	RCC low-power modes . . . . .	358
12.7	RCC interrupts . . . . .	359
12.8	RCC registers . . . . .	360

12.8.1	RCC clock control register (RCC_CR) . . . . .	360
12.8.2	RCC internal clock sources calibration register 3 (RCC_ICSCR3) . . .	362
12.8.3	RCC clock configuration register 1 (RCC_CFGR1) . . . . .	363
12.8.4	RCC clock configuration register 2 (RCC_CFGR2) . . . . .	364
12.8.5	RCC clock configuration register 3 (RCC_CFGR3) . . . . .	365
12.8.6	RCC PLL1 configuration register (RCC_PLL1CFGR) . . . . .	366
12.8.7	RCC PLL1 dividers register (RCC_PLL1DIVR) . . . . .	368
12.8.8	RCC PLL1 fractional divider register (RCC_PLL1FRACR) . . . . .	369
12.8.9	RCC clock interrupt enable register (RCC_CIER) . . . . .	370
12.8.10	RCC clock interrupt flag register (RCC_CIFR) . . . . .	372
12.8.11	RCC clock interrupt clear register (RCC_CICR) . . . . .	373
12.8.12	RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . .	375
12.8.13	RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . .	376
12.8.14	RCC AHB4 peripheral reset register (RCC_AHB4RSTR) . . . . .	378
12.8.15	RCC AHB5 peripheral reset register (RCC_AHB5RSTR) . . . . .	378
12.8.16	RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . .	379
12.8.17	RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . .	380
12.8.18	RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .	381
12.8.19	RCC APB7 peripheral reset register (RCC_APB7RSTR) . . . . .	382
12.8.20	RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . .	384
12.8.21	RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . .	386
12.8.22	RCC AHB4 peripheral clock enable register (RCC_AHB4ENR) . . . . .	388
12.8.23	RCC AHB5 peripheral clock enable register (RCC_AHB5ENR) . . . . .	389
12.8.24	RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . . .	390
12.8.25	RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . . .	391
12.8.26	RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .	392
12.8.27	RCC APB7 peripheral clock enable register (RCC_APB7ENR) . . . . .	394
12.8.28	RCC AHB1 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB1SMENR) . . . . .	395
12.8.29	RCC AHB2 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB2SMENR) . . . . .	397
12.8.30	RCC AHB4 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB4SMENR) . . . . .	400
12.8.31	RCC AHB5 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB5SMENR) . . . . .	400
12.8.32	RCC APB1 peripheral clocks enable in Sleep and Stop modes register 1 (RCC_APB1SMENR1) . . . . .	401
12.8.33	RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2 (RCC_APB1SMENR2) . . . . .	403

12.8.34	RCC APB2 peripheral clocks enable in Sleep and Stop modes register (RCC_APB2SMENR) .....	403
12.8.35	RCC APB7 peripheral clock enable in Sleep and Stop modes register (RCC_APB7SMENR) .....	405
12.8.36	RCC peripherals independent clock configuration register 1 (RCC_CCIPR1) .....	407
12.8.37	RCC peripherals independent clock configuration register 2 (RCC_CCIPR2) .....	410
12.8.38	RCC peripherals independent clock configuration register 3 (RCC_CCIPR3) .....	411
12.8.39	RCC Backup domain control register (RCC_BDCR1) .....	412
12.8.40	RCC control/status register (RCC_CSR) .....	417
12.8.41	RCC Backup domain control register (RCC_BDCR2) .....	419
12.8.42	RCC secure configuration register (RCC_SECCFGR) .....	420
12.8.43	RCC privilege configuration register (RCC_PRIVCFGR) .....	421
12.8.44	RCC audio synchronization control register (RCC_ASCR) .....	422
12.8.45	RCC audio synchronization interrupt enable register (RCC_ASIER) .....	422
12.8.46	RCC audio synchronization status register (RCC_ASSR) .....	423
12.8.47	RCC auto-reload register (RCC_ASCNTR) .....	424
12.8.48	RCC auto-reload register (RCC_ASARR) .....	424
12.8.49	RCC capture register (RCC_ASCAR) .....	425
12.8.50	RCC compare register (RCC_ASCOR) .....	425
12.8.51	RCC clock configuration register 2 (RCC_CFGR4) .....	426
12.8.52	RCC RADIO peripheral clock enable register (RCC_RADIOENR) .....	427
12.8.53	RCC external clock sources calibration register 1(RCC_ECSCR1) ..	428
12.8.54	RCC register map .....	429
13	Hardware semaphore (HSEM) .....	435
13.1	Introduction .....	435
13.2	Main features .....	435
13.3	Functional description .....	436
13.3.1	HSEM block diagram .....	436
13.3.2	HSEM internal signals .....	436
13.3.3	HSEM lock procedures .....	436
13.3.4	HSEM write/read/read lock register address .....	438
13.3.5	HSEM unlock procedures .....	438
13.3.6	HSEM LOCKID semaphore clear .....	439
13.3.7	HSEM interrupts .....	439

13.3.8	Semaphore attributes . . . . .	441
13.4	HSEM registers . . . . .	443
13.4.1	HSEM register semaphore x (HSEM_Rx) . . . . .	443
13.4.2	HSEM read lock register semaphore x (HSEM_RLRx) . . . . .	445
13.4.3	HSEM non-secure interrupt enable register (HSEM_IER) . . . . .	446
13.4.4	HSEM non-secure interrupt clear register (HSEM_ICR) . . . . .	447
13.4.5	HSEM non-secure interrupt status register (HSEM_ISR) . . . . .	447
13.4.6	HSEM non-secure interrupt status register (HSEM_MISR) . . . . .	448
13.4.7	HSEM secure interrupt enable register (HSEM_SIER) . . . . .	449
13.4.8	HSEM secure interrupt clear register (HSEM_SICR) . . . . .	449
13.4.9	HSEM secure interrupt status register (HSEM_SISR) . . . . .	450
13.4.10	HSEM secure masked interrupt status register (HSEM_MSISR) . . . . .	451
13.4.11	HSEM security configuration register (HSEM_SECCFGR) . . . . .	451
13.4.12	HSEM privilege configuration register (HSEM_PRIVCFGR) . . . . .	452
13.4.13	HSEM clear register (HSEM_CR) . . . . .	453
13.4.14	HSEM clear semaphore key register (HSEM_KEYR) . . . . .	453
13.4.15	HSEM register map . . . . .	455
14	General-purpose I/Os (GPIO) . . . . .	457
14.1	GPIO introduction . . . . .	457
14.2	GPIO main features . . . . .	457
14.3	GPIO implementation . . . . .	457
14.4	GPIO functional description . . . . .	458
14.4.1	GPIO general-purpose I/O . . . . .	459
14.4.2	GPIO pin alternate function multiplexer and mapping . . . . .	460
14.4.3	GPIO port additional function multiplexer . . . . .	461
14.4.4	GPIO port control registers . . . . .	461
14.4.5	GPIO port data registers . . . . .	461
14.4.6	GPIO data bitwise handling . . . . .	461
14.4.7	GPIO locking mechanism . . . . .	462
14.4.8	GPIO alternate function input/output . . . . .	462
14.4.9	GPIO external interrupt/wakeup lines . . . . .	462
14.4.10	GPIO input configuration . . . . .	463
14.4.11	GPIO output configuration . . . . .	463
14.4.12	GPIO alternate function configuration . . . . .	464
14.4.13	GPIO analog configuration . . . . .	465
14.4.14	GPIO using the LSE oscillator pins as GPIOs . . . . .	465

14.4.15	GPIO using GPIO pins with RTC . . . . .	465
14.4.16	GPIO using PH3 as GPIO . . . . .	465
14.4.17	GPIO TrustZone security . . . . .	466
14.4.18	GPIO privileged and unprivileged modes . . . . .	467
14.4.19	GPIO compensation cell . . . . .	467
14.4.20	GPIO standby retention . . . . .	467
14.5	GPIO port A registers . . . . .	468
14.5.1	GPIO port A mode register (GPIOA_MODER) . . . . .	468
14.5.2	GPIO port A output type register (GPIOA_OTYPER) . . . . .	469
14.5.3	GPIO port A output speed register (GPIOA_OSPEEDR) . . . . .	469
14.5.4	GPIO port A pull-up/pull-down register (GPIOA_PUPDR) . . . . .	470
14.5.5	GPIO port A input data register (GPIOA_IDR) . . . . .	471
14.5.6	GPIO port A output data register (GPIOA_ODR) . . . . .	471
14.5.7	GPIO port A bit set/reset register (GPIOA_BSRR) . . . . .	472
14.5.8	GPIO port A configuration lock register (GPIOA_LCKR) . . . . .	472
14.5.9	GPIO port A alternate function low register (GPIOA_AFRL) . . . . .	473
14.5.10	GPIO port A alternate function high register (GPIOA_AFRH) . . . . .	474
14.5.11	GPIO port A bit reset register (GPIOA_BRR) . . . . .	475
14.5.12	GPIO port A secure configuration register (GPIOA_SECCFGR) . . . . .	476
14.6	GPIO port B registers . . . . .	476
14.6.1	GPIO port B mode register (GPIOB_MODER) . . . . .	476
14.6.2	GPIO port B output type register (GPIOB_OTYPER) . . . . .	477
14.6.3	GPIO port B output speed register (GPIOB_OSPEEDR) . . . . .	477
14.6.4	GPIO port B pull-up/pull-down register (GPIOB_PUPDR) . . . . .	478
14.6.5	GPIO port B input data register (GPIOB_IDR) . . . . .	479
14.6.6	GPIO port B output data register (GPIOB_ODR) . . . . .	480
14.6.7	GPIO port B bit set/reset register (GPIOB_BSRR) . . . . .	480
14.6.8	GPIO port B configuration lock register (GPIOB_LCKR) . . . . .	480
14.6.9	GPIO port B alternate function low register (GPIOB_AFRL) . . . . .	481
14.6.10	GPIO port B alternate function high register (GPIOB_AFRH) . . . . .	482
14.6.11	GPIO port B bit reset register (GPIOB_BRR) . . . . .	483
14.6.12	GPIO port B secure configuration register (GPIOB_SECCFGR) . . . . .	484
14.7	GPIO port C registers . . . . .	484
14.7.1	GPIO port C mode register (GPIOC_MODER) . . . . .	484
14.7.2	GPIO port C output type register (GPIOC_OTYPER) . . . . .	485
14.7.3	GPIOC port output speed register (GPIOC_OSPEEDR) . . . . .	485
14.7.4	GPIO port C pull-up/pull-down register (GPIOC_PUPDR) . . . . .	486

14.7.5	GPIO port C input data register (GPIOC_IDR) . . . . .	486
14.7.6	GPIO port C output data register (GPIOC_ODR) . . . . .	487
14.7.7	GPIO port C bit set/reset register (GPIOC_BSRR) . . . . .	487
14.7.8	GPIO port C configuration lock register (GPIOC_LCKR) . . . . .	488
14.7.9	GPIO port C alternate function high register (GPIOC_AFRH) . . . . .	489
14.7.10	GPIO port C bit reset register (GPIOC_BRR) . . . . .	489
14.7.11	GPIO port C secure configuration register (GPIOC_SECCFGR) . . . . .	490
14.8	GPIO port H registers . . . . .	490
14.8.1	GPIO port H mode register (GPIOH_MODER) . . . . .	490
14.8.2	GPIO port H output type register (GPIOH_OTYPER) . . . . .	491
14.8.3	GPIO port H output speed register (GPIOH_OSPEEDR) . . . . .	491
14.8.4	GPIO port H pull-up/pull-down register (GPIOH_PUPDR) . . . . .	492
14.8.5	GPIO port H input data register (GPIOH_IDR) . . . . .	492
14.8.6	GPIO port H output data register (GPIOH_ODR) . . . . .	493
14.8.7	GPIO port H bit set/reset register (GPIOH_BSRR) . . . . .	493
14.8.8	GPIO port H configuration lock register (GPIOH_LCKR) . . . . .	494
14.8.9	GPIO port H alternate function low register (GPIOH_AFRL) . . . . .	495
14.8.10	GPIO port H bit reset register (GPIOH_BRR) . . . . .	495
14.8.11	GPIO port H secure configuration register (GPIOH_SECCFGR) . . . . .	496
14.8.12	GPIOA register map . . . . .	497
14.8.13	GPIOB register map . . . . .	499
14.8.14	GPIOC register map . . . . .	501
14.8.15	GPIOH register map . . . . .	502
15	System configuration controller (SYSCFG) . . . . .	503
15.1	SYSCFG main features . . . . .	503
15.2	SYSCFG functional description . . . . .	503
15.2.1	I/O compensation cell management . . . . .	503
15.2.2	SYSCFG TrustZone ^®security and privilege . . . . .	504
15.3	SYSCFG registers . . . . .	506
15.3.1	SYSCFG secure configuration register (SYSCFG_SECCFGR) . . . . .	506
15.3.2	SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . .	506
15.3.3	SYSCFG FPU interrupt mask register (SYSCFG_FPUIMR) . . . . .	508
15.3.4	SYSCFG CPU non-secure lock register (SYSCFG_CNSLCKR) . . . . .	509
15.3.5	SYSCFG CPU secure lock register (SYSCFG_CSLCKR) . . . . .	510
15.3.6	SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . .	511
15.3.7	SYSCFG memory erase status register (SYSCFG_MESR) . . . . .	512

15.3.8	SYSCFG compensation cell control/status register (SYSCFG_CCCSR) . . . . .	513
15.3.9	SYSCFG compensation cell value register (SYSCFG_CCVR) . . . . .	514
15.3.10	SYSCFG compensation cell code register (SYSCFG_CCCR) . . . . .	515
15.3.11	SYSCFG RSS command register (SYSCFG_RSSCMDR) . . . . .	515
15.3.12	SYSCFG register map . . . . .	517
16	Peripherals interconnect matrix . . . . .	518
16.1	Introduction . . . . .	518
16.2	Connection summary . . . . .	518
16.3	Interconnection details . . . . .	519
16.3.1	Master to slave interconnection for timers . . . . .	519
16.3.2	Triggers to ADC4 . . . . .	520
16.3.3	ADC4 analog watchdog as trigger to timer . . . . .	520
16.3.4	Internal clock source to timer . . . . .	521
16.3.5	Triggers to low-power timer . . . . .	522
16.3.6	Internal analog signals to analog peripheral . . . . .	522
16.3.7	System errors as break signals to timers . . . . .	522
16.3.8	Triggers to GPDMA1 . . . . .	523
16.3.9	Internal tamper sources . . . . .	523
16.3.10	Triggers to communication peripherals . . . . .	524
16.3.11	Output from tamper . . . . .	524
16.3.12	Timers generating IRTIM signal . . . . .	525
16.3.13	From encryption keys to AES/SAES . . . . .	525
16.3.14	From timer (TIM1/TIM2/TIM3) to comparators (COMP1/COMP2) . . . . .	525
16.3.15	From comparators (COMP1/COMP2) to timers . . . . .	525
17	General purpose direct memory access controller (GPDMA) . . . . .	527
17.1	GPDMA introduction . . . . .	527
17.2	GPDMA main features . . . . .	527
17.3	GPDMA implementation . . . . .	528
17.3.1	GPDMA channels . . . . .	528
17.3.2	GPDMA autonomous mode in low-power modes . . . . .	529
17.3.3	GPDMA requests . . . . .	529
17.3.4	GPDMA block requests . . . . .	531
17.3.5	GPDMA triggers . . . . .	531
17.4	GPDMA functional description . . . . .	533

17.4.1	GPDMA block diagram . . . . .	533
17.4.2	GPDMA channel state and direct programming without any linked-list	533
17.4.3	GPDMA channel suspend and resume . . . . .	534
17.4.4	GPDMA channel abort and restart . . . . .	535
17.4.5	GPDMA linked-list data structure . . . . .	536
17.4.6	Linked-list item transfer execution . . . . .	538
17.4.7	GPDMA channel state and linked-list programming in run-to-completion mode . . . . .	538
17.4.8	GPDMA channel state and linked-list programming in link step mode	542
17.4.9	GPDMA channel state and linked-list programming . . . . .	549
17.4.10	GPDMA FIFO-based transfers . . . . .	551
17.4.11	GPDMA transfer request and arbitration . . . . .	556
17.4.12	GPDMA triggered transfer . . . . .	560
17.4.13	GPDMA circular buffering with linked-list programming . . . . .	561
17.4.14	GPDMA secure/nonsecure channel . . . . .	563
17.4.15	GPDMA privileged/unprivileged channel . . . . .	564
17.4.16	GPDMA error management . . . . .	564
17.4.17	GPDMA autonomous mode . . . . .	566
17.5	GPDMA in debug mode . . . . .	567
17.6	GPDMA in low-power modes . . . . .	567
17.7	GPDMA interrupts . . . . .	568
17.8	GPDMA registers . . . . .	569
17.8.1	GPDMA secure configuration register (GPDMA_SECCFGR) . . . . .	569
17.8.2	GPDMA privileged configuration register (GPDMA_PRIVCFGR) . . . . .	570
17.8.3	GPDMA configuration lock register (GPDMA_RCFGLOCKR) . . . . .	570
17.8.4	GPDMA nonsecure masked interrupt status register (GPDMA_MISR) . . . . .	571
17.8.5	GPDMA secure masked interrupt status register (GPDMA_SMISR) . . . . .	572
17.8.6	GPDMA channel x linked-list base address register (GPDMA_CxLBAR) . . . . .	572
17.8.7	GPDMA channel x flag clear register (GPDMA_CxFGR) . . . . .	573
17.8.8	GPDMA channel x status register (GPDMA_CxSR) . . . . .	574
17.8.9	GPDMA channel x control register (GPDMA_CxCR) . . . . .	575
17.8.10	GPDMA channel x transfer register 1 (GPDMA_CxTR1) . . . . .	577
17.8.11	GPDMA channel x transfer register 2 (GPDMA_CxTR2) . . . . .	581
17.8.12	GPDMA channel x block register 1 (GPDMA_CxBR1) . . . . .	584
17.8.13	GPDMA channel x source address register (GPDMA_CxSAR) . . . . .	586

17.8.14	GPDMA channel x destination address register (GPDMA_CxDAR) . . .	587
17.8.15	GPDMA channel x linked-list address register (GPDMA_CxLLR) . . . .	588
17.8.16	GPDMA register map . . . . .	589
18	Nested vectored interrupt controller (NVIC) . . . . .	591
18.1	NVIC main features . . . . .	591
18.2	Interrupt and exception vectors . . . . .	591
19	Extended interrupts and event controller (EXTI) . . . . .	595
19.1	EXTI main features . . . . .	595
19.2	EXTI block diagram . . . . .	595
19.2.1	EXTI connections between peripherals and CPU . . . . .	597
19.2.2	EXTI interrupt/event mapping . . . . .	597
19.3	EXTI functional description . . . . .	597
19.3.1	EXTI configurable event input wake-up . . . . .	598
19.3.2	EXTI mux selection . . . . .	598
19.4	EXTI functional behavior . . . . .	599
19.5	EXTI event protection . . . . .	599
19.5.1	EXTI security protection . . . . .	600
19.5.2	EXTI privilege protection . . . . .	601
19.6	EXTI registers . . . . .	602
19.6.1	EXTI rising trigger selection register (EXTI_RTSR1) . . . . .	602
19.6.2	EXTI falling trigger selection register (EXTI_FTSR1) . . . . .	603
19.6.3	EXTI software interrupt event register (EXTI_SWIER1) . . . . .	603
19.6.4	EXTI rising edge pending register (EXTI_RPR1) . . . . .	604
19.6.5	EXTI falling edge pending register (EXTI_FPR1) . . . . .	605
19.6.6	EXTI security configuration register (EXTI_SECCFGR1) . . . . .	605
19.6.7	EXTI privilege configuration register (EXTI_PRIVCFGR1) . . . . .	606
19.6.8	EXTI external interrupt selection register (EXTI_EXTICR1) . . . . .	606
19.6.9	EXTI external interrupt selection register (EXTI_EXTICR2) . . . . .	608
19.6.10	EXTI external interrupt selection register (EXTI_EXTICR3) . . . . .	609
19.6.11	EXTI external interrupt selection register (EXTI_EXTICR4) . . . . .	611
19.6.12	EXTI lock register (EXTI_LOCKR) . . . . .	613
19.6.13	EXTI CPU wake-up with interrupt mask register (EXTI_IMR1) . . . . .	613
19.6.14	EXTI CPU wake-up with event mask register (EXTI_EMR1) . . . . .	614
19.6.15	EXTI register map . . . . .	615

20 Cyclic redundancy check calculation unit (CRC) . . . . . 617

20.1 Introduction . . . . . 617

20.2 CRC main features . . . . . 617

20.3 CRC functional description . . . . . 618

20.3.1 CRC block diagram . . . . . 618

20.3.2 CRC internal signals . . . . . 618

20.3.3 CRC operation . . . . . 618

20.4 CRC registers . . . . . 620

20.4.1 CRC data register (CRC_DR) . . . . . 620

20.4.2 CRC independent data register (CRC_IDR) . . . . . 620

20.4.3 CRC control register (CRC_CR) . . . . . 621

20.4.4 CRC initial value (CRC_INIT) . . . . . 622

20.4.5 CRC polynomial (CRC_POL) . . . . . 622

20.4.6 CRC register map . . . . . 623

21 Analog-to-digital converter (ADC4) . . . . . 624

21.1 Introduction . . . . . 624

21.2 ADC main features . . . . . 624

21.3 ADC implementation . . . . . 625

21.4 ADC functional description . . . . . 627

21.4.1 ADC block diagram . . . . . 627

21.4.2 ADC pins and internal signals . . . . . 628

21.4.3 ADC voltage regulator (ADVREGEN) . . . . . 629

21.4.4 Calibration (ADCAL) . . . . . 629

21.4.5 ADC on-off control (ADEN, ADDIS, ADRDY) . . . . . 631

21.4.6 ADC clock (PRESC[3:0]) . . . . . 633

21.4.7 ADC connectivity . . . . . 634

21.4.8 Configuring the ADC . . . . . 635

21.4.9 Channel selection (CHSEL, SCANDIR, CHSELRMOD) . . . . . 635

21.4.10 Programmable sampling time (SMPx[2:0]) . . . . . 636

21.4.11 Single conversion mode (CONT = 0) . . . . . 637

21.4.12 Continuous conversion mode (CONT = 1) . . . . . 637

21.4.13 Starting conversions (ADSTART) . . . . . 638

21.4.14 Timings . . . . . 639

21.4.15 Stopping an ongoing conversion (ADSTP) . . . . . 640

21.4.16	Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . . . . .	640
21.4.17	Discontinuous mode (DISCEN) . . . . .	641
21.4.18	Programmable resolution (RES) - fast conversion mode . . . . .	641
21.4.19	End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . .	642
21.4.20	End of conversion sequence (EOS flag) . . . . .	643
21.4.21	Example timing diagrams (single/continuous modes hardware/software triggers) . . . . .	643
21.4.22	Low-frequency trigger mode . . . . .	645
21.4.23	Data management . . . . .	645
21.4.24	Low-power features . . . . .	649
21.4.25	Analog window watchdog . . . . .	653
21.4.26	Oversampler . . . . .	657
21.4.27	Temperature sensor and internal reference voltage . . . . .	660
21.5	ADC low-power modes . . . . .	663
21.6	ADC interrupts . . . . .	663
21.7	ADC registers . . . . .	665
21.7.1	ADC interrupt and status register (ADC_ISR) . . . . .	665
21.7.2	ADC interrupt enable register (ADC_IER) . . . . .	666
21.7.3	ADC control register (ADC_CR) . . . . .	669
21.7.4	ADC configuration register 1 (ADC_CFGR1) . . . . .	671
21.7.5	ADC configuration register 2 (ADC_CFGR2) . . . . .	674
21.7.6	ADC sampling time register (ADC_SMPR) . . . . .	675
21.7.7	ADC watchdog threshold register (ADC_AWD1TR) . . . . .	676
21.7.8	ADC watchdog threshold register (ADC_AWD2TR) . . . . .	677
21.7.9	ADC channel selection register [alternate] (ADC_CHSELR) . . . . .	678
21.7.10	ADC channel selection register [alternate] (ADC_CHSELR) . . . . .	678
21.7.11	ADC watchdog threshold register (ADC_AWD3TR) . . . . .	680
21.7.12	ADC data register (ADC_DR) . . . . .	681
21.7.13	ADC power register (ADC_PWR) . . . . .	681
21.7.14	ADC Analog Watchdog 2 Configuration register (ADC_AWD2CR) . . . . .	682
21.7.15	ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR) . . . . .	682
21.7.16	ADC Calibration factor (ADC_CALFACT) . . . . .	683
21.7.17	ADC common configuration register (ADC_CCR) . . . . .	683
21.7.18	ADC register map . . . . .	684
22	Comparator (COMP) . . . . .	687

22.1 Introduction ..... 687
22.2 COMP main features ..... 687
22.3 COMP functional description ..... 688
- 22.3.1 COMP block diagram ..... 688
- 22.3.2 COMP pins and internal signals ..... 688
- 22.3.3 Comparator LOCK mechanism ..... 690
- 22.3.4 Window comparator ..... 690
- 22.3.5 Hysteresis ..... 691
- 22.3.6 Comparator output-blanking function ..... 691
- 22.3.7 COMP power and speed modes ..... 692
- 22.3.8 Scaler function ..... 692
22.4 COMP low-power modes ..... 693
22.5 COMP interrupts ..... 693
22.6 COMP registers ..... 694
- 22.6.1 COMP1 control and status register (COMP1_CSR) ..... 694
- 22.6.2 COMP2 control and status register (COMP2_CSR) ..... 695
- 22.6.3 COMP register map ..... 697

23 Touch sensing controller (TSC) ..... 698
- 23.1 Introduction ..... 698
- 23.2 TSC main features ..... 698
- 23.3 TSC functional description ..... 699
  - 23.3.1 TSC block diagram ..... 699
  - 23.3.2 Surface charge transfer acquisition overview ..... 699
  - 23.3.3 Reset and clocks ..... 702
  - 23.3.4 Charge transfer acquisition sequence ..... 702
  - 23.3.5 Spread spectrum feature ..... 703
  - 23.3.6 Max count error ..... 704
  - 23.3.7 Sampling capacitor I/O and channel I/O mode selection ..... 704
  - 23.3.8 Acquisition mode ..... 705
  - 23.3.9 I/O hysteresis and analog switch control ..... 705
- 23.4 TSC low-power modes ..... 706
- 23.5 TSC interrupts ..... 706
- 23.6 TSC registers ..... 706
  - 23.6.1 TSC control register (TSC_CR) ..... 706
  - 23.6.2 TSC interrupt enable register (TSC_IER) ..... 709

23.6.3	TSC interrupt clear register (TSC_ICR) . . . . .	710
23.6.4	TSC interrupt status register (TSC_ISR) . . . . .	710
23.6.5	TSC I/O hysteresis control register (TSC_IOHCR) . . . . .	711
23.6.6	TSC I/O analog switch control register (TSC_IOASCR) . . . . .	711
23.6.7	TSC I/O sampling control register (TSC_IOSCR) . . . . .	712
23.6.8	TSC I/O channel control register (TSC_IOCCR) . . . . .	712
23.6.9	TSC I/O group control status register (TSC_IOGCSR) . . . . .	713
23.6.10	TSC I/O group x counter register (TSC_IOGxCR) . . . . .	713
23.6.11	TSC register map . . . . .	714
24	True random number generator (RNG) . . . . .	716
24.1	Introduction . . . . .	716
24.2	RNG main features . . . . .	716
24.3	RNG functional description . . . . .	717
24.3.1	RNG block diagram . . . . .	717
24.3.2	RNG internal signals . . . . .	717
24.3.3	Random number generation . . . . .	717
24.3.4	RNG initialization . . . . .	720
24.3.5	RNG operation . . . . .	721
24.3.6	RNG clocking . . . . .	723
24.3.7	Error management . . . . .	723
24.3.8	RNG low-power use . . . . .	724
24.4	RNG interrupts . . . . .	725
24.5	RNG processing time . . . . .	725
24.6	RNG entropy source validation . . . . .	726
24.6.1	Introduction . . . . .	726
24.6.2	Validation conditions . . . . .	726
24.7	RNG registers . . . . .	727
24.7.1	RNG control register (RNG_CR) . . . . .	727
24.7.2	RNG status register (RNG_SR) . . . . .	729
24.7.3	RNG data register (RNG_DR) . . . . .	730
24.7.4	RNG noise source control register (RNG_NSCR) . . . . .	731
24.7.5	RNG health test control register (RNG_HTCR) . . . . .	732
24.7.6	RNG register map . . . . .	732
25	AES hardware accelerator (AES) . . . . .	733

25.1	Introduction . . . . .	733
25.2	AES main features . . . . .	733
25.3	AES implementation . . . . .	734
25.4	AES functional description . . . . .	734
25.4.1	AES block diagram . . . . .	734
25.4.2	AES internal signals . . . . .	735
25.4.3	AES reset and clocks . . . . .	735
25.4.4	AES symmetric cipher implementation . . . . .	735
25.4.5	AES encryption or decryption typical usage . . . . .	736
25.4.6	AES authenticated encryption, decryption, and cipher-based message authentication . . . . .	739
25.4.7	AES ciphertext stealing and data padding . . . . .	739
25.4.8	AES suspend and resume operations . . . . .	740
25.4.9	AES basic chaining modes (ECB, CBC) . . . . .	740
25.4.10	AES counter (CTR) mode . . . . .	744
25.4.11	AES Galois/counter mode (GCM) . . . . .	746
25.4.12	AES Galois message authentication code (GMAC) . . . . .	751
25.4.13	AES counter with CBC-MAC (CCM) . . . . .	752
25.4.14	AES key sharing with secure AES co-processor . . . . .	757
25.4.15	AES data registers and data swapping . . . . .	758
25.4.16	AES key registers . . . . .	760
25.4.17	AES initialization vector registers . . . . .	760
25.4.18	AES error management . . . . .	761
25.5	AES interrupts . . . . .	762
25.6	AES DMA requests . . . . .	762
25.7	AES processing latency . . . . .	763
25.8	AES registers . . . . .	765
25.8.1	AES control register (AES_CR) . . . . .	765
25.8.2	AES status register (AES_SR) . . . . .	767
25.8.3	AES data input register (AES_DINR) . . . . .	768
25.8.4	AES data output register (AES_DOUTR) . . . . .	769
25.8.5	AES key register 0 (AES_KEYR0) . . . . .	769
25.8.6	AES key register 1 (AES_KEYR1) . . . . .	770
25.8.7	AES key register 2 (AES_KEYR2) . . . . .	770
25.8.8	AES key register 3 (AES_KEYR3) . . . . .	770
25.8.9	AES initialization vector register 0 (AES_IVR0) . . . . .	771

25.8.10	AES initialization vector register 1 (AES_IVR1) . . . . .	771
25.8.11	AES initialization vector register 2 (AES_IVR2) . . . . .	771
25.8.12	AES initialization vector register 3 (AES_IVR3) . . . . .	772
25.8.13	AES key register 4 (AES_KEYR4) . . . . .	772
25.8.14	AES key register 5 (AES_KEYR5) . . . . .	772
25.8.15	AES key register 6 (AES_KEYR6) . . . . .	773
25.8.16	AES key register 7 (AES_KEYR7) . . . . .	773
25.8.17	AES suspend registers (AES_SUSPRx) . . . . .	773
25.8.18	AES interrupt enable register (AES_IER) . . . . .	774
25.8.19	AES interrupt status register (AES_ISR) . . . . .	775
25.8.20	AES interrupt clear register (AES_ICR) . . . . .	776
25.8.21	AES register map . . . . .	776
26	Secure AES coprocessor (SAES) . . . . .	779
26.1	Introduction . . . . .	779
26.2	SAES main features . . . . .	779
26.3	SAES implementation . . . . .	780
26.4	SAES functional description . . . . .	780
26.4.1	SAES block diagram . . . . .	780
26.4.2	SAES internal signals . . . . .	781
26.4.3	SAES reset and clocks . . . . .	782
26.4.4	SAES symmetric cipher implementation . . . . .	782
26.4.5	SAES encryption or decryption typical usage . . . . .	783
26.4.6	SAES authenticated encryption, decryption, and cipher-based message authentication . . . . .	785
26.4.7	SAES ciphertext stealing and data padding . . . . .	786
26.4.8	SAES suspend and resume operations . . . . .	786
26.4.9	SAES basic chaining modes (ECB, CBC) . . . . .	787
26.4.10	SAES counter (CTR) mode . . . . .	791
26.4.11	SAES Galois/counter mode (GCM) . . . . .	793
26.4.12	SAES Galois message authentication code (GMAC) . . . . .	797
26.4.13	SAES counter with CBC-MAC (CCM) . . . . .	799
26.4.14	SAES operation with wrapped keys . . . . .	804
26.4.15	SAES operation with shared keys . . . . .	808
26.4.16	SAES data registers and data swapping . . . . .	809
26.4.17	SAES key registers . . . . .	812
26.4.18	SAES initialization vector registers . . . . .	813

- 26.4.19 SAES error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
26.5 SAES interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
26.6 SAES DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
26.7 SAES processing latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
26.8 SAES registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
- 26.8.1 SAES control register (SAES_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
- 26.8.2 SAES status register (SAES_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
- 26.8.3 SAES data input register (SAES_DINR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
- 26.8.4 SAES data output register (SAES_DOUTR) . . . . . . . . . . . . . . . . . . . . . . . . . . 824
- 26.8.5 SAES key register 0 (SAES_KEYR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
- 26.8.6 SAES key register 1 (SAES_KEYR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
- 26.8.7 SAES key register 2 (SAES_KEYR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
- 26.8.8 SAES key register 3 (SAES_KEYR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
- 26.8.9 SAES initialization vector register 0 (SAES_IVR0) . . . . . . . . . . . . . . . . . . . . . 826
- 26.8.10 SAES initialization vector register 1 (SAES_IVR1) . . . . . . . . . . . . . . . . . . . . . 826
- 26.8.11 SAES initialization vector register 2 (SAES_IVR2) . . . . . . . . . . . . . . . . . . . . . 826
- 26.8.12 SAES initialization vector register 3 (SAES_IVR3) . . . . . . . . . . . . . . . . . . . . . 827
- 26.8.13 SAES key register 4 (SAES_KEYR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
- 26.8.14 SAES key register 5 (SAES_KEYR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
- 26.8.15 SAES key register 6 (SAES_KEYR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
- 26.8.16 SAES key register 7 (SAES_KEYR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
- 26.8.17 SAES suspend registers (SAES_SUSPRx) . . . . . . . . . . . . . . . . . . . . . . . . . . 828
- 26.8.18 SAES interrupt enable register (SAES_IER) . . . . . . . . . . . . . . . . . . . . . . . . . 829
- 26.8.19 SAES interrupt status register (SAES_ISR) . . . . . . . . . . . . . . . . . . . . . . . . . 830
- 26.8.20 SAES interrupt clear register (SAES_ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . 831
- 26.8.21 SAES register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832

27 Hash processor (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
- 27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
- 27.2 HASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
- 27.3 HASH implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
- 27.4 HASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
  - 27.4.1 HASH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
  - 27.4.2 HASH internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
  - 27.4.3 About secure hash algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
  - 27.4.4 Message data feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836

27.4.5	Message digest computing .....	838
27.4.6	Message padding .....	839
27.4.7	HMAC operation .....	841
27.4.8	HASH suspend/resume operations .....	843
27.4.9	HASH DMA interface .....	845
27.4.10	HASH error management .....	845
27.4.11	HASH processing time .....	845
27.5	HASH interrupts .....	846
27.6	HASH registers .....	847
27.6.1	HASH control register (HASH_CR) .....	847
27.6.2	HASH data input register (HASH_DIN) .....	848
27.6.3	HASH start register (HASH_STR) .....	849
27.6.4	HASH digest registers .....	850
27.6.5	HASH interrupt enable register (HASH_IMR) .....	851
27.6.6	HASH status register (HASH_SR) .....	852
27.6.7	HASH context swap registers .....	853
27.6.8	HASH register map .....	854
28	Public key accelerator (PKA) .....	856
28.1	PKA introduction .....	856
28.2	PKA main features .....	856
28.3	PKA functional description .....	857
28.3.1	PKA block diagram .....	857
28.3.2	PKA internal signals .....	857
28.3.3	PKA reset and clocks .....	857
28.3.4	PKA public key acceleration .....	858
28.3.5	Typical applications for PKA .....	860
28.3.6	PKA procedure to perform an operation .....	862
28.3.7	PKA error management .....	863
28.4	PKA operating modes .....	864
28.4.1	Introduction .....	864
28.4.2	Montgomery parameter computation .....	865
28.4.3	Modular addition .....	865
28.4.4	Modular subtraction .....	866
28.4.5	Modular and Montgomery multiplication .....	866
28.4.6	Modular exponentiation .....	867

28.4.7	Modular inversion . . . . .	869
28.4.8	Modular reduction . . . . .	869
28.4.9	Arithmetic addition . . . . .	870
28.4.10	Arithmetic subtraction . . . . .	870
28.4.11	Arithmetic multiplication . . . . .	871
28.4.12	Arithmetic comparison . . . . .	871
28.4.13	RSA CRT exponentiation . . . . .	871
28.4.14	Point on elliptic curve Fp check . . . . .	872
28.4.15	ECC Fp scalar multiplication . . . . .	873
28.4.16	ECDSA sign . . . . .	874
28.4.17	ECDSA verification . . . . .	876
28.4.18	ECC complete addition . . . . .	877
28.4.19	ECC double base ladder . . . . .	877
28.4.20	ECC projective to affine . . . . .	878
28.5	Example of configurations and processing times . . . . .	879
28.5.1	Supported elliptic curves . . . . .	879
28.5.2	Computation times . . . . .	881
28.6	PKA interrupts . . . . .	883
28.7	PKA registers . . . . .	884
28.7.1	PKA control register (PKA_CR) . . . . .	884
28.7.2	PKA status register (PKA_SR) . . . . .	886
28.7.3	PKA clear flag register (PKA_CLRFR) . . . . .	887
28.7.4	PKA RAM . . . . .	887
28.7.5	PKA register map . . . . .	888
29	Advanced-control timers (TIM1) . . . . .	889
29.1	TIM1 introduction . . . . .	889
29.2	TIM1 main features . . . . .	890
29.3	TIM1 functional description . . . . .	891
29.3.1	Block diagram . . . . .	891
29.3.2	TIM1 pins and internal signals . . . . .	892
29.3.3	Time-base unit . . . . .	896
29.3.4	Counter modes . . . . .	898
29.3.5	Repetition counter . . . . .	910
29.3.6	External trigger input . . . . .	911
29.3.7	Clock selection . . . . .	912

29.3.8	Capture/compare channels . . . . .	916
29.3.9	Input capture mode . . . . .	919
29.3.10	PWM input mode . . . . .	920
29.3.11	Forced output mode . . . . .	921
29.3.12	Output compare mode . . . . .	921
29.3.13	PWM mode . . . . .	923
29.3.14	Asymmetric PWM mode . . . . .	931
29.3.15	Combined PWM mode . . . . .	932
29.3.16	Combined 3-phase PWM mode . . . . .	933
29.3.17	Complementary outputs and dead-time insertion . . . . .	934
29.3.18	Using the break function . . . . .	937
29.3.19	Bidirectional break inputs . . . . .	943
29.3.20	Clearing the tim_ocxref signal on an external event . . . . .	944
29.3.21	6-step PWM generation . . . . .	946
29.3.22	One-pulse mode . . . . .	947
29.3.23	Retriggerable One-pulse mode . . . . .	949
29.3.24	Pulse on compare mode . . . . .	950
29.3.25	Encoder interface mode . . . . .	952
29.3.26	Direction bit output . . . . .	969
29.3.27	UIF bit remapping . . . . .	970
29.3.28	Timer input XOR function . . . . .	970
29.3.29	Interfacing with Hall sensors . . . . .	970
29.3.30	Timer synchronization . . . . .	972
29.3.31	ADC triggers . . . . .	977
29.3.32	DMA burst mode . . . . .	977
29.3.33	TIM1 DMA requests . . . . .	978
29.3.34	Debug mode . . . . .	978
29.4	TIM1 low-power modes . . . . .	979
29.5	TIM1 interrupts . . . . .	979
29.6	TIM1 registers . . . . .	980
29.6.1	TIM1 control register 1 (TIM1_CR1) . . . . .	980
29.6.2	TIM1 control register 2 (TIM1_CR2) . . . . .	981
29.6.3	TIM1 slave mode control register (TIM1_SMCR) . . . . .	985
29.6.4	TIM1 DMA/interrupt enable register (TIM1_DIER) . . . . .	989
29.6.5	TIM1 status register (TIM1_SR) . . . . .	990
29.6.6	TIM1 event generation register (TIM1_EGR) . . . . .	993
29.6.7	TIM1 capture/compare mode register 1 (TIM1_CCMR1) . . . . .	994

29.6.8	TIM1 capture/compare mode register 1 [alternate] (TIM1_CCMR1) . . . . .	996
29.6.9	TIM1 capture/compare mode register 2 (TIM1_CCMR2) . . . . .	999
29.6.10	TIM1 capture/compare mode register 2 [alternate] (TIM1_CCMR2) . . . . .	1000
29.6.11	TIM1 capture/compare enable register (TIM1_CCER) . . . . .	1003
29.6.12	TIM1 counter (TIM1_CNT) . . . . .	1007
29.6.13	TIM1 prescaler (TIM1_PSC) . . . . .	1007
29.6.14	TIM1 autoreload register (TIM1_ARR) . . . . .	1008
29.6.15	TIM1 repetition counter register (TIM1_RCR) . . . . .	1008
29.6.16	TIM1 capture/compare register 1 (TIM1_CCR1) . . . . .	1009
29.6.17	TIM1 capture/compare register 2 (TIM1_CCR2) . . . . .	1009
29.6.18	TIM1 capture/compare register 3 (TIM1_CCR3) . . . . .	1010
29.6.19	TIM1 capture/compare register 4 (TIM1_CCR4) . . . . .	1011
29.6.20	TIM1 break and dead-time register (TIM1_BDTR) . . . . .	1012
29.6.21	TIM1 capture/compare register 5 (TIM1_CCR5) . . . . .	1016
29.6.22	TIM1 capture/compare register 6 (TIM1_CCR6) . . . . .	1017
29.6.23	TIM1 capture/compare mode register 3 (TIM1_CCMR3) . . . . .	1018
29.6.24	TIM1 timer deadtime register 2 (TIM1_DTR2) . . . . .	1019
29.6.25	TIM1 timer encoder control register (TIM1_ECR) . . . . .	1020
29.6.26	TIM1 timer input selection register (TIM1_TISEL) . . . . .	1021
29.6.27	TIM1 alternate function option register 1 (TIM1_AF1) . . . . .	1022
29.6.28	TIM1 alternate function register 2 (TIM1_AF2) . . . . .	1025
29.6.29	TIM1 DMA control register (TIM1_DCR) . . . . .	1027
29.6.30	TIM1 DMA address for full transfer (TIM1_DMAR) . . . . .	1029
29.6.31	TIM1 register map . . . . .	1029
30	General-purpose timers (TIM2/TIM3) . . . . .	1032
30.1	TIM2/TIM3 introduction . . . . .	1032
30.2	TIM2/TIM3 main features . . . . .	1032
30.3	TIM2/TIM3 implementation . . . . .	1033
30.4	TIM2/TIM3 functional description . . . . .	1034
30.4.1	Block diagram . . . . .	1034
30.4.2	TIM2/TIM3 pins and internal signals . . . . .	1035
30.4.3	Time-base unit . . . . .	1038
30.4.4	Counter modes . . . . .	1040
30.4.5	Clock selection . . . . .	1051

30.4.6	Capture/compare channels .....	1055
30.4.7	Input capture mode .....	1057
30.4.8	PWM input mode .....	1058
30.4.9	Forced output mode .....	1059
30.4.10	Output compare mode .....	1059
30.4.11	PWM mode .....	1061
30.4.12	Asymmetric PWM mode .....	1069
30.4.13	Combined PWM mode .....	1070
30.4.14	Clearing the tim_ocxref signal on an external event .....	1071
30.4.15	One-pulse mode .....	1073
30.4.16	Retriggerable one-pulse mode .....	1074
30.4.17	Pulse on compare mode .....	1075
30.4.18	Encoder interface mode .....	1077
30.4.19	Direction bit output .....	1095
30.4.20	UIF bit remapping .....	1096
30.4.21	Timer input XOR function .....	1096
30.4.22	Timers and external trigger synchronization .....	1096
30.4.23	Timer synchronization .....	1100
30.4.24	ADC triggers .....	1105
30.4.25	DMA burst mode .....	1106
30.4.26	TIM2/TIM3 DMA requests .....	1107
30.4.27	Debug mode .....	1107
30.4.28	TIM2/TIM3 low-power modes .....	1107
30.4.29	TIM2/TIM3 interrupts .....	1108
30.5	TIM2/TIM3 registers .....	1109
30.5.1	TIMx control register 1 (TIMx_CR1)(x = 2, 3) .....	1109
30.5.2	TIMx control register 2 (TIMx_CR2)(x = 2, 3) .....	1110
30.5.3	TIMx slave mode control register (TIMx_SMCR)(x = 2, 3) .....	1112
30.5.4	TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2, 3) .....	1116
30.5.5	TIMx status register (TIMx_SR)(x = 2, 3) .....	1117
30.5.6	TIMx event generation register (TIMx_EGR)(x = 2, 3) .....	1119
30.5.7	TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2, 3) ..	1120
30.5.8	TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 2, 3) .....	1122
30.5.9	TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2, 3) ..	1124
30.5.10	TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)(x = 2, 3) .....	1125

30.5.11	TIMx capture/compare enable register (TIMx_CCER)(x = 2, 3) . . . .	1128
30.5.12	TIM3 counter (TIM3_CNT) . . . . .	1129
30.5.13	TIM2 counter (TIM2_CNT) . . . . .	1130
30.5.14	TIMx prescaler (TIMx_PSC)(x = 2, 3) . . . . .	1130
30.5.15	TIM3 autoreload register (TIM3_ARR) . . . . .	1131
30.5.16	TIM2 autoreload register (TIM2_ARR) . . . . .	1131
30.5.17	TIM3 capture/compare register 1 (TIM3_CCR1) . . . . .	1132
30.5.18	TIM2 capture/compare register 1 (TIM2_CCR1) . . . . .	1133
30.5.19	TIM3 capture/compare register 2 (TIM3_CCR2) . . . . .	1133
30.5.20	TIM2 capture/compare register 2 (TIM2_CCR2) . . . . .	1134
30.5.21	TIM3 capture/compare register 3 (TIM3_CCR3) . . . . .	1135
30.5.22	TIM2 capture/compare register 3 (TIM2_CCR3) . . . . .	1136
30.5.23	TIM3 capture/compare register 4 (TIM3_CCR4) . . . . .	1137
30.5.24	TIM2 capture/compare register 4 (TIM2_CCR4) . . . . .	1138
30.5.25	TIMx timer encoder control register (TIMx_ECR)(x = 2, 3) . . . . .	1139
30.5.26	TIMx timer input selection register (TIMx_TISEL)(x = 2, 3) . . . . .	1140
30.5.27	TIMx alternate function register 1 (TIMx_AF1)(x = 2, 3) . . . . .	1141
30.5.28	TIMx alternate function register 2 (TIMx_AF2)(x = 2, 3) . . . . .	1142
30.5.29	TIMx DMA control register (TIMx_DCR)(x = 2, 3) . . . . .	1143
30.5.30	TIMx DMA address for full transfer (TIMx_DMAR)(x = 2, 3) . . . . .	1144
30.5.31	TIMx register map . . . . .	1145
31	General purpose timers (TIM16/TIM17) . . . . .	1148
31.1	TIM16/TIM17 introduction . . . . .	1148
31.2	TIM16/TIM17 main features . . . . .	1148
31.3	TIM16/TIM17 functional description . . . . .	1149
31.3.1	Block diagram . . . . .	1149
31.3.2	TIM16/TIM17 pins and internal signals . . . . .	1149
31.3.3	Time-base unit . . . . .	1152
31.3.4	Counter modes . . . . .	1154
31.3.5	Repetition counter . . . . .	1158
31.3.6	Clock selection . . . . .	1159
31.3.7	Capture/compare channels . . . . .	1161
31.3.8	Input capture mode . . . . .	1163
31.3.9	Forced output mode . . . . .	1164
31.3.10	Output compare mode . . . . .	1164
31.3.11	PWM mode . . . . .	1166

31.3.12	Complementary outputs and dead-time insertion . . . . .	1171
31.3.13	Using the break function . . . . .	1173
31.3.14	Bidirectional break input . . . . .	1178
31.3.15	Clearing the tim_ocxref signal on an external event . . . . .	1179
31.3.16	6-step PWM generation . . . . .	1180
31.3.17	One-pulse mode . . . . .	1182
31.3.18	UIF bit remapping . . . . .	1183
31.3.19	Using timer output as trigger for other timers (TIM16/TIM17 only) . . . . .	1183
31.3.20	DMA burst mode . . . . .	1184
31.3.21	TIM16/TIM17 DMA requests . . . . .	1185
31.3.22	Debug mode . . . . .	1185
31.4	TIM16/TIM17 low-power modes . . . . .	1185
31.5	TIM16/TIM17 interrupts . . . . .	1185
31.6	TIM16/TIM17 registers . . . . .	1187
31.6.1	TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . .	1187
31.6.2	TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . .	1188
31.6.3	TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . .	1189
31.6.4	TIMx status register (TIMx_SR)(x = 16 to 17) . . . . .	1190
31.6.5	TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . .	1191
31.6.6	TIMx capture/compare mode register 1 (TIMx_CCMR1) (x = 16 to 17) . . . . .	1192
31.6.7	TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 16 to 17) . . . . .	1193
31.6.8	TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . . . .	1195
31.6.9	TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . .	1198
31.6.10	TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . .	1198
31.6.11	TIMx auto-reautoreload register (TIMx_ARR)(x = 16 to 17) . . . . .	1199
31.6.12	TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . .	1199
31.6.13	TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . .	1200
31.6.14	TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . .	1201
31.6.15	TIMx timer deadtime register 2 (TIMx_DTR2)(x = 16 to 17) . . . . .	1204
31.6.16	TIMx input selection register (TIMx_TISEL)(x = 16 to 17) . . . . .	1205
31.6.17	TIMx alternate function register 1 (TIMx_AF1)(x = 16 to 17) . . . . .	1205
31.6.18	TIMx alternate function register 2 (TIMx_AF2)(x = 16 to 17) . . . . .	1208
31.6.19	TIMx option register 1 (TIMx_OR1)(x = 16 to 17) . . . . .	1208
31.6.20	TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . .	1209
31.6.21	TIM16/TIM17 DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . .	1210

31.6.22 TIM16/TIM17 register map ..... 1211

32 Low-power timer (LPTIM) ..... 1213

32.1 Introduction ..... 1213

32.2 LPTIM main features ..... 1213

32.3 LPTIM implementation ..... 1214

32.4 LPTIM functional description ..... 1215

32.4.1 LPTIM block diagram ..... 1215

32.4.2 LPTIM pins and internal signals ..... 1215

32.4.3 LPTIM input and trigger mapping ..... 1217

32.4.4 LPTIM reset and clocks ..... 1218

32.4.5 Glitch filter ..... 1218

32.4.6 Prescaler ..... 1219

32.4.7 Trigger multiplexer ..... 1219

32.4.8 Operating mode ..... 1220

32.4.9 Timeout function ..... 1222

32.4.10 Waveform generation ..... 1222

32.4.11 Register update ..... 1223

32.4.12 Counter mode ..... 1224

32.4.13 Timer enable ..... 1225

32.4.14 Timer counter reset ..... 1225

32.4.15 Encoder mode ..... 1226

32.4.16 Repetition counter ..... 1227

32.4.17 Capture/compare channels ..... 1228

32.4.18 Input capture mode ..... 1229

32.4.19 PWM mode ..... 1231

32.4.20 Autonomous mode ..... 1233

32.4.21 DMA requests ..... 1234

32.4.22 Debug mode ..... 1235

32.5 LPTIM low-power modes ..... 1235

32.6 LPTIM interrupts ..... 1235

32.7 LPTIM registers ..... 1236

32.7.1 LPTIMx interrupt and status register [alternate] (LPTIMx_ISR)
(x = 1, 2) ..... 1237

32.7.2 LPTIMx interrupt and status register [alternate] (LPTIMx_ISR)
(x = 1, 2) ..... 1239

32.7.3	LPTIMx interrupt clear register [alternate] (LPTIMx_ICR) (x = 1, 2) . . . . .	1241
32.7.4	LPTIMx interrupt clear register [alternate] (LPTIMx_ICR) (x = 1, 2) . . . . .	1242
32.7.5	LPTIMx interrupt enable register [alternate] (LPTIMx_DIER) (x = 1, 2) . . . . .	1244
32.7.6	LPTIMx interrupt enable register [alternate] (LPTIMx_DIER) (x = 1, 2) . . . . .	1245
32.7.7	LPTIM configuration register (LPTIM_CFGR) . . . . .	1247
32.7.8	LPTIM control register (LPTIM_CR) . . . . .	1250
32.7.9	LPTIM compare register 1 (LPTIM_CCR1) . . . . .	1251
32.7.10	LPTIM autoreload register (LPTIM_ARR) . . . . .	1251
32.7.11	LPTIM counter register (LPTIM_CNT) . . . . .	1252
32.7.12	LPTIM configuration register 2 (LPTIM_CFGR2) . . . . .	1252
32.7.13	LPTIM repetition register (LPTIM_RCR) . . . . .	1253
32.7.14	LPTIM capture/compare mode register 1 (LPTIM_CCMR1) . . . . .	1254
32.7.15	LPTIM compare register 2 (LPTIM_CCR2) . . . . .	1256
32.7.16	LPTIM register map . . . . .	1257
33	Infrared interface (IRTIM) . . . . .	1259
34	Independent watchdog (IWDG) . . . . .	1260
34.1	Introduction . . . . .	1260
34.2	IWDG main features . . . . .	1260
34.3	IWDG implementation . . . . .	1260
34.4	IWDG functional description . . . . .	1261
34.4.1	IWDG block diagram . . . . .	1261
34.4.2	IWDG internal signals . . . . .	1262
34.4.3	Software and hardware watchdog modes . . . . .	1262
34.4.4	Window option . . . . .	1263
34.4.5	Debug . . . . .	1266
34.4.6	Register access protection . . . . .	1266
34.5	IWDG low power modes . . . . .	1267
34.6	IWDG interrupts . . . . .	1267
34.7	IWDG registers . . . . .	1269
34.7.1	IWDG key register (IWDG_KR) . . . . .	1270
34.7.2	IWDG prescaler register (IWDG_PR) . . . . .	1270
34.7.3	IWDG reload register (IWDG_RLR) . . . . .	1271

34.7.4	IWDG status register (IWDG_SR) . . . . .	1271
34.7.5	IWDG window register (IWDG_WINR) . . . . .	1273
34.7.6	IWDG early wake-up interrupt register (IWDG_EWCR) . . . . .	1273
34.7.7	IWDG register map . . . . .	1275
35	System window watchdog (WWDG) . . . . .	1276
35.1	Introduction . . . . .	1276
35.2	WWDG main features . . . . .	1276
35.3	WWDG implementation . . . . .	1276
35.4	WWDG functional description . . . . .	1277
35.4.1	WWDG block diagram . . . . .	1277
35.4.2	WWDG internal signals . . . . .	1277
35.4.3	Enabling the watchdog . . . . .	1278
35.4.4	Controlling the down-counter . . . . .	1278
35.4.5	How to program the watchdog timeout . . . . .	1278
35.4.6	Debug mode . . . . .	1279
35.5	WWDG interrupts . . . . .	1280
35.6	WWDG registers . . . . .	1280
35.6.1	WWDG control register (WWDG_CR) . . . . .	1280
35.6.2	WWDG configuration register (WWDG_CFR) . . . . .	1281
35.6.3	WWDG status register (WWDG_SR) . . . . .	1282
35.6.4	WWDG register map . . . . .	1282
36	Real-time clock (RTC) . . . . .	1283
36.1	Introduction . . . . .	1283
36.2	RTC main features . . . . .	1283
36.3	RTC functional description . . . . .	1283
36.3.1	RTC block diagram . . . . .	1283
36.3.2	RTC pins and internal signals . . . . .	1285
36.3.3	GPIOs controlled by the RTC and TAMP . . . . .	1286
36.3.4	RTC secure protection modes . . . . .	1288
36.3.5	RTC privilege protection modes . . . . .	1290
36.3.6	Clock and prescalers . . . . .	1291
36.3.7	Real-time clock and calendar . . . . .	1292
36.3.8	Calendar ultra-low power mode . . . . .	1293
36.3.9	Programmable alarms . . . . .	1293

36.3.10	Periodic auto-wake-up . . . . .	1293
36.3.11	RTC initialization and configuration . . . . .	1294
36.3.12	Reading the calendar . . . . .	1297
36.3.13	Resetting the RTC . . . . .	1298
36.3.14	RTC synchronization . . . . .	1298
36.3.15	RTC reference clock detection . . . . .	1299
36.3.16	RTC smooth digital calibration . . . . .	1300
36.3.17	Timestamp function . . . . .	1302
36.3.18	Calibration clock output . . . . .	1302
36.3.19	Tamper and alarm output . . . . .	1303
36.4	RTC low-power modes . . . . .	1303
36.5	RTC interrupts . . . . .	1304
36.6	RTC registers . . . . .	1305
36.6.1	RTC time register (RTC_TR) . . . . .	1306
36.6.2	RTC date register (RTC_DR) . . . . .	1307
36.6.3	RTC subsecond register (RTC_SSR) . . . . .	1308
36.6.4	RTC initialization control and status register (RTC_ICSR) . . . . .	1309
36.6.5	RTC prescaler register (RTC_PRER) . . . . .	1311
36.6.6	RTC wake-up timer register (RTC_WUTR) . . . . .	1312
36.6.7	RTC control register (RTC_CR) . . . . .	1312
36.6.8	RTC privilege mode control register (RTC_PRIVCFGR) . . . . .	1316
36.6.9	RTC secure configuration register (RTC_SECCFGR) . . . . .	1318
36.6.10	RTC write protection register (RTC_WPR) . . . . .	1319
36.6.11	RTC calibration register (RTC_CALR) . . . . .	1320
36.6.12	RTC shift control register (RTC_SHIFTR) . . . . .	1321
36.6.13	RTC timestamp time register (RTC_TSTR) . . . . .	1322
36.6.14	RTC timestamp date register (RTC_TSDR) . . . . .	1323
36.6.15	RTC timestamp subsecond register (RTC_TSSSR) . . . . .	1324
36.6.16	RTC alarm A register (RTC_ALRMAR) . . . . .	1324
36.6.17	RTC alarm A subsecond register (RTC_ALRMASSR) . . . . .	1326
36.6.18	RTC alarm B register (RTC_ALRMBR) . . . . .	1327
36.6.19	RTC alarm B subsecond register (RTC_ALRMBSSR) . . . . .	1328
36.6.20	RTC status register (RTC_SR) . . . . .	1329
36.6.21	RTC nonsecure masked interrupt status register (RTC_MISR) . . . . .	1330
36.6.22	RTC secure masked interrupt status register (RTC_SMISR) . . . . .	1331
36.6.23	RTC status clear register (RTC_SCR) . . . . .	1332
36.6.24	RTC alarm A binary mode register (RTC_ALRABINR) . . . . .	1333

36.6.25	RTC alarm B binary mode register (RTC_ALRBBINR) . . . . .	1334
36.6.26	RTC register map . . . . .	1335
37	Tamper and backup registers (TAMP) . . . . .	1337
37.1	Introduction . . . . .	1337
37.2	TAMP main features . . . . .	1337
37.3	TAMP functional description . . . . .	1338
37.3.1	TAMP block diagram . . . . .	1338
37.3.2	TAMP pins and internal signals . . . . .	1339
37.3.3	GPIOs controlled by the RTC and TAMP . . . . .	1342
37.3.4	TAMP register write protection . . . . .	1342
37.3.5	TAMP secure protection modes . . . . .	1342
37.3.6	Backup registers protection zones . . . . .	1343
37.3.7	TAMP privilege protection modes . . . . .	1343
37.3.8	Boot hardware key (BHK) . . . . .	1344
37.3.9	Tamper detection . . . . .	1344
37.3.10	TAMP backup registers and other device secrets erase . . . . .	1344
37.3.11	Tamper detection configuration and initialization . . . . .	1346
37.4	TAMP low-power modes . . . . .	1352
37.5	TAMP interrupts . . . . .	1353
37.6	TAMP registers . . . . .	1353
37.6.1	TAMP control register 1 (TAMP_CR1) . . . . .	1353
37.6.2	TAMP control register 2 (TAMP_CR2) . . . . .	1355
37.6.3	TAMP control register 3 (TAMP_CR3) . . . . .	1358
37.6.4	TAMP filter control register (TAMP_FLTCR) . . . . .	1359
37.6.5	TAMP active tamper control register 1 (TAMP_ATCR1) . . . . .	1360
37.6.6	TAMP active tamper seed register (TAMP_ATSEEDR) . . . . .	1363
37.6.7	TAMP active tamper output register (TAMP_ATOR) . . . . .	1364
37.6.8	TAMP active tamper control register 2 (TAMP_ATCR2) . . . . .	1364
37.6.9	TAMP secure configuration register (TAMP_SECCFGR) . . . . .	1367
37.6.10	TAMP privilege configuration register (TAMP_PRIVCFGR) . . . . .	1368
37.6.11	TAMP interrupt enable register (TAMP_IER) . . . . .	1369
37.6.12	TAMP status register (TAMP_SR) . . . . .	1371
37.6.13	TAMP nonsecure masked interrupt status register (TAMP_MISR) . . . . .	1373
37.6.14	TAMP secure masked interrupt status register (TAMP_SMISR) . . . . .	1374
37.6.15	TAMP status clear register (TAMP_SCR) . . . . .	1376

37.6.16	TAMP monotonic counter 1 register (TAMP_COUNT1R) . . . . .	1378
37.6.17	TAMP resources protection configuration register (TAMP_RPCFGGR) . . . . .	1378
37.6.18	TAMP backup x register (TAMP_BKPxR) . . . . .	1379
37.6.19	TAMP register map . . . . .	1381
38	Inter-integrated circuit interface (I2C) . . . . .	1383
38.1	I2C introduction . . . . .	1383
38.2	I2C main features . . . . .	1383
38.3	I2C implementation . . . . .	1384
38.4	I2C functional description . . . . .	1384
38.4.1	I2C block diagram . . . . .	1385
38.4.2	I2C pins and internal signals . . . . .	1385
38.4.3	I2C clock requirements . . . . .	1387
38.4.4	I2C mode selection . . . . .	1387
38.4.5	I2C initialization . . . . .	1388
38.4.6	I2C reset . . . . .	1392
38.4.7	I2C data transfer . . . . .	1393
38.4.8	I2C target mode . . . . .	1395
38.4.9	I2C controller mode . . . . .	1404
38.4.10	I2C_TIMINGR register configuration examples . . . . .	1415
38.4.11	SMBus specific features . . . . .	1417
38.4.12	SMBus initialization . . . . .	1419
38.4.13	SMBus I2C_TIMEOUTR register configuration examples . . . . .	1421
38.4.14	SMBus target mode . . . . .	1422
38.4.15	SMBus controller mode . . . . .	1425
38.4.16	Autonomous mode . . . . .	1428
38.4.17	Error conditions . . . . .	1430
38.5	I2C in low-power modes . . . . .	1431
38.6	I2C interrupts . . . . .	1432
38.7	I2C DMA requests . . . . .	1432
38.7.1	Transmission using DMA . . . . .	1432
38.7.2	Reception using DMA . . . . .	1433
38.7.3	Controller event control using DMA . . . . .	1433
38.8	I2C debug modes . . . . .	1434
38.9	I2C registers . . . . .	1434
38.9.1	I2C control register 1 (I2C_CR1) . . . . .	1434

38.9.2	I2C control register 2 (I2C_CR2) . . . . .	1437
38.9.3	I2C own address 1 register (I2C_OAR1) . . . . .	1439
38.9.4	I2C own address 2 register (I2C_OAR2) . . . . .	1439
38.9.5	I2C timing register (I2C_TIMINGR) . . . . .	1440
38.9.6	I2C timeout register (I2C_TIMEOUTR) . . . . .	1441
38.9.7	I2C interrupt and status register (I2C_ISR) . . . . .	1442
38.9.8	I2C interrupt clear register (I2C_ICR) . . . . .	1445
38.9.9	I2C PEC register (I2C_PECR) . . . . .	1446
38.9.10	I2C receive data register (I2C_RXDR) . . . . .	1446
38.9.11	I2C transmit data register (I2C_TXDR) . . . . .	1447
38.9.12	I2C autonomous mode control register (I2C_AUTOCR) . . . . .	1447
38.9.13	I2C register map . . . . .	1449
39	Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . .	1451
39.1	Introduction . . . . .	1451
39.2	USART main features . . . . .	1451
39.3	USART extended features . . . . .	1452
39.4	USART implementation . . . . .	1452
39.5	USART functional description . . . . .	1454
39.5.1	USART block diagram . . . . .	1454
39.5.2	USART pins and internal signals . . . . .	1454
39.5.3	USART clocks . . . . .	1457
39.5.4	USART character description . . . . .	1457
39.5.5	USART FIFOs and thresholds . . . . .	1459
39.5.6	USART transmitter . . . . .	1459
39.5.7	USART receiver . . . . .	1462
39.5.8	USART baud rate generation . . . . .	1469
39.5.9	Tolerance of the USART receiver to clock deviation . . . . .	1471
39.5.10	USART auto baud rate detection . . . . .	1472
39.5.11	USART multiprocessor communication . . . . .	1474
39.5.12	USART Modbus communication . . . . .	1476
39.5.13	USART parity control . . . . .	1477
39.5.14	USART LIN (local interconnection network) mode . . . . .	1478
39.5.15	USART synchronous mode . . . . .	1480
39.5.16	USART single-wire half-duplex communication . . . . .	1484
39.5.17	USART receiver timeout . . . . .	1484

39.5.18	USART smartcard mode .....	1485
39.5.19	USART IrDA SIR ENDEC block .....	1489
39.5.20	Continuous communication using USART and DMA .....	1492
39.5.21	RS232 hardware flow control and RS485 driver enable .....	1494
39.5.22	USART autonomous mode .....	1496
39.6	USART in low-power modes .....	1498
39.7	USART interrupts .....	1498
39.8	USART registers .....	1501
39.8.1	USART control register 1 (USART_CR1) .....	1501
39.8.2	USART control register 1 [alternate] (USART_CR1) .....	1505
39.8.3	USART control register 2 (USART_CR2) .....	1508
39.8.4	USART control register 3 (USART_CR3) .....	1512
39.8.5	USART control register 3 [alternate] (USART_CR3) .....	1516
39.8.6	USART baud rate register (USART_BRR) .....	1519
39.8.7	USART guard time and prescaler register (USART_GTPR) .....	1520
39.8.8	USART receiver timeout register (USART_RTOR) .....	1521
39.8.9	USART request register (USART_RQR) .....	1522
39.8.10	USART interrupt and status register (USART_ISR) .....	1523
39.8.11	USART interrupt and status register [alternate] (USART_ISR) .....	1529
39.8.12	USART interrupt flag clear register (USART_ICR) .....	1534
39.8.13	USART receive data register (USART_RDR) .....	1535
39.8.14	USART transmit data register (USART_TDR) .....	1536
39.8.15	USART prescaler register (USART_PRESC) .....	1536
39.8.16	USART autonomous mode control register (USART_AUTOCR) .....	1537
39.8.17	USART register map .....	1538
40	Low-power universal asynchronous receiver transmitter (LPUART) .....	1540
40.1	Introduction .....	1540
40.2	LPUART main features .....	1540
40.3	LPUART implementation .....	1541
40.4	LPUART functional description .....	1542
40.4.1	LPUART block diagram .....	1542
40.4.2	LPUART pins and internal signals .....	1543
40.4.3	LPUART clocks .....	1545
40.4.4	LPUART character description .....	1545

- 40.4.5 LPUART FIFOs and thresholds . . . . . 1547
- 40.4.6 LPUART transmitter . . . . . 1547
- 40.4.7 LPUART receiver . . . . . 1551
- 40.4.8 LPUART baud rate generation . . . . . 1555
- 40.4.9 Tolerance of the LPUART receiver to clock deviation . . . . . 1556
- 40.4.10 LPUART multiprocessor communication . . . . . 1557
- 40.4.11 LPUART parity control . . . . . 1559
- 40.4.12 LPUART single-wire half-duplex communication . . . . . 1560
- 40.4.13 Continuous communication using DMA and LPUART . . . . . 1560
- 40.4.14 RS232 hardware flow control and RS485 driver enable . . . . . 1563
- 40.4.15 LPUART autonomous mode . . . . . 1565
40.5 LPUART in low-power modes . . . . . 1567
40.6 LPUART interrupts . . . . . 1568
40.7 LPUART registers . . . . . 1569
- 40.7.1 LPUART control register 1 (LPUART_CR1) . . . . . 1569
- 40.7.2 LPUART control register 1 [alternate] (LPUART_CR1) . . . . . 1572
- 40.7.3 LPUART control register 2 (LPUART_CR2) . . . . . 1575
- 40.7.4 LPUART control register 3 (LPUART_CR3) . . . . . 1577
- 40.7.5 LPUART control register 3 [alternate] (LPUART_CR3) . . . . . 1579
- 40.7.6 LPUART baud rate register (LPUART_BRR) . . . . . 1581
- 40.7.7 LPUART request register (LPUART_RQR) . . . . . 1581
- 40.7.8 LPUART interrupt and status register (LPUART_ISR) . . . . . 1582
- 40.7.9 LPUART interrupt and status register [alternate] (LPUART_ISR) . . . . . 1587
- 40.7.10 LPUART interrupt flag clear register (LPUART_ICR) . . . . . 1590
- 40.7.11 LPUART receive data register (LPUART_RDR) . . . . . 1591
- 40.7.12 LPUART transmit data register (LPUART_TDR) . . . . . 1591
- 40.7.13 LPUART prescaler register (LPUART_PRESC) . . . . . 1592
- 40.7.14 LPUART autonomous mode control register (LPUART_AUTOOCR) . . . . . 1593
- 40.7.15 LPUART register map . . . . . 1593

41 Serial peripheral interface (SPI) . . . . . 1596
- 41.1 Introduction . . . . . 1596
- 41.2 SPI main features . . . . . 1596
- 41.3 SPI implementation . . . . . 1597
- 41.4 SPI functional description . . . . . 1598
  - 41.4.1 SPI block diagram . . . . . 1598

41.4.2	SPI pins and internal signals . . . . .	1599
41.4.3	SPI communication general aspects . . . . .	1601
41.4.4	Communications between one master and one slave . . . . .	1601
41.4.5	Standard multislave communication . . . . .	1604
41.4.6	Multimaster communication . . . . .	1607
41.4.7	Slave select (NSS pin) management . . . . .	1608
41.4.8	Ready pin (RDY) management . . . . .	1612
41.4.9	Communication formats . . . . .	1612
41.4.10	Configuring the SPI . . . . .	1614
41.4.11	Enabling the SPI . . . . .	1615
41.4.12	SPI data transmission and reception procedures . . . . .	1616
41.4.13	Disabling the SPI . . . . .	1620
41.4.14	Communication using DMA (direct memory addressing) . . . . .	1621
41.4.15	Autonomous mode . . . . .	1622
41.5	SPI specific modes and control . . . . .	1624
41.5.1	TI mode . . . . .	1624
41.5.2	SPI error flags . . . . .	1625
41.5.3	CRC computation . . . . .	1628
41.6	SPI in low-power modes . . . . .	1629
41.7	SPI interrupts . . . . .	1629
41.8	SPI registers . . . . .	1631
41.8.1	SPI control register 1 (SPI_CR1) . . . . .	1631
41.8.2	SPI control register 2 (SPI_CR2) . . . . .	1633
41.8.3	SPI configuration register 1 (SPI_CFG1) . . . . .	1633
41.8.4	SPI configuration register 2 (SPI_CFG2) . . . . .	1636
41.8.5	SPI interrupt enable register (SPI_IER) . . . . .	1638
41.8.6	SPI status register (SPI_SR) . . . . .	1639
41.8.7	SPI interrupt/status flags clear register (SPI_IFCR) . . . . .	1642
41.8.8	SPI autonomous mode control register (SPI_AUTOCR) . . . . .	1643
41.8.9	SPI transmit data register (SPI_TXDR) . . . . .	1643
41.8.10	SPI receive data register (SPI_RXDR) . . . . .	1644
41.8.11	SPI polynomial register (SPI_CRCPOLY) . . . . .	1644
41.8.12	SPI transmitter CRC register (SPI_TXCRC) . . . . .	1645
41.8.13	SPI receiver CRC register (SPI_RXCRC) . . . . .	1646
41.8.14	SPI underrun data register (SPI_UDRDR) . . . . .	1646
41.8.15	SPI register map . . . . .	1647

42 Serial audio interface (SAI) . . . . . 1648

42.1 Introduction . . . . . 1648

42.2 SAI main features . . . . . 1648

42.3 SAI implementation . . . . . 1649

42.4 SAI functional description . . . . . 1650

42.4.1 SAI block diagram . . . . . 1650

42.4.2 SAI pins and internal signals . . . . . 1651

42.4.3 Main SAI modes . . . . . 1651

42.4.4 SAI synchronization mode . . . . . 1652

42.4.5 Audio data size . . . . . 1653

42.4.6 Frame synchronization . . . . . 1653

42.4.7 Slot configuration . . . . . 1656

42.4.8 SAI clock generator . . . . . 1658

42.4.9 Internal FIFOs . . . . . 1661

42.4.10 PDM interface . . . . . 1663

42.4.11 AC'97 link controller . . . . . 1671

42.4.12 SPDIF output . . . . . 1672

42.4.13 Specific features . . . . . 1675

42.4.14 Error flags . . . . . 1679

42.4.15 Disabling the SAI . . . . . 1682

42.4.16 SAI DMA interface . . . . . 1682

42.5 SAI interrupts . . . . . 1683

42.6 SAI registers . . . . . 1685

42.6.1 SAI configuration register 1 (SAI_ACR1) . . . . . 1685

42.6.2 SAI configuration register 2 (SAI_ACR2) . . . . . 1687

42.6.3 SAI frame configuration register (SAI_AFRCR) . . . . . 1689

42.6.4 SAI slot register (SAI_ASLOTR) . . . . . 1690

42.6.5 SAI interrupt mask register (SAI_AIM) . . . . . 1691

42.6.6 SAI status register (SAI_ASR) . . . . . 1693

42.6.7 SAI clear flag register (SAI_ACLRFR) . . . . . 1695

42.6.8 SAI data register (SAI_ADR) . . . . . 1696

42.6.9 SAI configuration register 1 (SAI_BCR1) . . . . . 1696

42.6.10 SAI configuration register 2 (SAI_BCR2) . . . . . 1699

42.6.11 SAI frame configuration register (SAI_BFRCR) . . . . . 1701

42.6.12 SAI slot register (SAI_BSLOTR) . . . . . 1702

42.6.13 SAI interrupt mask register (SAI_BIM) . . . . . 1703

42.6.14	SAI status register (SAI_BSR) . . . . .	1704
42.6.15	SAI clear flag register (SAI_BCLRFR) . . . . .	1706
42.6.16	SAI data register (SAI_BDR) . . . . .	1707
42.6.17	SAI PDM control register (SAI_PDMCR) . . . . .	1708
42.6.18	SAI PDM delay register (SAI_PDMDLY) . . . . .	1709
42.6.19	SAI register map . . . . .	1711
43	Debug support (DBG) . . . . .	1713
43.1	DBG introduction and main features . . . . .	1713
43.2	DBG functional description . . . . .	1714
43.2.1	DBG block diagram . . . . .	1714
43.2.2	DBG pins and internal signals . . . . .	1714
43.2.3	DBG reset and clocks . . . . .	1714
43.2.4	DBG power domains . . . . .	1715
43.2.5	DBG low-power modes . . . . .	1715
43.2.6	DBG security . . . . .	1715
43.2.7	Serial-wire and JTAG debug port . . . . .	1717
43.2.8	JTAG debug port . . . . .	1718
43.2.9	Serial-wire debug port . . . . .	1720
43.3	Debug port registers . . . . .	1721
43.3.1	DP identification register [alternate] (DP_PIDR) . . . . .	1722
43.3.2	DP abort register [alternate] (DP_ABORTR) . . . . .	1722
43.3.3	DP control and status register (DP_CTRLSTATR) . . . . .	1723
43.3.4	DP data link control register (DP_DLCR) . . . . .	1724
43.3.5	DP target identification register (DP_TARGETIDR) . . . . .	1725
43.3.6	DP data link protocol identification register (DP_DLPIDR) . . . . .	1726
43.3.7	DP resend register (DP_EVENSTATR) . . . . .	1726
43.3.8	DP resend register (DP_RESENR) . . . . .	1726
43.3.9	DP access port select register (DP_SELECTR) . . . . .	1727
43.3.10	DP read buffer register (DP_BUFFR) . . . . .	1727
43.3.11	DP register map and reset values . . . . .	1728
43.4	Access port . . . . .	1730
43.4.1	Access port registers . . . . .	1730
43.4.2	AP control/status word register (APx_CSWR) (x = 0 to 1) . . . . .	1731
43.4.3	AP transfer address register (APx_TAR) (x = 0 to 1) . . . . .	1732
43.4.4	AP data read/write register (APx_DRWR) (x = 0 to 1) . . . . .	1732
43.4.5	AP banked data registers y (APx_BDyR) (x = 0 to 1) . . . . .	1732

43.4.6	AP configuration register (APx_CFGGR) (x = 0 to 1) . . . . .	1733
43.4.7	AP base address register (APx_BASER) (x = 0 to 1) . . . . .	1733
43.4.8	AP identification register (APx_IDR) (x = 0 to 1) . . . . .	1734
43.4.9	Access port register map and reset values . . . . .	1734
43.5	System debug AP0 features . . . . .	1736
43.5.1	System debug ROM table . . . . .	1736
43.5.2	System debug memory type register (SYSROM_MEMTYPER) . . . . .	1737
43.5.3	System debug CoreSight peripheral identity register 4 (SYSROM_PIDR4) . . . . .	1737
43.5.4	System debug CoreSight peripheral identity register 0 (SYSROM_PIDR0) . . . . .	1737
43.5.5	System debug CoreSight peripheral identity register 1 (SYSROM_PIDR1) . . . . .	1738
43.5.6	System debug CoreSight peripheral identity register 2 (SYSROM_PIDR2) . . . . .	1738
43.5.7	System debug CoreSight peripheral identity register 3 (SYSROM_PIDR3) . . . . .	1739
43.5.8	System debug CoreSight component identity register 0 (SYSROM_CIDR0) . . . . .	1739
43.5.9	System debug CoreSight peripheral identity register 1 (SYSROM_CIDR1) . . . . .	1740
43.5.10	System debug CoreSight component identity register 2 (SYSROM_CIDR2) . . . . .	1740
43.5.11	System debug CoreSight component identity register 3 (SYSROM_CIDR3) . . . . .	1740
43.5.12	System debug ROM table register map and reset values . . . . .	1742
43.6	Cortex-M33 AP1 features . . . . .	1743
43.6.1	CPU ROM tables . . . . .	1743
43.6.2	MCU and processor ROM memory type register (ROM_MEMTYPER) . . . . .	1745
43.6.3	MCU and processor ROM CoreSight peripheral identity register 4 (ROM_PIDR4) . . . . .	1746
43.6.4	MCU and processor ROM CoreSight peripheral identity register 0 (ROM_PIDR0) . . . . .	1746
43.6.5	MCU and processor ROM CoreSight peripheral identity register 1 (ROM_PIDR1) . . . . .	1747
43.6.6	MCU and processor ROM CoreSight peripheral identity register 2 (ROM_PIDR2) . . . . .	1747
43.6.7	MCU and processor ROM CoreSight peripheral identity register 3 (ROM_PIDR3) . . . . .	1748

43.6.8	MCU and processor ROM CoreSight component identity register 0 (ROM_CIDR0) . . . . .	1748
43.6.9	MCU and processor ROM CoreSight peripheral identity register 1 (ROM_CIDR1) . . . . .	1749
43.6.10	MCU and processor ROM CoreSight component identity register 2 (ROM_CIDR2) . . . . .	1749
43.6.11	MCU and processor ROM CoreSight component identity register 3 (ROM_CIDR3) . . . . .	1750
43.6.12	MCU and processor ROM tables register map and reset values . . . . .	1751
43.7	Data watchpoint and trace unit (DWT) . . . . .	1752
43.7.1	DWT control register (DWT_CTRLR) . . . . .	1753
43.7.2	DWT cycle count register (DWT_CYCCNTR) . . . . .	1754
43.7.3	DWT CPI count register (DWT_CPICNTR) . . . . .	1755
43.7.4	DWT exception count register (DWT_EXCCNTR) . . . . .	1755
43.7.5	DWT sleep count register (DWT_SLP CNTR) . . . . .	1755
43.7.6	DWT LSU count register (DWT_LSUCNTR) . . . . .	1756
43.7.7	DWT fold count register (DWT_FOLDCNTR) . . . . .	1756
43.7.8	DWT program counter sample register (DWT_PCSR) . . . . .	1756
43.7.9	DWT comparator register x (DWT_COMPxR) . . . . .	1757
43.7.10	DWT function register 0(DWT_FUNCTR0) . . . . .	1757
43.7.11	DWT device type architecture register (DWT_DEVARCHR) . . . . .	1761
43.7.12	DWT device type register 4 (DWT_DEVTYPE) . . . . .	1762
43.7.13	DWT CoreSight peripheral identity register 4 (DWT_PIDR4) . . . . .	1762
43.7.14	DWT CoreSight peripheral identity register 0 (DWT_PIDR0) . . . . .	1763
43.7.15	DWT CoreSight peripheral identity register 1 (DWT_PIDR1) . . . . .	1763
43.7.16	DWT CoreSight peripheral identity register 2 (DWT_PIDR2) . . . . .	1763
43.7.17	DWT CoreSight peripheral identity register 3 (DWT_PIDR3) . . . . .	1764
43.7.18	DWT CoreSight component identity register 0 (DWT_CIDR0) . . . . .	1764
43.7.19	DWT CoreSight peripheral identity register 1 (DWT_CIDR1) . . . . .	1765
43.7.20	DWT CoreSight component identity register 2 (DWT_CIDR2) . . . . .	1765
43.7.21	DWT CoreSight component identity register 3 (DWT_CIDR3) . . . . .	1766
43.7.22	DWT register map and reset values . . . . .	1767
43.8	Instrumentation trace macrocell (ITM) . . . . .	1770
43.8.1	ITM registers . . . . .	1770
43.8.2	ITM stimulus register x (ITM_STIMRx) . . . . .	1770
43.8.3	ITM trace enable register (ITM_TER) . . . . .	1771
43.8.4	ITM trace privilege register (ITM_TPR) . . . . .	1771
43.8.5	ITM trace control register (ITM_TCR) . . . . .	1772

43.8.6	ITM device type architecture register (ITM_DEVARCHR) . . . . .	1773
43.8.7	ITM device type register 4 (ITM_DEVTYPE) . . . . .	1773
43.8.8	ITM CoreSight peripheral identity register 4 (ITM_PIDR4) . . . . .	1774
43.8.9	ITM CoreSight peripheral identity register 0 (ITM_PIDR0) . . . . .	1774
43.8.10	ITM CoreSight peripheral identity register 1 (ITM_PIDR1) . . . . .	1775
43.8.11	ITM CoreSight peripheral identity register 2 (ITM_PIDR2) . . . . .	1775
43.8.12	ITM CoreSight peripheral identity register 3 (ITM_PIDR3) . . . . .	1776
43.8.13	ITM CoreSight component identity register 0 (ITM_CIDR0) . . . . .	1776
43.8.14	ITM CoreSight peripheral identity register 1 (ITM_CIDR1) . . . . .	1777
43.8.15	ITM CoreSight component identity register 2 (ITM_CIDR2) . . . . .	1777
43.8.16	ITM CoreSight component identity register 3 (ITM_CIDR3) . . . . .	1778
43.8.17	ITM register map and reset values . . . . .	1779
43.9	Breakpoint unit (BPU) . . . . .	1781
43.9.1	BPU control register (BPU_CTRLR) . . . . .	1781
43.9.2	BPU comparator x register (BPU_COMPxR) . . . . .	1781
43.9.3	BPU device type architecture register (BPU_DEVARCHR) . . . . .	1782
43.9.4	BPU device type register 4 (BPU_DEVTYPE) . . . . .	1782
43.9.5	BPU CoreSight peripheral identity register 4 (BPU_PIDR4) . . . . .	1783
43.9.6	BPU CoreSight peripheral identity register 0 (BPU_PIDR0) . . . . .	1783
43.9.7	BPU CoreSight peripheral identity register 1 (BPU_PIDR1) . . . . .	1784
43.9.8	BPU CoreSight peripheral identity register 2 (BPU_PIDR2) . . . . .	1784
43.9.9	BPU CoreSight peripheral identity register 3 (BPU_PIDR3) . . . . .	1785
43.9.10	BPU CoreSight component identity register 0 (BPU_CIDR0) . . . . .	1785
43.9.11	BPU CoreSight peripheral identity register 1 (BPU_CIDR1) . . . . .	1786
43.9.12	BPU CoreSight component identity register 2 (BPU_CIDR2) . . . . .	1786
43.9.13	BPU CoreSight component identity register 3 (BPU_CIDR3) . . . . .	1787
43.9.14	BPU register map and reset values . . . . .	1788
43.10	Trace port interface unit (TPIU) . . . . .	1789
43.10.1	TPIU registers . . . . .	1789
43.10.2	TPIU supported port size register (TPIU_SSPSR) . . . . .	1789
43.10.3	TPIU current port size register (TPIU_CSPSR) . . . . .	1790
43.10.4	TPIU asynchronous clock prescaler register (TPIU_ACPR) . . . . .	1790
43.10.5	TPIU selected pin protocol register (TPIU_SPPR) . . . . .	1790
43.10.6	TPIU formatter and flush status register (TPIU_FFSR) . . . . .	1791
43.10.7	TPIU formatter and flush control register (TPIU_FFCR) . . . . .	1792
43.10.8	TPIU formatter synchronization counter register (TPIU_FSCR) . . . . .	1792
43.10.9	TPIU claim tag set register (TPIU_CLAIMSETR) . . . . .	1793

43.10.10	TPIU claim tag clear register (TPIU_CLAIMCLR) . . . . .	1793
43.10.11	TPIU device configuration register (TPIU_DEVIDR) . . . . .	1794
43.10.12	TPIU device type identifier register (TPIU_DEVTYPE) . . . . .	1795
43.10.13	TPIU CoreSight peripheral identity register 4 (TPIU_PIDR4) . . . . .	1795
43.10.14	TPIU CoreSight peripheral identity register 0 (TPIU_PIDR0) . . . . .	1796
43.10.15	TPIU CoreSight peripheral identity register 1 (TPIU_PIDR1) . . . . .	1796
43.10.16	TPIU CoreSight peripheral identity register 2 (TPIU_PIDR2) . . . . .	1797
43.10.17	TPIU CoreSight peripheral identity register 3 (TPIU_PIDR3) . . . . .	1797
43.10.18	TPIU CoreSight component identity register 0 (TPIU_CIDR0) . . . . .	1798
43.10.19	TPIU CoreSight peripheral identity register 1 (TPIU_CIDR1) . . . . .	1798
43.10.20	TPIU CoreSight component identity register 2 (TPIU_CIDR2) . . . . .	1799
43.10.21	TPIU CoreSight component identity register 3 (TPIU_CIDR3) . . . . .	1799
43.10.22	TPIU register map and reset values . . . . .	1800
43.11	Cross trigger interface (CTI) . . . . .	1802
43.11.1	CTI registers . . . . .	1803
43.12	Microcontroller debug unit (DBGMCU) . . . . .	1816
43.12.1	DBGMCU access . . . . .	1816
43.12.2	Device ID . . . . .	1816
43.12.3	Part number codification . . . . .	1816
43.12.4	Low-power mode emulation . . . . .	1816
43.12.5	Low-power mode status . . . . .	1818
43.12.6	Peripheral clock freeze . . . . .	1818
43.12.7	DBGMCU registers . . . . .	1819
43.12.8	DBGMCU register map and reset values . . . . .	1831
43.13	References . . . . .	1833
44	Device electronic signature (DESIG) . . . . .	1834
44.1	Device electronic signature registers . . . . .	1834
44.1.1	DESIG package data register (DESIG_PKGR) . . . . .	1834
44.1.2	DESIG 96-bit unique device ID register 1 (DESIG_UIDR1) . . . . .	1834
44.1.3	DESIG 96-bit unique device ID register 2 (DESIG_UIDR2) . . . . .	1835
44.1.4	DESIG 96-bit unique device ID register 3 (DESIG_UIDR3) . . . . .	1835
44.1.5	DESIG temperature calibration 1 register (DESIG_TSCAL1R) . . . . .	1835
44.1.6	DESIG temperature calibration 2 register (DESIG_TSCAL2R) . . . . .	1836
44.1.7	DESIG FLASH size data register (DESIG_FLASHSIZER) . . . . .	1836
44.1.8	DESIG internal voltage reference calibration register (DESIG_VREFINTCALR) . . . . .	1837

44.1.9	DESIG resistor calibration register (DESIG_RCALR) . . . . .	1837
44.1.10	DESIG radio gain calibration register (DESIG_RFGAINCALR) . . . . .	1837
44.1.11	DESIG IEEE 64-bit unique device ID register 1 (DESIG_UID64R1) . . . . .	1838
44.1.12	DESIG IEEE 64-bit unique device ID register 2 (DESIG_UID64R2) . . . . .	1838
44.1.13	DESIG register map . . . . .	1839
45	Important security notice . . . . .	1841
46	Revision history . . . . .	1842

List of tables

Table 1.	Bus matrix access arbitration . . . . .	74
Table 2.	Memory map security attribution example vs. SAU configuration regions . . . . .	75
Table 3.	Securable peripherals by TZSC . . . . .	76
Table 4.	TrustZone-aware peripherals . . . . .	77
Table 5.	Memory map and peripheral register boundary addresses . . . . .	81
Table 6.	Configuring security attributes with IDAU and SAU . . . . .	91
Table 7.	MPCBBx resources . . . . .	93
Table 8.	DMA channel use (security) . . . . .	96
Table 9.	Secure alternate function between peripherals and allocated I/Os . . . . .	98
Table 10.	Nonsecure peripheral functions not connected to secure I/Os . . . . .	99
Table 11.	Nonsecure peripheral functions that can be connected to secure I/Os . . . . .	99
Table 12.	TrustZone-aware DBGMCU accesses management . . . . .	100
Table 13.	DMA channel use (privilege). . . . .	105
Table 14.	Internal tampers in TAMP . . . . .	108
Table 15.	Effect of low-power modes on TAMP . . . . .	110
Table 16.	Accelerated cryptographic operations . . . . .	112
Table 17.	Main product life-cycle transitions. . . . .	114
Table 18.	Typical product life-cycle phases . . . . .	115
Table 19.	OEM key RDP unlocking methods . . . . .	117
Table 20.	Debug protection with RDP . . . . .	118
Table 21.	Software intellectual property protection with RDP. . . . .	120
Table 22.	Boot modes when TrustZone is disabled (TZEN = 0). . . . .	121
Table 23.	Boot modes when TrustZone is enabled (TZEN = 1). . . . .	121
Table 24.	Boot space versus RDP protection. . . . .	122
Table 25.	GTZC features . . . . .	126
Table 26.	GTZC sub-blocks address offset . . . . .	126
Table 27.	MPCBB resource assignment. . . . .	127
Table 28.	GTZC interrupt request. . . . .	130
Table 29.	GTZC1 TZSC register map and reset values . . . . .	141
Table 30.	GTZC1 TZIC register map and reset values. . . . .	159
Table 31.	GTZC1 MPCBB1 and MPCBB2 register map and reset values. . . . .	163
Table 32.	GTZC1 MPCBB6 register map and reset values . . . . .	164
Table 33.	SRAMs features . . . . .	166
Table 34.	SRAM parity access error. . . . .	167
Table 35.	SRAM parity error bus master ID . . . . .	167
Table 36.	Number of wait states versus hclk frequency and voltage range scaling . . . . .	167
Table 37.	Effect of low-power modes on RAMCFG . . . . .	168
Table 38.	RAMCFG interrupt requests . . . . .	168
Table 39.	RAMCFG register map and reset values . . . . .	175
Table 40.	Flash module 1-Mbyte single bank organization . . . . .	177
Table 41.	Number of wait states according to CPU clock (hclk1) frequency (LPM = 0). . . . .	179
Table 42.	Number of wait states according to CPU clock (hclk1) frequency (LPM = 1). . . . .	179
Table 43.	Program and erase suspend control. . . . .	188
Table 44.	Flash operation interrupted by a system reset . . . . .	191
Table 45.	User option byte organization mapping . . . . .	192
Table 46.	Default secure option bytes after TZEN activation . . . . .	195
Table 47.	Secure watermark-based area . . . . .	196
Table 48.	Secure hide protection . . . . .	197

Table 49.	Flash security state . . . . .	198
Table 50.	WRP protection. . . . .	199
Table 51.	Flash memory readout protection status (TZEN=0) . . . . .	200
Table 52.	Access status versus protection level and execution modes when TZEN = 0 . . . . .	201
Table 53.	Flash memory readout protection status (TZEN = 1) . . . . .	202
Table 54.	Access status versus protection level and execution modes when TZEN = 1 . . . . .	203
Table 55.	Flash memory access vs. RDP level when TrustZone is active (TZEN = 1) . . . . .	209
Table 56.	Flash memory access vs. RDP level when TrustZone is disabled (TZEN = 0) . . . . .	209
Table 57.	Flash memory mass erase versus RDP level when TrustZone is active (TZEN = 1) . . . . .	210
Table 58.	Flash system memory, OTP and RSS accesses . . . . .	210
Table 59.	Flash registers access . . . . .	211
Table 60.	Flash page access versus privilege mode . . . . .	211
Table 61.	Flash mass erase versus privilege mode . . . . .	211
Table 62.	SECBBRx registers access when TrustZone is active (TZEN = 1) . . . . .	211
Table 63.	PRIVBBRx registers access when TrustZone is active (TZEN = 1) . . . . .	212
Table 64.	PRIVBBRx registers access when TrustZone is disabled (TZEN = 0) . . . . .	212
Table 65.	Flash interrupt requests . . . . .	212
Table 66.	FLASH register map and reset values . . . . .	237
Table 67.	ICACHE features . . . . .	242
Table 68.	TAG memory dimensioning parameters for n-way set associative operating mode (default) . . . . .	244
Table 69.	TAG memory dimensioning parameters for direct-mapped cache mode . . . . .	245
Table 70.	ICACHE cacheability for AHB transaction . . . . .	247
Table 71.	Memory configurations . . . . .	247
Table 72.	ICACHE remap region size, base address, and remap address . . . . .	248
Table 73.	ICACHE interrupts . . . . .	252
Table 74.	ICACHE register map and reset values . . . . .	257
Table 75.	2.4 GHz RADIO implementation . . . . .	259
Table 76.	Input / output pins . . . . .	259
Table 77.	PA output power table format . . . . .	260
Table 78.	2.4 GHz RADIO supply configuration . . . . .	261
Table 79.	Effect of low-power modes on the 2.4 GHz RADIO . . . . .	262
Table 80.	2.4 PTACONV input/output pins . . . . .	264
Table 81.	PTACONV internal input/output signals . . . . .	264
Table 82.	2.4 PTACONV timing parameters . . . . .	268
Table 83.	Effect of low-power modes on the PTACONV . . . . .	269
Table 84.	PTACONV register map and reset values . . . . .	272
Table 85.	PWR input/output pins . . . . .	274
Table 86.	PWR internal input/output signals . . . . .	274
Table 87.	PWR wake-up source selection . . . . .	275
Table 88.	Low-power mode summary . . . . .	288
Table 89.	Functionalities depending on the working mode . . . . .	289
Table 90.	Sleep mode . . . . .	295
Table 91.	Stop 0 mode . . . . .	297
Table 92.	Stop 1 mode . . . . .	299
Table 93.	GPIO retention pin with pull-up and pull-down . . . . .	301
Table 94.	Standby mode . . . . .	302
Table 95.	Power modes output states versus MCU power modes . . . . .	303
Table 96.	PWR security configuration summary . . . . .	304
Table 97.	PWR interrupt requests . . . . .	306
Table 98.	PWR register map and reset values . . . . .	328
Table 99.	RCC input/output signals connected to package pins or balls . . . . .	331

Table 100.	LSI clock selection . . . . .	342
Table 101.	SYSCLK and bus maximum frequency . . . . .	343
Table 102.	Clock source maximum frequency . . . . .	344
Table 103.	2.4 GHz RADIO bus clock control . . . . .	347
Table 104.	Autonomous peripherals . . . . .	354
Table 105.	RCC security configuration summary . . . . .	356
Table 106.	Interrupt sources and control . . . . .	359
Table 107.	RCC register map and reset values . . . . .	429
Table 108.	HSEM internal input/output signals . . . . .	436
Table 109.	Semaphore attributes . . . . .	441
Table 110.	Authorized AHB bus master ID . . . . .	442
Table 111.	HSEM register map and reset values . . . . .	455
Table 112.	GPIO implementation . . . . .	457
Table 113.	Port bit configuration . . . . .	459
Table 114.	GPIO secured bits . . . . .	467
Table 115.	GPIOA register map and reset values . . . . .	497
Table 116.	GPIOB register map and reset values . . . . .	499
Table 117.	GPIOC register map and reset values . . . . .	501
Table 118.	GPIOH register map and reset values . . . . .	502
Table 119.	Effect of low-power modes on I/O compensation . . . . .	504
Table 120.	TrustZone security and privilege register accesses . . . . .	504
Table 121.	BOOSTEN and ANASWVDD set/reset . . . . .	508
Table 122.	SYSCFG register map and reset values . . . . .	517
Table 123.	Peripherals interconnect matrix . . . . .	518
Table 124.	GPDMA1 implementation . . . . .	528
Table 125.	GPDMA1 channel implementation . . . . .	529
Table 126.	GPDMA1 autonomous mode and wake-up in low-power modes . . . . .	529
Table 127.	Programmed GPDMA1 request . . . . .	529
Table 128.	Programmed GPDMA1 request as a block request . . . . .	531
Table 129.	Programmed GPDMA1 trigger . . . . .	531
Table 130.	Programmed GPDMA source/destination burst . . . . .	551
Table 131.	Programmed data handling . . . . .	554
Table 132.	Effect of low-power modes on GPDMA . . . . .	567
Table 133.	GPDMA interrupt requests . . . . .	568
Table 134.	GPDMA register map and reset values . . . . .	589
Table 135.	Vector table . . . . .	591
Table 136.	EXTI pin overview . . . . .	596
Table 137.	EVG pin overview . . . . .	596
Table 138.	EXTI line connections . . . . .	597
Table 139.	Masking functionality . . . . .	599
Table 140.	Register protection overview . . . . .	600
Table 141.	EXTI register map sections . . . . .	602
Table 142.	EXTI register map and reset values . . . . .	615
Table 143.	CRC internal input/output signals . . . . .	618
Table 144.	CRC register map and reset values . . . . .	623
Table 145.	ADC features . . . . .	625
Table 146.	Memory location of the temperature sensor calibration values . . . . .	626
Table 147.	Memory location of the internal reference voltage sensor calibration value . . . . .	626
Table 148.	ADC input/output pins . . . . .	628
Table 149.	ADC internal input/output signals . . . . .	628
Table 150.	ADC interconnection . . . . .	628

Table 151.	Latency between trigger and start of conversion . . . . .	633
Table 152.	Configuring the trigger polarity . . . . .	640
Table 153.	$t_{SAR}$ timings depending on resolution . . . . .	642
Table 154.	Analog watchdog comparison . . . . .	654
Table 155.	Analog watchdog 1 channel selection . . . . .	654
Table 156.	Maximum output results vs N and M. Grayed values indicates truncation . . . . .	658
Table 157.	Effect of low-power modes on the ADC . . . . .	663
Table 158.	ADC wake-up and interrupt requests . . . . .	664
Table 159.	ADC register map and reset values . . . . .	684
Table 160.	COMP1 noninverting input assignment . . . . .	688
Table 161.	COMP1 inverting input assignment . . . . .	689
Table 162.	COMP2 noninverting input assignment . . . . .	689
Table 163.	COMP2 inverting input assignment . . . . .	689
Table 164.	COMP1 output-blanking PWM assignment . . . . .	690
Table 165.	COMP2 output-blanking PWM assignment . . . . .	690
Table 166.	Comparator behavior in the low-power modes . . . . .	693
Table 167.	Interrupt control bits . . . . .	694
Table 168.	COMP register map and reset values . . . . .	697
Table 169.	Acquisition sequence summary . . . . .	701
Table 170.	Spread spectrum deviation versus AHB clock frequency . . . . .	703
Table 171.	I/O state depending on its mode and IODEF bit value . . . . .	704
Table 172.	Effect of low-power modes on TSC . . . . .	706
Table 173.	Interrupt control bits . . . . .	706
Table 174.	TSC register map and reset values . . . . .	714
Table 175.	RNG internal input/output signals . . . . .	717
Table 176.	RNG interrupt requests . . . . .	725
Table 177.	RNG initialization times . . . . .	726
Table 178.	RNG configurations . . . . .	726
Table 179.	Configuration selection . . . . .	727
Table 180.	RNG register map and reset map . . . . .	732
Table 181.	AES versus SAES features . . . . .	734
Table 182.	AES internal input/output signals . . . . .	735
Table 183.	AES approved symmetric key functions . . . . .	736
Table 184.	Counter mode initialization vector definition . . . . .	745
Table 185.	Initialization of IV registers in GCM mode . . . . .	748
Table 186.	GCM last block definition . . . . .	748
Table 187.	Initialization of IV registers in CCM mode . . . . .	755
Table 188.	AES data swapping example . . . . .	758
Table 189.	Key endianness in AES_KEYRx registers (128/256-bit keys) . . . . .	760
Table 190.	IVI bitfield spread over AES_IVRx registers . . . . .	761
Table 191.	AES interrupt requests . . . . .	762
Table 192.	Processing latency for ECB, CBC and CTR . . . . .	763
Table 193.	Processing latency for GCM and CCM (in clock cycles) . . . . .	764
Table 194.	AES register map and reset values . . . . .	776
Table 195.	AES versus SAES features . . . . .	780
Table 196.	SAES internal input/output signals . . . . .	781
Table 197.	SAES approved symmetric key functions . . . . .	782
Table 198.	Counter mode initialization vector definition . . . . .	792
Table 199.	Initialization of IV registers in GCM mode . . . . .	795
Table 200.	GCM last block definition . . . . .	795
Table 201.	Initialization of IV registers in CCM mode . . . . .	801
Table 202.	AES data swapping example . . . . .	810

Table 203.	Key endianness in SAES_KEYRx registers (128/256-bit keys) . . . . .	812
Table 204.	IVI bitfield spread over SAES_IVRx registers. . . . .	814
Table 205.	SAES interrupt requests . . . . .	816
Table 206.	Processing latency for ECB, CBC and CTR. . . . .	817
Table 207.	Processing latency for GCM and CCM (in SAES kernel clock cycles) . . . . .	817
Table 208.	SAES register map and reset values . . . . .	832
Table 209.	HASH internal input/output signals . . . . .	836
Table 210.	Hash processor outputs . . . . .	839
Table 211.	Processing time (in clock cycle) . . . . .	845
Table 212.	HASH interrupt requests. . . . .	846
Table 213.	HASH register map and reset values . . . . .	854
Table 214.	Internal input/output signals . . . . .	857
Table 215.	PKA integer arithmetic functions list . . . . .	858
Table 216.	PKA prime field (Fp) elliptic curve functions list . . . . .	859
Table 217.	Montgomery parameter computation . . . . .	865
Table 218.	Modular addition . . . . .	866
Table 219.	Modular subtraction . . . . .	866
Table 220.	Montgomery multiplication . . . . .	867
Table 221.	Modular exponentiation (normal mode) . . . . .	868
Table 222.	Modular exponentiation (fast mode) . . . . .	868
Table 223.	Modular exponentiation (protected mode) . . . . .	869
Table 224.	Modular inversion . . . . .	869
Table 225.	Modular reduction . . . . .	870
Table 226.	Arithmetic addition . . . . .	870
Table 227.	Arithmetic subtraction . . . . .	870
Table 228.	Arithmetic multiplication . . . . .	871
Table 229.	Arithmetic comparison . . . . .	871
Table 230.	CRT exponentiation . . . . .	872
Table 231.	Point on elliptic curve Fp check . . . . .	873
Table 232.	ECC Fp scalar multiplication. . . . .	873
Table 233.	ECDSA sign - Inputs. . . . .	875
Table 234.	ECDSA sign - Outputs . . . . .	875
Table 235.	Extended ECDSA sign - Extra outputs . . . . .	876
Table 236.	ECDSA verification - Inputs . . . . .	876
Table 237.	ECDSA verification - Outputs . . . . .	877
Table 238.	ECC complete addition . . . . .	877
Table 239.	ECC double base ladder. . . . .	878
Table 240.	ECC projective to affine . . . . .	879
Table 241.	Family of supported curves for ECC operations . . . . .	880
Table 242.	Modular exponentiation . . . . .	881
Table 243.	ECC scalar multiplication . . . . .	881
Table 244.	ECDSA signature average computation time . . . . .	882
Table 245.	ECDSA verification average computation times . . . . .	882
Table 246.	ECC double base ladder average computation times . . . . .	882
Table 247.	ECC projective to affine average computation times . . . . .	882
Table 248.	ECC complete addition average computation times . . . . .	882
Table 249.	Point on elliptic curve Fp check average computation times . . . . .	882
Table 250.	Montgomery parameters average computation times. . . . .	883
Table 251.	PKA interrupt requests . . . . .	883
Table 252.	PKA register map and reset values . . . . .	888
Table 253.	TIM input/output pins . . . . .	892
Table 254.	TIM internal input/output signals. . . . .	892

Table 255.	Interconnect to the tim_ti1 input multiplexer . . . . .	894
Table 256.	Interconnect to the tim_ti2 input multiplexer . . . . .	894
Table 257.	Interconnect to the tim_ti3 input multiplexer . . . . .	894
Table 258.	Interconnect to the tim_ti4 input multiplexer . . . . .	894
Table 259.	Internal trigger connection . . . . .	894
Table 260.	Interconnect to the tim_etr input multiplexer . . . . .	895
Table 261.	Timer break interconnect . . . . .	895
Table 262.	Timer break2 interconnect . . . . .	896
Table 263.	System break interconnect . . . . .	896
Table 264.	Interconnect to the ocref_clr input multiplexer . . . . .	896
Table 265.	CCR and ARR register change dithering pattern . . . . .	929
Table 266.	CCR register change dithering pattern in center-aligned PWM mode . . . . .	930
Table 267.	Behavior of timer outputs versus tim_brk/tim_brk2 inputs . . . . .	942
Table 268.	Break protection disarming conditions . . . . .	944
Table 269.	Counting direction versus encoder signals (CC1P = CC2P = 0) . . . . .	953
Table 270.	Counting direction versus encoder signals and polarity settings . . . . .	957
Table 271.	DMA request . . . . .	978
Table 272.	Effect of low-power modes on TIM1 . . . . .	979
Table 273.	Interrupt requests . . . . .	979
Table 274.	Output control bits for complementary tim_ocx and tim_ocxn channels with break feature . . . . .	1006
Table 275.	TIM1 register map and reset values . . . . .	1029
Table 276.	General purpose timers . . . . .	1033
Table 277.	TIM input/output pins . . . . .	1035
Table 278.	TIM internal input/output signals . . . . .	1035
Table 279.	Interconnect to the tim_ti1 input multiplexer . . . . .	1036
Table 280.	Interconnect to the tim_ti2 input multiplexer . . . . .	1036
Table 281.	Interconnect to the tim_ti3 input multiplexer . . . . .	1036
Table 282.	Interconnect to the tim_ti4 input multiplexer . . . . .	1037
Table 283.	TIMx internal trigger connection . . . . .	1037
Table 284.	Interconnect to the tim_etr input multiplexer . . . . .	1037
Table 285.	Interconnect to the tim_ocref_clr input multiplexer . . . . .	1038
Table 286.	CCR and ARR register change dithering pattern . . . . .	1068
Table 287.	CCR register change dithering pattern in center-aligned PWM mode . . . . .	1069
Table 288.	Counting direction versus encoder signals(CC1P = CC2P = 0) . . . . .	1078
Table 289.	Counting direction versus encoder signals and polarity settings . . . . .	1083
Table 290.	DMA request . . . . .	1107
Table 291.	Effect of low-power modes on TIM2/TIM3 . . . . .	1107
Table 292.	Interrupt requests . . . . .	1108
Table 293.	Output control bit for standard tim_ocx channels . . . . .	1129
Table 294.	TIM2/TIM3 register map and reset values . . . . .	1145
Table 295.	TIM input/output pins . . . . .	1149
Table 296.	TIM internal input/output signals . . . . .	1150
Table 297.	Interconnect to the tim_ti1 input multiplexer . . . . .	1151
Table 298.	Timer break interconnect . . . . .	1151
Table 299.	System break interconnect . . . . .	1151
Table 300.	Interconnect to the ocref_clr input multiplexer . . . . .	1152
Table 301.	CCR and ARR register change dithering pattern . . . . .	1170
Table 302.	Break protection disarming conditions . . . . .	1178
Table 303.	DMA request . . . . .	1185
Table 304.	Effect of low-power modes on TIM16/TIM17 . . . . .	1185
Table 305.	Interrupt requests . . . . .	1186

Table 306.	Output control bits for complementary tim_oc1 and tim_oc1n channels with break feature (TIM16/TIM17) . . . . .	1197
Table 307.	TIM16/TIM17 register map and reset values . . . . .	1211
Table 308.	LPTIM features . . . . .	1214
Table 309.	LPTIM1/2 input/output pins . . . . .	1215
Table 310.	LPTIM1/2 internal signals . . . . .	1216
Table 311.	LPTIM1/2 external trigger connections . . . . .	1217
Table 312.	LPTIM1/2 input 1 connections . . . . .	1217
Table 313.	LPTIM1/2 input 2 connections . . . . .	1217
Table 314.	LPTIM1/2 input capture 1 connections . . . . .	1217
Table 315.	LPTIM1/2 input capture 2 connections . . . . .	1218
Table 316.	Prescaler division ratios . . . . .	1219
Table 317.	Encoder counting scenarios . . . . .	1226
Table 318.	Input capture Glitch filter latency (in counter step unit). . . . .	1230
Table 319.	Effect of low-power modes on the LPTIM . . . . .	1235
Table 320.	Interrupt events . . . . .	1236
Table 321.	LPTIM register map and reset values . . . . .	1257
Table 322.	IWDG features . . . . .	1260
Table 323.	IWDG delays versus actions . . . . .	1261
Table 324.	IWDG internal input/output signals . . . . .	1262
Table 325.	Effect of low power modes on IWDG . . . . .	1267
Table 326.	IWDG interrupt request . . . . .	1269
Table 327.	IWDG register map and reset values . . . . .	1275
Table 328.	WWDG features . . . . .	1276
Table 329.	WWDG internal input/output signals . . . . .	1277
Table 330.	WWDG interrupt requests . . . . .	1280
Table 331.	WWDG register map and reset values . . . . .	1282
Table 332.	RTC input/output pins . . . . .	1285
Table 333.	RTC internal input/output signals . . . . .	1285
Table 334.	RTC interconnection . . . . .	1286
Table 335.	RTC pin PC13 configuration . . . . .	1286
Table 336.	RTC_OUT mapping . . . . .	1288
Table 337.	Effect of low-power modes on RTC . . . . .	1303
Table 338.	RTC pins functionality over modes . . . . .	1304
Table 339.	Nonsecure interrupt requests . . . . .	1304
Table 340.	Secure interrupt requests . . . . .	1305
Table 341.	RTC register map and reset values . . . . .	1335
Table 342.	TAMP input/output pins . . . . .	1339
Table 343.	TAMP internal input/output signals . . . . .	1339
Table 344.	TAMP interconnection . . . . .	1340
Table 345.	Device resource x tamper protection . . . . .	1346
Table 346.	Active tamper output change period . . . . .	1349
Table 347.	Minimum ATPER value . . . . .	1350
Table 348.	Active tamper filtered pulse duration . . . . .	1351
Table 349.	Effect of low-power modes on TAMP . . . . .	1352
Table 350.	TAMP pins functionality over modes (STM32WBA52xx only) . . . . .	1353
Table 351.	TAMP pins functionality over modes (STM32WBA54/55xx only) . . . . .	1353
Table 352.	Interrupt requests . . . . .	1353
Table 353.	TAMP register map and reset values . . . . .	1381
Table 354.	I2C implementation . . . . .	1384
Table 355.	I2C input/output pins . . . . .	1385
Table 356.	I2C internal input/output signals . . . . .	1386

Table 357.	I2C1 interconnection . . . . .	1386
Table 358.	I2C3 interconnection . . . . .	1386
Table 359.	Comparison of analog and digital filters . . . . .	1389
Table 360.	I ²C-bus and SMBus specification data setup and hold times . . . . .	1391
Table 361.	I2C configuration . . . . .	1395
Table 362.	I ²C-bus and SMBus specification clock timings . . . . .	1406
Table 363.	Timing settings for f _I2CCLKof 8 MHz . . . . .	1416
Table 364.	Timing settings for f _I2CCLKof 16 MHz . . . . .	1416
Table 365.	SMBus timeout specifications . . . . .	1418
Table 366.	SMBus with PEC configuration . . . . .	1420
Table 367.	TIMEOUTA[11:0] for maximum t _TTIMEOUT of 25 ms . . . . .	1421
Table 368.	TIMEOUTB[11:0] for maximum t _LOW:SEXTand t _LOW:MEXTof 8 ms . . . . .	1421
Table 369.	TIMEOUTA[11:0] for maximum t _DLEof 50 µs . . . . .	1421
Table 370.	Effect of low-power modes to I2C . . . . .	1431
Table 371.	I2C interrupt requests . . . . .	1432
Table 372.	I2C register map and reset values . . . . .	1449
Table 373.	Instance implementation . . . . .	1452
Table 374.	USART/LPUART features . . . . .	1452
Table 375.	USART/UART input/output pins . . . . .	1455
Table 376.	USART internal input/output signals . . . . .	1456
Table 377.	USART interconnection (USART1/2) . . . . .	1456
Table 378.	Noise detection from sampled data . . . . .	1468
Table 379.	Tolerance of the USART receiver when BRR [3:0] = 0000 . . . . .	1472
Table 380.	Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . .	1472
Table 381.	USART frame formats . . . . .	1477
Table 382.	Effect of low-power modes on the USART . . . . .	1498
Table 383.	USART interrupt requests . . . . .	1499
Table 384.	USART register map and reset values . . . . .	1538
Table 385.	Instance implementation . . . . .	1541
Table 386.	USART/LPUART features . . . . .	1541
Table 387.	LPUART input/output pins . . . . .	1543
Table 388.	LPUART internal input/output signals . . . . .	1543
Table 389.	LPUART interconnections (LPUART1) . . . . .	1544
Table 390.	Error calculation for programmed baud rates at lpuart_ker_ck_pres= 32.768 kHz . . . . .	1555
Table 391.	Tolerance of the LPUART receiver . . . . .	1556
Table 393.	Effect of low-power modes on the LPUART . . . . .	1567
Table 394.	LPUART interrupt requests . . . . .	1568
Table 395.	LPUART register map and reset values . . . . .	1593
Table 396.	SPI features . . . . .	1597
Table 397.	SPI input/output pins . . . . .	1599
Table 398.	SPI internal input/output signals . . . . .	1600
Table 399.	SPI interconnection (SPI1) . . . . .	1600
Table 400.	SPI interconnection (SPI3) . . . . .	1601
Table 401.	Effect of low-power modes on the SPI . . . . .	1629
Table 402.	SPI wake-up and interrupt requests . . . . .	1630
Table 403.	SPI register map and reset values . . . . .	1647
Table 404.	SAI features . . . . .	1649
Table 405.	SAI internal input/output signals . . . . .	1651
Table 406.	SAI input/output pins . . . . .	1651
Table 407.	MCLK_x activation conditions . . . . .	1658
Table 408.	Clock generator programming examples . . . . .	1661
Table 409.	SAI_A configuration for TDM mode . . . . .	1668

Table 410.	TDM frame configuration examples . . . . .	1670
Table 411.	SOPD pattern . . . . .	1673
Table 412.	Parity bit calculation . . . . .	1673
Table 413.	Audio sampling frequency versus symbol rates . . . . .	1674
Table 414.	SAI interrupt sources . . . . .	1683
Table 415.	SAI register map and reset values . . . . .	1711
Table 416.	JTAG/Serial-wire debug port pins . . . . .	1714
Table 417.	Single-wire trace port pins . . . . .	1714
Table 418.	Debug features control . . . . .	1716
Table 419.	JTAG-DP data registers . . . . .	1719
Table 420.	Packet request . . . . .	1721
Table 421.	ACK response . . . . .	1721
Table 422.	Data transfer . . . . .	1721
Table 423.	DP register map and reset values . . . . .	1728
Table 424.	AP register map and reset values . . . . .	1735
Table 425.	System debug ROM table . . . . .	1736
Table 426.	AP register map and reset values . . . . .	1742
Table 427.	MCU ROM table . . . . .	1743
Table 428.	Processor ROM table . . . . .	1744
Table 429.	ROM table register map and reset values . . . . .	1751
Table 430.	DWT register map and reset values . . . . .	1767
Table 431.	ITM register map and reset values . . . . .	1779
Table 432.	BPU register map and reset values . . . . .	1788
Table 433.	TPIU register map and reset values . . . . .	1800
Table 434.	CTI inputs . . . . .	1802
Table 435.	CTI outputs . . . . .	1802
Table 436.	CTI register map and reset values . . . . .	1814
Table 437.	Low power debug overview . . . . .	1817
Table 438.	Low-power mode status flags . . . . .	1818
Table 439.	Peripheral clock freeze control bits . . . . .	1818
Table 440.	Access to peripheral clock freeze control . . . . .	1819
Table 441.	DBGMCU register map and reset values . . . . .	1831
Table 442.	DESIG register map and reset values . . . . .	1839
Table 443.	Document revision history . . . . .	1842

List of figures

Figure 1.	System architecture . . . . .	73
Figure 2.	Memory map . . . . .	80
Figure 3.	Secure/nonsecure partitioning using TrustZone technology . . . . .	89
Figure 4.	Sharing memory map between CPU in secure and nonsecure state . . . . .	90
Figure 5.	Secure world transition and memory partitioning . . . . .	91
Figure 6.	Global TrustZone framework and TrustZone awareness . . . . .	92
Figure 7.	Flash memory TrustZone protections . . . . .	95
Figure 8.	Flash memory secure HDP area . . . . .	102
Figure 9.	Key management principle . . . . .	111
Figure 10.	Device life-cycle security . . . . .	114
Figure 11.	RDP level transition scheme . . . . .	116
Figure 12.	Collaborative development principle . . . . .	119
Figure 13.	GTZC in Armv8-M subsystem block diagram . . . . .	126
Figure 14.	GTZC block diagram . . . . .	128
Figure 15.	MPCBB block diagram . . . . .	129
Figure 16.	RDP level transition scheme when TrustZone is disabled (TZEN = 0) . . . . .	205
Figure 17.	RDP level transition scheme when TrustZone is enabled (TZEN = 1) . . . . .	206
Figure 18.	ICACHE block diagram . . . . .	243
Figure 19.	ICACHE TAG and data memories functional view . . . . .	245
Figure 20.	ICACHE remapping address mechanism . . . . .	248
Figure 21.	Radio system block diagram . . . . .	259
Figure 22.	Transmit path and output power control . . . . .	260
Figure 23.	Bluetooth ^®LE AoA/AoD antennas control . . . . .	261
Figure 24.	PTACONV block diagram . . . . .	264
Figure 25.	4-wire PTA grant protocol . . . . .	265
Figure 26.	4-wire PTA deny protocol . . . . .	266
Figure 27.	3-wire time-multiplexed PTA_STATUS . . . . .	267
Figure 28.	Power supply overview . . . . .	276
Figure 29.	Application power supply schemes . . . . .	278
Figure 30.	Brownout reset waveform . . . . .	283
Figure 31.	PVD thresholds . . . . .	284
Figure 32.	Operating modes . . . . .	287
Figure 33.	Simplified diagram of the reset circuit . . . . .	332
Figure 34.	Clock tree . . . . .	335
Figure 35.	HSE 32 clock sources . . . . .	337
Figure 36.	LSE 32 clock sources . . . . .	341
Figure 37.	Radio control . . . . .	348
Figure 38.	Audio synchronization counter block diagram . . . . .	352
Figure 39.	Audio synchronization timing example . . . . .	352
Figure 40.	HSEM block diagram . . . . .	436
Figure 41.	Procedure state diagram . . . . .	437
Figure 42.	Interrupt state diagram . . . . .	440
Figure 43.	Structure of 3 V- or 5 V-tolerant GPIO (TT or FT) . . . . .	458
Figure 44.	Input floating / pull-up / pull-down configurations . . . . .	463
Figure 45.	Output configuration . . . . .	464
Figure 46.	Alternate function configuration . . . . .	464
Figure 47.	High-impedance analog configuration . . . . .	465
Figure 48.	I/O compensation cell block diagram . . . . .	503

Figure 49.	GPDMA block diagram . . . . .	533
Figure 50.	GPDMA channel direct programming without linked-list (GPDMA_CxLLLR = 0) . . . . .	534
Figure 51.	GPDMA channel suspend and resume sequence . . . . .	535
Figure 52.	GPDMA channel abort and restart sequence . . . . .	536
Figure 53.	Static linked-list data structure (all Uxx = 1) of a linear addressing channel x . . . . .	537
Figure 54.	GPDMA dynamic linked-list data structure of a linear addressing channel x . . . . .	538
Figure 55.	GPDMA channel execution and linked-list programming in run-to-completion mode (GPDMA_CxCR.LSM = 0) . . . . .	540
Figure 56.	Inserting a LLIn with an auxiliary GPDMA channel y . . . . .	542
Figure 57.	GPDMA channel execution and linked-list programming in link step mode (GPDMA_CxCR.LSM = 1) . . . . .	544
Figure 58.	Building LLIn+1: GPDMA dynamic linked-lists in link step mode . . . . .	545
Figure 59.	Replace with a new LLIn' in register file in link step mode . . . . .	546
Figure 60.	Replace with a new LLIn' and LLIn+1' in memory in link step mode (option 1) . . . . .	547
Figure 61.	Replace with a new LLIn' and LLIn+1' in memory in link step mode (option 2) . . . . .	548
Figure 62.	GPDMA channel execution and linked-list programming . . . . .	550
Figure 63.	GPDMA arbitration policy . . . . .	558
Figure 64.	Trigger hit, memorization, and overrun waveform . . . . .	561
Figure 65.	GPDMA circular buffer programming: update of the memory start address with a linear addressing channel . . . . .	562
Figure 66.	Shared GPDMA channel with circular buffering: update of the memory start address with a linear addressing channel . . . . .	563
Figure 67.	EXTI block diagram . . . . .	596
Figure 68.	Configurable event trigger logic CPU wake-up . . . . .	598
Figure 69.	EXTI mux GPIO selection . . . . .	599
Figure 70.	CRC calculation unit block diagram . . . . .	618
Figure 71.	ADC block diagram . . . . .	627
Figure 72.	ADC calibration . . . . .	630
Figure 73.	Calibration factor forcing . . . . .	631
Figure 74.	Enabling/disabling the ADC . . . . .	632
Figure 75.	ADC clock scheme . . . . .	633
Figure 76.	ADC4 connectivity . . . . .	634
Figure 77.	Analog-to-digital conversion time . . . . .	639
Figure 78.	ADC conversion timings . . . . .	639
Figure 79.	Stopping an ongoing conversion . . . . .	640
Figure 80.	Single conversions of a sequence, software trigger . . . . .	643
Figure 81.	Continuous conversion of a sequence, software trigger . . . . .	644
Figure 82.	Single conversions of a sequence, hardware trigger . . . . .	644
Figure 83.	Continuous conversions of a sequence, hardware trigger . . . . .	645
Figure 84.	Data alignment and resolution (oversampling disabled: OVSE = 0) . . . . .	646
Figure 85.	Example of overrun (OVR) . . . . .	647
Figure 86.	Wait conversion mode (continuous mode, software trigger) . . . . .	649
Figure 87.	Auto-off mode state diagram . . . . .	651
Figure 88.	ADC behavior with WAIT = 0 and AUTOFF = 1 . . . . .	651
Figure 89.	ADC behavior with WAIT = 1 and AUTOFF = 1 . . . . .	652
Figure 90.	Autonomous mode state diagram . . . . .	653
Figure 91.	Analog watchdog guarded area . . . . .	654
Figure 92.	ADC_AWDx_OUT signal generation . . . . .	655
Figure 93.	ADC_AWDx_OUT signal generation (AWDx flag not cleared by software) . . . . .	656
Figure 94.	ADC_AWDx_OUT signal generation (on a single channel) . . . . .	656

Figure 95.	Analog watchdog threshold update . . . . .	657
Figure 96.	20-bit to 16-bit result truncation . . . . .	657
Figure 97.	Numerical example with 5-bits shift and rounding . . . . .	658
Figure 98.	Triggered oversampling mode (TOVS bit = 1) . . . . .	660
Figure 99.	Temperature sensor and VREFINT channel block diagram . . . . .	661
Figure 100.	Comparator block diagrams . . . . .	688
Figure 101.	Window mode . . . . .	691
Figure 102.	Comparator hysteresis . . . . .	691
Figure 103.	Comparator output blanking . . . . .	692
Figure 104.	Scaler . . . . .	693
Figure 105.	TSC block diagram . . . . .	699
Figure 106.	Surface charge transfer analog I/O group structure . . . . .	700
Figure 107.	Sampling capacitor voltage variation . . . . .	701
Figure 108.	Charge transfer acquisition sequence . . . . .	702
Figure 109.	Spread spectrum variation principle . . . . .	703
Figure 110.	RNG block diagram . . . . .	717
Figure 111.	NIST SP800-90B entropy source model . . . . .	718
Figure 112.	RNG initialization overview . . . . .	721
Figure 113.	AES block diagram . . . . .	735
Figure 114.	Encryption/ decryption typical usage . . . . .	736
Figure 115.	Typical operation with authentication . . . . .	739
Figure 116.	Example of suspend mode management . . . . .	740
Figure 117.	ECB encryption . . . . .	741
Figure 118.	ECB decryption . . . . .	741
Figure 119.	CBC encryption . . . . .	741
Figure 120.	CBC decryption . . . . .	742
Figure 121.	Message construction in CTR mode . . . . .	744
Figure 122.	CTR encryption . . . . .	745
Figure 123.	Message construction in GCM . . . . .	746
Figure 124.	GCM authenticated encryption . . . . .	748
Figure 125.	Message construction in GMAC mode . . . . .	751
Figure 126.	GMAC authentication mode . . . . .	752
Figure 127.	Message construction in CCM mode . . . . .	753
Figure 128.	CCM mode authenticated encryption . . . . .	754
Figure 129.	128-bit block construction according to the data type . . . . .	759
Figure 130.	SAES block diagram . . . . .	781
Figure 131.	Encryption/ decryption typical usage . . . . .	783
Figure 132.	Typical operation with authentication . . . . .	785
Figure 133.	Example of suspend mode management . . . . .	786
Figure 134.	ECB encryption . . . . .	787
Figure 135.	ECB decryption . . . . .	787
Figure 136.	CBC encryption . . . . .	788
Figure 137.	CBC decryption . . . . .	788
Figure 138.	Message construction in CTR mode . . . . .	791
Figure 139.	CTR encryption . . . . .	792
Figure 140.	Message construction in GCM . . . . .	793
Figure 141.	GCM authenticated encryption . . . . .	795
Figure 142.	Message construction in GMAC mode . . . . .	798
Figure 143.	GMAC authentication mode . . . . .	798
Figure 144.	Message construction in CCM mode . . . . .	799
Figure 145.	CCM mode authenticated encryption . . . . .	801
Figure 146.	Operation with wrapped keys for SAES in ECB and CBC modes . . . . .	804

Figure 147. Operation with wrapped keys for SAES in CTR mode . . . . .	807
Figure 148. Usage of Shared-key mode . . . . .	808
Figure 149. 128-bit block construction according to the data type. . . . .	811
Figure 150. Key protection mechanisms . . . . .	813
Figure 151. HASH block diagram . . . . .	835
Figure 152. Message data swapping feature. . . . .	837
Figure 153. HASH suspend/resume mechanism. . . . .	843
Figure 154. PKA block diagram . . . . .	857
Figure 155. Advanced-control timer block diagram . . . . .	891
Figure 156. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	897
Figure 157. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	898
Figure 158. Counter timing diagram, internal clock divided by 1 . . . . .	899
Figure 159. Counter timing diagram, internal clock divided by 2 . . . . .	900
Figure 160. Counter timing diagram, internal clock divided by 4 . . . . .	900
Figure 161. Counter timing diagram, internal clock divided by N. . . . .	901
Figure 162. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .	901
Figure 163. Counter timing diagram, update event when ARPE = 1 (TIMx_ARR preloaded). . . . .	902
Figure 164. Counter timing diagram, internal clock divided by 1 . . . . .	903
Figure 165. Counter timing diagram, internal clock divided by 2 . . . . .	904
Figure 166. Counter timing diagram, internal clock divided by 4 . . . . .	904
Figure 167. Counter timing diagram, internal clock divided by N. . . . .	905
Figure 168. Counter timing diagram, update event when repetition counter is not used. . . . .	905
Figure 169. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .	907
Figure 170. Counter timing diagram, internal clock divided by 2 . . . . .	907
Figure 171. Counter timing diagram, internal clock divided by 4, TIMx_ARR = 0x36 . . . . .	908
Figure 172. Counter timing diagram, internal clock divided by N. . . . .	908
Figure 173. Counter timing diagram, update event with ARPE = 1 (counter underflow) . . . . .	909
Figure 174. Counter timing diagram, Update event with ARPE = 1 (counter overflow). . . . .	910
Figure 175. Update rate examples depending on mode and TIMx_RCR register settings . . . . .	911
Figure 177. Control circuit in normal mode, internal clock divided by 1 . . . . .	913
Figure 178. tim_ti2 external clock connection example . . . . .	913
Figure 179. Control circuit in external clock mode 1 . . . . .	914
Figure 180. External trigger input block . . . . .	915
Figure 181. Control circuit in external clock mode 2 . . . . .	916
Figure 182. Capture/compare channel (example: channel 1 input stage). . . . .	916
Figure 183. Capture/compare channel 1 main circuit . . . . .	917
Figure 184. Output stage of capture/compare channel (channel 1, idem ch. 2, 3 and 4) . . . . .	918
Figure 185. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .	918
Figure 186. PWM input mode timing . . . . .	921
Figure 187. Output compare mode, toggle on tim_oc1 . . . . .	923
Figure 188. Edge-aligned PWM waveforms (ARR = 8) . . . . .	924
Figure 189. Center-aligned PWM waveforms (ARR = 8). . . . .	925
Figure 190. Dithering principle . . . . .	926
Figure 191. Data format and register coding in dithering mode. . . . .	927
Figure 192. PWM resolution vs frequency . . . . .	928
Figure 193. PWM dithering pattern . . . . .	929
Figure 194. Dithering effect on duty cycle in center-aligned PWM mode . . . . .	930
Figure 195. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .	932
Figure 196. Combined PWM mode on channel 1 and 3 . . . . .	933
Figure 197. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .	934

Figure 198. Complementary output with symmetrical dead-time insertion . . . . .	935
Figure 199. Asymmetrical deadtime . . . . .	936
Figure 200. Dead-time waveforms with delay greater than the negative pulse . . . . .	936
Figure 201. Dead-time waveforms with delay greater than the positive pulse. . . . .	936
Figure 202. Break and Break2 circuitry overview . . . . .	939
Figure 203. Various output behavior in response to a break event on tim_brk (OSSI = 1) . . . . .	941
Figure 204. PWM output state following tim_brk and tim_brk2 assertion (OSSI = 1) . . . . .	942
Figure 205. PWM output state following tim_brk assertion (OSSI = 0) . . . . .	943
Figure 206. Output redirection (tim_brk2 request not represented). . . . .	944
Figure 207. tim_ocref_clr input selection multiplexer. . . . .	945
Figure 208. Clearing TIMx tim_ocxref . . . . .	946
Figure 209. 6-step generation, COM example (OSSR = 1) . . . . .	947
Figure 210. Example of one pulse mode. . . . .	948
Figure 211. Retriggerable one-pulse mode . . . . .	949
Figure 212. Pulse generator circuitry. . . . .	950
Figure 213. Pulse generation on compare event, for edge-aligned and encoder modes . . . . .	951
Figure 214. Extended pulsewidth in case of concurrent triggers . . . . .	952
Figure 215. Example of counter operation in encoder interface mode. . . . .	954
Figure 216. Example of encoder interface mode with tim_ti1fp1 polarity inverted. . . . .	954
Figure 217. Quadrature encoder counting modes . . . . .	955
Figure 218. Direction plus clock encoder mode. . . . .	956
Figure 219. Directional clock encoder mode (CC1P = CC2P = 0). . . . .	956
Figure 220. Directional clock encoder mode (CC1P = CC2P = 1). . . . .	957
Figure 221. Index gating options . . . . .	958
Figure 222. Jittered Index signals . . . . .	958
Figure 223. Index generation for IPOS[1:0] = 11 . . . . .	959
Figure 224. Counter reading with index gated on channel A (IPOS[1:0] = 11) . . . . .	959
Figure 225. Counter reading with index ungated (IPOS[1:0] = 00) . . . . .	960
Figure 226. Counter reading with index gated on channel A and B. . . . .	960
Figure 227. Encoder mode behavior in case of narrow index pulse (IPOS[1:0] = 11). . . . .	961
Figure 228. Counter reset Narrow index pulse (closer view, ARR = 0x07) . . . . .	962
Figure 229. Index behavior in x1 and x2 mode (IPOS[1:0] = 01). . . . .	963
Figure 230. Directional index sensitivity. . . . .	963
Figure 231. Counter reset as function of FIDX bit setting . . . . .	964
Figure 232. Index blanking. . . . .	964
Figure 233. Index behavior in clock + direction mode, IPOS[0] = 1. . . . .	965
Figure 234. Index behavior in directional clock mode, IPOS[0] = 1 . . . . .	965
Figure 235. State diagram for quadrature encoded signals. . . . .	966
Figure 236. Up-counting encoder error detection . . . . .	967
Figure 237. Down-counting encode error detection. . . . .	968
Figure 238. Encoder mode change with preload transferred on update (SMSPS = 0) . . . . .	969
Figure 239. Measuring time interval between edges on three signals. . . . .	970
Figure 240. Example of Hall sensor interface . . . . .	972
Figure 241. Control circuit in reset mode . . . . .	973
Figure 242. Control circuit in Gated mode . . . . .	974
Figure 243. Control circuit in trigger mode. . . . .	975
Figure 244. Control circuit in external clock mode 2 + trigger mode . . . . .	976
Figure 245. General-purpose timer block diagram . . . . .	1034
Figure 246. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	1039
Figure 247. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	1039
Figure 248. Counter timing diagram, internal clock divided by 1 . . . . .	1040
Figure 249. Counter timing diagram, internal clock divided by 2 . . . . .	1041

Figure 250. Counter timing diagram, internal clock divided by 4 . . . . .	1041
Figure 251. Counter timing diagram, internal clock divided by N . . . . .	1042
Figure 252. Counter timing diagram, Update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .	1042
Figure 253. Counter timing diagram, Update event when ARPE = 1 (TIMx_ARR preloaded). . . . .	1043
Figure 254. Counter timing diagram, internal clock divided by 1 . . . . .	1044
Figure 255. Counter timing diagram, internal clock divided by 2 . . . . .	1045
Figure 256. Counter timing diagram, internal clock divided by 4 . . . . .	1045
Figure 257. Counter timing diagram, internal clock divided by N . . . . .	1046
Figure 258. Counter timing diagram, Update event . . . . .	1046
Figure 259. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .	1048
Figure 260. Counter timing diagram, internal clock divided by 2 . . . . .	1048
Figure 261. Counter timing diagram, internal clock divided by 4, TIMx_ARR = 0x36 . . . . .	1049
Figure 262. Counter timing diagram, internal clock divided by N . . . . .	1049
Figure 263. Counter timing diagram, Update event with ARPE = 1 (counter underflow). . . . .	1050
Figure 264. Counter timing diagram, Update event with ARPE = 1 (counter overflow). . . . .	1051
Figure 265. Control circuit in normal mode, internal clock divided by 1 . . . . .	1052
Figure 266. tim_ti2 external clock connection example . . . . .	1052
Figure 267. Control circuit in external clock mode 1 . . . . .	1053
Figure 268. External trigger input block . . . . .	1054
Figure 269. Control circuit in external clock mode 2 . . . . .	1055
Figure 270. Capture/compare channel (example: channel 1 input stage). . . . .	1055
Figure 271. Capture/compare channel 1 main circuit . . . . .	1056
Figure 272. Output stage of capture/compare channel (channel 1, idem ch.2, 3 and 4). . . . .	1056
Figure 273. PWM input mode timing . . . . .	1059
Figure 274. Output compare mode, toggle on tim_oc1 . . . . .	1061
Figure 275. Edge-aligned PWM waveforms (ARR = 8). . . . .	1062
Figure 276. Center-aligned PWM waveforms (ARR = 8). . . . .	1063
Figure 277. Dithering principle . . . . .	1064
Figure 278. Data format and register coding in dithering mode . . . . .	1065
Figure 279. PWM resolution vs frequency (16-bit mode). . . . .	1066
Figure 280. PWM resolution vs frequency (32-bit mode). . . . .	1066
Figure 281. PWM dithering pattern . . . . .	1067
Figure 282. Dithering effect on duty cycle in center-aligned PWM mode . . . . .	1068
Figure 283. Generation of two phase-shifted PWM signals with 50% duty cycle . . . . .	1070
Figure 284. Combined PWM mode on channels 1 and 3 . . . . .	1071
Figure 285. OCREF_CLR input selection multiplexer . . . . .	1072
Figure 286. Clearing TIMx tim_ocxref . . . . .	1072
Figure 287. Example of One-pulse mode . . . . .	1073
Figure 288. Retriggerable one-pulse mode . . . . .	1075
Figure 289. Pulse generator circuitry . . . . .	1076
Figure 290. Pulse generation on compare event, for edge-aligned and encoder modes . . . . .	1076
Figure 291. Extended pulse width in case of concurrent triggers . . . . .	1077
Figure 292. Example of counter operation in encoder interface mode . . . . .	1079
Figure 293. Example of encoder interface mode with tim_ti1fp1 polarity inverted . . . . .	1079
Figure 294. Quadrature encoder counting modes . . . . .	1080
Figure 295. Direction plus clock encoder mode . . . . .	1081
Figure 296. Directional clock encoder mode (CC1P = CC2P = 0). . . . .	1082
Figure 297. Directional clock encoder mode (CC1P = CC2P = 1). . . . .	1082
Figure 298. Index gating options . . . . .	1084
Figure 299. Jittered Index signals . . . . .	1084
Figure 300. Index generation for IPOS[1:0] = 11 . . . . .	1085
Figure 301. Counter reading with index gated on channel A (IPOS[1:0] = 11) . . . . .	1085

Figure 302. Counter reading with index ungated (IPOS[1:0] = 00) . . . . .	1086
Figure 303. Counter reading with index gated on channel A and B. . . . .	1086
Figure 304. Encoder mode behavior in case of narrow index pulse (IPOS[1:0] = 11). . . . .	1087
Figure 305. Counter reset Narrow index pulse (closer view, ARR = 0x07) . . . . .	1088
Figure 306. Index behavior in x1 and x2 mode (IPOS[1:0] = 01). . . . .	1089
Figure 307. Directional index sensitivity. . . . .	1089
Figure 308. Counter reset as function of FIDX bit setting . . . . .	1090
Figure 309. Index blanking. . . . .	1090
Figure 310. Index behavior in clock + direction mode, IPOS[0] = 1. . . . .	1091
Figure 311. Index behavior in directional clock mode, IPOS[0] = 1 . . . . .	1091
Figure 312. State diagram for quadrature encoded signals. . . . .	1092
Figure 313. Up-counting encoder error detection . . . . .	1093
Figure 314. Down-counting encode error detection. . . . .	1094
Figure 315. Encoder mode change with preload transferred on update (SMSPS = 0) . . . . .	1095
Figure 316. Control circuit in reset mode . . . . .	1097
Figure 317. Control circuit in gated mode . . . . .	1098
Figure 318. Control circuit in trigger mode. . . . .	1098
Figure 319. Control circuit in external clock mode 2 + trigger mode . . . . .	1100
Figure 320. Master/Slave timer example . . . . .	1100
Figure 321. Master/slave connection example with 1 channel only timers . . . . .	1101
Figure 322. Gating TIM_slv with tim_oc1ref of TIM_mstr . . . . .	1102
Figure 323. Gating TIM_slv with Enable of TIM_mstr . . . . .	1103
Figure 324. Triggering TIM_slv with update of TIM_mstr. . . . .	1104
Figure 325. Triggering TIM_slv with Enable of TIM_mstr . . . . .	1104
Figure 326. Triggering TIM_mstr and TIM_slv with TIM_mstr tim_ti1 input. . . . .	1105
Figure 327. TIM16/TIM17 block diagram . . . . .	1149
Figure 328. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	1153
Figure 329. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	1153
Figure 330. Counter timing diagram, internal clock divided by 1 . . . . .	1155
Figure 331. Counter timing diagram, internal clock divided by 2 . . . . .	1155
Figure 332. Counter timing diagram, internal clock divided by 4 . . . . .	1156
Figure 333. Counter timing diagram, internal clock divided by N. . . . .	1156
Figure 334. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .	1157
Figure 335. Counter timing diagram, update event when ARPE = 1 (TIMx_ARR preloaded). . . . .	1158
Figure 336. Update rate examples depending on mode and TIMx_RCR register settings . . . . .	1159
Figure 337. Control circuit in normal mode, internal clock divided by 1 . . . . .	1160
Figure 338. tim_ti2 external clock connection example . . . . .	1160
Figure 339. Control circuit in external clock mode 1 . . . . .	1161
Figure 340. Capture/compare channel (example: channel 1 input stage). . . . .	1162
Figure 341. Capture/compare channel 1 main circuit . . . . .	1162
Figure 342. Output stage of capture/compare channel (channel 1). . . . .	1163
Figure 343. Output compare mode, toggle on tim_oc1 . . . . .	1166
Figure 344. Edge-aligned PWM waveforms (ARR = 8) . . . . .	1167
Figure 345. Dithering principle . . . . .	1168
Figure 346. Data format and register coding in dithering mode. . . . .	1168
Figure 347. PWM resolution vs frequency . . . . .	1169
Figure 348. PWM dithering pattern . . . . .	1170
Figure 349. Complementary output with symmetrical dead-time insertion. . . . .	1172
Figure 350. Asymmetrical deadtime . . . . .	1172
Figure 351. Dead-time waveforms with delay greater than the negative pulse. . . . .	1173

Figure 352. Dead-time waveforms with delay greater than the positive pulse. . . . .	1173
Figure 353. Break circuitry overview . . . . .	1175
Figure 354. Output behavior in response to a break event on tim_brk . . . . .	1177
Figure 355. Output redirection . . . . .	1179
Figure 356. tim_ocref_clr input selection multiplexer. . . . .	1180
Figure 357. 6-step generation, COM example (OSSR = 1) . . . . .	1181
Figure 358. Example of one pulse mode. . . . .	1182
Figure 359. LPTIM block diagram ⁽¹⁾. . . . .	1215
Figure 360. Glitch filter timing diagram . . . . .	1219
Figure 361. LPTIM output waveform, single-counting mode configuration when repetition register content is different than zero (with PRELOAD = 1) . . . . .	1221
Figure 362. LPTIM output waveform, single-counting mode configuration and Set-once mode activated (WAVE bit is set). . . . .	1221
Figure 363. LPTIM output waveform, Continuous counting mode configuration . . . . .	1222
Figure 364. Waveform generation . . . . .	1223
Figure 365. Encoder mode counting sequence . . . . .	1227
Figure 366. Continuous counting mode when repetition register LPTIM_RCR different from zero (with PRELOAD = 1). . . . .	1228
Figure 367. Capture/compare input stage (channel 1) . . . . .	1229
Figure 368. Capture/compare output stage (channel 1) . . . . .	1229
Figure 369. Edge-aligned PWM mode (PRELOAD = 1) . . . . .	1231
Figure 370. Edge-aligned PWM waveforms (ARR=8 and CCxP = 0) . . . . .	1232
Figure 371. PWM mode with immediate update versus preloaded update . . . . .	1233
Figure 372. IRTIM internal hardware connections with TIM16 and TIM17 . . . . .	1259
Figure 373. Independent watchdog block diagram . . . . .	1261
Figure 374. Reset timing due to timeout . . . . .	1263
Figure 375. Reset timing due to refresh in the not allowed area . . . . .	1264
Figure 376. Changing PR, RL, and performing a refresh ⁽¹⁾. . . . .	1265
Figure 377. Window comparator update ⁽¹⁾. . . . .	1266
Figure 378. Independent watchdog interrupt timing diagram. . . . .	1268
Figure 379. Early wake-up comparator update ⁽¹⁾. . . . .	1269
Figure 380. Watchdog block diagram . . . . .	1277
Figure 381. Window watchdog timing diagram . . . . .	1279
Figure 382. RTC block diagram . . . . .	1284
Figure 383. TAMP block diagram . . . . .	1338
Figure 384. Backup registers protection zones . . . . .	1343
Figure 385. Tamper sampling with precharge pulse . . . . .	1348
Figure 386. Low level detection with precharge and filtering . . . . .	1348
Figure 387. Active tamper filtering . . . . .	1350
Figure 388. Block diagram . . . . .	1385
Figure 389. I ²C-bus protocol . . . . .	1388
Figure 390. Setup and hold timings . . . . .	1390
Figure 391. I2C initialization flow . . . . .	1392
Figure 392. Data reception . . . . .	1393
Figure 393. Data transmission . . . . .	1394
Figure 394. Target initialization flow . . . . .	1397
Figure 395. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . .	1399
Figure 396. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . .	1400
Figure 397. Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . .	1401
Figure 398. Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . .	1402
Figure 399. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . .	1403
Figure 400. Transfer bus diagrams for I2C target receiver

(mandatory events only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 447. lpuart_ker_ck clock divider block diagram . . . . .	1554
Figure 448. Mute mode using Idle line detection . . . . .	1558
Figure 449. Mute mode using address mark detection . . . . .	1559
Figure 450. Transmission using DMA . . . . .	1561
Figure 451. Reception using DMA . . . . .	1562
Figure 452. Hardware flow control between two LPUARTs . . . . .	1563
Figure 453. RS232 RTS flow control . . . . .	1563
Figure 454. RS232 CTS flow control . . . . .	1564
Figure 455. SPI block diagram . . . . .	1598
Figure 456. Full-duplex single master/ single slave application . . . . .	1602
Figure 457. Half-duplex single master/ single slave application . . . . .	1602
Figure 458. Simplex single master / single slave application (master in transmit-only / slave in receive-only mode) . . . . .	1604
Figure 459. Master and three independent slaves connected in star topology . . . . .	1605
Figure 460. Master and three slaves connected in circular (daisy chain) topology . . . . .	1607
Figure 461. Multimaster application . . . . .	1608
Figure 462. Scheme of NSS control logic . . . . .	1610
Figure 463. Data flow timing control (SSOE = 1, SSOM = 0, SSM = 0) . . . . .	1610
Figure 464. NSS interleaving pulses between data (SSOE = 1, SSOM = 1, SSM = 0) . . . . .	1611
Figure 465. Data clock timing diagram . . . . .	1613
Figure 466. Data alignment when data size is not equal to 8, 16 or 32 bits . . . . .	1614
Figure 467. TI mode transfer . . . . .	1624
Figure 468. Optional configurations of the slave behavior when an underrun condition is detected . . . . .	1626
Figure 469. SAI functional block diagram . . . . .	1650
Figure 470. Audio frame . . . . .	1653
Figure 471. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .	1655
Figure 472. FS role is start of frame (FSDEF = 0) . . . . .	1656
Figure 473. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .	1657
Figure 474. First bit offset . . . . .	1657
Figure 475. Audio block clock generator overview . . . . .	1659
Figure 476. PDM typical connection and timing . . . . .	1663
Figure 477. Detailed PDM interface block diagram . . . . .	1664
Figure 478. Start-up sequence . . . . .	1665
Figure 479. SAI_ADR format in TDM mode, 32-bit slot width . . . . .	1666
Figure 480. SAI_ADR format in TDM mode, 16-bit slot width . . . . .	1667
Figure 481. SAI_ADR format in TDM mode, 8-bit slot width . . . . .	1668
Figure 482. AC'97 audio frame . . . . .	1671
Figure 483. SPDIF format . . . . .	1672
Figure 484. SAI_xDR register ordering . . . . .	1673
Figure 485. Data companding hardware in an audio block in the SAI . . . . .	1676
Figure 486. Tristate strategy on SD output line on an inactive slot . . . . .	1678
Figure 487. Tristate on output data line in a protocol like I2S . . . . .	1679
Figure 488. Overrun detection error . . . . .	1680
Figure 489. FIFO underrun event . . . . .	1680
Figure 490. Block diagram of debug support infrastructure . . . . .	1714
Figure 491. JTAG TAP state machine . . . . .	1718
Figure 492. AP0: CoreSight topology . . . . .	1736
Figure 493. CPU CoreSight topology . . . . .	1745
Figure 494. TPIU architecture . . . . .	1789
Figure 495. Embedded cross trigger . . . . .	1802

RM0493-STM32WBA5

Introduction

Contents

List of tables

List of figures

Chapters