33. Revision history

Section Fast programming - row size corrected.

Table 18: Organization of option bytes now contains links to option registers and the duplicated description is removed.

Format of reset values of option registers updated and/or corrected.

Note in bit 16 of FLASH security register (FLASH_SECR) updated.

Updated Section 17.3.18: Clearing the OCxREF signal on an external event .

OC1M[3:0] bitfield description updated in Section 17.4.8: TIM1 capture/compare mode register 1 [alternate] (TIM1_CCMR1) , Section 18.4.8: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 2 to 3), Section 19.4.6: TIM14 capture/compare mode register 1 [alternate] (TIM14_CCMR1) , and Section 20.6.7: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 16 to 17).

USART2 information in Table 27: Device resources enabled in different operating modes corrected.

Spurious “TIM15” removed from Section 6.2.7: Clock security system (CSS) .

Cross-reference to DBG added in WWDG Section 23.3.5: Debug mode .

Section 24.2: RTC main features corrected (spurious “or by a tamper event” removed).

First public release.

Section 5.3.2: Low-power modes , bulleted point Standby mode.

Section 6.2: Clocks , bulleted point TIMx.

Figure 9: Clock tree .

Section 6.3: Low-power modes , removal of “USART2”.

Section Converting a supply-relative ADC measurement to an absolute voltage value .

Figure 100: Break and Break2 circuitry overview - note under the figure corrected.

Section 17.3.25: Interfacing with Hall sensors - removal of “TIM4”.

Figure 207: Break circuitry overview - note under the figure corrected.

Document device reference from “STM32C0x1” to “STM32C0 series”;

Integration of the information relative to STM32C071xx.

Cover page: added reference to the errata sheets.

Added Section 7: Clock recovery system (CRS) and Section 29: Universal serial bus full-speed host/device interface (USB) .

Memory mapping: Added Table 1: Peripherals or functions versus products .

Updated Figure 2: Memory map , Table 2: STM32C011xx and STM32C031xx boundary addresses , and Table 7: STM32C0 series peripheral register boundary addresses ; added Table 4: STM32C071xx boundary addresses .

Promoted Section 3: Boot modes to the first level and updated. Demoted Section 3.1: Boot configuration as a subsection. Reworked Section 3.1.4: Empty check . In the table of boundary addresses, “Code” replaced with “FLASH” and “FLASH or SRAM”;

Boot modes: updated Section 3.1: Boot configuration ;

FLASH: Section 4.2: FLASH main features , Section 4.3.1: Flash memory organization (added Section Table 12.: Flash memory organization for STM32C071xx ), sections Flash memory page erase , Flash memory bank or mass erase , Standard programming , and Fast programming ; adapted sizes of PCROP1A_STRT, PCROP1A_END, PCROP1B_STRT, PCROP1B_END, WRP1A_STRT, WRP1A_END, WRP1B_STRT, WRP1B_END, SEC_SIZE and PNB bitfields; updated Section 4.5.1: FLASH read protection (RDP) , Section 4.5.6: Forcing boot from main flash memory , and Table 22: PCROP protection , sections Changing the read protection level , Fast programming , and Option byte loading , registers FLASH_ACR, FLASH_SR, FLASH_CR; option bytes FLASH_OPTR factory value, BOR_EN reset value; HSI48 division corrected from four to three; BOOT_LOCK bit note modified; all nBOOTx and nRSTx bits renamed to NBOOTx and NRSTx; Removed section FLASH empty check ;

PWR: updated Section 5.1: Power supplies and voltage references (Figure 5: Power supply overview) , Table 27: Device resources enabled in different operating modes , and registers PWR_CR3, PWR_CR4, PWR_SR1, PWR_SR2, PWR_SCR, PWR_PUCRC, PWR_PDCRC, PWR_PUCRD, PWR_PDCRD, PWR_PUCRF, and PWR_PDCRF; Added register PWR_CR2; corrected PVM_VDDIO2_OUT description;

RCC: Added HSIUSB48 RC oscillator in multiple sections, tables, and figures; updated Figure 9: Clock tree , added Section 6.2.3: HSIUSB48 clock , updated registers RCC_CR, RCC_CFGR, RCC_CIER, RCC_CIFR, RCC_CICR, RCC_APBSTR1, RCC_APBENR1, RCC_APBSMENR1, RCC_APBSMENR2, and RCC_CCIPR1 (to RCC_CCIPR); added registers RCC_CCIPR2 and RCC_CRRCR; Corrected RCC_CFGR bitmap, LSERDYIE bit name, LSIRDYF bit description, HSIDIV[2:0] and HSIKERDIV[2:0] reset values in the register map, and missing bits added; updated Section 6.2.15: Peripheral clock enable registers ; RCC_RC register access specified; HSIUSB48 added to SW[2:0] and SWS[2:0] bitfields; LSIRDYF description corrected; updated section NRST (external reset) ; pin name PF2 or NRST corrected to PF2-NRST; bitfield PINRSTF of RCC_CSR2 register updated; corrected reference in section External crystal/ceramic resonator (HSE crystal) ; updated section External source (HSE bypass) and TIM17 ;

CRS: added Section 7.4.2: CRS internal signals ; updated Table 34: CRS interconnection title;

GPIO: Updated register GPIOx_PUPDR, Section 8.3.14: Low pin count package adjustment , and Section 8.3.15: Reset pin (PF2-NRST) in GPIO mode ; removed section Boot0 pin (PA14) in GPIO mode ;

SYSCFG: Updated registers SYSCFG_CFGR1, SYSCFG_CFGR3, SYSCFG_ITLINE11, added registers SYSCFG_ITLINE9, SYSCFG_ITLINE15, SYSCFG_ITLINE24, and SYSCFG_ITLINE25; added register SYSCFG_ITLINE1; corrected “system reset value” to “reset value” for all registers; updated register SYSCFG_CFGR3 description; updated Table 41: SYSCFG register map and reset values ;

DMAMUX: Updated Table 49: DMAMUX: assignment of multiplexer inputs to resources , Table 50: DMAMUX: assignment of trigger inputs to resources , and Table 51: DMAMUX: assignment of synchronization inputs to resources ;

Interconnect matrix: Updated Table 42: Interconnect matrix and sections Section 10.3.1 and Section 10.3.2 ; Added TIM2;

NVIC: Updated Table 55: Vector table ; added VDDIO2 monitor interrupt;

EXTI: Updated Table 59: EXTI line connections ; added registers EXTI_RTSR2, EXTI_FTSR2, EXTI_SWIER2, EXTI_RPR2, EXTI_FPR2, EXTI_IMR2, and EXTI_EMR2; updated EXTI_EXTICRx register description by replacing the “m” substitution of the repeating part of the formula in all bitfield names and enumerated value descriptions; updated Table 59: EXTI line connections , Section 14.5.14: EXTI CPU wake-up with interrupt mask register 2 (EXTI_IMR2) , Section 14.5.15: EXTI CPU wake-up with event mask register 2 (EXTI_EMR2) , and Section 14.5.16: EXTI register map

TIMERS: updated Table 20.6.20: TIM17 input selection register (TIM17_TISEL) ;

I2C: general update;

DBG: Updated Section 30.5.3: SW-DP state machine (reset, idle states, ID code) (ID code), Table 177: DEV_ID bitfield values and the DBG_APB_FZ1 register; added reset value to the DBG_IDCODE register; REV_ID bitfield definition reported to the errata sheets;

Device electronic signature: Updated Section 31.3: Package data register (PCKR)

IDWG: Corrected descriptions of the IWDG_SR register bitfields WVU and RVU;

USART: Extended note in the description of the PRESCALER[3:0] bitfield of the USART_PRESC register;

USB: updated Table 29.4.2: USB pins and internal signals and Section 29.4.5: Description of USB blocks used in both Device and Host modes ; register description split to USB registers and USB SRAM registers;

Device electronic signature: Corrected all LQPF occurrences to LQFP.

Multiple sections: SPI1/I2S or SPI1 used as instance name of the peripheral corrected to SPI2S1.

Added information specific to STM32C051xx and STM32C09xxx devices;

Document conventions: Added Section 1.3: Register reset value ;

Memory and bus architecture: Added Section 2.4: FDCAN RAM , Table 3 , Table 5 , and Table 6 ; updated Table 7 ,

FLASH: Added Table 11 and Table 13 ; updated Table 21 , Section 4.7.6: FLASH option register (FLASH_OPTR) ; updates for integrating STM32C051xx and STM32C09xxx, and FDCAN;

PWR: Updated Table 27: Device resources enabled in different operating modes , Section : Peripheral clock gating ; updates for integrating STM32C051xx and STM32C09xxx;

RCC: Updates for integrating STM32C051xx and STM32C09xxx, and FDCAN; updated Figure 9: Clock tree , Section 6.2.6: System clock (SYSCLK) selection ;

CRS: Added Table 33: CRS internal input/output signals ; general update;

GPIO: Added Section 8.4: GPIO in low-power modes ; updates for integrating STM32C051xx and STM32C09xxx;

SYSCFG: Added sections Section 9.1.22 , Section 9.1.31 , Section 9.1.32 , and Section 9.1.33 ;

DMAMUX: Updates for integrating STM32C051xx and STM32C09xxx;

EXTI: Updates for introducing TIM15, USART3, USART4, and FDCAN;

Interconnect matrix: Updated Section 10.3.1 , Section 10.3.2 , and Section 10.3.6 ;

ADC: Updated software calibration procedure, ADC clock symbol, TSEN and VREFEN bitfields;

Timers: Update of advanced timer and general-purpose timer sections, with the addition of TIM15;

I2C: General update, with the deprecated terms master and slave replaced with controller and target , respectively;

Added Section 28: FD controller area network (FDCAN) ;

Added Section 32: Important security notice