2. Memory and bus architecture

2.1 System architecture

The main system consists of:

• • Two masters:
  • – Cortex ^® -M0+ core
  • – General-purpose DMA
• • Three slaves:
  • – Internal SRAM
  • – Internal flash memory
  • – AHB with AHB-to-APB bridge that connects all the APB peripherals

These are interconnected using a multilayer AHB bus architecture as shown in Figure 1 .

Figure 1. System architecture

System bus (S-bus)

This bus connects the system bus of the Cortex ^® -M0+ core (peripheral bus) to a bus matrix that manages the arbitration between the core and the DMA.

DMA bus

This bus connects the AHB master interface of the DMA to the bus matrix that manages the access of CPU and DMA to SRAM, flash memory and AHB/APB peripherals.

Bus matrix

The bus matrix arbitrates the access between the core system bus and the DMA master bus. The arbitration uses a Round Robin algorithm. The bus matrix is composed of masters (CPU, DMA) and slaves (flash memory interface, SRAM and AHB-to-APB bridge).

AHB peripherals are connected to the system bus through the bus matrix to allow DMA access.

AHB-to-APB bridge (APB)

The AHB-to-APB bridge provides full synchronous connections between the AHB and the APB bus.

Refer to Section 2.2: Memory organization for the address mapping of the peripherals connected to this bridge.

After each device reset, all peripheral clocks are disabled (except for the SRAM and flash memory). Before using a peripheral, its clock must first be enabled through the RCC_AHBENR, RCC_APBENRx, or RCC_IOPENR register.

Note: Unless otherwise specified, when a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

2.2 Memory organization

2.2.1 Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word's least significant byte and the highest numbered byte the most significant.

2.2.2 Memory map and register boundary addresses

Figure 2. Memory map

1. 0x0000 7FFF for STM32C011xx and STM32C031xx; 0x0800 FFFF for STM32C051xx; 0x0001 FFFF for STM32C071xx; 0x0003 FFFF for STM32C091xx/92xx

2. 0x0800 7FFF for STM32C011xx and STM32C031xx; 0x0000 FFFF for STM32C051xx; 0x0801 FFFF for STM32C071xx; 0x0803 FFFF for STM32C091xx/92xx

3. Depends on boot configuration

All the memory map areas that are not allocated to on-chip memories and peripherals are considered as reserved. For the detailed mapping of available memory and register areas, refer to the following tables.

Table 4. STM32C071xx boundary addresses

Table 5. STM32C091xx boundary addresses

Table 6. STM32C092xx boundary addresses

Table 7. STM32C0 series peripheral register boundary addresses

Table 7. STM32C0 series peripheral register boundary addresses (continued)

1. SYSCFG (ITLINE) registers use 0x4001 0000 as reference peripheral base address.

2.3 Embedded SRAM

The following table summarizes the SRAM resources on the devices, with parity check enabled and disabled.

Table 8. SRAM size (continued)

The SRAM can be accessed by bytes, half-words (16 bits) or full words (32 bits), at maximum system clock frequency without wait state and thus by both CPU and DMA.

Parity check

The user can enable the parity check using the option bit RAM_PARITY_CHECK in the user option byte (refer to Section 4.4: FLASH option bytes ).

The data bus width is 36 bits because 4 bits are available for parity check (1 bit per byte) in order to increase memory robustness, as required for instance by Class B or SIL norms.

The parity bits are computed and stored when writing into the SRAM. Then, they are automatically checked when reading. If one bit fails, an NMI is generated.

Note: When enabling the SRAM parity check, it is advised to initialize by software the whole SRAM at the beginning of the code, to avoid getting parity errors when reading non-initialized locations.

2.4 FDCAN RAM

FDCAN RAM is only present on the STM32C092xx devices.

The FDCAN peripheral uses the first 1 KB of FDCAN RAM as a message RAM. The next 5 KB (FDCAN scratch RAM) can be accessed by the user. As the memory is accessible only from APB bus, it can only be accessed by words. See section AHB-to-APB bridge (APB) .

Note: Before accessing the FDCAN RAM, enable the FDCAN1 clock.

2.5 Flash memory overview

The flash memory is composed of two distinct physical areas:

• • The main flash memory block. It contains the application program and user data if necessary.
• • The information block. It is composed of three parts:
  • – Option bytes for hardware and memory protection user configuration.
  • – System memory which contains the proprietary boot loader code.
  • – OTP (one-time programmable) area
  Refer to Section 4: Embedded flash memory (FLASH) for more details.

The flash memory interface implements instruction access and data access based on the AHB protocol. It implements the prefetch buffer that speeds up CPU code execution. It also implements the logic necessary to carry out the flash memory operations (Program/Erase) controlled through the flash memory registers.