RM0490-STM32C0

This reference manual complements the datasheets of the STM32C0 series microcontrollers, providing information required for application and in particular for software development. It pertains to the superset of feature sets available on STM32C0 series microcontrollers.

For feature set, ordering information, and mechanical and electrical characteristics of a particular STM32C0 series device, refer to its corresponding datasheet.

For information on the Arm ® Cortex ® -M0+ core, refer to the Cortex ® -M0+ technical reference manual.

The STM32C0 series microcontrollers include ST state-of-the-art patented technology.

a. Available on STMicroelectronics website www.st.com

Contents

4.4FLASH option bytes . . . . .66
4.4.1FLASH option byte description . . . . .66
4.4.2FLASH option byte programming . . . . .67
4.5Flash memory protection . . . . .69
4.5.1FLASH read protection (RDP) . . . . .69
4.5.2FLASH proprietary code readout protection (PCROP) . . . . .72
4.5.3FLASH write protection (WRP) . . . . .73
4.5.4Securable memory area . . . . .74
4.5.5Disabling core debug access . . . . .75
4.5.6Forcing boot from main flash memory . . . . .75
4.6FLASH interrupts . . . . .76
4.7FLASH registers . . . . .77
4.7.1FLASH access control register (FLASH_ACR) . . . . .77
4.7.2FLASH key register (FLASH_KEYR) . . . . .78
4.7.3FLASH option key register (FLASH_OPTKEYR) . . . . .78
4.7.4FLASH status register (FLASH_SR) . . . . .79
4.7.5FLASH control register (FLASH_CR) . . . . .81
4.7.6FLASH option register (FLASH_OPTR) . . . . .83
4.7.7FLASH PCROP area A start address register
(FLASH_PCROP1ASR) . . . . .		85
4.7.8FLASH PCROP area A end address register
(FLASH_PCROP1AER) . . . . .		86
4.7.9FLASH WRP area A address register (FLASH_WRP1AR) . . . . .86
4.7.10FLASH WRP area B address register (FLASH_WRP1BR) . . . . .87
4.7.11FLASH PCROP area B start address register
(FLASH_PCROP1BSR) . . . . .		88
4.7.12FLASH PCROP area B end address register
(FLASH_PCROP1BER) . . . . .		88
4.7.13FLASH security register (FLASH_SECR) . . . . .89
4.7.14FLASH register map . . . . .90
5Power control (PWR) . . . . .92
5.1Power supplies and voltage references . . . . .92
5.1.1ADC reference voltage . . . . .92
5.1.2Voltage regulator . . . . .93
5.2Power supply supervisor . . . . .93
5.2.1Power-on reset (POR) / power-down reset (PDR) / brown-out reset
(BOR) . . . . .		93
5.3Operating modes . . . . .95
5.3.1Power saving in run mode . . . . .97
5.3.2Low-power modes . . . . .98
5.4PWR registers . . . . .102
5.4.1PWR control register 1 (PWR_CR1) . . . . .102
5.4.2PWR control register 1 (PWR_CR2) . . . . .103
5.4.3PWR control register 3 (PWR_CR3) . . . . .104
5.4.4PWR control register 4 (PWR_CR4) . . . . .105
5.4.5PWR status register 1 (PWR_SR1) . . . . .106
5.4.6PWR status register 2 (PWR_SR2) . . . . .107
5.4.7PWR status clear register (PWR_SCR) . . . . .108
5.4.8PWR Port A pull-up control register (PWR_PUCRA) . . . . .109
5.4.9PWR Port A pull-down control register (PWR_PDCRA) . . . . .109
5.4.10PWR Port B pull-up control register (PWR_PUCRB) . . . . .110
5.4.11PWR Port B pull-down control register (PWR_PDCRB) . . . . .110
5.4.12PWR Port C pull-up control register (PWR_PUCRC) . . . . .111
5.4.13PWR Port C pull-down control register (PWR_PDCRC) . . . . .111
5.4.14PWR Port D pull-up control register (PWR_PUCRD) . . . . .112
5.4.15PWR Port D pull-down control register (PWR_PDCRD) . . . . .113
5.4.16PWR Port F pull-up control register (PWR_PUCRF) . . . . .114
5.4.17PWR Port F pull-down control register (PWR_PDCRF) . . . . .114
5.4.18PWR backup x register (PWR_BKPxR) . . . . .115
5.4.19PWR register map . . . . .115
6Reset and clock control (RCC) . . . . .118
6.1Reset . . . . .118
6.1.1Power reset . . . . .118
6.1.2System reset . . . . .118
6.1.3RTC domain reset . . . . .120
6.2Clocks . . . . .121
6.2.1HSE clock . . . . .123
6.2.2HSI48 clock . . . . .125
6.2.3HSIUSB48 clock . . . . .125
6.2.4LSE clock . . . . .126
6.2.5LSI clock . . . . .126
6.2.6System clock (SYSCLK) selection . . . . .127
6.2.7Clock security system (CSS) . . . . .127
6.2.8Clock security system for LSE clock (LSECSS) .....127
6.2.9ADC clock .....128
6.2.10RTC clock .....128
6.2.11Timer clock .....128
6.2.12Watchdog clock .....129
6.2.13Clock-out capability .....129
6.2.14Internal/external clock measurement with TIM14/TIM16/TIM17 .....129
6.2.15Peripheral clock enable registers .....132
6.3Low-power modes .....132
6.4RCC registers .....133
6.4.1RCC clock control register (RCC_CR) .....133
6.4.2RCC internal clock source calibration register (RCC_ICSCR) .....135
6.4.3RCC clock configuration register (RCC_CFGR) .....136
6.4.4RCC clock recovery RC register (RCC_CRRRCR) .....139
6.4.5RCC clock interrupt enable register (RCC_CIER) .....139
6.4.6RCC clock interrupt flag register (RCC_CIFR) .....140
6.4.7RCC clock interrupt clear register (RCC_CICR) .....142
6.4.8RCC I/O port reset register (RCC_IOPRSTR) .....143
6.4.9RCC AHB peripheral reset register (RCC_AHBRSTR) .....144
6.4.10RCC APB peripheral reset register 1 (RCC_APBSTR1) .....144
6.4.11RCC APB peripheral reset register 2 (RCC_APBSTR2) .....146
6.4.12RCC I/O port clock enable register (RCC_IOPENR) .....147
6.4.13RCC AHB peripheral clock enable register (RCC_AHBENR) .....148
6.4.14RCC APB peripheral clock enable register 1 (RCC_APBENR1) .....149
6.4.15RCC APB peripheral clock enable register 2(RCC_APBENR2) .....151
6.4.16RCC I/O port in Sleep mode clock enable register
(RCC_IOPSMENR) .....		153
6.4.17RCC AHB peripheral clock enable in Sleep/Stop mode register
(RCC_AHBSMENR) .....		154
6.4.18RCC APB peripheral clock enable in Sleep/Stop mode register 1
(RCC_APBSMENR1) .....		154
6.4.19RCC APB peripheral clock enable in Sleep/Stop mode register 2
(RCC_APBSMENR2) .....		157
6.4.20RCC peripherals independent clock configuration register 1
(RCC_CCIPR) .....		158
6.4.21RCC peripherals independent clock configuration register 2
(RCC_CCIPR2) .....		159
6.4.22RCC control/status register 1 (RCC_CSR1) .....159
6.4.23RCC control/status register 2 (RCC_CSR2) .....161

6.4.24 RCC register map ..... 163

7 Clock recovery system (CRS) ..... 166

7.1 CRS introduction ..... 166

7.2 CRS main features ..... 166

7.3 CRS implementation ..... 166

7.4 CRS functional description ..... 167

7.4.1 CRS block diagram ..... 167

7.4.2 CRS internal signals ..... 167

7.4.3 Synchronization input ..... 168

7.4.4 Frequency error measurement ..... 168

7.4.5 Frequency error evaluation and automatic trimming ..... 169

7.4.6 CRS initialization and configuration ..... 170

7.5 CRS in low-power modes ..... 171

7.6 CRS interrupts ..... 171

7.7 CRS registers ..... 171

7.7.1 CRS control register (CRS_CR) ..... 171

7.7.2 CRS configuration register (CRS_CFGR) ..... 172

7.7.3 CRS interrupt and status register (CRS_ISR) ..... 173

7.7.4 CRS interrupt flag clear register (CRS_ICR) ..... 175

7.7.5 CRS register map ..... 176

8 General-purpose I/Os (GPIO) ..... 177

8.1 Introduction ..... 177

8.2 GPIO main features ..... 177

8.3 GPIO functional description ..... 177

8.3.1 General-purpose I/O (GPIO) ..... 179

8.3.2 I/O pin alternate function multiplexer and mapping ..... 180

8.3.3 I/O port control registers ..... 181

8.3.4 I/O port data registers ..... 181

8.3.5 I/O data bitwise handling ..... 181

8.3.6 GPIO locking mechanism ..... 181

8.3.7 I/O alternate function input/output ..... 182

8.3.8 External interrupt/wake-up lines ..... 182

8.3.9 Input configuration ..... 182

8.3.10 Output configuration ..... 183

8.3.11Alternate function configuration . . . . .184
8.3.12Analog configuration . . . . .185
8.3.13Using the HSE or LSE oscillator pins as GPIOs . . . . .186
8.3.14Low pin count package adjustment . . . . .186
8.3.15Reset pin (PF2-NRST) in GPIO mode . . . . .186
8.4GPIO in low-power modes . . . . .186
8.5GPIO registers . . . . .187
8.5.1GPIO port mode register (GPIOx_MODER)
(x =A, B, C, D, F) . . . . .		187
8.5.2GPIO port output type register (GPIOx_OTYPER)
(x = A, B, C, D, F) . . . . .		188
8.5.3GPIO port output speed register (GPIOx_OSPEEDR)
(x = A, B, C, D, F) . . . . .		188
8.5.4GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A, B, C, D, F) . . . . .		188
8.5.5GPIO port input data register (GPIOx_IDR)
(x = A, B, C, D, F) . . . . .		189
8.5.6GPIO port output data register (GPIOx_ODR)
(x = A, B, C, D, F) . . . . .		189
8.5.7GPIO port bit set/reset register (GPIOx_BSRR)
(x = A, B, C, D, F) . . . . .		190
8.5.8GPIO port configuration lock register (GPIOx_LCKR)
(x = A, B, C, D, F) . . . . .		190
8.5.9GPIO alternate function low register (GPIOx_AFRL)
(x = A, B, C, D, F) . . . . .		191
8.5.10GPIO alternate function high register (GPIOx_AFRH)
(x = A, B, C, D, F) . . . . .		192
8.5.11GPIO port bit reset register (GPIOx_BRR) (x = A, B, C, D, F) . . . . .193
8.5.12GPIO register map . . . . .194
9System configuration controller (SYSCFG) . . . . .195
9.1SYSCFG registers . . . . .195
9.1.1SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . .195
9.1.2SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . .197
9.1.3SYSCFG configuration register 3 (SYSCFG_CFGR3) . . . . .198
9.1.4SYSCFG interrupt line 0 status register (SYSCFG_ITLINE0) . . . . .201
9.1.5SYSCFG interrupt line 1 status register (SYSCFG_ITLINE1) . . . . .202
9.1.6SYSCFG interrupt line 2 status register (SYSCFG_ITLINE2) . . . . .202
9.1.7SYSCFG interrupt line 3 status register (SYSCFG_ITLINE3) . . . . .203
9.1.8SYSCFG interrupt line 4 status register (SYSCFG_ITLINE4) . . . . .203

9.1.9 SYSCFG interrupt line 5 status register (SYSCFG_ITLINE5) . . . . . 204

9.1.10 SYSCFG interrupt line 6 status register (SYSCFG_ITLINE6) . . . . . 204

9.1.11 SYSCFG interrupt line 7 status register (SYSCFG_ITLINE7) . . . . . 204

9.1.12 SYSCFG interrupt line 8 status register (SYSCFG_ITLINE8) . . . . . 205

9.1.13 SYSCFG interrupt line 9 status register (SYSCFG_ITLINE9) . . . . . 205

9.1.14 SYSCFG interrupt line 10 status register (SYSCFG_ITLINE10) . . . . . 206

9.1.15 SYSCFG interrupt line 11 status register (SYSCFG_ITLINE11) . . . . . 206

9.1.16 SYSCFG interrupt line 12 status register (SYSCFG_ITLINE12) . . . . . 207

9.1.17 SYSCFG interrupt line 13 status register (SYSCFG_ITLINE13) . . . . . 207

9.1.18 SYSCFG interrupt line 14 status register (SYSCFG_ITLINE14) . . . . . 207

9.1.19 SYSCFG interrupt line 15 status register (SYSCFG_ITLINE15) . . . . . 208

9.1.20 SYSCFG interrupt line 16 status register (SYSCFG_ITLINE16) . . . . . 208

9.1.21 SYSCFG interrupt line 19 status register (SYSCFG_ITLINE19) . . . . . 208

9.1.22 SYSCFG interrupt line 20 status register (SYSCFG_ITLINE20) . . . . . 209

9.1.23 SYSCFG interrupt line 21 status register (SYSCFG_ITLINE21) . . . . . 209

9.1.24 SYSCFG interrupt line 22 status register (SYSCFG_ITLINE22) . . . . . 209

9.1.25 SYSCFG interrupt line 23 status register (SYSCFG_ITLINE23) . . . . . 210

9.1.26 SYSCFG interrupt line 24 status register (SYSCFG_ITLINE24) . . . . . 210

9.1.27 SYSCFG interrupt line 25 status register (SYSCFG_ITLINE25) . . . . . 210

9.1.28 SYSCFG interrupt line 26 status register (SYSCFG_ITLINE26) . . . . . 211

9.1.29 SYSCFG interrupt line 27 status register (SYSCFG_ITLINE27) . . . . . 211

9.1.30 SYSCFG interrupt line 28 status register (SYSCFG_ITLINE28) . . . . . 211

9.1.31 SYSCFG interrupt line 29 status register (SYSCFG_ITLINE29) . . . . . 212

9.1.32 SYSCFG interrupt line 30 status register (SYSCFG_ITLINE30) . . . . . 212

9.1.33 SYSCFG interrupt line 31 status register (SYSCFG_ITLINE31) . . . . . 213

9.1.34 SYSCFG register map . . . . . 213

10 Interconnect matrix . . . . . 217

10.1 Introduction . . . . . 217

10.2 Connection summary . . . . . 217

10.3 Interconnection details . . . . . 218

10.3.1 From TIM1, TIM2, TIM3, TIM14, TIM15, and TIM17, to TIM1, TIM2, and TIM3 . . . . . 218

10.3.2 From TIM1, TIM2, TIM3, TIM15, and EXTI, to ADC . . . . . 219

10.3.3 From ADC to TIM1 . . . . . 219

10.3.4 From HSE, LSE, LSI, MCO, MCO2, and RTC, to TIM14, TIM16, and TIM17 . . . . . 219

10.3.5From internal analog sources to ADC .....220
10.3.6From system errors to TIM1, TIM15, TIM16, and TIM17 .....220
10.3.7From TIM16, TIM17, USART1, and USART2, to IRTIM .....220
10.3.8From TIM14 and EXTI to DMAMUX .....221
11Direct memory access controller (DMA) .....222
11.1Introduction .....222
11.2DMA main features .....222
11.3DMA implementation .....223
11.3.1DMA1 .....223
11.3.2DMA request mapping .....223
11.4DMA functional description .....223
11.4.1DMA block diagram .....223
11.4.2DMA pins and internal signals .....224
11.4.3DMA transfers .....224
11.4.4DMA arbitration .....225
11.4.5DMA channels .....225
11.4.6DMA data width, alignment, and endianness .....229
11.4.7DMA error management .....230
11.5DMA interrupts .....231
11.6DMA registers .....231
11.6.1DMA interrupt status register (DMA_ISR) .....231
11.6.2DMA interrupt flag clear register (DMA_IFCR) .....233
11.6.3DMA channel x configuration register (DMA_CCRx) .....235
11.6.4DMA channel x number of data to transfer register (DMA_CNDTRx) ..237
11.6.5DMA channel x peripheral address register (DMA_CPARx) .....238
11.6.6DMA channel x memory address register (DMA_CMARx) .....239
11.6.7DMA register map .....239
12DMA request multiplexer (DMAMUX) .....242
12.1Introduction .....242
12.2DMAMUX main features .....243
12.3DMAMUX implementation .....243
12.3.1DMAMUX instantiation .....243
12.3.2DMAMUX mapping .....243
12.4DMAMUX functional description .....246
12.4.1DMAMUX block diagram . . . . .246
12.4.2DMAMUX signals . . . . .247
12.4.3DMAMUX channels . . . . .247
12.4.4DMAMUX request line multiplexer . . . . .247
12.4.5DMAMUX request generator . . . . .250
12.5DMAMUX interrupts . . . . .251
12.6DMAMUX registers . . . . .252
12.6.1DMAMUX request line multiplexer channel x configuration register
(DMAMUX_CxCR) . . . . .		252
12.6.2DMAMUX request line multiplexer interrupt channel status register
(DMAMUX_CSR) . . . . .		253
12.6.3DMAMUX request line multiplexer interrupt clear flag register
(DMAMUX_CFR) . . . . .		253
12.6.4DMAMUX request generator channel x configuration register
(DMAMUX_RGxCR) . . . . .		254
12.6.5DMAMUX request generator interrupt status register
(DMAMUX_RGSR) . . . . .		255
12.6.6DMAMUX request generator interrupt clear flag register
(DMAMUX_RGCFR) . . . . .		255
12.6.7DMAMUX register map . . . . .256
13Nested vectored interrupt controller (NVIC) . . . . .257
13.1Main features . . . . .257
13.2SysTick calibration value register . . . . .257
13.3Interrupt and exception vectors . . . . .257
14Extended interrupt and event controller (EXTI) . . . . .260
14.1EXTI main features . . . . .260
14.2EXTI block diagram . . . . .260
14.2.1EXTI connections between peripherals and CPU . . . . .262
14.3EXTI functional description . . . . .262
14.3.1EXTI configurable event input wake-up . . . . .263
14.3.2EXTI direct event input wake-up . . . . .263
14.3.3EXTI multiplexer . . . . .264
14.4EXTI functional behavior . . . . .265
14.5EXTI registers . . . . .266
14.5.1EXTI rising trigger selection register 1 (EXTI_RTSR1) . . . . .266
14.5.2EXTI falling trigger selection register 1 (EXTI_FTSR1) . . . . .267
14.5.3EXTI software interrupt event register 1 (EXTI_SWIER1) . . . . .267
14.5.4EXTI rising edge pending register 1 (EXTI_RPR1) . . . . .268
14.5.5EXTI falling edge pending register 1 (EXTI_FPR1) . . . . .268
14.5.6EXTI rising trigger selection register 2 (EXTI_RTSR2) . . . . .269
14.5.7EXTI falling trigger selection register 2 (EXTI_FTSR2) . . . . .269
14.5.8EXTI software interrupt event register 2 (EXTI_SWIER2) . . . . .270
14.5.9EXTI rising edge pending register 2 (EXTI_RPR2) . . . . .270
14.5.10EXTI falling edge pending register 2 (EXTI_FPR2) . . . . .271
14.5.11EXTI external interrupt selection register (EXTI_EXTICRx) . . . . .271
14.5.12EXTI CPU wake-up with interrupt mask register 1 (EXTI_IMR1) . . . . .273
14.5.13EXTI CPU wake-up with event mask register (EXTI_EMR1) . . . . .274
14.5.14EXTI CPU wake-up with interrupt mask register 2 (EXTI_IMR2) . . . . .274
14.5.15EXTI CPU wake-up with event mask register 2 (EXTI_EMR2) . . . . .275
14.5.16EXTI register map . . . . .276
15Cyclic redundancy check calculation unit (CRC) . . . . .278
15.1Introduction . . . . .278
15.2CRC main features . . . . .278
15.3CRC functional description . . . . .279
15.3.1CRC block diagram . . . . .279
15.3.2CRC internal signals . . . . .279
15.3.3CRC operation . . . . .279
15.4CRC registers . . . . .281
15.4.1CRC data register (CRC_DR) . . . . .281
15.4.2CRC independent data register (CRC_IDR) . . . . .281
15.4.3CRC control register (CRC_CR) . . . . .282
15.4.4CRC initial value (CRC_INIT) . . . . .283
15.4.5CRC polynomial (CRC_POL) . . . . .283
15.4.6CRC register map . . . . .284
16Analog-to-digital converter (ADC) . . . . .285
16.1Introduction . . . . .285
16.2ADC main features . . . . .286
16.3ADC implementation . . . . .287
16.4ADC functional description . . . . .288
16.4.1ADC pins and internal signals . . . . .289
16.4.2ADC voltage regulator (ADVREGEN) . . . . .290
16.4.3Calibration (ADCAL) . . . . .290
16.4.4ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .292
16.4.5ADC clock (CKMODE, PRESC[3:0]) . . . . .294
16.4.6ADC connectivity . . . . .296
16.4.7Configuring the ADC . . . . .297
16.4.8Channel selection (CHSEL, SCANDIR, CHSELRMOD) . . . . .297
16.4.9Programmable sampling time (SMPx[2:0]) . . . . .298
16.4.10Single conversion mode (CONT = 0) . . . . .299
16.4.11Continuous conversion mode (CONT = 1) . . . . .299
16.4.12Starting conversions (ADSTART) . . . . .300
16.4.13Timings . . . . .301
16.4.14Stopping an ongoing conversion (ADSTP) . . . . .302
16.5Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . . . . .302
16.5.1Discontinuous mode (DISCEN) . . . . .303
16.5.2Programmable resolution (RES) - Fast conversion mode . . . . .303
16.5.3End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . .304
16.5.4End of conversion sequence (EOS flag) . . . . .304
16.5.5Example timing diagrams (single/continuous modes
hardware/software triggers) . . . . .		305
16.5.6Low frequency trigger mode . . . . .307
16.6Data management . . . . .307
16.6.1Data register and data alignment (ADC_DR, ALIGN) . . . . .307
16.6.2ADC overrun (OVR, OVRMOD) . . . . .307
16.6.3Managing a sequence of data converted without using the DMA . . . . .309
16.6.4Managing converted data without using the DMA without overrun . . . . .309
16.6.5Managing converted data using the DMA . . . . .309
16.7Low-power features . . . . .310
16.7.1Wait mode conversion . . . . .310
16.7.2Auto-off mode (AUTOFF) . . . . .311
16.8Analog window watchdogs . . . . .313
16.8.1Description of analog watchdog 1 . . . . .313
16.8.2Description of analog watchdog 2 and 3 . . . . .314
16.8.3ADC_AWDx_OUT output signal generation . . . . .314
16.8.4Analog watchdog threshold control . . . . .316
16.9Oversampler . . . . .317
16.9.1ADC operating modes supported when oversampling . . . . .318
16.9.2Analog watchdog . . . . .319
16.9.3Triggered mode . . . . .319
16.10Temperature sensor and internal reference voltage . . . . .319
16.11ADC interrupts . . . . .322
16.12ADC registers . . . . .324
16.12.1ADC interrupt and status register (ADC_ISR) . . . . .324
16.12.2ADC interrupt enable register (ADC_IER) . . . . .325
16.12.3ADC control register (ADC_CR) . . . . .327
16.12.4ADC configuration register 1 (ADC_CFGR1) . . . . .329
16.12.5ADC configuration register 2 (ADC_CFGR2) . . . . .332
16.12.6ADC sampling time register (ADC_SMPR) . . . . .334
16.12.7ADC watchdog threshold register (ADC_AWD1TR) . . . . .335
16.12.8ADC watchdog threshold register (ADC_AWD2TR) . . . . .335
16.12.9ADC channel selection register (ADC_CHSELR) . . . . .335
16.12.10ADC channel selection register [alternate] (ADC_CHSELR) . . . . .336
16.12.11ADC watchdog threshold register (ADC_AWD3TR) . . . . .338
16.12.12ADC data register (ADC_DR) . . . . .339
16.12.13ADC analog watchdog 2 configuration register (ADC_AWD2CR) . . . . .339
16.12.14ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR) . . . . .340
16.12.15ADC calibration factor (ADC_CALFACT) . . . . .340
16.12.16ADC common configuration register (ADC_CCR) . . . . .341
16.13ADC register map . . . . .342
17Advanced-control timer (TIM1) . . . . .344
17.1TIM1 introduction . . . . .344
17.2TIM1 main features . . . . .345
17.3TIM1 functional description . . . . .347
17.3.1Time-base unit . . . . .347
17.3.2Counter modes . . . . .349
17.3.3Repetition counter . . . . .360
17.3.4External trigger input . . . . .362
17.3.5Clock selection . . . . .363
17.3.6Capture/compare channels . . . . .367
17.3.7Input capture mode . . . . .369
17.3.8PWM input mode . . . . .370
17.3.9Forced output mode . . . . .371
17.3.10Output compare mode . . . . .372
17.3.11PWM mode . . . . .373
17.3.12Asymmetric PWM mode . . . . .376
17.3.13Combined PWM mode . . . . .377
17.3.14Combined 3-phase PWM mode . . . . .378
17.3.15Complementary outputs and dead-time insertion . . . . .379
17.3.16Using the break function . . . . .381
17.3.17Bidirectional break inputs . . . . .387
17.3.18Clearing the OCxREF signal on an external event . . . . .389
17.3.196-step PWM generation . . . . .390
17.3.20One-pulse mode . . . . .391
17.3.21Retriggerable one pulse mode . . . . .392
17.3.22Encoder interface mode . . . . .393
17.3.23UIF bit remapping . . . . .395
17.3.24Timer input XOR function . . . . .396
17.3.25Interfacing with Hall sensors . . . . .396
17.3.26Timer synchronization . . . . .399
17.3.27ADC synchronization . . . . .403
17.3.28DMA burst mode . . . . .403
17.3.29Debug mode . . . . .404
17.4TIM1 registers . . . . .405
17.4.1TIM1 control register 1 (TIM1_CR1) . . . . .405
17.4.2TIM1 control register 2 (TIM1_CR2) . . . . .406
17.4.3TIM1 slave mode control register
(TIM1_SMCR) . . . . .		409
17.4.4TIM1 DMA/interrupt enable register
(TIM1_DIER) . . . . .		411
17.4.5TIM1 status register (TIM1_SR) . . . . .413
17.4.6TIM1 event generation register (TIM1_EGR) . . . . .415
17.4.7TIM1 capture/compare mode register 1 (TIM1_CCMR1) . . . . .416
17.4.8TIM1 capture/compare mode register 1 [alternate]
(TIM1_CCMR1) . . . . .		417
17.4.9TIM1 capture/compare mode register 2 (TIM1_CCMR2) . . . . .420
17.4.10TIM1 capture/compare mode register 2 [alternate]
(TIM1_CCMR2) . . . . .		421
17.4.11TIM1 capture/compare enable register
(TIM1_CCER) . . . . .		423
17.4.12TIM1 counter (TIM1_CNT) . . . . .426
17.4.13TIM1 prescaler (TIM1_PSC) . . . . .426
17.4.14TIM1 auto-reload register (TIM1_ARR) . . . . .426
17.4.15TIM1 repetition counter register (TIM1_RCR) . . . . .427
17.4.16TIM1 capture/compare register 1
(TIM1_CCR1) . . . . .		427
17.4.17TIM1 capture/compare register 2
(TIM1_CCR2) . . . . .		428
17.4.18TIM1 capture/compare register 3
(TIM1_CCR3) . . . . .		428
17.4.19TIM1 capture/compare register 4
(TIM1_CCR4) . . . . .		429
17.4.20TIM1 break and dead-time register
(TIM1_BDTR) . . . . .		429
17.4.21TIM1 DMA control register
(TIM1_DCR) . . . . .		433
17.4.22TIM1 DMA address for full transfer
(TIM1_DMAR) . . . . .		434
17.4.23TIM1 capture/compare mode register 3
(TIM1_CCMR3) . . . . .		435
17.4.24TIM1 capture/compare register 5
(TIM1_CCR5) . . . . .		436
17.4.25TIM1 capture/compare register 6
(TIM1_CCR6) . . . . .		437
17.4.26TIM1 alternate function option register 1 (TIM1_AF1) . . . . .437
17.4.27TIM1 Alternate function register 2 (TIM1_AF2) . . . . .438
17.4.28TIM1 timer input selection register (TIM1_TISEL) . . . . .439
17.4.29TIM1 register map . . . . .440
18General-purpose timers (TIM2/TIM3) . . . . .443
18.1TIM2/TIM3 introduction . . . . .443
18.2TIM2/TIM3 main features . . . . .443
18.3TIM2/TIM3 functional description . . . . .445
18.3.1Time-base unit . . . . .445
18.3.2Counter modes . . . . .447
18.3.3Clock selection . . . . .457
18.3.4Capture/Compare channels . . . . .461
18.3.5Input capture mode . . . . .463
18.3.6PWM input mode . . . . .464
18.3.7Forced output mode . . . . .465
18.3.8Output compare mode . . . . .465
18.3.9PWM mode .....466
18.3.10Asymmetric PWM mode .....470
18.3.11Combined PWM mode .....470
18.3.12Clearing the OCxREF signal on an external event .....471
18.3.13One-pulse mode .....473
18.3.14Retriggerable one pulse mode .....474
18.3.15Encoder interface mode .....475
18.3.16UIF bit remapping .....477
18.3.17Timer input XOR function .....477
18.3.18Timers and external trigger synchronization .....478
18.3.19Timer synchronization .....481
18.3.20DMA burst mode .....486
18.3.21Debug mode .....487
18.4TIM2/TIM3 registers .....488
18.4.1TIMx control register 1 (TIMx_CR1)(x = 2 to 3) .....488
18.4.2TIMx control register 2 (TIMx_CR2)(x = 2 to 3) .....489
18.4.3TIMx slave mode control register (TIMx_SMCR)(x = 2 to 3) .....491
18.4.4TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 3) .....494
18.4.5TIMx status register (TIMx_SR)(x = 2 to 3) .....496
18.4.6TIMx event generation register (TIMx_EGR)(x = 2 to 3) .....497
18.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 3) ..498
18.4.8TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 2 to 3) .....		500
18.4.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 3) ..502
18.4.10TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 2 to 3) .....		503
18.4.11TIMx capture/compare enable register
(TIMx_CCER)(x = 2 to 3) .....		504
18.4.12TIMx counter (TIMx_CNT)(x = 2 to 3) .....505
18.4.13TIMx counter [alternate] (TIMx_CNT)(x = 2 to 3) .....506
18.4.14TIMx prescaler (TIMx_PSC)(x = 2 to 3) .....506
18.4.15TIMx auto-reload register (TIMx_ARR)(x = 2 to 3) .....507
18.4.16TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 3) .....507
18.4.17TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 3) .....508
18.4.18TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 3) .....508
18.4.19TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 3) .....509
18.4.20TIMx DMA control register (TIMx_DCR)(x = 2 to 3) .....510
18.4.21TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 3) .....510
18.4.22TIM2 alternate function option register 1 (TIM2_AF1) . . . . .511
18.4.23TIM3 alternate function option register 1 (TIM3_AF1) . . . . .511
18.4.24TIM2 timer input selection register (TIM2_TISEL) . . . . .512
18.4.25TIM3 timer input selection register (TIM3_TISEL) . . . . .512
18.4.26TIMx register map . . . . .514
19General-purpose timers (TIM14) . . . . .517
19.1TIM14 introduction . . . . .517
19.2TIM14 main features . . . . .517
19.2.1TIM14 main features . . . . .517
19.3TIM14 functional description . . . . .519
19.3.1Time-base unit . . . . .519
19.3.2Counter modes . . . . .521
19.3.3Clock selection . . . . .524
19.3.4Capture/compare channels . . . . .525
19.3.5Input capture mode . . . . .526
19.3.6Forced output mode . . . . .527
19.3.7Output compare mode . . . . .528
19.3.8PWM mode . . . . .529
19.3.9One-pulse mode . . . . .530
19.3.10UIF bit remapping . . . . .530
19.3.11Using timer output as trigger for other timers (TIM14) . . . . .531
19.3.12Debug mode . . . . .531
19.4TIM14 registers . . . . .532
19.4.1TIM14 control register 1 (TIM14_CR1) . . . . .532
19.4.2TIM14 Interrupt enable register (TIM14_DIER) . . . . .533
19.4.3TIM14 status register (TIM14_SR) . . . . .533
19.4.4TIM14 event generation register (TIM14_EGR) . . . . .534
19.4.5TIM14 capture/compare mode register 1 (TIM14_CCMR1) . . . . .535
19.4.6TIM14 capture/compare mode register 1 [alternate] (TIM14_CCMR1) . . . . .536
19.4.7TIM14 capture/compare enable register (TIM14_CCER) . . . . .538
19.4.8TIM14 counter (TIM14_CNT) . . . . .539
19.4.9TIM14 prescaler (TIM14_PSC) . . . . .540
19.4.10TIM14 auto-reload register (TIM14_ARR) . . . . .540
19.4.11TIM14 capture/compare register 1 (TIM14_CCR1) . . . . .540
19.4.12TIM14 timer input selection register (TIM14_TISEL) . . . . .541
19.4.13TIM14 register map . . . . .541
20General-purpose timers (TIM15/TIM16/TIM17) . . . . .543
20.1TIM15/TIM16/TIM17 introduction . . . . .543
20.2TIM15 main features . . . . .543
20.3TIM16/TIM17 main features . . . . .544
20.4TIM15/TIM16/TIM17 functional description . . . . .547
20.4.1Time-base unit . . . . .547
20.4.2Counter modes . . . . .549
20.4.3Repetition counter . . . . .553
20.4.4Clock selection . . . . .554
20.4.5Capture/compare channels . . . . .556
20.4.6Input capture mode . . . . .558
20.4.7PWM input mode (only for TIM15) . . . . .559
20.4.8Forced output mode . . . . .560
20.4.9Output compare mode . . . . .561
20.4.10PWM mode . . . . .562
20.4.11Combined PWM mode (TIM15 only) . . . . .563
20.4.12Complementary outputs and dead-time insertion . . . . .564
20.4.13Using the break function . . . . .566
20.4.14Bidirectional break inputs . . . . .571
20.4.156-step PWM generation . . . . .572
20.4.16One-pulse mode . . . . .574
20.4.17Retriggerable one pulse mode (TIM15 only) . . . . .575
20.4.18UIF bit remapping . . . . .576
20.4.19Timer input XOR function (TIM15 only) . . . . .577
20.4.20External trigger synchronization (TIM15 only) . . . . .578
20.4.21Slave mode – combined reset + trigger mode . . . . .580
20.4.22DMA burst mode . . . . .580
20.4.23Timer synchronization (TIM15) . . . . .582
20.4.24Using timer output as trigger for other timers (TIM16/TIM17) . . . . .582
20.4.25Debug mode . . . . .582
20.5TIM15 registers . . . . .583
20.5.1TIM15 control register 1 (TIM15_CR1) . . . . .583
20.5.2TIM15 control register 2 (TIM15_CR2) . . . . .584
20.5.3TIM15 slave mode control register (TIM15_SMCR) . . . . .586
20.5.4TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .587
20.5.5TIM15 status register (TIM15_SR) . . . . .588
20.5.6TIM15 event generation register (TIM15_EGR) .....590
20.5.7TIM15 capture/compare mode register 1 (TIM15_CCMR1) .....591
20.5.8TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) .....		592
20.5.9TIM15 capture/compare enable register (TIM15_CCER) .....595
20.5.10TIM15 counter (TIM15_CNT) .....598
20.5.11TIM15 prescaler (TIM15_PSC) .....598
20.5.12TIM15 auto-reload register (TIM15_ARR) .....598
20.5.13TIM15 repetition counter register (TIM15_RCR) .....599
20.5.14TIM15 capture/compare register 1 (TIM15_CCR1) .....599
20.5.15TIM15 capture/compare register 2 (TIM15_CCR2) .....600
20.5.16TIM15 break and dead-time register (TIM15_BDTR) .....600
20.5.17TIM15 DMA control register (TIM15_DCR) .....603
20.5.18TIM15 DMA address for full transfer (TIM15_DMAR) .....603
20.5.19TIM15 alternate register 1 (TIM15_AF1) .....604
20.5.20TIM15 input selection register (TIM15_TISEL) .....604
20.5.21TIM15 register map .....605
20.6TIM16/TIM17 registers .....608
20.6.1TIMx control register 1 (TIMx_CR1)(x = 16 to 17) .....608
20.6.2TIMx control register 2 (TIMx_CR2)(x = 16 to 17) .....609
20.6.3TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) .....610
20.6.4TIMx status register (TIMx_SR)(x = 16 to 17) .....611
20.6.5TIMx event generation register (TIMx_EGR)(x = 16 to 17) .....612
20.6.6TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 16 to 17) .....		613
20.6.7TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) .....		614
20.6.8TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) ..616
20.6.9TIMx counter (TIMx_CNT)(x = 16 to 17) .....618
20.6.10TIMx prescaler (TIMx_PSC)(x = 16 to 17) .....619
20.6.11TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) .....619
20.6.12TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) .....620
20.6.13TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) .....620
20.6.14TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) .....621
20.6.15TIMx DMA control register (TIMx_DCR)(x = 16 to 17) .....624
20.6.16TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) .....624
20.6.17TIM16 alternate function register 1 (TIM16_AF1) .....625
20.6.18TIM16 input selection register (TIM16_TISEL) .....625
20.6.19TIM17 alternate function register 1 (TIM17_AF1) .....626
20.6.20TIM17 input selection register (TIM17_TISEL) .....626
20.6.21TIM16/TIM17 register map .....628
21Infrared interface (IRTIM) .....630
22Independent watchdog (IWDG) .....631
22.1Introduction .....631
22.2IWDG main features .....631
22.3IWDG functional description .....631
22.3.1IWDG block diagram .....631
22.3.2Window option .....632
22.3.3Hardware watchdog .....633
22.3.4Register access protection .....633
22.3.5Debug mode .....633
22.4IWDG registers .....634
22.4.1IWDG key register (IWDG_KR) .....634
22.4.2IWDG prescaler register (IWDG_PR) .....635
22.4.3IWDG reload register (IWDG_RLR) .....636
22.4.4IWDG status register (IWDG_SR) .....637
22.4.5IWDG window register (IWDG_WINR) .....638
22.4.6IWDG register map .....639
23System window watchdog (WWDG) .....640
23.1Introduction .....640
23.2WWDG main features .....640
23.3WWDG functional description .....640
23.3.1WWDG block diagram .....641
23.3.2Enabling the watchdog .....641
23.3.3Controlling the down-counter .....641
23.3.4How to program the watchdog timeout .....641
23.3.5Debug mode .....643
23.4WWDG interrupts .....643
23.5WWDG registers .....643
23.5.1WWDG control register (WWDG_CR) .....643
23.5.2WWDG configuration register (WWDG_CFR) .....644
23.5.3WWDG status register (WWDG_SR) .....645
23.5.4WWDG register map .....645
24Real-time clock (RTC) .....646
24.1Introduction .....646
24.2RTC main features .....646
24.3RTC functional description .....647
24.3.1RTC block diagram .....647
24.3.2RTC pins and internal signals .....648
24.3.3GPIO controlled by the RTC .....648
24.3.4Clock and prescalers .....650
24.3.5Real-time clock and calendar .....651
24.3.6Programmable alarms .....651
24.3.7RTC initialization and configuration .....652
24.3.8Reading the calendar .....653
24.3.9Resetting the RTC .....654
24.3.10RTC synchronization .....654
24.3.11RTC reference clock detection .....655
24.3.12RTC smooth digital calibration .....656
24.3.13Timestamp function .....657
24.3.14Calibration clock output .....658
24.3.15Alarm output .....658
24.4RTC low-power modes .....659
24.5RTC interrupts .....659
24.6RTC registers .....660
24.6.1RTC time register (RTC_TR) .....660
24.6.2RTC date register (RTC_DR) .....661
24.6.3RTC sub second register (RTC_SSR) .....662
24.6.4RTC initialization control and status register (RTC_ICSR) .....662
24.6.5RTC prescaler register (RTC_PRER) .....664
24.6.6RTC control register (RTC_CR) .....664
24.6.7RTC write protection register (RTC_WPR) .....667
24.6.8RTC calibration register (RTC_CALR) .....667
24.6.9RTC shift control register (RTC_SHIFTTR) .....668
24.6.10RTC timestamp time register (RTC_TSTR) .....669
24.6.11RTC timestamp date register (RTC_TSDR) .....670

24.6.12 RTC timestamp sub second register (RTC_TSSSR) . . . . . 670

24.6.13 RTC alarm A register (RTC_ALRMAR) . . . . . 671

24.6.14 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . 672

24.6.15 RTC status register (RTC_SR) . . . . . 672

24.6.16 RTC masked interrupt status register (RTC_MISR) . . . . . 673

24.6.17 RTC status clear register (RTC_SCR) . . . . . 674

24.6.18 RTC register map . . . . . 675

25 Inter-integrated circuit interface (I2C) . . . . . 677

25.1 Introduction . . . . . 677

25.2 I2C main features . . . . . 677

25.3 I2C implementation . . . . . 678

25.4 I2C functional description . . . . . 678

25.4.1 I2C block diagram . . . . . 679

25.4.2 I2C pins and internal signals . . . . . 680

25.4.3 I2C clock requirements . . . . . 680

25.4.4 I2C mode selection . . . . . 680

25.4.5 I2C initialization . . . . . 681

25.4.6 I2C reset . . . . . 685

25.4.7 I2C data transfer . . . . . 686

25.4.8 I2C target mode . . . . . 688

25.4.9 I2C controller mode . . . . . 697

25.4.10 I2C_TIMINGR register configuration examples . . . . . 708

25.4.11 SMBus specific features . . . . . 710

25.4.12 SMBus initialization . . . . . 713

25.4.13 SMBus I2C_TIMEOUTR register configuration examples . . . . . 715

25.4.14 SMBus target mode . . . . . 716

25.4.15 SMBus controller mode . . . . . 719

25.4.16 Wake-up from Stop mode on address match . . . . . 722

25.4.17 Error conditions . . . . . 723

25.5 I2C in low-power modes . . . . . 725

25.6 I2C interrupts . . . . . 725

25.7 I2C DMA requests . . . . . 726

25.7.1 Transmission using DMA . . . . . 726

25.7.2 Reception using DMA . . . . . 726

25.8 I2C debug modes . . . . . 727

25.9I2C registers . . . . .727
25.9.1I2C control register 1 (I2C_CR1) . . . . .727
25.9.2I2C control register 2 (I2C_CR2) . . . . .730
25.9.3I2C own address 1 register (I2C_OAR1) . . . . .732
25.9.4I2C own address 2 register (I2C_OAR2) . . . . .733
25.9.5I2C timing register (I2C_TIMINGR) . . . . .734
25.9.6I2C timeout register (I2C_TIMEOUTR) . . . . .735
25.9.7I2C interrupt and status register (I2C_ISR) . . . . .736
25.9.8I2C interrupt clear register (I2C_ICR) . . . . .738
25.9.9I2C PEC register (I2C_PECR) . . . . .739
25.9.10I2C receive data register (I2C_RXDR) . . . . .739
25.9.11I2C transmit data register (I2C_TXDR) . . . . .740
25.9.12I2C register map . . . . .741
26Universal synchronous receiver transmitter (USART) . . . . .742
26.1USART introduction . . . . .742
26.2USART main features . . . . .743
26.3USART extended features . . . . .744
26.4USART implementation . . . . .744
26.5USART functional description . . . . .746
26.5.1USART block diagram . . . . .746
26.5.2USART signals . . . . .747
26.5.3USART character description . . . . .748
26.5.4USART FIFOs and thresholds . . . . .750
26.5.5USART transmitter . . . . .750
26.5.6USART receiver . . . . .754
26.5.7USART baud rate generation . . . . .761
26.5.8Tolerance of the USART receiver to clock deviation . . . . .762
26.5.9USART auto baud rate detection . . . . .764
26.5.10USART multiprocessor communication . . . . .766
26.5.11USART Modbus communication . . . . .768
26.5.12USART parity control . . . . .769
26.5.13USART LIN (local interconnection network) mode . . . . .770
26.5.14USART synchronous mode . . . . .772
26.5.15USART single-wire half-duplex communication . . . . .776
26.5.16USART receiver timeout . . . . .776
26.5.17USART smartcard mode . . . . .777
26.5.18USART IrDA SIR ENDEC block . . . . .781
26.5.19Continuous communication using USART and DMA . . . . .784
26.5.20RS232 hardware flow control and RS485 Driver Enable . . . . .786
26.5.21USART low-power management . . . . .789
26.6USART in low-power modes . . . . .792
26.7USART interrupts . . . . .793
26.8USART registers . . . . .794
26.8.1USART control register 1 (USART_CR1) . . . . .794
26.8.2USART control register 1 [alternate] (USART_CR1) . . . . .797
26.8.3USART control register 2 (USART_CR2) . . . . .801
26.8.4USART control register 3 (USART_CR3) . . . . .805
26.8.5USART baud rate register (USART_BRR) . . . . .809
26.8.6USART guard time and prescaler register (USART_GTPR) . . . . .809
26.8.7USART receiver timeout register (USART_RTOR) . . . . .810
26.8.8USART request register (USART_RQR) . . . . .811
26.8.9USART interrupt and status register (USART_ISR) . . . . .812
26.8.10USART interrupt and status register [alternate] (USART_ISR) . . . . .818
26.8.11USART interrupt flag clear register (USART_ICR) . . . . .823
26.8.12USART receive data register (USART_RDR) . . . . .825
26.8.13USART transmit data register (USART_TDR) . . . . .825
26.8.14USART prescaler register (USART_PRESC) . . . . .826
26.8.15USART register map . . . . .827
27Serial peripheral interface / integrated interchip sound (SPI/I2S) . . .829
27.1Introduction . . . . .829
27.2SPI main features . . . . .829
27.3I2S main features . . . . .830
27.4SPI/I2S implementation . . . . .830
27.5SPI functional description . . . . .831
27.5.1General description . . . . .831
27.5.2Communications between one master and one slave . . . . .832
27.5.3Standard multislave communication . . . . .834
27.5.4Multimaster communication . . . . .835
27.5.5Slave select (NSS) pin management . . . . .836
27.5.6Communication formats . . . . .837
27.5.7Configuration of SPI . . . . .839
27.5.8Procedure for enabling SPI . . . . .840
27.5.9Data transmission and reception procedures . . . . .840
27.5.10SPI status flags . . . . .850
27.5.11SPI error flags . . . . .851
27.5.12NSS pulse mode . . . . .852
27.5.13TI mode . . . . .852
27.5.14CRC calculation . . . . .853
27.6SPI interrupts . . . . .855
27.7I2S functional description . . . . .856
27.7.1I2S general description . . . . .856
27.7.2Supported audio protocols . . . . .857
27.7.3Start-up description . . . . .864
27.7.4Clock generator . . . . .866
27.7.5I 2 S master mode . . . . .869
27.7.6I 2 S slave mode . . . . .870
27.7.7I2S status flags . . . . .872
27.7.8I2S error flags . . . . .873
27.7.9DMA features . . . . .874
27.8I2S interrupts . . . . .874
27.9SPI and I2S registers . . . . .875
27.9.1SPI control register 1 (SPIx_CR1) . . . . .875
27.9.2SPI control register 2 (SPIx_CR2) . . . . .877
27.9.3SPI status register (SPIx_SR) . . . . .879
27.9.4SPI data register (SPIx_DR) . . . . .881
27.9.5SPI CRC polynomial register (SPIx_CRCPR) . . . . .881
27.9.6SPI Rx CRC register (SPIx_RXCRCR) . . . . .881
27.9.7SPI Tx CRC register (SPIx_TXCRCR) . . . . .882
27.9.8SPIx_I2S configuration register (SPIx_I2SCFGR) . . . . .882
27.9.9SPIx_I2S prescaler register (SPIx_I2SPR) . . . . .884
27.9.10SPI/I2S register map . . . . .886
28FD controller area network (FDCAN) . . . . .887
28.1Introduction . . . . .887
28.2FDCAN main features . . . . .889
28.3FDCAN functional description . . . . .890
28.3.1FDCAN block diagram . . . . .890
28.3.2FDCAN pins and internal signals . . . . .891
28.3.3Bit timing . . . . .892
28.3.4Operating modes . . . . .893
28.3.5Error management . . . . .902
28.3.6Message RAM . . . . .903
28.3.7FIFO acknowledge handling . . . . .912
28.3.8FDCAN Rx FIFO element . . . . .912
28.3.9FDCAN Tx buffer element . . . . .914
28.3.10FDCAN Tx event FIFO element . . . . .916
28.3.11FDCAN standard message ID filter element . . . . .917
28.3.12FDCAN extended message ID filter element . . . . .918
28.4FDCAN registers . . . . .920
28.4.1FDCAN core release register (FDCAN_CREL) . . . . .920
28.4.2FDCAN endian register (FDCAN_ENDN) . . . . .920
28.4.3FDCAN data bit timing and prescaler register (FDCAN_DBTP) . . . . .920
28.4.4FDCAN test register (FDCAN_TEST) . . . . .921
28.4.5FDCAN RAM watchdog register (FDCAN_RWD) . . . . .922
28.4.6FDCAN CC control register (FDCAN_CCCR) . . . . .923
28.4.7FDCAN nominal bit timing and prescaler register (FDCAN_NBTP) . . . . .924
28.4.8FDCAN timestamp counter configuration register (FDCAN_TSCC) . . . . .926
28.4.9FDCAN timestamp counter value register (FDCAN_TSCV) . . . . .926
28.4.10FDCAN timeout counter configuration register (FDCAN_TOCC) . . . . .927
28.4.11FDCAN timeout counter value register (FDCAN_TOCV) . . . . .928
28.4.12FDCAN error counter register (FDCAN_ECR) . . . . .928
28.4.13FDCAN protocol status register (FDCAN_PSR) . . . . .929
28.4.14FDCAN transmitter delay compensation register (FDCAN_TDCR) . . . . .931
28.4.15FDCAN interrupt register (FDCAN_IR) . . . . .931
28.4.16FDCAN interrupt enable register (FDCAN_IE) . . . . .934
28.4.17FDCAN interrupt line select register (FDCAN_ILS) . . . . .936
28.4.18FDCAN interrupt line enable register (FDCAN_ILE) . . . . .937
28.4.19FDCAN global filter configuration register (FDCAN_RXGFC) . . . . .937
28.4.20FDCAN extended ID and mask register (FDCAN_XIDAM) . . . . .939
28.4.21FDCAN high-priority message status register (FDCAN_HPMS) . . . . .939
28.4.22FDCAN Rx FIFO 0 status register (FDCAN_RXF0S) . . . . .940
28.4.23CAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A) . . . . .941
28.4.24FDCAN Rx FIFO 1 status register (FDCAN_RXF1S) . . . . .941
28.4.25FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A) . . . . .942
28.4.26FDCAN Tx buffer configuration register (FDCAN_TXBC) . . . . .942
28.4.27FDCAN Tx FIFO/queue status register (FDCAN_TXFQS) . . . . .943
28.4.28FDCAN Tx buffer request pending register (FDCAN_TXBRP) . . . . .943
28.4.29FDCAN Tx buffer add request register (FDCAN_TXBAR) . . . . .944
28.4.30FDCAN Tx buffer cancellation request register (FDCAN_TXBCR) . . . . .945
28.4.31FDCAN Tx buffer transmission occurred register (FDCAN_TXBTO) . . . . .945
28.4.32FDCAN Tx buffer cancellation finished register (FDCAN_TXBCF) . . . . .946
28.4.33FDCAN Tx buffer transmission interrupt enable register
(FDCAN_TXBTIE) . . . . .		946
28.4.34FDCAN Tx buffer cancellation finished interrupt enable register
(FDCAN_TXBCIE) . . . . .		947
28.4.35FDCAN Tx event FIFO status register (FDCAN_TXEFS) . . . . .947
28.4.36FDCAN Tx event FIFO acknowledge register (FDCAN_TXEFA) . . . . .948
28.4.37FDCAN CFG clock divider register (FDCAN_CKDIV) . . . . .948
28.4.38FDCAN register map . . . . .949
29Universal serial bus full-speed host/device interface (USB) . . . . .953
29.1Introduction . . . . .953
29.2USB main features . . . . .953
29.3USB implementation . . . . .953
29.4USB functional description . . . . .954
29.4.1USB block diagram . . . . .954
29.4.2USB pins and internal signals . . . . .955
29.4.3USB reset and clocks . . . . .955
29.4.4General description and Device mode functionality . . . . .955
29.4.5Description of USB blocks used in both Device and Host modes . . . . .956
29.4.6Description of host frame scheduler (HFS) specific to Host mode . . . . .957
29.5Programming considerations for Device and Host modes . . . . .958
29.5.1Generic USB Device programming . . . . .958
29.5.2System and power-on reset . . . . .959
29.5.3Double-buffered endpoints and usage in Device mode . . . . .966
29.5.4Double buffered channels: usage in Host mode . . . . .968
29.5.5Isochronous transfers in Device mode . . . . .969
29.5.6Isochronous transfers in Host mode . . . . .970
29.5.7Suspend/resume events . . . . .971
29.6USB registers . . . . .975
29.6.1USB control register (USB_CNTR) . . . . .975
29.6.2USB interrupt status register (USB_ISTR) . . . . .978
29.6.3USB frame number register (USB_FNR) . . . . .982
29.6.4USB Device address (USB_DADDR) . . . . .982
29.6.5USB LPM control and status register (USB_LPMCSR) . . . . .983
29.6.6USB battery charging detector (USB_BCDR) . . . . .984
29.6.7USB endpoint/channel n register (USB_CHEPnR) . . . . .985
29.6.8USB register map . . . . .994
29.7USBFSRAM registers . . . . .995
29.7.1Channel/endpoint transmit buffer descriptor n
(USB_CHEP_TXRXBD_n) . . . . .		996
29.7.2Channel/endpoint receive buffer descriptor n [alternate]
(USB_CHEP_TXRXBD_n) . . . . .		996
29.7.3Channel/endpoint receive buffer descriptor n
(USB_CHEP_RXTXBD_n) . . . . .		998
29.7.4Channel/endpoint transmit buffer descriptor n [alternate]
(USB_CHEP_RXTXBD_n) . . . . .		999
29.7.5USBFSRAM register map . . . . .1000
30Debug support (DBG) . . . . .1001
30.1Overview . . . . .1001
30.2Reference Arm documentation . . . . .1002
30.3Pinout and debug port pins . . . . .1002
30.3.1SWD port pins . . . . .1002
30.3.2SW-DP pin assignment . . . . .1002
30.3.3Internal pull-up & pull-down on SWD pins . . . . .1003
30.4ID codes and locking mechanism . . . . .1003
30.5SWD port . . . . .1003
30.5.1SWD protocol introduction . . . . .1003
30.5.2SWD protocol sequence . . . . .1003
30.5.3SW-DP state machine (reset, idle states, ID code) . . . . .1004
30.5.4DP and AP read/write accesses . . . . .1005
30.5.5SW-DP registers . . . . .1005
30.5.6SW-AP registers . . . . .1006
30.6Core debug . . . . .1007
30.7BPU (break point unit) . . . . .1007
30.7.1BPU functionality . . . . .1008
30.8DWT (data watchpoint) . . . . .1008
30.8.1DWT functionality . . . . .1008
30.8.2DWT Program counter sample register . . . . .1008
30.9MCU debug component (DBG) . . . . .1008
30.9.1Debug support for low-power modes . . . . .1008
30.9.2Debug support for timers, watchdog, and I2C . . . . .1009
30.10DBG registers . . . . .1009
30.10.1DBG device ID code register (DBG_IDCODE) . . . . .1009
30.10.2DBG configuration register (DBG_CR) . . . . .1010
30.10.3DBG APB freeze register 1 (DBG_APB_FZ1) . . . . .1010
30.10.4DBG APB freeze register 2 (DBG_APB_FZ2) . . . . .1012
30.10.5DBG register map . . . . .1014
31Device electronic signature . . . . .1015
31.1Unique device ID register (96 bits) (UID) . . . . .1015
31.2Flash memory size data register (FSIZER) . . . . .1016
31.3Package data register (PCKR) . . . . .1016
32Important security notice . . . . .1018
33Revision history . . . . .1019

List of tables

Table 1. Peripherals or functions versus products . . . . . 42

Table 2. STM32C011xx and STM32C031xx boundary addresses. . . . . 47

Table 3. STM32C051xx boundary addresses . . . . . 47

Table 4. STM32C071xx boundary addresses . . . . . 48

Table 5. STM32C091xx boundary addresses . . . . . 48

Table 6. STM32C092xx boundary addresses . . . . . 49

Table 7. STM32C0 series peripheral register boundary addresses . . . . . 49

Table 8. SRAM size . . . . . 51

Table 9. Boot modes. . . . . 53

Table 10. Flash memory organization for STM32C011xx and STM32C031xx. . . . . 57

Table 11. Flash memory organization for STM32C051xx. . . . . 57

Table 12. Flash memory organization for STM32C071xx. . . . . 58

Table 13. Flash memory organization for STM32C091xx/92xx . . . . . 58

Table 14. LATENCY[2:0] setting as function of HCLK frequency. . . . . 59

Table 15. Page erase overview . . . . . 61

Table 16. Mass erase overview . . . . . 62

Table 17. Option byte format . . . . . 66

Table 18. Organization of option bytes . . . . . 66

Table 19. Flash memory read protection status . . . . . 69

Table 21. Access status versus protection level and execution modes . . . . . 71

Table 22. PCROP protection . . . . . 73

Table 24. Securable memory erase at RDP level 1 to level 0 change . . . . . 75

Table 25. FLASH interrupt requests . . . . . 76

Table 26. FLASH register map and reset values . . . . . 90

Table 27. Device resources enabled in different operating modes. . . . . 96

Table 28. Low-power mode entry overview . . . . . 99

Table 29. Low-power mode exit overview . . . . . 101

Table 30. PWR register map and reset values. . . . . 115

Table 31. RCC register map and reset values . . . . . 163

Table 32. CRS features . . . . . 166

Table 33. CRS internal input/output signals . . . . . 167

Table 34. CRS interconnection. . . . . 168

Table 35. Effect of low-power modes on CRS . . . . . 171

Table 36. Interrupt control bits . . . . . 171

Table 37. CRS register map and reset values . . . . . 176

Table 38. Port bit configuration table . . . . . 178

Table 39. Effect of low-power modes on the GPIO . . . . . 186

Table 40. GPIO register map and reset values . . . . . 194

Table 41. SYSCFG register map and reset values. . . . . 213

Table 42. Interconnect matrix . . . . . 217

Table 43. DMA implementation . . . . . 223

Table 44. DMA internal input/output signals . . . . . 224

Table 45. Programmable data width and endian behavior (when PINC = MINC = 1) . . . . . 229

Table 46. DMA interrupt requests. . . . . 231

Table 47. DMA register map and reset values . . . . . 239

Table 48. DMAMUX instantiation . . . . . 243

Table 49. DMAMUX: assignment of multiplexer inputs to resources . . . . . 244

Table 50. DMAMUX: assignment of trigger inputs to resources. . . . . 244

Table 51.DMAMUX: assignment of synchronization inputs to resources . . . . .245
Table 52.DMAMUX signals . . . . .247
Table 53.DMAMUX interrupts . . . . .251
Table 54.DMAMUX register map and reset values . . . . .256
Table 55.Vector table . . . . .257
Table 56.EXTI signal overview . . . . .261
Table 57.EVG pin overview . . . . .261
Table 58.EXTI event input configurations and register control . . . . .262
Table 59.EXTI line connections . . . . .265
Table 60.Masking functionality . . . . .265
Table 61.EXTI register map sections . . . . .266
Table 62.EXTI controller register map and reset values . . . . .276
Table 63.CRC internal input/output signals . . . . .279
Table 64.CRC register map and reset values . . . . .284
Table 65.ADC main features . . . . .287
Table 66.ADC input/output pins . . . . .289
Table 67.ADC internal input/output signals . . . . .289
Table 68.External triggers . . . . .289
Table 69.Latency between trigger and start of conversion . . . . .295
Table 70.Configuring the trigger polarity . . . . .302
Table 71.tSAR timings depending on resolution . . . . .304
Table 72.Analog watchdog comparison . . . . .313
Table 73.Analog watchdog 1 channel selection . . . . .314
Table 74.Maximum output results vs N and M. Grayed values indicates truncation . . . . .318
Table 75.ADC interrupts . . . . .322
Table 76.ADC register map and reset values . . . . .342
Table 77.Behavior of timer outputs versus BRK/BRK2 inputs . . . . .386
Table 78.Break protection disarming conditions . . . . .388
Table 79.Counting direction versus encoder signals . . . . .394
Table 80.TIM1 internal trigger connection . . . . .411
Table 81.Output control bits for complementary OCx and OCxN channels with break feature . . . . .425
Table 82.TIM1 register map and reset values . . . . .440
Table 83.Counting direction versus encoder signals . . . . .476
Table 84.TIM2/TIM3 internal trigger connection . . . . .494
Table 85.Output control bit for standard OCx channels . . . . .505
Table 86.TIM2/TIM3 register map and reset values . . . . .514
Table 87.Output control bit for standard OCx channels . . . . .539
Table 88.TIM14 register map and reset values . . . . .541
Table 89.Break protection disarming conditions . . . . .571
Table 90.TIMx Internal trigger connection . . . . .587
Table 91.Output control bits for complementary OCx and OCxN channels with break feature
(TIM15) . . . . .		597
Table 92.TIM15 register map and reset values . . . . .605
Table 93.Output control bits for complementary OCx and OCxN channels with break feature
(TIM16/17) . . . . .		618
Table 94.TIM16/TIM17 register map and reset values . . . . .628
Table 95.IWDG register map and reset values . . . . .639
Table 96.WWDG register map and reset values . . . . .645
Table 97.RTC input/output pins . . . . .648
Table 98.RTC internal input/output signals . . . . .648
Table 99.Pin configuration . . . . .649
Table 100.RTC_OUT mapping . . . . .650
Table 101.Effect of low-power modes on RTC . . . . .659
Table 102.RTC pins functionality over modes . . . . .659
Table 103.Interrupt requests . . . . .659
Table 104.RTC register map and reset values . . . . .675
Table 105.I2C implementation . . . . .678
Table 106.I2C input/output pins . . . . .680
Table 107.I2C internal input/output signals . . . . .680
Table 108.Comparison of analog and digital filters . . . . .682
Table 109.I 2 C-bus and SMBus specification data setup and hold times . . . . .684
Table 110.I2C configuration . . . . .688
Table 111.I 2 C-bus and SMBus specification clock timings . . . . .699
Table 112.Timing settings for f I2CCLK of 8 MHz . . . . .709
Table 113.Timing settings for f I2CCLK of 16 MHz . . . . .709
Table 114.Timing settings for f I2CCLK of 48 MHz . . . . .710
Table 115.SMBus timeout specifications . . . . .712
Table 116.SMBus with PEC configuration . . . . .714
Table 117.TIMEOUTA[11:0] for maximum t TIMEOUT of 25 ms . . . . .715
Table 118.TIMEOUTB[11:0] for maximum t LOW:SEXT and t LOW:MEXT of 8 ms . . . . .715
Table 119.TIMEOUTA[11:0] for maximum t IDLE of 50 µs . . . . .715
Table 120.Effect of low-power modes to I2C . . . . .725
Table 121.I2C interrupt requests . . . . .725
Table 122.I2C register map and reset values . . . . .741
Table 123.Instance implementation on STM32C0 series . . . . .744
Table 124.USART features . . . . .745
Table 125.USART input/output pins . . . . .748
Table 126.USART internal input/output signals . . . . .748
Table 127.Noise detection from sampled data . . . . .760
Table 128.Tolerance of the USART receiver when BRR [3:0] = 0000 . . . . .763
Table 129.Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . .764
Table 130.USART frame formats . . . . .769
Table 131.Effect of low-power modes on the USART . . . . .792
Table 132.USART interrupt requests . . . . .793
Table 133.USART register map and reset values . . . . .827
Table 134.STM32C0 series SPI/I2S implementation . . . . .830
Table 135.SPI interrupt requests . . . . .855
Table 136.Audio-frequency precision using 48 MHz clock derived from HSE . . . . .868
Table 137.I2S interrupt requests . . . . .874
Table 138.SPI/I2S register map and reset values . . . . .886
Table 139.CAN subsystem I/O signals . . . . .891
Table 140.CAN subsystem I/O pins . . . . .891
Table 141.DLC coding in FDCAN . . . . .895
Table 142.Possible configurations for frame transmission . . . . .909
Table 143.Rx FIFO element . . . . .912
Table 144.Rx FIFO element description . . . . .912
Table 145.Tx buffer and FIFO element . . . . .914
Table 146.Tx buffer element description . . . . .914
Table 147.Tx event FIFO element . . . . .916
Table 148.Tx event FIFO element description . . . . .916
Table 149.Standard message ID filter element . . . . .917
Table 150.Standard message ID filter element field description . . . . .918
Table 151.Extended message ID filter element . . . . .918
Table 152.Extended message ID filter element field description . . . . .919
Table 153.FDCAN register map and reset values . . . . .949
Table 154.STM32C0 series USB implementation . . . . .953
Table 155.USB input/output pins . . . . .955
Table 156.Double-buffering buffer flag definition . . . . .967
Table 157.Bulk double-buffering memory buffers usage (Device mode). . . . .967
Table 158.Bulk double-buffering memory buffers usage (Host mode) . . . . .969
Table 159.Isochronous memory buffers usage . . . . .970
Table 160.Isochronous memory buffers usage . . . . .971
Table 161.Resume event detection . . . . .973
Table 162.Resume event detection for host . . . . .974
Table 163.Reception status encoding . . . . .992
Table 164.Endpoint/channel type encoding . . . . .992
Table 165.Endpoint/channel kind meaning . . . . .992
Table 166.Transmission status encoding . . . . .992
Table 167.USB register map and reset values . . . . .994
Table 168.Definition of allocated buffer memory . . . . .997
Table 169.USBFSRAM register map and reset values . . . . .1000
Table 170.SW debug port pins . . . . .1002
Table 171.Packet request (8-bits) . . . . .1004
Table 172.ACK response (3 bits). . . . .1004
Table 173.DATA transfer (33 bits). . . . .1004
Table 174.SW-DP registers . . . . .1005
Table 175.32-bit debug port registers addressed through the shifted value A[3:2] . . . . .1006
Table 176.Core debug registers . . . . .1007
Table 177.DEV_ID bitfield values . . . . .1009
Table 178.DBG register map and reset values . . . . .1014
Table 179.Document revision history . . . . .1019

List of figures

Figure 1.System architecture . . . . .43
Figure 2.Memory map . . . . .46
Figure 3.Changing read protection (RDP) level . . . . .71
Figure 4.Example of disabling core debug access . . . . .75
Figure 5.Power supply overview . . . . .92
Figure 6.POR, PDR, and BOR thresholds . . . . .94
Figure 7.Low-power mode transit diagram . . . . .95
Figure 8.Simplified diagram of the reset circuit . . . . .119
Figure 9.Clock tree . . . . .123
Figure 10.HSE/ LSE clock sources . . . . .124
Figure 11.Frequency measurement with TIM14 in capture mode . . . . .130
Figure 12.Frequency measurement with TIM16 in capture mode . . . . .130
Figure 13.Frequency measurement with TIM17 in capture mode . . . . .131
Figure 14.CRS block diagram . . . . .167
Figure 15.CRS counter behavior . . . . .169
Figure 16.Basic structure of an I/O port bit . . . . .178
Figure 17.Input floating/pull up/pull down configurations . . . . .183
Figure 18.Output configuration . . . . .184
Figure 19.Alternate function configuration- . . . . .185
Figure 20.High impedance-analog configuration . . . . .185
Figure 21.DMA block diagram . . . . .223
Figure 22.DMAMUX block diagram . . . . .246
Figure 23.Synchronization mode of the DMAMUX request line multiplexer channel . . . . .249
Figure 24.Event generation of the DMA request line multiplexer channel . . . . .249
Figure 25.EXTI block diagram . . . . .261
Figure 26.Configurable event trigger logic CPU wake-up . . . . .263
Figure 27.Direct event trigger logic CPU wake-up . . . . .264
Figure 28.EXTI GPIO multiplexer . . . . .264
Figure 29.CRC calculation unit block diagram . . . . .279
Figure 30.ADC block diagram . . . . .288
Figure 31.ADC calibration . . . . .292
Figure 32.Calibration factor forcing . . . . .292
Figure 33.Enabling/disabling the ADC . . . . .293
Figure 34.ADC clock scheme . . . . .294
Figure 35.ADC connectivity . . . . .296
Figure 36.Analog-to-digital conversion time . . . . .301
Figure 37.ADC conversion timings . . . . .301
Figure 38.Stopping an ongoing conversion . . . . .302
Figure 39.Single conversions of a sequence, software trigger . . . . .305
Figure 40.Continuous conversion of a sequence, software trigger . . . . .305
Figure 41.Single conversions of a sequence, hardware trigger . . . . .306
Figure 42.Continuous conversions of a sequence, hardware trigger . . . . .306
Figure 43.Data alignment and resolution (oversampling disabled: OVSE = 0) . . . . .307
Figure 44.Example of overrun (OVR) . . . . .308
Figure 45.Wait mode conversion (continuous mode, software trigger) . . . . .311
Figure 46.Behavior with WAIT = 0, AUTOFF = 1 . . . . .312
Figure 47.Behavior with WAIT = 1, AUTOFF = 1 . . . . .312
Figure 48.Analog watchdog guarded area . . . . .313
Figure 49.ADC_AWDx_OUT signal generation . . . . .315
Figure 50.ADC_AWDx_OUT signal generation (AWDx flag not cleared by software) . . . . .315
Figure 51.ADC_AWDx_OUT signal generation (on a single channel) . . . . .316
Figure 52.Analog watchdog threshold update . . . . .316
Figure 53.20-bit to 16-bit result truncation . . . . .317
Figure 54.Numerical example with 5-bit shift and rounding . . . . .317
Figure 55.Triggered oversampling mode (TOVS bit = 1) . . . . .319
Figure 56.Temperature sensor and VREFINT channel block diagram . . . . .320
Figure 57.Advanced-control timer block diagram . . . . .346
Figure 58.Counter timing diagram with prescaler division change from 1 to 2 . . . . .348
Figure 59.Counter timing diagram with prescaler division change from 1 to 4 . . . . .348
Figure 60.Counter timing diagram, internal clock divided by 1 . . . . .350
Figure 61.Counter timing diagram, internal clock divided by 2 . . . . .350
Figure 62.Counter timing diagram, internal clock divided by 4 . . . . .351
Figure 63.Counter timing diagram, internal clock divided by N . . . . .351
Figure 64.Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .352
Figure 65.Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .352
Figure 66.Counter timing diagram, internal clock divided by 1 . . . . .354
Figure 67.Counter timing diagram, internal clock divided by 2 . . . . .354
Figure 68.Counter timing diagram, internal clock divided by 4 . . . . .355
Figure 69.Counter timing diagram, internal clock divided by N . . . . .355
Figure 70.Counter timing diagram, update event when repetition counter is not used . . . . .356
Figure 71.Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .357
Figure 72.Counter timing diagram, internal clock divided by 2 . . . . .358
Figure 73.Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .358
Figure 74.Counter timing diagram, internal clock divided by N . . . . .359
Figure 75.Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .359
Figure 76.Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .360
Figure 77.Update rate examples depending on mode and TIMx_RCR register settings . . . . .361
Figure 78.External trigger input block . . . . .362
Figure 79.TIM1 ETR input circuitry . . . . .362
Figure 80.Control circuit in normal mode, internal clock divided by 1 . . . . .363
Figure 81.TI2 external clock connection example . . . . .364
Figure 82.Control circuit in external clock mode 1 . . . . .365
Figure 83.External trigger input block . . . . .365
Figure 84.Control circuit in external clock mode 2 . . . . .366
Figure 85.Capture/compare channel (example: channel 1 input stage) . . . . .367
Figure 86.Capture/compare channel 1 main circuit . . . . .367
Figure 87.Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .368
Figure 88.Output stage of capture/compare channel (channel 4) . . . . .368
Figure 89.Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .369
Figure 90.PWM input mode timing . . . . .371
Figure 91.Output compare mode, toggle on OC1 . . . . .373
Figure 92.Edge-aligned PWM waveforms (ARR=8) . . . . .374
Figure 93.Center-aligned PWM waveforms (ARR=8) . . . . .375
Figure 94.Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .377
Figure 95.Combined PWM mode on channel 1 and 3 . . . . .378
Figure 96.3-phase combined PWM signals with multiple trigger pulses per period . . . . .379
Figure 97.Complementary output with dead-time insertion . . . . .380
Figure 98.Dead-time waveforms with delay greater than the negative pulse . . . . .380
Figure 99.Dead-time waveforms with delay greater than the positive pulse . . . . .381
Figure 100.Break and Break2 circuitry overview . . . . .383
Figure 101. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .385
Figure 102. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . .386
Figure 103. PWM output state following BRK assertion (OSSI=0) . . . . .387
Figure 104. Output redirection (BRK2 request not represented) . . . . .388
Figure 105. Clearing TIMx_OCxREF . . . . .389
Figure 106. 6-step generation, COM example (OSSR=1) . . . . .390
Figure 107. Example of one pulse mode. . . . .391
Figure 108. Retriggerable one pulse mode . . . . .393
Figure 109. Example of counter operation in encoder interface mode. . . . .394
Figure 110. Example of encoder interface mode with TI1FP1 polarity inverted. . . . .395
Figure 111. Measuring time interval between edges on 3 signals . . . . .396
Figure 112. Example of Hall sensor interface . . . . .398
Figure 113. Control circuit in reset mode . . . . .399
Figure 114. Control circuit in Gated mode . . . . .400
Figure 115. Control circuit in trigger mode . . . . .401
Figure 116. Control circuit in external clock mode 2 + trigger mode . . . . .402
Figure 117. General-purpose timer block diagram . . . . .444
Figure 118. Counter timing diagram with prescaler division change from 1 to 2 . . . . .446
Figure 119. Counter timing diagram with prescaler division change from 1 to 4 . . . . .446
Figure 120. Counter timing diagram, internal clock divided by 1 . . . . .447
Figure 121. Counter timing diagram, internal clock divided by 2 . . . . .448
Figure 122. Counter timing diagram, internal clock divided by 4 . . . . .448
Figure 123. Counter timing diagram, internal clock divided by N . . . . .449
Figure 124. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .449
Figure 125. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .450
Figure 126. Counter timing diagram, internal clock divided by 1 . . . . .451
Figure 127. Counter timing diagram, internal clock divided by 2 . . . . .451
Figure 128. Counter timing diagram, internal clock divided by 4 . . . . .452
Figure 129. Counter timing diagram, internal clock divided by N . . . . .452
Figure 130. Counter timing diagram, Update event . . . . .453
Figure 131. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .454
Figure 132. Counter timing diagram, internal clock divided by 2 . . . . .455
Figure 133. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .455
Figure 134. Counter timing diagram, internal clock divided by N . . . . .456
Figure 135. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .456
Figure 136. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .457
Figure 137. Control circuit in normal mode, internal clock divided by 1 . . . . .458
Figure 138. TI2 external clock connection example. . . . .458
Figure 139. Control circuit in external clock mode 1 . . . . .459
Figure 140. External trigger input block . . . . .460
Figure 141. Control circuit in external clock mode 2 . . . . .461
Figure 142. Capture/Compare channel (example: channel 1 input stage) . . . . .461
Figure 143. Capture/Compare channel 1 main circuit . . . . .462
Figure 144. Output stage of Capture/Compare channel (channel 1). . . . .462
Figure 145. PWM input mode timing . . . . .464
Figure 146. Output compare mode, toggle on OC1 . . . . .466
Figure 147. Edge-aligned PWM waveforms (ARR=8) . . . . .467
Figure 148. Center-aligned PWM waveforms (ARR=8). . . . .469
Figure 149. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .470
Figure 150. Combined PWM mode on channels 1 and 3 . . . . .471
Figure 151. Clearing TIMx_OCxREF . . . . .472
Figure 152. Example of one-pulse mode. . . . .473
Figure 153. Retriggerable one-pulse mode . . . . .475
Figure 154. Example of counter operation in encoder interface mode . . . . .476
Figure 155. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .477
Figure 156. Control circuit in reset mode . . . . .478
Figure 157. Control circuit in gated mode . . . . .479
Figure 158. Control circuit in trigger mode . . . . .480
Figure 159. Control circuit in external clock mode 2 + trigger mode . . . . .481
Figure 160. Master/Slave timer example . . . . .482
Figure 161. Master/slave connection example with 1 channel only timers . . . . .482
Figure 162. Gating TIMz with OC1REF of TIMy . . . . .483
Figure 163. Gating TIMz with Enable of TIMy . . . . .484
Figure 164. Triggering TIMz with update of TIMy . . . . .485
Figure 165. Triggering TIMz with Enable of TIMy . . . . .485
Figure 166. Triggering TIMy and TIMz with TIMy TI1 input . . . . .486
Figure 167. General-purpose timer block diagram (TIM14) . . . . .518
Figure 168. Counter timing diagram with prescaler division change from 1 to 2 . . . . .520
Figure 169. Counter timing diagram with prescaler division change from 1 to 4 . . . . .520
Figure 170. Counter timing diagram, internal clock divided by 1 . . . . .521
Figure 171. Counter timing diagram, internal clock divided by 2 . . . . .522
Figure 172. Counter timing diagram, internal clock divided by 4 . . . . .522
Figure 173. Counter timing diagram, internal clock divided by N . . . . .523
Figure 174. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .523
Figure 175. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .524
Figure 176. Control circuit in normal mode, internal clock divided by 1 . . . . .525
Figure 177. Capture/compare channel (example: channel 1 input stage) . . . . .525
Figure 178. Capture/compare channel 1 main circuit . . . . .526
Figure 179. Output stage of capture/compare channel (channel 1) . . . . .526
Figure 180. Output compare mode, toggle on OC1 . . . . .529
Figure 181. Edge-aligned PWM waveforms (ARR=8) . . . . .530
Figure 182. TIM15 block diagram . . . . .545
Figure 183. TIM16/TIM17 block diagram . . . . .546
Figure 184. Counter timing diagram with prescaler division change from 1 to 2 . . . . .548
Figure 185. Counter timing diagram with prescaler division change from 1 to 4 . . . . .548
Figure 186. Counter timing diagram, internal clock divided by 1 . . . . .550
Figure 187. Counter timing diagram, internal clock divided by 2 . . . . .550
Figure 188. Counter timing diagram, internal clock divided by 4 . . . . .551
Figure 189. Counter timing diagram, internal clock divided by N . . . . .551
Figure 190. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .552
Figure 191. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .552
Figure 192. Update rate examples depending on mode and TIMx_RCR register settings . . . . .554
Figure 193. Control circuit in normal mode, internal clock divided by 1 . . . . .555
Figure 194. TI2 external clock connection example . . . . .555
Figure 195. Control circuit in external clock mode 1 . . . . .556
Figure 196. Capture/compare channel (example: channel 1 input stage) . . . . .557
Figure 197. Capture/compare channel 1 main circuit . . . . .557
Figure 198. Output stage of capture/compare channel (channel 1) . . . . .558
Figure 199. Output stage of capture/compare channel (channel 2 for TIM15) . . . . .558
Figure 200. PWM input mode timing . . . . .560
Figure 201. Output compare mode, toggle on OC1 . . . . .562
Figure 202. Edge-aligned PWM waveforms (ARR=8) . . . . .563
Figure 203. Combined PWM mode on channel 1 and 2 . . . . .564
Figure 204. Complementary output with dead-time insertion. . . . .565
Figure 205. Dead-time waveforms with delay greater than the negative pulse. . . . .565
Figure 206. Dead-time waveforms with delay greater than the positive pulse. . . . .566
Figure 207. Break circuitry overview . . . . .568
Figure 208. Output behavior in response to a break . . . . .570
Figure 209. Output redirection . . . . .572
Figure 210. 6-step generation, COM example (OSSR=1) . . . . .573
Figure 211. Example of one pulse mode . . . . .574
Figure 212. Retriggerable one pulse mode . . . . .576
Figure 213. Measuring time interval between edges on 2 signals . . . . .577
Figure 214. Control circuit in reset mode . . . . .578
Figure 215. Control circuit in gated mode . . . . .579
Figure 216. Control circuit in trigger mode . . . . .580
Figure 217. IRTIM internal hardware connections with TIM16 and TIM17 . . . . .630
Figure 218. Independent watchdog block diagram . . . . .631
Figure 219. Watchdog block diagram . . . . .641
Figure 220. Window watchdog timing diagram . . . . .642
Figure 221. RTC block diagram . . . . .647
Figure 222. Block diagram . . . . .679
Figure 223. I 2 C-bus protocol . . . . .681
Figure 224. Setup and hold timings . . . . .683
Figure 225. I2C initialization flow . . . . .685
Figure 226. Data reception . . . . .686
Figure 227. Data transmission . . . . .687
Figure 228. Target initialization flow . . . . .690
Figure 229. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . .692
Figure 230. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . .693
Figure 231. Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . .694
Figure 232. Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . .695
Figure 233. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . .696
Figure 234. Transfer bus diagrams for I2C target receiver
(mandatory events only) . . . . .		696
Figure 235. Controller clock generation . . . . .698
Figure 236. Controller initialization flow . . . . .700
Figure 237. 10-bit address read access with HEAD10R = 0 . . . . .700
Figure 238. 10-bit address read access with HEAD10R = 1 . . . . .701
Figure 239. Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes. . . . .702
Figure 240. Transfer sequence flow for I2C controller transmitter, N > 255 bytes. . . . .703
Figure 241. Transfer bus diagrams for I2C controller transmitter
(mandatory events only) . . . . .		704
Figure 242. Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes . . . . .706
Figure 243. Transfer sequence flow for I2C controller receiver, N > 255 bytes. . . . .707
Figure 244. Transfer bus diagrams for I2C controller receiver
(mandatory events only) . . . . .		708
Figure 245. Timeout intervals for \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \) . . . . .713
Figure 246. Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . .716
Figure 247. Transfer bus diagram for SMBus target transmitter (SBC = 1). . . . .717
Figure 248. Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . .718
Figure 249. Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . .719
Figure 250. Bus transfer diagrams for SMBus controller transmitter . . . . .720
Figure 251. Bus transfer diagrams for SMBus controller receiver . . . . .722
Figure 252. USART block diagram . . . . .746
Figure 253. Word length programming . . . . .749
Figure 254. Configurable stop bits . . . . .751
Figure 255. TC/TXE behavior when transmitting . . . . .754
Figure 256. Start bit detection when oversampling by 16 or 8 . . . . .755
Figure 257. usart_ker_ck clock divider block diagram . . . . .758
Figure 258. Data sampling when oversampling by 16 . . . . .759
Figure 259. Data sampling when oversampling by 8 . . . . .760
Figure 260. Mute mode using Idle line detection . . . . .767
Figure 261. Mute mode using address mark detection . . . . .768
Figure 262. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .771
Figure 263. Break detection in LIN mode vs. Framing error detection. . . . .772
Figure 264. USART example of synchronous master transmission. . . . .773
Figure 265. USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . .		773
Figure 266. USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . .		774
Figure 267. USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . .		775
Figure 268. ISO 7816-3 asynchronous protocol . . . . .777
Figure 269. Parity error detection using the 1.5 stop bits . . . . .779
Figure 270. IrDA SIR ENDEC block diagram. . . . .783
Figure 271. IrDA data modulation (3/16) - normal mode . . . . .783
Figure 272. Transmission using DMA . . . . .785
Figure 273. Reception using DMA . . . . .786
Figure 274. Hardware flow control between 2 USARTs . . . . .786
Figure 275. RS232 RTS flow control . . . . .787
Figure 276. RS232 CTS flow control . . . . .788
Figure 277. Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . .791
Figure 278. Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		791
Figure 279. SPI block diagram. . . . .831
Figure 280. Full-duplex single master/ single slave application. . . . .832
Figure 281. Half-duplex single master/ single slave application . . . . .833
Figure 282. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .		834
Figure 283. Master and three independent slaves. . . . .835
Figure 284. Multimaster application . . . . .836
Figure 285. Hardware/software slave select management . . . . .837
Figure 286. Data clock timing diagram . . . . .838
Figure 287. Data alignment when data length is not equal to 8-bit or 16-bit . . . . .839
Figure 288. Packing data in FIFO for transmission and reception. . . . .843
Figure 289. Master full-duplex communication . . . . .846
Figure 290. Slave full-duplex communication . . . . .847
Figure 291. Master full-duplex communication with CRC . . . . .848
Figure 292. Master full-duplex communication in packed mode . . . . .849
Figure 293. NSSP pulse generation in Motorola SPI master mode. . . . .852
Figure 294. TI mode transfer . . . . .853
Figure 295. I2S block diagram . . . . .856
Figure 296. I 2 S Philips protocol waveforms (16/32-bit full accuracy). . . . .858
Figure 297. I 2 S Philips standard waveforms (24-bit frame) . . . . .858
Figure 298. Transmitting 0x8EAA33 . . . . .859
Figure 299. Receiving 0x8EAA33 . . . . .859
Figure 300. I 2 S Philips standard (16-bit extended to 32-bit packet frame) . . . . .859
Figure 301. Example of 16-bit data frame extended to 32-bit channel frame . . . . .859
Figure 302. MSB Justified 16-bit or 32-bit full-accuracy length . . . . .860
Figure 303. MSB justified 24-bit frame length . . . . .860
Figure 304. MSB justified 16-bit extended to 32-bit packet frame . . . . .861
Figure 305. LSB justified 16-bit or 32-bit full-accuracy . . . . .861
Figure 306. LSB justified 24-bit frame length . . . . .861
Figure 307. Operations required to transmit 0x3478AE. . . . .862
Figure 308. Operations required to receive 0x3478AE . . . . .862
Figure 309. LSB justified 16-bit extended to 32-bit packet frame . . . . .862
Figure 310. Example of 16-bit data frame extended to 32-bit channel frame . . . . .863
Figure 311. PCM standard waveforms (16-bit) . . . . .863
Figure 312. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . .864
Figure 313. Start sequence in master mode . . . . .865
Figure 314. Audio sampling frequency definition . . . . .866
Figure 315. I 2 S clock generator architecture . . . . .866
Figure 316. CAN subsystem. . . . .888
Figure 317. FDCAN block diagram . . . . .890
Figure 318. Bit timing . . . . .892
Figure 319. Transceiver delay measurement . . . . .897
Figure 320. Pin control in bus monitoring mode . . . . .898
Figure 321. Pin control in loop-back mode . . . . .901
Figure 322. CAN error state diagram. . . . .902
Figure 323. Message RAM configuration. . . . .903
Figure 324. Standard message ID filter path . . . . .906
Figure 325. Extended message ID filter path. . . . .907
Figure 326. USB peripheral block diagram . . . . .954
Figure 327. Packet buffer areas with examples of buffer description table locations . . . . .961
Figure 328. Block diagram of STM32C0 series MCU and Cortex ® -M0+-level debug support . . . . .1001

Chapters