60. Revision history

Table 653. Document revision history

DateRevisionChanges
25-Nov-20251Initial release.
16-Dec-20252

Updated programming manual reference in the whole document.

Memory and bus architecture:

Updated Section 2.1: System architecture .

Updated Figure 2: Memory map based on IDAU mapping .

System security:

Updated introduction to Section 3: System security .

Updated introduction to Section : Securing peripherals .

Updated Table 16: OEM1/2 RDP unlocking methods .

GTZC:

Updated Section 5.3.4: GTZC1 TZIC interrupt enable register 4 (GTZC1_TZIC_IER4) to Section 5.3.12: GTZC1 TZIC flag clear register 4 (GTZC1_TZIC_FCR4) .

RAMCFG:

Updated Section 6.3.1: Internal SRAMs features .

FLASH:

Updated Table 33: Flash module 1-Mbyte dual-bank organization for STM32U375/385 .

Updated Section 7.5.4: Secure hide protection extension (HDP extension) .

Updated Figure 18: Secure, HDP, and HDP extension areas .

Updated Figure 17: Flash memory security attributes and protections in case of no bank swap (SWAP_BANK = 0) .

Updated Figure 18: Flash memory security attributes and protections in case of bank swap (SWAP_BANK = 1) .

Updated Table 62: Flash memory access versus HDPx and HDPx extended (x = 1 or 2) .

Updated Section 7.10.14: FLASH option register (FLASH_OPTR) .

Updated Section 7.10.34: FLASH OEM1 key register 1 (FLASH_OEM1KEYR1) to Section 7.10.42: FLASH OEM key status register (FLASH_OEMKEYSR) .

ICACHE:

Updated Section 8.1: ICACHE introduction .

PWR:

Updated Section : Programmable voltage detector (PVD) .

Updated Section 9.3.5: PWR power management .

Updated Section : Exiting a low-power mode .

Updated Section : Entering Stop 3 mode .

Added Section 9.5.20: PWR port B pull-up control register (PWR_PUCRB) .

Updated Section 9.5.22: PWR port C pull-up control register (PWR_PUCRC) to Section 9.5.27: PWR port E pull-down control register (PWR_PDCRE) .

RCC:

Updated Figure 34: Clock tree .

Table 653. Document revision history

DateRevisionChanges
16-Dec-20252

Updated Section 10.5.2: RCC internal clock source calibration register 1 (RCC_ICSCR1) .

CRS:

Updated Section 11.7.1: CRS control register (CRS_CR) .

Updated Section 11.7.4: CRS interrupt flag clear register (CRS_ICR) .

Peripheral interconnect matrix:

Updated Section 14.1: Interconnect matrix introduction .

Updated Table 112: Peripherals interconnect matrix .

Updated Section 14.3.7: Clock sources to timers .

GPDMA:

Updated Section 15.4.5: GPDMA linked-list data structure .

Updated Section 15.4.14: GPDMA transfer in peripheral flow-control mode .

Updated Section 15.8.11: GPDMA channel x transfer register 2 (GPDMA_CxTR2) .

Updated Section 15.8.18: GPDMA channel x linked-list address register (GPDMA_CxLLR) .

NVIC:

Updated Table 134: STM32U3 series vector table .

CRC:

Updated Section 18.3.3: CRC operation .

OCTOSPI:

Updated Table 165: OCTOSPI implementation .

Updated Section 20.4.5: OCTOSPI regular-command protocol signal interface .

Updated Section 20.4.11: OCTOSPI memory-mapped mode .

Updated Section : OCTOSPI delayed data sampling when DQS is used .

Updated Section 20.7.17: OCTOSPI alternate bytes register (OCTOSPI_ABR) .

Updated Figure 126: NCS when CKMODE = 0 (T = CLK period) .

Updated Figure 127: NCS when CKMODE = 1 in SDR mode (T = CLK period) .

Updated Figure 128: NCS when CKMODE = 1 in DTR mode (T = CLK period) .

Updated Figure 129: NCS when CKMODE = 1 with an abort (T = CLK period) .

Updated Section 20.7.1: OCTOSPI control register (OCTOSPI_CR) .

Updated Section 20.7.2: OCTOSPI device configuration register 1 (OCTOSPI_DCR1) .

Updated Section 20.7.6: OCTOSPI status register (OCTOSPI_SR) .

Updated Section 20.7.7: OCTOSPI flag clear register (OCTOSPI_FCR) .

ADC:

Whole section re-edited.

DAC:

Updated Section 24.4.14: DAC channel conversion modes .

Updated Section 24.7.1: DAC control register (DAC_CR) .

CCB:

Updated introduction to Section 31: Coupling and chaining bridge (CCB) .

Updated and moved Section 31.4.5: CCB error management .

Updated introduction to Section 31.5: CCB coupling and chaining operations .

Updated Section 31.5.1: Preliminary steps before any protected operation .

Table 653. Document revision history

DateRevisionChanges
16-Dec-20252

Updated Section : ECDSA signature blob usage for ECDSA signature .
Updated Section : ECDSA signature blob creation .
Updated Table 288: Blob use steps for ECDSA signature (CCOP = 0b11000011) .
Updated Table 289: Blob use steps for signing public key computation (CCOP = 0b10000001) .
Updated Table 291: Blob use steps for scalar multiplication (CCOP = 0b10000001) .
Updated Table 292: Blob creation steps for modular exponentiation (CCOP = 0b01000100) .
RNG:
Updated Section 32.3.3: Random number generation .
Updated Section 32.3.4: RNG initialization .
Updated Section 32.3.5: RNG operation .
Updated Section 32.3.7: Error management .
Updated Section 32.3.8: RNG low-power use .
AES:
Updated introduction to Section 45: Secure AES coprocessor AES hardware accelerator (SAES) .
Updated Section : GCM encryption and decryption process .
Updated Section : CCM encryption and decryption process .
Updated Section 33.8.1: AES control register (AES_CR) .
SAES:
Updated introduction to Section 27: Secure AES coprocessor AES hardware accelerator (SAES) .
Updated introduction to Section 34.1: SAES introduction .
Updated introduction to Section 34.2: SAES main features .
Updated Section : GCM encryption and decryption process .
Updated Section : CCM encryption and decryption process .
Updated Section 34.8.1: SAES control register (SAES_CR) .
HASH:
Updated Section 35.1: HASH introduction .
Updated Section 35.2: HASH main features .
Updated Section 35.4.5: Message digest computing .
Updated Section 35.6.1: HASH control register (HASH_CR) .
Updated Section 35.6.3: HASH start register (HASH_STR) .
Updated Section : HASH digest register x (HASH_HRx) .
Updated Section : HASH supplementary digest register x (HASH_HRx) .
Updated Section 35.6.7: HASH context swap registers .
PKA:
Whole section re-edited.
TIM1:
Updated Figure 398: Combined PWM mode on channel 1 and 3 .
TIM2/TIM3/TIM4:
Updated Section : External clock source mode 2 .
Updated Section 38.4.8: PWM input mode .
Updated Section 38.4.13: Combined PWM mode .
Updated Figure 486: Combined PWM mode on channels 1 and 3 .

Table 653. Document revision history

DateRevisionChanges
16-Dec-20252

Updated Section 38.4.14: Clearing the tim_ocxref signal on an external event .

TIM15/TIM16/TIM17:

Updated Section : External clock source mode 2 .

Updated Figure 592: Edge-aligned PWM waveforms (ARR = 8) .

IWDG:

Updated Section 41.4.3: Software and hardware watchdog modes .

Updated Section 44.7.4: IWDG status register (IWDG_SR) .

Updated Section 44.7.6: IWDG early wake-up interrupt register (IWDG_EWCR) .

RTC:

Whole section re-edited.

TAMP:

Updated Section 47.3.5: TAMP secure protection modes .

Updated Section 47.3.7: TAMP privilege protection modes .

Updated Section 44.6.5: TAMP secure configuration register (TAMP_SECCFGR) .

Updated Section 44.6.6: TAMP privileged configuration register (TAMP_PRIVCFGR) .

Updated Section 44.6.12: TAMP monotonic counter 1 register (TAMP_COUNT1R) .

I2C:

Updated Figure 650: Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 .

Updated Section 48.9.1: I2C control register 1 (I2C_CR1) .

I3C:

Whole section re-edited.

USART:

Updated Section 51.8.2: USART control register 1 [alternate] (USART_CR1) .

LPUART:

Updated Section 52.7.2: LPUART control register 1 [alternate] (LPUART_CR1) .

SAI:

Updated Table 586: SAI internal input/output signals .

FDCAN:

Updated Section 55.4.3: Bit timing .

Updated Section 55.5.7: FDCAN nominal bit timing and prescaler register (FDCAN_NBTP) .

USB:

Updated Table 627: Definition of allocated buffer memory .

DEBUG:

Updated Section : DP target identification register (DP_TARGETID) .

Added Section 57.5: ROM tables .

Updated Section : CTI application trigger set register (CTI_APPSET) .

Updated introduction to Section 57.10.1: TPIU registers .

Updated Section : TPIU supported port size register (TPIU_SSPSR) .

Updated Section : TPIU formatter and flush control register (TPIU_FFCR) .

Table 653. Document revision history

DateRevisionChanges
16-Dec-20252Updated Section : TPIU periodic synchronization counter register (TPIU_PSCR) .
Added Section 57.12: Microcontroller debug unit (DBGMCU) .
Updated Section : DBGMCU configuration register (DBGMCU_CR) .
Device electronic signature:
Updated Section 58.3: Package data register .
26-Feb-20263Addition of:
  • • STM32U356/366 (512 KB devices).
  • • STM32U3B5/3C5 (2 MB devices).
FLASH:
Updated Section 7.5.3: Secure hide protection (HDP) .
PWR:
Updated Table 86: Low-power mode summary .
Updated Table 87: Functionalities depending on the working mode .
RCC:
Updated Section : Clock-out capability .
RNG:
Entire section edited.
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